Low-delay data exchange system based on distributed assembly line

Abstract

The invention discloses a low-delay frame exchange system based on a distributed pipeline. The low-delay frame exchange system comprises a routing arbitration module and a multi-group port UDP (User Datagram Protocol) frame exchange module, the port UDP frame exchange module comprises an RX port unit, an additional routing value unit, a frame buffer / frame broadcast unit, a frame selective receiving / frame buffer unit, a deletion routing value unit and a TX port unit; the additional routing value unit acquires the UDP frame stream from the RX port unit, and adds a frame exchange destination port identifier; the frame buffer / frame broadcast unit obtains the port with the sending authority through the routing arbitration module, and sends the data frame; the frame selective receiving / frame caching unit receives a data frame through a port of receiving permission obtained by the routing arbitration module; the routing value deleting unit deletes a frame exchange destination port identifier; and the routing arbitration module outputs corresponding signals to the frame broadcasting unit and the frame selective receiving unit at each fixed period time. According to the invention, the number of layers of various board cards accessed to the protocol stack of the data exchange system is reduced, the time delay is reduced, and the usage amount of hardware resources is reduced.

Description

Technical Field

[0001] This invention relates to the field of high-speed data transmission, and more specifically to a low-latency data exchange system based on distributed pipelines. Background Technology

[0002] Optoelectronic signal processors are widely used in fields such as photoelectric detection, target recognition, and laser communication. Their core consists of an optoelectronic data exchange unit and an optoelectronic signal processing unit. The optoelectronic data exchange unit is responsible for realizing the data interaction function between the photoelectric detector data acquisition unit and the optoelectronic signal processing unit. With the rapid development of optical frequency technology, optoelectronic signal processor systems have the characteristics of high data transmission rate and high data transmission bandwidth. The requirements for real-time data exchange and high bandwidth are becoming increasingly higher, and the demand for large bandwidth and low latency is becoming increasingly urgent.

[0003] In traditional optoelectronic signal processor data exchange systems, multiple boards typically handle the interaction and processing of various types of data. The data exchange between these boards is the core of the entire optoelectronic signal processor. Different types of data often need to be exchanged and transmitted between the various boards, involving multiple communication protocols, interface rates, and transmission media. This results in a complex system architecture and extremely high technical development difficulty. Traditional solutions use dedicated commercial-grade 10 Gigabit Ethernet switching ASIC chips, which do not support the conversion between multiple protocols, and data frame buffering and latency are uncontrollable. Summary of the Invention

[0004] Based on the above research background, this invention aims to provide a low-latency UDP data exchange system with features such as the fusion of optoelectronic image data and unstructured multi-source data in the field of optoelectronic signal processing architecture, so as to solve the problems of high data exchange latency, small bandwidth and complex interface of traditional optoelectronic signal processors.

[0005] This invention discloses a low-latency frame switching system based on distributed pipelines, which includes a routing arbitration module and a multi-port UDP frame switching module.

[0006] The port UDP frame switching module includes an RX port unit, an additional route value unit, a frame buffer / frame broadcast unit, a frame select / frame buffer unit, a route value deletion unit, and a TX port unit.

[0007] The RX port unit is an internal bus of the chip used to receive UDP frame streams;

[0008] The additional routing value unit connects to the RX port unit in the same group, obtains the UDP frame stream, and appends the frame-switched destination port identifier to the UDP frame;

[0009] The frame buffer / frame broadcast unit connects to the routing arbitration module, the additional routing value unit in the same group, and the frame selection / frame buffer unit of all groups; it buffers UDP frames with the destination port identifier of the frame exchange, extracts the destination port number identifier of the exchange, and submits it to the routing arbitration module; and the routing arbitration module obtains the port with the sending permission and sends the UDP frames in the frame buffer unit to the frame selection / frame buffer unit of the group corresponding to the specified destination port.

[0010] The frame selection / frame buffer unit connects to the routing arbitration module and the delete route value unit in the same group; the frame selection / frame buffer unit obtains the receiving permission from the port of the routing arbitration module, receives data frames from the frame buffer / frame broadcast unit of the corresponding group of the specified port, and stores the received data frames;

[0011] Remove the connection between the routing value unit and the frame selection / frame buffer unit, delete the frame switching destination port identifier, and restore the UDP frame;

[0012] The TX port unit is an internal bus of the chip, connected to the delete route value unit, and is used to send UDP frames through the TX port;

[0013] The routing arbitration module extracts the exchange requests from each frame broadcast buffer unit at each fixed period, selects the ports with sending and receiving permissions according to priority, and outputs the corresponding signals to the frame broadcast unit and the frame receiving unit.

[0014] Furthermore, the additional routing value unit maps the identifier of the switching destination port based on the UDP destination port number and the static routing table, and appends the frame switching destination port identifier to the UDP frame frontend.

[0015] Furthermore, the frame switching destination port identifier uses a multi-bit value as the forwarding destination port identifier, with identifier 1 indicating forwarding and identifier 0 indicating no forwarding;

[0016] For multiple ports, each bit value represents the forwarding status of one port, and the port identifiers from right to left represent the first port to the last port.

[0017] Furthermore, the frame buffer / frame broadcast unit adopts a pipelined processing method, using multiple FIFO registers for frame buffering. While the current frame is being forwarded sequentially, the next frame is also being buffered sequentially, with a gap of 1 position between them.

[0018] Furthermore, the internal state transition scheme of the frame buffer / frame broadcast unit is as follows:

[0019] When the frame buffer / frame broadcast unit receives a signal indicating that data exists in the additional routing value unit (FIFO_Valid=1) in the reset state, the frame buffer / frame broadcast unit begins to work in a loop. It buffers data frames and waits for the enable signal from the routing arbitration module. When it receives the broadcast enable signal and there is no data in the additional routing value unit (FIFO_Valid=0), it broadcasts the data frame and waits for the next data to enter the routing arbitration module. When it receives the broadcast enable signal and there is data in the additional routing value unit (FIFO_Valid=1), it broadcasts the data frame, requests the next frame of data in the additional routing value unit to be forwarded, and continues to wait for the arbitration enable signal.

[0020] Furthermore, the routing arbitration module has a preset number of clock cycles in an enable cycle. Each clock cycle is used to check one port. The number of clock cycles should be greater than the number of ports. After completing the arbitration of the data frame that needs to be forwarded in an enable cycle, it outputs broadcast enable and select-receive enable signals.

[0021] Furthermore, the state transition process of the routing arbitration module is as follows:

[0022] When the routing arbitration module receives the enable cycle start signal EN=1 in the reset state, it sets the highest priority port number to 0. Starting from the highest priority port number, it checks port forwarding requests and outputs broadcast / selective receive enable signals. It then determines whether the current port is the last port. If not, it starts checking the forwarding requests of the next port and outputs broadcast / selective receive enable signals, and checks whether the next port is the last port. This process continues until the last port's forwarding requests have been checked and broadcast / selective receive enable signals have been output. When the next enable cycle start signal EN=1 is triggered, the highest priority port number is incremented by 1, and the process starts again from the highest priority port number to check port forwarding requests and output broadcast / selective receive enable signals. This continues until the last port also becomes the highest priority port, and then the cycle starts again from port 0 as the highest priority port.

[0023] The beneficial effects achieved by this invention are:

[0024] This invention employs a standard UDP frame format for image data transmission and exchange architecture. Referencing the OSI layered design, it uses standard UDP frames as the exchange unit, effectively shielding the complexity caused by various transmission protocols, physical interfaces, and speeds. It supports point-to-point unicast, point-to-multipoint broadcast, and multipoint-to-single-point operating modes. This exchange operates at the transport layer, significantly reducing the number of protocol stack layers required for various boards to access the data exchange system, lowering latency, and reducing hardware resource usage.

[0025] This invention proposes a low-latency data exchange technology based on distributed pipelines, which simultaneously receives data from 16 ports. By using a distributed pipeline approach, it completes the reception of 16 data frames. The scheduling module selects the port to send based on the broadcast domain mapping relationship, thereby completing the data transmission and realizing the data exchange operation. Attached Figure Description

[0026] Figure 1 A schematic diagram of a low-latency frame switching system based on a distributed pipeline provided by the present invention;

[0027] Figure 2 A network layer diagram of a low-latency frame switching system based on distributed pipelines provided by the present invention;

[0028] Figure 3 A schematic diagram of a static routing table in a low-latency frame switching system based on distributed pipelines provided by the present invention;

[0029] Figure 4 A schematic diagram illustrating the addition of routing identifiers in a low-latency frame switching system based on distributed pipelines provided by the present invention;

[0030] Figure 5 A schematic diagram of frame buffer / frame broadcast pipeline operation in a low-latency frame switching system based on distributed pipeline provided by the present invention;

[0031] Figure 6 A schematic diagram illustrating the internal state transition of a frame buffer / frame broadcast unit in a low-latency frame switching system based on distributed pipelines, provided by the present invention.

[0032] Figure 7 This is a schematic diagram illustrating the state transition of the routing arbitration module in a low-latency frame switching system based on distributed pipelines, as provided by the present invention. Detailed Implementation

[0033] The present invention will be further described below with reference to specific embodiments, and the advantages and features of the present invention will become clearer as a result. However, these embodiments are merely exemplary and do not constitute any limitation on the scope of the present invention. Those skilled in the art should understand that modifications or substitutions can be made to the details and form of the technical solutions of the present invention without departing from the spirit and scope of the present invention, but all such modifications and substitutions fall within the protection scope of the present invention.

[0034] like Figure 1 As shown, the present invention provides a low-latency frame switching system based on distributed pipeline, which includes a routing arbitration module and a multi-port UDP frame switching module.

[0035] The port UDP frame switching module includes an RX port unit, an additional route value unit, a frame buffer / frame broadcast unit, a frame select / frame buffer unit, a route value deletion unit, and a TX port unit.

[0036] The RX port unit is an internal bus of the chip used to receive UDP frame streams;

[0037] The additional routing value unit connects to the RX port unit in the same group, obtains the UDP frame stream, and uses it to map the identifier of the switching destination port according to the UDP destination port number and the static routing table, and appends the frame switching destination port identifier to the front end of the UDP frame.

[0038] The destination port identifier for frame switching uses a multi-bit value as the forwarding destination port identifier, with 1 indicating forwarding and 0 indicating no forwarding. Taking a switching system with a 16-port UDP frame switching module as an example, if the 16-bit value of the destination port identifier is 0000_0000_1111_1111, then the data frame is forwarded to ports 0-7 and not forwarded to ports 8-15. The rightmost number corresponds to the first port and the leftmost number corresponds to the last port.

[0039] like Figure 2 As shown, a static forwarding routing table is formed by mapping the destination port number in the UDP frame header to the forwarding destination port identifier. UDP frames are applied directly at the data link layer, omitting the network layer and media access control layer. This simplifies the network layer and reduces switching latency.

[0040] The frame buffer / frame broadcast unit connects to the routing arbitration module, the additional routing value unit in the same group, and the frame selection / frame buffer unit of all groups; it buffers UDP frames with the destination port identifier of the frame exchange, extracts the destination port number identifier of the exchange, and submits it to the routing arbitration module; and the routing arbitration module obtains the port with the sending permission and sends the UDP frames in the frame buffer unit to the frame selection / frame buffer unit of the group corresponding to the specified destination port.

[0041] The frame selection / frame buffer unit connects to the routing arbitration module and the delete route value unit in the same group; the frame selection / frame buffer unit obtains the receiving permission from the port of the routing arbitration module, receives data frames from the frame buffer / frame broadcast unit of the corresponding group of the specified port, and stores the received data frames;

[0042] Remove the connection between the routing value unit and the frame selection / frame buffer unit, delete the frame switching destination port identifier, and restore the UDP frame;

[0043] The TX port unit is an internal bus of the chip, connected to the delete route value unit, and is used to send UDP frames through the TX port;

[0044] The routing arbitration module extracts the exchange requests from each frame broadcast buffer unit at each fixed period. Since each frame selection / frame buffer unit can only receive one frame of data within a fixed period, the routing arbitration module selects the port with sending permission and the port with receiving permission according to priority, and outputs the corresponding signals to the frame broadcast unit and the frame selection unit.

[0045] In this embodiment, the switching system has a total of 16 ports, a system operating frequency of 200MHz, and a bus width of 512 bits for each port, so the bandwidth of a single port is approximately 100Gbps.

[0046] UDP frames support a maximum length of 1480 bytes, so in this system, frame switching is performed at a fixed period of 24 (1480*8 / 512 rounded down).

[0047] like Figure 3 As shown, the static routing table uses RAM to store the forwarding port identifier, and the destination port number of the UDP frame is the RAM address.

[0048] like Figure 4 As shown, the additional routing value unit adds a forwarding port identifier to the UDP frame frontend. The process is as follows: based on the UDP destination port number, the identifier of the switching destination port is mapped, and the frame switching destination port identifier is added to the UDP frame frontend.

[0049] like Figure 5 As shown, the frame buffer / frame broadcast unit adopts a pipelined processing method and uses 24 512-bit registers for frame buffering. While the current frame is forwarded in sequence, the next frame is buffered in sequence, with a gap of 1 position between them.

[0050] like Figure 6 As shown, the internal state transition scheme of the frame buffer / frame broadcast unit is as follows: After receiving the signal that there is data in the additional routing value unit (FIFO_Valid=1) in the reset state, the frame buffer / frame broadcast unit starts to work in a loop. It buffers data frames and waits for the enable signal of the routing arbitration module. When it receives the broadcast enable and there is no data in the additional routing value unit (FIFO_Valid=0), it broadcasts the data frame and waits for the next data to enter the routing arbitration module. When it receives the broadcast enable and there is data in the additional routing value unit (FIFO_Valid=1), it broadcasts the data frame and requests the next frame of data in the additional routing value unit to be forwarded, and continues to wait for the arbitration enable.

[0051] like Figure 7 As shown, the routing arbitration module completes the arbitration of the data frames to be forwarded in the next 24 clock cycles within the 24 clock cycles of this broadcast, and outputs broadcast enable and select-receive enable signals. Its state transition process is shown in the figure below:

[0052] When the routing arbitration module receives the enable cycle start signal EN=1 in the reset state, it sets the highest priority port number to 0. Starting from the highest priority port number, it checks port forwarding requests and outputs broadcast / selective receive enable signals. It then determines whether the current port is the last port. If not, it starts checking the forwarding requests of the next port and outputs broadcast / selective receive enable signals, and checks whether the next port is the last port. This process continues until the last port's forwarding requests have been checked and broadcast / selective receive enable signals have been output. When the next enable cycle start signal EN=1 is triggered, the highest priority port number is incremented by 1, and the process starts again from the highest priority port number to check port forwarding requests and output broadcast / selective receive enable signals. This continues until the last port also becomes the highest priority port, and then the cycle starts again from port 0 as the highest priority port.

[0053] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the scope of protection of the present invention; all technical solutions formed by equivalent transformations or equivalent substitutions fall within the scope of protection of the present invention; the parts of the present invention not described in detail are well known to those skilled in the art.

Claims

1. A low-latency frame switching system based on distributed pipelines, characterized in that, The low-latency frame switching system based on distributed pipelines includes a routing arbitration module and a multi-port UDP frame switching module. The port UDP frame switching module includes an RX port unit, an additional route value unit, a frame buffer / frame broadcast unit, a frame select / frame buffer unit, a route value deletion unit, and a TX port unit. The RX port unit is an internal bus of the chip used to receive UDP frame streams; The additional routing value unit connects to the RX port unit in the same group, obtains the UDP frame stream, and appends the frame-switched destination port identifier to the UDP frame; The frame buffer / frame broadcast unit connects to the routing arbitration module, the additional routing value unit in the same group, and the frame selection / frame buffer unit of all groups; The UDP frame with the destination port identifier of the frame exchange is buffered, the destination port number identifier of the exchange is extracted, and submitted to the routing arbitration module; The port that the routing arbitration module obtains the right to send will send the UDP frames in the frame buffer unit to the frame selection / frame buffer unit of the corresponding group of the specified destination port; The frame selection / frame buffer unit connects to the routing arbitration module and the delete route value unit in the same group; the frame selection / frame buffer unit obtains the receiving permission from the port of the routing arbitration module, receives data frames from the frame buffer / frame broadcast unit of the corresponding group of the specified port, and stores the received data frames; Remove the connection between the routing value unit and the frame selection / frame buffer unit, delete the frame switching destination port identifier, and restore the UDP frame; The TX port unit is an internal bus of the chip, connected to the delete route value unit, and is used to send UDP frames through the TX port; The routing arbitration module extracts the exchange requests from each frame broadcast buffer unit at each fixed period, selects the ports with sending and receiving permissions according to priority, and outputs the corresponding signals to the frame broadcast unit and the frame receiving unit.

2. The low-latency frame switching system based on distributed pipelines according to claim 1, characterized in that, The appended routing value unit maps the identifier of the destination port of the frame to the front end of the UDP frame based on the UDP destination port number and the static routing table.

3. The low-latency frame switching system based on distributed pipelines according to claim 1, characterized in that, The frame switching destination port identifier uses a multi-bit value as the forwarding destination port identifier, with identifier 1 indicating forwarding and identifier 0 indicating no forwarding; For multiple ports, each bit value represents the forwarding status of one port, and the port identifiers from right to left represent the first port to the last port.

4. The low-latency frame switching system based on distributed pipelines according to claim 1, characterized in that, The frame buffer / frame broadcast unit adopts a pipelined processing method and uses multiple FIFO registers for frame buffering. While the current frame is forwarded in sequence, the next frame is buffered in sequence, with a gap of 1 position between them.

5. The low-latency frame switching system based on distributed pipelines according to claim 1, characterized in that, The internal state transition scheme of the frame buffer / frame broadcast unit is as follows: When the frame buffer / frame broadcast unit receives a signal indicating that data exists in the additional routing value unit (FIFO_Valid=1) in the reset state, the frame buffer / frame broadcast unit begins to work in a loop. It buffers data frames and waits for the enable signal from the routing arbitration module. When it receives the broadcast enable signal and there is no data in the additional routing value unit (FIFO_Valid=0), it broadcasts the data frame and waits for the next data to enter the routing arbitration module. When it receives the broadcast enable signal and there is data in the additional routing value unit (FIFO_Valid=1), it broadcasts the data frame, requests the next frame of data in the additional routing value unit to be forwarded, and continues to wait for the arbitration enable signal.

6. The low-latency frame switching system based on distributed pipelines according to claim 1, characterized in that, The routing arbitration module has a preset number of clock cycles in an enable cycle. Each clock cycle is used to check one port. The number of clock cycles should be greater than the number of ports. After completing the arbitration of the data frame that needs to be forwarded in an enable cycle, it outputs broadcast enable and select-receive enable signals.

7. The low-latency frame switching system based on distributed pipelines according to claim 6, characterized in that, The state transition process of the routing arbitration module is as follows: When the routing arbitration module receives the enable cycle start signal EN=1 in the reset state, it sets the highest priority port number to 0. Starting from the highest priority port number, it checks port forwarding requests and outputs broadcast / selective receive enable signals. It then determines whether the current port is the last port. If not, it starts checking the forwarding requests of the next port and outputs broadcast / selective receive enable signals, and checks whether the next port is the last port. This process continues until the last port's forwarding requests have been checked and broadcast / selective receive enable signals have been output. When the next enable cycle start signal EN=1 is triggered, the highest priority port number is incremented by 1, and the process starts again from the highest priority port number to check port forwarding requests and output broadcast / selective receive enable signals. This continues until the last port also becomes the highest priority port, and then the cycle starts again from port 0 as the highest priority port.

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