Solid-state imaging element

Abstract

The present invention relates to a solid-state imaging element comprising: first and second photoelectric conversion elements that convert incident light into first and second charges, respectively; first and second upstream amplification transistors converting the first and second charges into first and second voltages, respectively, and connected to the first and second upstream nodes, respectively; a predetermined number of first capacitive elements each having a first end connected to a first upstream node; a predetermined number of first selection transistors inserted in respective paths between a second end of each of the first capacitive elements and the downstream node; a predetermined number of second capacitive elements each having a first end connected to a second upstream node; a predetermined number of second selection transistors inserted in respective paths between a second end of each of the second capacitive elements and the downstream node; a reset transistor having a source or drain connected to a downstream node; and a downstream amplification transistor having a gate connected to the downstream node and outputting a pixel signal.

Description

[0001] This application is a divisional application of patent application No. 202180025466.5, entitled "Solid-State Imaging Element and Imaging Apparatus," filed on February 17, 2021. Technical Field

[0002] This technology relates to solid-state imaging elements. Specifically, this technology relates to solid-state imaging elements and imaging devices that perform analog-to-digital (AD) conversion on each column. Background Technology

[0003] Typically, to miniaturize pixels, column analog-to-digital converter (ADC) systems have been used in solid-state imaging elements. In these systems, an ADC is arranged outside the pixel array for each column, and pixel signals are read sequentially row by row. In such column ADC systems, when exposure is performed using a rolling shutter system that starts exposure row by row, there is a possibility of rolling shutter distortion. Therefore, a solid-state imaging element has been proposed in which a pair of capacitors is provided for each pixel to maintain a reset level and a signal level in the capacitors, thereby achieving a global shutter system that starts exposure simultaneously in all pixels (e.g., refer to Non-Patent Document 1). This pair of capacitors is connected in series with a source follower circuit via a node, and the reset level and signal level are read sequentially by the source follower circuit.

[0004] List of cited references

[0005] Non-patent literature

[0006] Non-Patent Literature 1: Jae-kyu Lee et al., A 2.1e-Temporal Noise and -105 dB Parasitic Light Sensitivity Backside-Illuminated2.3 μm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology, ISSCC 2020. Summary of the Invention

[0007] The technical problem that the invention aims to solve

[0008] In the aforementioned conventional techniques, the global shutter system of a column ADC system is implemented by maintaining a reset level and a signal level in a pair of capacitors for each pixel. However, when the transistors of the source follower circuit initialize the nodes connected to the capacitors, the following problem exists: kTC noise (in other words, reset noise) is generated at the level corresponding to the capacitors, causing the image quality of the image data to be degraded due to noise.

[0009] This technology was developed in view of this situation, and its purpose is to improve the image quality of solid-state imaging elements that perform exposure on all pixels simultaneously.

[0010] Solutions to technical problems

[0011] This technology was developed to solve the aforementioned problems, and its first aspect relates to a solid-state imaging element, comprising: a predetermined number of capacitive elements; an upstream circuit block that generates a predetermined reset level and each of a plurality of signal levels corresponding to an exposure, and maintains the reset level and the plurality of signal levels by capacitive elements that are different from each other; a selection unit that sequentially executes control to connect the capacitive elements maintaining the reset level among the predetermined number of capacitive elements to a predetermined downstream node, control to disconnect the predetermined number of capacitive elements from the predetermined downstream node, and control to connect the capacitive elements maintaining any of the plurality of signal levels among the predetermined number of capacitive elements to the downstream node; a downstream reset transistor that initializes the level of the downstream node when the predetermined number of capacitive elements are disconnected from the downstream node; and a downstream circuit that sequentially reads the reset level and each of the plurality of signal levels via the downstream node. This produces the effect of reducing kTC noise.

[0012] Furthermore, in the first aspect, the predetermined number of capacitor elements may include a first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element; the upstream circuit block may include: a first upstream circuit that sequentially generates a first reset level and a first signal level, and maintains the first capacitor element and the second capacitor element at the first reset level and the first signal level; and a second upstream circuit that sequentially generates a second reset level and a second signal level, and maintains the third capacitor element and the fourth capacitor element at the second reset level and the second signal level; and the selection unit may include: a first selection circuit that connects either the first capacitor element or the second capacitor element to the downstream node; and a second selection circuit that connects either the third capacitor element or the fourth capacitor element to the downstream node. This produces the effect of maintaining the reset level and signal level of each of the two pixels.

[0013] Furthermore, in a first aspect, the first upstream circuit may include: a first photoelectric conversion element; a first upstream transfer transistor that transfers charge from the first photoelectric conversion element to a first floating diffusion layer; a first reset transistor that initializes the first floating diffusion layer; and a first upstream amplification transistor that amplifies the voltage of the first floating diffusion layer; and the second upstream circuit may include: a second photoelectric conversion element; a second upstream transfer transistor that transfers charge from the second photoelectric conversion element to a second floating diffusion layer; a second reset transistor that initializes the second floating diffusion layer; and a second upstream amplification transistor that amplifies the voltage of the second floating diffusion layer. This produces the effect of maintaining a level corresponding to the voltage of the floating diffusion layer.

[0014] Furthermore, in a first aspect, the first upstream circuit may further include a first current source transistor connected to a first upstream node; the second upstream circuit may further include a second current source transistor connected to a second upstream node; the first upstream amplifying transistor may amplify the voltage of the first floating diffusion layer and output the amplified voltage to the first upstream node; the second upstream amplifying transistor may amplify the voltage of the second floating diffusion layer and output the amplified voltage to the second upstream node; the first capacitor element and the second capacitor element may each have a first terminal commonly connected to the first upstream node and a second terminal connected to the first selection circuit; and the third capacitor element and the fourth capacitor element may each have a first terminal commonly connected to the second upstream node and a second terminal connected to the second selection circuit. This produces the effect of providing a constant current for each pixel.

[0015] Furthermore, in the first aspect, the first upstream transport transistor and the second upstream transport transistor can transfer charge to the first floating diffusion layer and the second floating diffusion layer, and at a predetermined exposure start time, the first reset transistor and the second reset transistor can initialize the first photoelectric conversion element and the second photoelectric conversion element together with the first floating diffusion layer and the second floating diffusion layer; and at a predetermined exposure end time, the first upstream transport transistor and the second upstream transport transistor can transfer charge to the first floating diffusion layer and the second floating diffusion layer. This produces the effect of simultaneously exposing all pixels.

[0016] Furthermore, in the first aspect, the selection unit can sequentially execute control to connect one of the first and second capacitor elements to the downstream node, control to connect the other of the first and second capacitor elements to the downstream node, control to connect one of the third and fourth capacitor elements to the downstream node, and control to connect the other of the third and fourth capacitor elements to the downstream node. This produces the effect of sequentially reading the reset level and signal level of each of the two pixels.

[0017] Furthermore, in the first aspect, the selection unit, in a predetermined addition mode, can sequentially perform: control to connect one of the first and second capacitor elements and one of the third and fourth capacitor elements to the downstream node; and control to connect the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the downstream node. This produces the effect of reading the signal obtained by pixel addition.

[0018] Furthermore, in the first aspect, the first upstream circuit may further include a first upstream selection transistor, which outputs a voltage amplified by the first upstream amplification transistor to a predetermined upstream node according to a predetermined first selection signal; the second upstream circuit may further include: a second upstream selection transistor, which outputs a voltage amplified by the second upstream amplification transistor to the upstream node according to a predetermined second selection signal; and a current source transistor connected to the upstream node; the first capacitor element and the second capacitor element may each have a first terminal commonly connected to the upstream node and a second terminal connected to the first selection circuit; and the third capacitor element and the fourth capacitor element may each have a first terminal commonly connected to the upstream node and a second terminal connected to the second selection circuit. This results in the effect that the current source transistor is shared by two pixels.

[0019] Furthermore, in the first aspect, the first upstream selection transistor and the second upstream selection transistor can sequentially switch to a closed-circuit state immediately before and after the predetermined exposure end time. When the first upstream selection transistor is in the closed-circuit state, the first reset transistor can initialize the first floating diffusion layer; when the second upstream selection transistor is in the closed-circuit state, the second reset transistor can initialize the second floating diffusion layer. The first upstream selection transistor and the second upstream selection transistor can sequentially switch to a closed-circuit state immediately after the exposure end time, and the first upstream transfer transistor and the second upstream transfer transistor can transfer charge at the predetermined exposure end time. This generates the effect of simultaneously exposing all pixels in a configuration where the current source transistor is shared by two pixels.

[0020] Furthermore, in the first aspect, a short-circuit transistor may be provided, which opens and closes the path between the first downstream node and the second downstream node; the predetermined number of capacitor elements may include a first capacitor element, a second capacitor element, a third capacitor element, a fourth capacitor element, a fifth capacitor element, a sixth capacitor element, a seventh capacitor element, and an eighth capacitor element; the selection unit may include: a first selection circuit that connects either the first capacitor element or the second capacitor element to the first downstream node; a second selection circuit that connects either the third capacitor element or the fourth capacitor element to the first downstream node; a third selection circuit that connects either the fifth capacitor element or the sixth capacitor element to the second downstream node; and a fourth selection circuit that connects either the seventh capacitor element or the eighth capacitor element to the second downstream node. This produces the effect of short-circuiting the first downstream node and the second downstream node.

[0021] Furthermore, in the first aspect, the short-circuit transistor can be in an open-circuit state in a predetermined non-additive mode, and in the non-additive mode, the selection unit can execute control in a predetermined order to sequentially connect each of the first and second capacitor elements to the first downstream node, to sequentially connect each of the third and fourth capacitor elements to the first downstream node, to sequentially connect each of the fifth and sixth capacitor elements to the second downstream node, and to sequentially connect each of the seventh and eighth capacitor elements to the second downstream node. This produces the effect of sequentially reading the reset level and signal level of each of the four pixels in the non-additive mode.

[0022] Furthermore, in the first aspect, the short-circuit transistor can be in a closed-circuit state in a predetermined addition mode, and in the addition mode, the selection unit can sequentially execute control to connect one of the fifth and sixth capacitor elements and one of the seventh and eighth capacitor elements to the second downstream node, while simultaneously connecting one of the first and second capacitor elements and one of the third and fourth capacitor elements to the first downstream node; and control to connect the other of the fifth and sixth capacitor elements and the other of the seventh and eighth capacitor elements to the second downstream node, while simultaneously connecting the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the first downstream node. This produces the effect of adding four pixels in a pixel addition mode.

[0023] Furthermore, in the first aspect, the predetermined number of capacitor elements may include a first capacitor element, a second capacitor element, and a third capacitor element; the upstream circuit block may include: a first photoelectric conversion element; a first upstream transfer transistor that transfers charge from the first photoelectric conversion element to a predetermined floating diffusion layer; a second photoelectric conversion element; a second upstream transfer transistor that transfers charge from the second photoelectric conversion element to the predetermined floating diffusion layer; a reset transistor that initializes the floating diffusion layer; and an upstream amplification transistor that amplifies the voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node; and the first capacitor element, the second capacitor element, and the third capacitor element may each have a first terminal commonly connected to the upstream node and a second terminal connected to the selection unit. This produces the effect of maintaining the reset level and the plurality of signal levels.

[0024] Furthermore, in the first aspect, the first upstream transport transistor and the second upstream transport transistor can transfer charge to the floating diffusion layer at a predetermined exposure start time, and the reset transistor can initialize the first photoelectric conversion element and the second photoelectric conversion element together with the floating diffusion layer; and the first upstream transport transistor and the second upstream transport transistor can sequentially transfer charge to the floating diffusion layer at a predetermined exposure end time. This produces the effect of exposing all pixels.

[0025] Furthermore, in the first aspect, the selection unit can sequentially execute control to connect one of the first capacitor element and the second capacitor element to the downstream node, control to connect the other of the first capacitor element and the second capacitor element to the downstream node, and control to connect the third capacitor element to the downstream node. This produces the effect of sequentially reading the reset level and the plurality of signal levels.

[0026] Furthermore, in the first aspect, the upstream circuit block can be disposed on the first chip, and the predetermined number of capacitor elements, the selection section, the downstream reset transistor, and the downstream circuit can be disposed on the second chip. This facilitates pixel miniaturization.

[0027] Furthermore, in the first aspect, an analog-to-digital converter can be provided that sequentially converts the output reset level and the multiple output signal levels into digital signals, and the analog-to-digital converter can be located on the second chip. This facilitates pixel miniaturization.

[0028] Furthermore, in the first aspect, an analog-to-digital converter can be provided that sequentially converts the output reset level and the multiple output signal levels into digital signals, and the analog-to-digital converter can be located on a third chip. This creates an effect that facilitates pixel miniaturization.

[0029] Furthermore, a second aspect of this technology relates to an imaging apparatus, comprising: a predetermined number of capacitive elements; an upstream circuit block that generates a predetermined reset level and each of a plurality of signal levels respectively corresponding to an exposure amount, and maintains the reset level and the plurality of signal levels by capacitive elements that are different from each other; a selection unit that sequentially executes control to connect the capacitive elements maintaining the reset level among the predetermined number of capacitive elements to a predetermined downstream node, control to disconnect the predetermined number of capacitive elements from the predetermined downstream node, and control to connect the capacitive elements maintaining any of the plurality of signal levels among the predetermined number of capacitive elements to the downstream node; a downstream reset transistor that initializes the level of the downstream node when the predetermined number of capacitive elements are disconnected from the downstream node; a downstream circuit that sequentially reads the reset level and each of the plurality of signal levels via the downstream node; and a signal processing circuit that sequentially converts the reset level and the plurality of signal levels into digital signals and processes the digital signals. This produces the effect of generating image data with reduced kTC noise.

[0030] Furthermore, a third aspect of this technology relates to a solid-state imaging element, comprising: a first photoelectric conversion element that converts incident light into electrical charge; a second photoelectric conversion element that converts incident light into electrical charge; an upstream amplifying transistor that converts the electrical charge into voltage; a predetermined number of capacitor elements, each capacitor element having a first terminal connected to an upstream node, the upstream node being the output destination of the upstream amplifying transistor; a predetermined number of selection transistors inserted in respective paths between the predetermined number of capacitor elements and predetermined downstream nodes; a reset transistor having a source or drain connected to the downstream node; and a downstream amplifying transistor having a gate connected to the downstream node and outputting a pixel signal. This results in a reduction of kTC noise. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating a construction example of an imaging device according to a first embodiment of the present technology.

[0032] Figure 2 This is a block diagram illustrating a construction example of a solid-state imaging element according to a first embodiment of the present technology.

[0033] Figure 3 This is a circuit diagram illustrating an example of the construction of a pixel block according to a first embodiment of the present technology.

[0034] Figure 4 This is a circuit diagram illustrating an example of the construction of the upstream circuit and the selection circuit of the first embodiment of the present technology.

[0035] Figure 5 This is a block diagram illustrating an example of the construction of a column signal processing circuit according to a first embodiment of the present technology.

[0036] Figure 6 This is a timing diagram illustrating an example of global shutter operation in the first embodiment of the present technology.

[0037] Figure 7 This is a timing diagram illustrating an example of a readout operation of the first pixel of a pixel block according to a first embodiment of the present technology.

[0038] Figure 8 This is a timing diagram illustrating an example of a reading operation of the second pixel of a pixel block according to a first embodiment of the present technology.

[0039] Figure 9 This is a circuit diagram showing an example of the construction of a pixel in a comparative example.

[0040] Figure 10 This is a diagram illustrating an example of the state of a pixel block in the first embodiment of the present technology when reading the reset level and when initializing the downstream node.

[0041] Figure 11 This is a diagram illustrating an example of the state of a pixel block in the first embodiment of the present technology when reading signal levels.

[0042] Figure 12 This is a flowchart illustrating an operational example of a solid-state imaging element according to a first embodiment of the present technology.

[0043] Figure 13 This is a timing diagram illustrating an example of reading the reset level and signal level in a first variation of the first embodiment of the present invention.

[0044] Figure 14 This is a diagram illustrating an example of a stacked structure of a solid-state imaging element of a second variation of the first embodiment of the present technology.

[0045] Figure 15 This is a circuit diagram illustrating a construction example of a pixel block of a second variation of the first embodiment of the present technology.

[0046] Figure 16 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element according to a third variation of the first embodiment of the present technology.

[0047] Figure 17 This is a plan view illustrating an example of the construction of the pixel array section of the second embodiment of the present technology.

[0048] Figure 18 This is a circuit diagram illustrating an example of the construction of a pixel block according to a second embodiment of the present technology.

[0049] Figure 19 This is a circuit diagram illustrating an example of the construction of the upstream circuit and the selection circuit in the second embodiment of the present technology.

[0050] Figure 20 This is a timing diagram illustrating an example of the reading operation of the first and second pixels of a pixel block in a second embodiment of the present technology.

[0051] Figure 21 This is a timing diagram illustrating an example of the readout operation of the third and fourth pixels of a pixel block in a second embodiment of the present technology.

[0052] Figure 22 This is a timing diagram illustrating an example of a read operation in the addition mode of the second embodiment of the present technology.

[0053] Figure 23 This is a circuit diagram illustrating an example of the construction of a pixel block according to a third embodiment of the present technology.

[0054] Figure 24 This is a timing diagram illustrating an example of global shutter operation in the third embodiment of this technology.

[0055] Figure 25 This is a timing diagram illustrating a control example of the third embodiment of the present technology immediately after exposure.

[0056] Figure 26 This is a circuit diagram illustrating an example of the construction of a pixel block according to a fourth embodiment of the present technology.

[0057] Figure 27 This is a timing diagram illustrating an example of global shutter operation in the fourth embodiment of the present technology.

[0058] Figure 28 This is a timing diagram illustrating an operational example of reading the reset level and signal level in the fourth embodiment of this technology.

[0059] Figure 29 This is a block diagram illustrating a schematic example of the construction of a vehicle control system.

[0060] Figure 30 This is an explanatory diagram showing an example of the mounting position of the imaging unit. Detailed Implementation

[0061] The following will describe the modes used to implement this technology (hereinafter referred to as implementation schemes). They will be shown in the following order.

[0062] 1. First implementation scheme (example of maintaining reset level and signal level in multiple capacitors)

[0063] 2. Second implementation scheme (example in which reset level and signal level are maintained in multiple capacitors and downstream node is short-circuited)

[0064] 3. Third implementation scheme (an example of maintaining reset level and signal level in multiple capacitors and sharing a current source)

[0065] 4. Fourth implementation scheme (example of maintaining the reset level in one capacitor and maintaining the signal level in multiple capacitors)

[0066] 5. Application examples for moving objects

[0067] <1. First Implementation Plan>

[0068] [Example of imaging device construction]

[0069] Figure 1This is a block diagram illustrating a construction example of an imaging apparatus 100 according to a first embodiment of the present technology. The imaging apparatus 100 is an apparatus for imaging image data and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. As the imaging apparatus 100, it is assumed to be a digital camera or an electronic device with imaging capabilities (smartphone, personal computer, etc.).

[0070] The solid-state imaging element 200 images image data under the control of the imaging control unit 130. The solid-state imaging element 200 supplies image data to the recording unit 120 via the signal line 209.

[0071] Imaging lens 110 collects light and guides it to solid-state imaging element 200. Imaging control unit 130 controls solid-state imaging element 200 to image data. Imaging control unit 130 supplies imaging control signals, including vertical synchronization signal VSYNC, to solid-state imaging element 200 via signal line 139. Recording unit 120 records image data.

[0072] Here, the vertical synchronization signal VSYNC is a signal that represents the imaging timing, and as the vertical synchronization signal VSYNC, a period signal with a constant frequency (such as 60Hz) is used.

[0073] Incidentally, the imaging device 100 records image data and can transmit the image data to an external location. In this case, an external interface configured for transmitting image data is also provided. Alternatively, the imaging device 100 can also display image data. In this case, a display unit is also provided.

[0074] [Example of solid-state imaging element construction]

[0075] Figure 2 This is a block diagram illustrating a construction example of a solid-state imaging element 200 according to a first embodiment of the present invention. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array section 220, a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array section 220, a plurality of pixel blocks 300 are arranged in a two-dimensional grid pattern. Each pixel block 300 contains a plurality of pixels (e.g., two pixels). Furthermore, each circuit in the solid-state imaging element 200 is disposed, for example, on a single semiconductor chip.

[0076] In the following text, the pixel blocks 300 or pixel groups arranged along the horizontal direction are referred to as "rows", and the pixel blocks 300 or pixel groups arranged along the direction perpendicular to the rows are referred to as "columns".

[0077] The timing control circuit 212 controls the operating timing of each of the vertical scanning circuit 211, DAC 213 and column signal processing circuit 260 in sync with the vertical synchronization signal VSYNC from the imaging control unit 130.

[0078] DAC 213 generates a sawtooth-shaped ramp signal through digital-to-analog (DA) conversion. DAC 213 supplies the generated ramp signal to column signal processing circuit 260.

[0079] The vertical scanning circuit 211 sequentially selects and drives rows and outputs analog pixel signals. Pixels perform photoelectric conversion on incident light to generate analog pixel signals. These pixel signals are then supplied to the column signal processing circuit 260 via the load MOS circuit block 250.

[0080] In the load MOS circuit block 250, a MOS transistor that supplies a constant current is provided for each column.

[0081] The column signal processing circuit 260 performs signal processing such as AD conversion and correlated double sampling (CDS) processing on the pixel signals of each column. The column signal processing circuit 260 supplies image data including the processed signals to the recording unit 120. Incidentally, the column signal processing circuit 260 is an example of the signal processing circuit described in the claims.

[0082] [Example of pixel block construction]

[0083] Figure 3 This is a circuit diagram illustrating a construction example of a pixel block 300 according to a first embodiment of the present invention. In the pixel block 300, an upstream circuit block 305, capacitor elements 331, 332, 336, and 337, a selection unit 340, a downstream reset transistor 361, and a downstream circuit 370 are arranged. For example, capacitors having a metal-insulator-metal (MIM) structure are used as capacitor elements 331, 332, 336, and 337.

[0084] Incidentally, capacitor elements 331 and 332 are examples of the first and second capacitor elements as claimed in the claims, and capacitor elements 336 and 337 are examples of the third and fourth capacitor elements as claimed in the claims.

[0085] Furthermore, upstream circuit 310 and upstream circuit 320 are arranged in upstream circuit block 305. Selection circuit 350 and selection circuit 355 are arranged in selection section 340. Downstream circuit 370 includes downstream amplification transistor 371 and downstream selection transistor 372.

[0086] Upstream circuit 310 sequentially generates a reset level and a signal level, and maintains capacitor elements 331 and 332 at the reset and signal levels, respectively. Upstream circuit 320 sequentially generates a reset level and a signal level, and maintains capacitor elements 336 and 337 at the reset and signal levels, respectively. Incidentally, upstream circuit 310 is an example of the first upstream circuit as described in claim 1, and upstream circuit 320 is an example of the second upstream circuit as described in claim 2.

[0087] Selection circuit 350 connects one of capacitor elements 331 and 332 to downstream node 360. Selection circuit 355 connects one of capacitor elements 336 and 337 to downstream node 360. Incidentally, selection circuit 350 is an example of the first selection circuit as claimed, and selection circuit 355 is an example of the second selection circuit as claimed.

[0088] Figure 4 This is a circuit diagram illustrating an example of the construction of upstream circuits 310 and 320, as well as selection circuits 350 and 355, according to a first embodiment of the present technology.

[0089] The upstream circuit 310 includes a photoelectric conversion element 311, a transmission transistor 312, a floating diffusion (FD) reset transistor 313, an FD 314, an upstream amplification transistor 315, and a current source transistor 316.

[0090] In addition, the upstream circuit 320 includes a photoelectric conversion element 321, a transmission transistor 322, an FD reset transistor 323, an FD 324, an upstream amplification transistor 325, and a current source transistor 326.

[0091] Photoelectric conversion elements 311 and 321 generate charge through photoelectric conversion. Transfer transistor 312 transfers charge from photoelectric conversion element 311 to FD 314 according to the transfer signal trg1 from the vertical scanning circuit 211. Transfer transistor 322 transfers charge from photoelectric conversion element 321 to FD 324 according to the transfer signal trg2 from the vertical scanning circuit 211.

[0092] Incidentally, photoelectric conversion elements 311 and 321 are examples of the first and second photoelectric conversion elements as claimed in the claims. Transmission transistors 312 and 322 are examples of the first and second transmission transistors as claimed in the claims.

[0093] FD reset transistor 313 extracts and initializes charge from FD 314 according to FD reset signal rst1 from vertical scan circuit 211. FD reset transistor 323 extracts and initializes charge from FD 324 according to FD reset signal rst2 from vertical scan circuit 211. FD 314 and FD 324 accumulate charge and generate voltages corresponding to the amount of charge.

[0094] Incidentally, FD reset transistors 313 and 323 are examples of the first and second reset transistors as claimed. FD 314 and FD 324 are examples of the first and second floating diffusion layers as claimed.

[0095] Upstream amplifying transistor 315 amplifies the voltage level of FD 314 and outputs the amplified voltage to upstream node 330. Upstream amplifying transistor 325 amplifies the voltage level of FD 324 and outputs the amplified voltage to upstream node 335. Incidentally, upstream amplifying transistors 315 and 325 are examples of the first and second upstream amplifying transistors as described in the claims.

[0096] The drains of FD reset transistors 313 and 323, as well as upstream amplifier transistors 315 and 325, are connected to the power supply voltage VDD. Current source transistor 316 is connected to the source of upstream amplifier transistor 315. Current source transistor 316 supplies current id11 under the control of vertical scan circuit 211. Current source transistor 326 is connected to the source of upstream amplifier transistor 325. Current source transistor 326 supplies current id12 under the control of vertical scan circuit 211.

[0097] Incidentally, current source transistor 316 and current source transistor 326 are examples of the first current source transistor and the second current source transistor as claimed in the claims.

[0098] Capacitor elements 331 and 332 share a common connection to one end of upstream node 330 and the other end of selection circuit 350. Capacitor elements 336 and 337 share a common connection to one end of upstream node 335 and the other end of selection circuit 355.

[0099] Selection circuit 350 includes selection transistor 351 and selection transistor 352. Selection transistor 351 turns on and off the path between capacitor element 331 and downstream node 360 ​​according to selection signal Φr1 from vertical scan circuit 211. Selection transistor 352 turns on and off the path between capacitor element 332 and downstream node 360 ​​according to selection signal Φs1 from vertical scan circuit 211.

[0100] Selection circuit 355 includes selection transistor 356 and selection transistor 357. Selection transistor 356 turns on and off the path between capacitor element 336 and downstream node 360 ​​according to selection signal Φr2 from vertical scan circuit 211. Selection transistor 357 turns on and off the path between capacitor element 337 and downstream node 360 ​​according to selection signal Φs2 from vertical scan circuit 211.

[0101] The downstream reset transistor 361 initializes the level of the downstream node 360 ​​to a predetermined potential Vreg based on the downstream reset signal rstb from the vertical scan circuit 211. As potential Vreg, a potential different from the power supply potential VDD is set (e.g., a potential lower than VDD).

[0102] In downstream circuit 370, downstream amplifying transistor 371 amplifies the level of downstream node 360. Downstream selection transistor 372 outputs the signal amplified by downstream amplifying transistor 371 as a pixel signal to vertical signal line 309 based on the downstream selection signal selb from vertical scan circuit 211.

[0103] Incidentally, for example, in pixel block 300, n-channel metal-oxide-semiconductor (nMOS) transistors are used as various transistors (transfer transistor 312, etc.).

[0104] The circuitry described above, including upstream circuitry 310, capacitors 331 and 332, selection circuitry 350, downstream reset transistor 361, and downstream circuitry 370, functions as one pixel. Additionally, the circuitry including upstream circuitry 320, capacitors 336 and 337, selection circuitry 355, downstream reset transistor 361, and downstream circuitry 370 also functions as one pixel. These two pixels share downstream reset transistor 361 and downstream circuitry 370.

[0105] Furthermore, for example, the two pixels of pixel block 300 are arranged along the column direction. In other words, these two pixels are arranged in odd-numbered rows and even-numbered rows. Incidentally, the positional relationship between the two pixels of pixel block 300 is not limited to odd-numbered rows and even-numbered rows. For example, the two pixels can also be arranged in odd-numbered columns and even-numbered columns. Alternatively, one of the two pixels can be arranged obliquely above the other.

[0106] When exposure begins, the vertical scan circuit 211 supplies a high-level FD reset signal (rst1 or rst2) and a high-level transmission signal (trg1 or trg2) to all rows. This initializes the photoelectric conversion element (311 or 321). This control will be referred to as "PD reset" below.

[0107] Then, the vertical scan circuit 211 supplies high-level FD reset signals rst1 and rst2 to all rows during the pulse period, while simultaneously setting the downstream reset signal rstb and selection signals Φr1 and Φr2 to high level just before the end of the exposure. Therefore, FD 314 and FD 324 are initialized, and the levels corresponding to the levels of FD 314 and FD 324 are held in capacitor elements 331 and 336. Hereinafter, this control will be referred to as "FD reset".

[0108] The levels of FD 314 and FD 324 during FD reset, and the corresponding levels (levels maintained in capacitor elements 331 and 336 and the level of vertical signal line 309) are collectively referred to below as "P phase" or "reset level".

[0109] When the exposure ends, the vertical scan circuit 211 supplies high-level transmission signals trg1 and trg2 to all rows within a pulse period, while simultaneously setting the downstream reset signal rstb and selection signals Φs1 and Φs2 to high levels. Therefore, the signal charge corresponding to the exposure amount is transferred to FD 314 and FD 324, and the levels corresponding to the levels of FD 314 and FD 324 are held in capacitor elements 332 and 337, respectively.

[0110] The levels of FD 314 and FD 324 when transmitting signal charge, as well as the levels corresponding to these levels (levels maintained in capacitor elements 332 and 337 and the level of vertical signal line 309), are collectively referred to below as "D phase" or "signal level".

[0111] This exposure control, which starts and ends exposure simultaneously for all pixels, is called a global shutter system. This exposure control causes the upstream circuitry 310 of all pixels to sequentially generate reset and signal levels. The reset level is held in capacitors 331 and 336, and the signal level is held in capacitors 332 and 337.

[0112] After exposure, the vertical scan circuit 211 sequentially selects rows and outputs the reset level and signal level for each row. When a reset level needs to be output, the vertical scan circuit 211 supplies a high-level selection signal Φr1 or Φr2 for a predetermined period, while simultaneously setting the FD reset signal rst1 or FD reset signal rst2 for the selected row and the downstream selection signal selb to a high level. Therefore, capacitor element 331 or capacitor element 336 is connected to the downstream node 360 ​​to read the reset level.

[0113] After reading the reset level, the vertical scan circuit 211 supplies a high-level downstream reset signal rstb during the pulse period, while simultaneously setting the FD reset signal rst1 or FD reset signal rst2 and the downstream selection signal selb of the selected row to a high level. This initializes the level of the downstream node 360. At this time, selection transistors 351, 352, 356, and 357 are in an open-circuit state, and capacitors 331, 332, 336, and 337 are disconnected from the downstream node 360.

[0114] After downstream node 360 ​​is initialized, vertical scan circuit 211 supplies high-level selection signal Φs1 or high-level selection signal Φs2 for a predetermined period, while maintaining the FD reset signal (rst1 or rst2) of the selected row and the downstream selection signal selb at a high level. Therefore, capacitor element 332 or capacitor element 337 is connected to downstream node 360 ​​to read the signal level.

[0115] Under the above-described read control, the selection circuit 350 of the selected row sequentially executes the control of connecting capacitor element 331 to downstream node 360, the control of disconnecting capacitor element 331 and capacitor element 332 from downstream node 360, and the control of connecting capacitor element 332 to downstream node 360.

[0116] In addition, the selection circuit 355 of the selected row sequentially executes the control of connecting capacitor element 336 to downstream node 360, the control of disconnecting capacitor element 336 and capacitor element 337 from downstream node 360, and the control of connecting capacitor element 337 to downstream node 360.

[0117] Furthermore, when capacitor elements 331, 332, 336, and 337 are disconnected from downstream node 360, the downstream reset transistor 361 of the selected row initializes the level of downstream node 360. Additionally, the downstream circuit 370 of the selected row sequentially reads the reset level and signal level from capacitor elements 331 and 332 (or capacitor elements 336 and 337) via downstream node 360, and outputs the read reset level and signal level to vertical signal line 309.

[0118] [Example of signal processing circuit construction]

[0119] Figure 5 This is a block diagram illustrating a construction example of the column signal processing circuit 260 of the first embodiment of the present technology.

[0120] In the load MOS circuit block 250, vertical signal lines 309 are routed for each column of the pixel block 300. When the number of columns is I (I is an integer), I vertical signal lines 309 are routed. In addition, a load MOS transistor 251 supplying a constant current id2 is connected to each vertical signal line 309.

[0121] In the column signal processing circuit 260, multiple ADCs 261 and digital signal processing units 262 are arranged. The ADCs 261 are arranged for each column. When the number of columns is I, I ADCs 261 are arranged.

[0122] ADC 261 uses the ramp signal Rmp from DAC 213 to convert the analog pixel signal from the corresponding column into a digital signal. ADC 261 then supplies this digital signal to digital signal processing unit 262. For example, a single-slope ADC including a comparator and a counter is arranged as ADC 261.

[0123] The digital signal processing unit 262 performs predetermined signal processing, such as CDS processing, on each digital signal in each column. The digital signal processing unit 262 supplies image data including the processed digital signals to the recording unit 120.

[0124] [Operational Example of a Solid-State Imaging Element]

[0125] Figure 6 This is a timing diagram illustrating an example of global shutter operation according to a first embodiment of the present technology. From time T0 immediately before the start of exposure to time T1 after a pulse period, the vertical scan circuit 211 supplies high-level FD reset signals rst1 and rst2, as well as high-level transmission signals trg1 and trg2, to all rows (in other words, all pixels). Therefore, all pixels are reset by the PD, and exposure begins simultaneously in all rows.

[0126] Here, rst1_[n], rst2_[n], trg1_[n], and trg2_[n] in the diagram represent signals about the nth row of pixels in N rows. N is an integer representing the total number of rows in the pixel block 300, and n is an integer from 1 to N. When two pixels in pixel block 300 are pixels in even-numbered and odd-numbered rows, the nth row of pixel block 300 consists of two rows, namely, an odd-numbered row and an even-numbered row.

[0127] At time T2, immediately preceding the end of the exposure period, in all rows, the vertical scan circuit 211 provides high-level FD reset signals rst1 and rst2 for the pulse period, while simultaneously setting the downstream reset signal rstb, as well as the selection signals Φr1 and Φr2, to high level. Therefore, all pixels undergo FD reset, and the reset level is sampled and held. Here, rstb_[n], Φr1_[n], and Φr2_[n] in the figure represent the signals for the nth row of pixels.

[0128] At time T3, after time T2, the vertical scanning circuit 211 returns the selection signal Φr1 and the selection signal Φr2 to a low level.

[0129] At the end of exposure time T4, the vertical scan circuit 211 supplies high-level transmission signals trg1 and trg2 for the pulse period, while simultaneously setting the downstream reset signal rstb and selection signals Φs1 and Φs2 to high level in all rows. Therefore, the signal levels are sampled and held. Furthermore, Φs1_[n] and Φs2_[n] in the figure represent the signals with respect to the nth row pixel.

[0130] At time T5, after time T4, the vertical scanning circuit 211 returns the selection signal Φs1 and the selection signal Φs2 to a low level.

[0131] Figure 7 This is a timing diagram illustrating an example of the readout operation of the first pixel of pixel block 300 according to the first embodiment of the present technology. During the readout of the nth row starting from time T10, the vertical scan circuit 211 sets the FD reset signals rst1 and rst2 for the nth row, as well as the downstream selection signal selb, to a high level. Furthermore, the downstream reset signals rstb for all rows are controlled to a low level at time T10. Here, selb_[n] in the diagram represents the signal for the nth row pixel.

[0132] Vertical scanning circuit 211 supplies a high-level selection signal Φr1 to the nth row during the period from time T11 to time T12, immediately following time T10. The potential of downstream node 360 ​​becomes the reset level Vrst1. ADC 261 performs AD conversion on this reset level.

[0133] The vertical scanning circuit 211 supplies a high-level downstream reset signal rstb to the nth row during a pulse period starting from time T13 immediately following time T12. Therefore, when parasitic capacitance exists in the downstream node 360, the history of previous signals held in the parasitic capacitance can be erased.

[0134] Vertical scanning circuit 211 supplies a high-level selection signal Φs1 to the nth row from time T14 to time T15, immediately following the initialization of downstream node 360. The potential of downstream node 360 ​​becomes signal level Vsig1. ADC 261 performs AD conversion on this signal level. The difference between reset level Vrst1 and signal level Vsig1 corresponds to the net signal level after removing reset noise and offset noise from FD.

[0135] Figure 8 This is a timing diagram illustrating an example of a readout operation of the second pixel of pixel block 300 in the first embodiment of the present technology.

[0136] The vertical scanning circuit 211 supplies a high-level downstream reset signal rstb to the nth row from the pulse period starting at time T16 immediately following time T15.

[0137] Vertical scanning circuit 211 supplies a high-level selection signal Φr2 to the nth row from time T17 to time T18, immediately following the initialization of downstream node 360. The potential of downstream node 360 ​​becomes the reset level Vrst2. ADC 261 performs AD conversion on this reset level.

[0138] The vertical scanning circuit 211 supplies a high-level downstream reset signal rstb to the nth row during a pulse period starting from time T19 immediately following time T18.

[0139] Vertical scanning circuit 211 supplies a high-level selection signal Φs2 to the nth row from time T20 to time T21 immediately following the initialization of downstream node 360. The potential of downstream node 360 ​​becomes the signal level Vsig2. ADC 261 performs AD conversion on this signal level.

[0140] Furthermore, at time T21, the vertical scan circuit 211 returns the FD reset signals rst1 and rst2 of the nth row, as well as the downstream selection signal selb, to a low level.

[0141] like Figure 7 and Figure 8 As shown, high-level selection signals Φr1, Φs1, Φr2, and Φs2 are supplied sequentially. Based on these selection signals, the selection unit 340 sequentially connects capacitor elements 331, 332, 336, and 337 to the downstream node 360. Then, the reset level Vrst1 and signal level Vsig1 of the first pixel of the pixel block 300, and the reset level Vrst2 and signal level Vsig2 of the second pixel are read sequentially.

[0142] Incidentally, the solid-state imaging element 200 reads the signal level after reading the reset level, but is not limited to this order. The solid-state imaging element 200 may also read the reset level after reading the signal level. In this case, the vertical scanning circuit 211 supplies the high-level selection signal Φr after supplying the high-level selection signal Φs. Furthermore, in this case, the slope of the ramp signal needs to be reversed.

[0143] Figure 9 This is a circuit diagram illustrating a construction example of a pixel in a comparative example. In this comparative example, the selection circuit 350 is not provided, and the transmission transistor is inserted between the upstream node 330 and the upstream circuit. Furthermore, capacitors C1 and C2 are inserted instead of capacitor elements 331 and 332. Capacitor C1 is inserted between the upstream node 330 and the ground terminal, and capacitor C2 is inserted between the upstream node 330 and the downstream node 360.

[0144] For example, in non-patent literature 1 Figure 5 Section 5.2 describes the pixel exposure control and readout control for this comparative example. In this comparative example, assuming the capacitance values ​​of capacitors C1 and C2 are each C, the level Vn of the kTC noise during exposure and readout is expressed by the following formula.

[0145] Vn = (3 * kT / C) 1 / 2 ... Equation 1

[0146] In the above formula, k is the Boltzmann constant, and its unit is, for example, joules per kelvin (J / K). T is the absolute temperature, and its unit is, for example, kelvin (K). Furthermore, the unit of Vn is, for example, volts (V), and the unit of C is, for example, farads (F).

[0147] Figure 10 This is a diagram illustrating an example of the state of a pixel block according to the first embodiment of the present technology when reading a reset level and when initializing a downstream node. In the figure, a represents the state of pixel block 300 when reading a reset level, and b represents the state of pixel block 300 when initializing a downstream node 360. Furthermore, in the figure, for ease of illustration, selection transistor 351, selection transistor 352, and downstream reset transistor 361 are represented by switch graphic symbols.

[0148] As shown in Figure a, the vertical scan circuit 211 sets the selection transistor 351 to a closed state and sets the selection transistor 352 and the downstream reset transistor 361 to an open state. Therefore, the reset level of the first pixel is read via the downstream circuit 370.

[0149] As shown in Figure b, after reading the reset level, the vertical scan circuit 211 sets select transistors 351 and 352 to the open-circuit state and sets the downstream reset transistor 361 to the closed-circuit state. Therefore, capacitors 331 and 332 are disconnected from the downstream node 360, and the level of the downstream node 360 ​​is initialized.

[0150] In this way, the capacitance value of the parasitic capacitance Cp at the downstream node 360, which is disconnected from capacitor elements 331 and 332, is set to be much smaller than the capacitance values ​​of capacitor elements 331 and 332. For example, assuming the parasitic capacitance Cp is a few femtofarads (fF), then capacitor elements 331 and 332 are approximately in the tens of femtofarads range.

[0151] Figure 11 This is a diagram illustrating an example of the state of pixel block 300 when the read signal level is in the first embodiment of this technology.

[0152] After the downstream node 360 ​​is initialized, the vertical scan circuit 211 sets the selection transistor 352 to a closed state and sets the selection transistor 351 and the downstream reset transistor 361 to an open state. Therefore, the signal level of the first pixel is read via the downstream circuit 370.

[0153] Here, we consider the kTC noise during pixel exposure. During exposure, kTC noise occurs in both the sample of the reset level and the sample of the signal level immediately preceding the end of exposure. Assuming the capacitance of each of capacitors 331 and 332 is C, the level Vn of the kTC noise during exposure is expressed by the following formula.

[0154] Vn = (2 * kT / C) 1 / 2 ... Equation 2

[0155] In addition, in such Figure 10 and Figure 11 During the read operation, downstream reset transistor 361 is driven, resulting in kTC noise. However, when downstream reset transistor 361 is driven, capacitors 331 and 332 are disconnected, and the parasitic capacitance Cp is very small. Therefore, the kTC noise during read operation is negligible compared to the kTC noise during exposure. Thus, the kTC noise during exposure and read operation is represented by Equation 2.

[0156] According to Equations 1 and 2, the kTC noise in pixel block 300 where the capacitor is disconnected during reading is less than the kTC noise in the comparison example where the capacitor is not disconnected during reading. Therefore, it is possible to improve the image quality of the image data.

[0157] Furthermore, since the two pixels in pixel block 300 share the downstream reset transistor 361 and downstream circuit 370, the circuit size of pixel array section 220 can be reduced compared to the case where the downstream reset transistor 361 and downstream circuit 370 are not shared. Incidentally, the number of pixels to be shared is not limited to two pixels. Three or more pixels may also share the downstream reset transistor 361 and downstream circuit 370.

[0158] Figure 12 This is a flowchart illustrating an operational example of the solid-state imaging element 200 according to a first embodiment of the present technology. For example, the operation begins when a predetermined application for imaging image data is performed.

[0159] The vertical scanning circuit 211 exposes all pixels (step S901). Then, the vertical scanning circuit 211 selects the row of pixel block 300 to be read (step S902). The column signal processing circuit 260 reads the reset level of the first pixel of the pixel block 300 in that row (step S903), and then reads the signal level of that pixel (step S904). Next, the column signal processing circuit 260 reads the reset level of the second pixel (step S905), and then reads the signal level of that pixel (step S906).

[0160] The solid-state imaging element 200 determines whether all rows have been read (step S907). If not all rows have been read (step S907: No), the solid-state imaging element 200 repeats step S902 and subsequent steps. On the other hand, if all rows have been read (step S907: Yes), the solid-state imaging element 200 performs CDS processing, etc., and ends the imaging operation. When multiple image data are captured continuously, steps S901 to S907 are repeatedly executed in sync with the vertical synchronization signal.

[0161] In this manner, in the first embodiment of this technology, when the selection circuit 350 disconnects capacitor elements 331 and 332 from the downstream node 360, the downstream reset transistor 361 initializes the downstream node 360. Since capacitor elements 331 and 332 are disconnected, the level of reset noise caused by the drive of the downstream reset transistor 361 becomes a level corresponding to a parasitic capacitance smaller than its own capacitance. This noise reduction can improve the image quality of the image data.

[0162] Furthermore, since the two pixels share the downstream reset transistor 361 and the downstream circuit 370, the circuit size of the pixel array section 220 can be reduced compared to the case where the downstream reset transistor 361 and the downstream circuit 370 are not shared.

[0163] [First Variation]

[0164] Although the solid-state imaging element 200 in the first embodiment reads the pixel signals of each of the two pixels of the pixel block 300 sequentially, there is a possibility of insufficient reading speed in this configuration. The solid-state imaging element 200 in the first variation of the first embodiment differs from the first embodiment in that it performs pixel addition.

[0165] Figure 13 This is a timing diagram illustrating an operational example of reading the reset level and signal level in a first variation of the first embodiment of the present invention. In the solid-state imaging element 200 of the first variation of the first embodiment, any of a plurality of modes are provided, including a non-additive mode that does not perform pixel addition and an additive mode that performs pixel addition. The global shutter operation and readout operation in the non-additive mode are similar to those in the first embodiment. The global shutter operation in the additive mode is similar to that in the non-additive mode.

[0166] As shown in the figure, when reading is performed in addition mode, during the pulse period at time T10 when reading the nth row begins, the vertical scan circuit 211 supplies high-level FD reset signals rst1 and rst2. Furthermore, during the reading period from time T10 to time T15, the vertical scan circuit 211 sets the downstream selection signal selb to a high level.

[0167] During the period from time T11 to time T12, immediately following time T10, the vertical scan circuit 211 supplies high-level selection signals Φr1 and Φr2 to the nth row. Therefore, the potential of the downstream node 360 ​​becomes the reset level Vrst. The reset level Vrst is a value obtained by adding the reset levels of the two pixels in the pixel block 300.

[0168] During the pulse period starting from time T13 immediately following time T12, the vertical scanning circuit 211 supplies a high-level downstream reset signal rstb to the nth row.

[0169] During the period from time T14 to time T15 immediately following the initialization of downstream node 360, the vertical scan circuit 211 supplies high-level selection signals Φs1 and Φs2 to the nth row. Therefore, the potential of downstream node 360 ​​becomes the signal level Vsig. The signal level Vsig is a value obtained by adding the signal levels of the two pixels in pixel block 300.

[0170] As shown in the figure, high-level selection signals Φr1 and Φr2 are supplied, and the selection unit 340 connects capacitor elements 331 and 336 to the downstream node 360 ​​according to these selection signals. In other words, capacitor elements 331 and 336 are short-circuited. Therefore, the reset levels of the two pixels are added together. Furthermore, high-level selection signals Φs1 and Φs2 are supplied, and the selection unit 340 connects capacitor elements 332 and 337 to the downstream node 360 ​​according to these selection signals. In other words, capacitor elements 332 and 337 are short-circuited. Therefore, the signal levels of the two pixels are added together. This pixel addition improves sensitivity and readout speed compared to the case where no addition is performed. Furthermore, pixel addition reduces the number of rows to be read, thus reducing power consumption.

[0171] Incidentally, the solid-state imaging element 200 reads the signal level after reading the reset level, but is not limited to this order, and may also read the reset level after reading the signal level.

[0172] In this way, according to a first variation of the first embodiment of the present technology, since the selection unit 340 connects capacitor elements 331 and 336 to the downstream node 360, and also connects capacitor elements 332 and 337 to the downstream node 360, the pixel signals of the two pixels can be added together. Therefore, compared with the case where no addition is performed, sensitivity and readout speed can be improved, and power consumption can be reduced.

[0173] [Second variation]

[0174] Although the circuitry of the solid-state imaging element 200 in the first embodiment described above is disposed on a single semiconductor chip, there is a possibility that the element is not suitable for the semiconductor chip when miniaturizing pixels in this manner. The solid-state imaging element 200 of the second variation of the first embodiment differs from that of the first embodiment in that the circuitry of the solid-state imaging element 200 is distributed across two semiconductor chips.

[0175] Figure 14 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element 200 according to a second variation of the first embodiment of the present invention. The solid-state imaging element 200 of the second variation of the first embodiment includes a lower pixel chip 202 and an upper pixel chip 201 stacked on the lower pixel chip 202. These chips are electrically connected via, for example, Cu-Cu bonding. Incidentally, in addition to Cu-Cu bonding, they can also be connected via vias or bumps.

[0176] The upper pixel array section 221 is arranged on the upper pixel chip 201. The lower pixel array section 222 and the column signal processing circuit 260 are arranged on the lower pixel chip 202. For each pixel in the pixel array section 220, a portion of it is arranged in the upper pixel array section 221, and the remainder is arranged in the lower pixel array section 222.

[0177] In addition, the vertical scanning circuit 211, timing control circuit 212, DAC 213, and load MOS circuit block 250 are also arranged on the lower pixel chip 202. These circuits are not shown in the figure.

[0178] Furthermore, the upper pixel chip 201 is manufactured, for example, using a pixel-specific process, and the lower pixel chip 202 is manufactured, for example, using a complementary MOS (CMOS) process. Incidentally, the upper pixel chip 201 is an example of the first chip described in claim 1, and the lower pixel chip 202 is an example of the second chip described in claim 2.

[0179] Figure 15 This is a circuit diagram illustrating a construction example of a pixel block 300 according to a second variation of the first embodiment of the present invention. In pixel block 300, upstream circuit block 305 is disposed on upper pixel chip 201, and other circuits and components (such as capacitor element 331 and capacitor element 332, etc.) are disposed on lower pixel chip 202. Incidentally, current source transistor 316 and current source transistor 326 may also be arranged on lower pixel chip 202. Since the components of pixel block 300 are distributed on the stacked upper pixel chip 201 and lower pixel chip 202 as shown, the pixel area can be reduced, and pixel miniaturization is facilitated.

[0180] In this way, since the circuitry and components of the pixel block 300 are distributed on two semiconductor chips of the second variant of the first embodiment of the present invention, pixel miniaturization is facilitated.

[0181] [Third variation]

[0182] In a second variation of the first embodiment described above, a portion of the pixel block 300 and peripheral circuitry (such as column signal processing circuitry 260) are disposed on the lower pixel chip 202. However, in this configuration, the area of ​​the circuitry and components on the lower pixel chip 202 side is larger than the area of ​​the peripheral circuitry on the upper pixel chip 201, thus creating the possibility of unnecessary space in the upper pixel chip 201 that does not contain circuitry and components. The solid-state imaging element 200 of the third variation of the first embodiment differs from the solid-state imaging element 200 of the second variation of the first embodiment in that the circuitry of the solid-state imaging element 200 is distributed across three semiconductor chips.

[0183] Figure 16 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element 200 according to a third variation of the first embodiment of the present invention. The solid-state imaging element 200 of the third variation of the first embodiment includes an upper pixel chip 201, a lower pixel chip 202, and a circuit chip 203. These chips are stacked and electrically connected, for example, by Cu-Cu bonding. Incidentally, in addition to Cu-Cu bonding, the connection can be made by vias or bumps.

[0184] The upper pixel array section 221 is arranged on the upper pixel chip 201. The lower pixel array section 222 is arranged on the lower pixel chip 202. For each pixel of the pixel array section 220, a portion is arranged in the upper pixel array section 221, and the remainder is arranged in the lower pixel array section 222.

[0185] In addition, column signal processing circuit 260, vertical scanning circuit 211, timing control circuit 212, DAC 213, and load MOS circuit block 250 are arranged on circuit chip 203. Circuits other than column signal processing circuit 260 are not shown in the figure.

[0186] Incidentally, the upper pixel chip 201 is an example of the first chip as claimed in the claim, and the lower pixel chip 202 is an example of the second chip as claimed in the claim. The circuit chip 203 is an example of the third chip as claimed in the claim.

[0187] Because of the three-layer configuration shown in the figure, unnecessary space can be reduced and pixels can be further miniaturized compared to a two-layer configuration. Furthermore, the lower pixel chip 204 of the second layer can be manufactured using a dedicated process for capacitors or switches.

[0188] In this way, since the circuitry of the solid-state imaging element 200 is distributed across the three semiconductor chips of the third variation of the first embodiment of the present technology, the pixels can be further miniaturized compared to the case where the circuitry is distributed across two semiconductor chips.

[0189] <2. Second Implementation Plan>

[0190] Although the solid-state imaging element 200 in the first embodiment reads the pixel signals of each of the two pixels of the pixel block 300 sequentially, there is a possibility of insufficient readout speed in this configuration. The solid-state imaging element 200 in the second embodiment differs from that in the first embodiment in that it performs pixel addition.

[0191] Figure 17This is a plan view illustrating a construction example of the pixel array section 220 according to the second embodiment of the present technology. In this figure, a is a plan view showing an example of the pixel array section 220 in a Bayer array. In this figure, b is a plan view showing an example of the pixel array section 220 in a Quadra-Bayer array.

[0192] As shown in Figure a, red (R), green (G), and blue (B) pixels are arranged in the Bayer array of the pixel array section 220 in the second embodiment. The solid-state imaging element 200 can add the pixel signals of R pixel 301 and its neighboring R pixels 302 to 304. Similarly, for G and B pixels, the solid-state imaging element 200 can add the individual pixel signals of four adjacent pixels.

[0193] Incidentally, instead of a Bayer array, the pixels can be arranged in a Quadra-Bayer array as shown in Figure b. In a Quadra-Bayer array, four pixels of the same color are arranged adjacent to each other in a 2x2 row. Then, focusing on the four R pixels, four B pixels are arranged to the lower right of the R pixels, and four G pixels are arranged to the right and lower side of the R pixels. The solid-state imaging element 200 can add the pixel signals of four adjacent pixels of the same color (pixels 301 to 304, etc.) among these pixels.

[0194] Incidentally, the pixel array is not limited to Bayer or Quadra-Bayer arrays. For example, R, G, B, and W (white) pixels can also be arranged.

[0195] Figure 18 This is a circuit diagram illustrating a construction example of pixel block 300 according to a second embodiment of the present technology. In pixel block 300 of the second embodiment, four pixels are arranged to be added during pixel addition. For example, Figure 17 Pixels 301 to 304 are arranged in pixel block 300.

[0196] The pixel block 300 in the second embodiment further includes capacitor elements 431, 432, 436, and 437, a short-circuit transistor 480, a downstream reset transistor 461, and a downstream circuit 470. Furthermore, in the second embodiment, upstream circuits 410 and 420 are further arranged in upstream circuit block 305, and selection circuits 450 and 455 are further arranged in selection section 340. Vertical scanning circuit 211 supplies downstream reset signal rstb1 to downstream reset transistor 361 and downstream reset signal rstb2 to downstream reset transistor 461.

[0197] In downstream circuit 470, downstream amplification transistor 471 and downstream selection transistor 472 are arranged. For example, nMOS transistors are used as these transistors. Furthermore, the circuit configuration of downstream reset transistor 461 and downstream circuit 470 is similar to that of downstream reset transistor 361 and downstream circuit 370. Downstream circuits 370 and 470 are connected to the same vertical signal line 309. Vertical scan circuit 211 supplies downstream selection signal selb1 to downstream selection transistor 372 and downstream selection signal selb2 to downstream selection transistor 472.

[0198] Upstream circuit 410 sequentially generates a reset level and a signal level, and maintains capacitor elements 431 and 432 at the reset and signal levels, respectively. Upstream circuit 420 sequentially generates a reset level and a signal level, and maintains capacitor elements 436 and 437 at the reset and signal levels, respectively. Incidentally, capacitor elements 431 and 432 are examples of the fifth and sixth capacitor elements as described in claims, and capacitor elements 436 and 437 are examples of the seventh and eighth capacitor elements as described in claims.

[0199] Furthermore, selection circuit 450 connects either capacitor element 431 or capacitor element 432 to downstream node 460, and selection circuit 455 connects either capacitor element 436 or capacitor element 437 to downstream node 460. Incidentally, selection circuit 450 is an example of the third selection circuit as claimed in claim 1, and selection circuit 455 is an example of the fourth selection circuit as claimed in claim 2. Furthermore, downstream node 360 ​​is an example of the first downstream node as claimed in claim 3, and downstream node 460 is an example of the second downstream node as claimed in claim 4.

[0200] The short-circuit transistor 480 opens and closes the path between downstream nodes 360 and 460 according to the short-circuit signal sht from the vertical scan circuit 211. For example, an nMOS transistor is used as the short-circuit transistor 480.

[0201] Figure 19 This is a circuit diagram illustrating an example of the construction of upstream circuits 410 and 420, as well as selection circuits 450 and 455, in the second embodiment of the present technology.

[0202] The upstream circuit 410 includes a photoelectric conversion element 411, a transmission transistor 412, an FD reset transistor 413, an FD 414, an upstream amplification transistor 415, and a current source transistor 416. The vertical scanning circuit 211 supplies the transmission signal trg3 and the FD reset signal rst3 to the transmission transistor 412 and the FD reset transistor 413.

[0203] In addition, the upstream circuit 420 includes a photoelectric conversion element 421, a transmission transistor 422, an FD reset transistor 423, an FD 424, an upstream amplification transistor 425, and a current source transistor 426. The vertical scanning circuit 211 supplies the transmission signal trg4 and the FD reset signal rst4 to the transmission transistor 422 and the FD reset transistor 423.

[0204] Selection circuit 450 includes selection transistors 451 and 452, and selection circuit 455 includes selection transistors 456 and 457. Vertical scanning circuit 211 supplies selection signals Φr3 and Φs3 to selection transistors 451 and 452, and selection signals Φr4 and Φs4 to selection transistors 456 and 457.

[0205] The circuit configurations of upstream circuits 410 and 420 are similar to those of upstream circuits 310 and 320. Furthermore, the circuit configurations of selection circuits 450 and 455 are similar to those of selection circuits 350 and 355.

[0206] Figure 20 This is a timing diagram illustrating an example of the readout operation of the first and second pixels of the pixel block 300 in the second embodiment of the present invention. The solid-state imaging element 200 of the second embodiment is provided with any of a variety of modes, including a non-additive mode that does not perform pixel addition and an additive mode that performs pixel addition. The global shutter operation and readout operation in the non-additive mode are similar to those in the first embodiment. The global shutter operation in the additive mode is similar to that in the non-additive mode.

[0207] In non-additive mode, the vertical scan circuit 211 sets the short-circuit signal sht to a low level. Furthermore, at time T10, when reading the nth row of pixel block 300 begins, the vertical scan circuit 211 sets the FD reset signals rst1 to rst4 to a high level. Additionally, from time T10 to time T18, the vertical scan circuit 211 sets the downstream selection signal selb1 to a high level and the downstream selection signal selb2 to a low level.

[0208] Furthermore, during the pulse period from time T10 to time T11, the vertical scanning circuit 211 supplies a high-level downstream reset signal rstb1, and during the period from time T11 to time T12, it supplies a high-level selection signal Φr1. During this period, the reset level Vrst1 of the first pixel is read via the vertical signal line 309.

[0209] During the pulse cycle from time T12 to time T13, the vertical scan circuit 211 supplies a high-level downstream reset signal rstb1, and during the period from time T13 to time T14, it supplies a high-level selection signal Φs1. During this period, the signal level Vsig1 of the first pixel is read via the vertical signal line 309.

[0210] Next, the vertical scanning circuit 211 supplies a high-level downstream reset signal rstb1 during the pulse cycle from time T14 to time T15, and a high-level selection signal Φr2 during the period from time T15 to time T16. During this period, the reset level Vrst2 of the second pixel is read via the vertical signal line 309.

[0211] The vertical scanning circuit 211 supplies a high-level downstream reset signal rstb1 during the pulse cycle from time T16 to time T17, and a high-level selection signal Φs2 during the period from time T17 to time T18. During this period, the signal level Vsig2 of the second pixel is read via the vertical signal line 309.

[0212] Figure 21 This is a timing diagram illustrating an example of the readout operation of the third and fourth pixels of pixel block 300 in the second embodiment of the present technology.

[0213] The vertical scanning circuit 211 sets the downstream selection signal selb1 to low and the downstream selection signal selb2 to high during the period from time T18 to time T26.

[0214] Furthermore, the vertical scanning circuit 211 provides a high-level downstream reset signal rstb2 during the pulse period from time T18 to time T19, and a high-level selection signal Φr3 during the period from time T19 to time T20. During this period, the reset level Vrst3 of the third pixel is read via the vertical signal line 309.

[0215] The vertical scanning circuit 211 supplies a high-level downstream reset signal rstb2 during the pulse cycle from time T20 to time T21, and a high-level selection signal Φs3 during the period from time T21 to time T22. During this period, the signal level Vsig3 of the third pixel is read via the vertical signal line 309.

[0216] Next, the vertical scanning circuit 211 supplies a high-level downstream reset signal rstb2 during the pulse cycle from time T22 to time T23, and a high-level selection signal Φr4 during the period from time T23 to time T24. During this period, the reset level Vrst4 of the fourth pixel is read via the vertical signal line 309.

[0217] The vertical scanning circuit 211 supplies a high-level downstream reset signal rstb2 during the pulse cycle from time T24 to time T25, and a high-level selection signal Φs4 during the period from time T25 to time T26. During this period, the signal level Vsig4 of the fourth pixel is read via the vertical signal line 309.

[0218] In addition, the vertical scanning circuit 211 sets the FD reset signals rst1 to rst4 to low level at the time T26 when the reading of the nth row ends.

[0219] like Figure 20 and Figure 21 As shown, short-circuit transistor 480 is controlled to be in an open-circuit state in non-additive mode. Furthermore, capacitors 331 and 332 are sequentially connected to downstream node 360, and the reset level and signal level of the first pixel are read sequentially. Capacitors 336 and 337 are sequentially connected to downstream node 360, and the reset level and signal level of the second pixel are read sequentially. Next, capacitors 431 and 432 are sequentially connected to downstream node 460, and the reset and signal levels of the third pixel are read sequentially. Capacitors 436 and 437 are sequentially connected to downstream node 460, and the reset and signal levels of the fourth pixel are read sequentially. In this way, the reset and signal levels of each of the four pixels in pixel block 300 are read sequentially.

[0220] Figure 22 This is a timing diagram illustrating an example of a read operation in the addition mode of the second embodiment of the present technology. In addition mode, the vertical scan circuit 211 sets the short-circuit signal sht to a high level. During the period from time T10 to time T14 when the nth row of pixel block 300 is read, the vertical scan circuit 211 sets the FD reset signals rst1 to rst4, as well as the downstream selection signals selb1 and selb2, to a high level.

[0221] Furthermore, during the pulse cycle from time T10 to time T11, the vertical scan circuit 211 supplies high-level downstream reset signals rstb1 and rstb2, and during the period from time T11 to time T12, it supplies high-level selection signals Φr1 to Φr4. During this period, the reset level Vrst is read via the vertical signal line 309. The reset level Vrst is a value obtained by adding the reset levels of the four pixels of the pixel block 300.

[0222] Next, during the pulse cycle from time T12 to time T13, the vertical scan circuit 211 supplies high-level downstream reset signals rstb1 and rstb2, and during the period from time T13 to time T14, supplies high-level selection signals Φs1 to Φs4. During this period, the signal level Vsig is read via the vertical signal line 309. The signal level Vsig is a value obtained by adding the signal levels of the four pixels of the pixel block 300.

[0223] Here, by increasing the number of pixels in the shared downstream circuit 370 to four in the pixel block 300 of the first embodiment, four pixels can be added together. However, increasing the number of pixels in the shared downstream circuit 370 leads to adverse effects. When the number of pixels in the shared downstream circuit 370 is four, the wiring of the downstream node 360 ​​extends across four pixels, increasing the parasitic capacitance of the downstream node 360. Due to the increase in parasitic capacitance, the signal gain is reduced when pixel addition is not performed. This is because when connected to the downstream node 360, the parasitic capacitance reduces the voltage held in capacitor elements 331 and 332. This reduction in gain results in a decrease in the signal-to-noise (SN) ratio.

[0224] On the other hand, in the second embodiment with short-circuit transistor 480, by keeping short-circuit transistor 480 in an open-circuit state in non-addition mode, the number of pixels sharing downstream circuit 370 and each of downstream circuit 470 can be set to two pixels. Therefore, compared to the case where four pixels share downstream circuit 370, the increase in parasitic capacitance of downstream nodes can be suppressed. Using this configuration, pixel addition of two or more pixels can be achieved while suppressing the decrease in the SN ratio in non-addition mode.

[0225] Incidentally, Figure 18 The downstream circuits 370 and 470 of the pixel block 300 shown share a single vertical signal line 309, but the invention is not limited to this configuration. Vertical signal lines 309-1 and 309-2 can also be arranged, with downstream circuit 370 connected to vertical signal line 309-1 and downstream circuit 470 connected to vertical signal line 309-2. In this case, the number of downstream load MOS transistors 251 and ADC 261 needs to be doubled according to the number of vertical signal lines. Instead, in non-additive mode, one of the two pixels sharing downstream circuit 370 and one of the two pixels sharing downstream circuit 470 can be read simultaneously, thus improving readout speed. Furthermore, in additive mode, only one of vertical signal lines 309-1 and 309-2 is used, and the load MOS transistor 251 corresponding to the other is controlled to be in an off state.

[0226] Incidentally, the first to third variations of the first implementation scheme can also be applied to the second implementation scheme.

[0227] In this way, since the downstream node 360 ​​is short-circuited by the short-circuit transistor 480 according to the second embodiment of the present invention, the pixel block 300 is able to add the pixel signals of the four pixels respectively. Therefore, compared with not performing the addition, sensitivity and readout speed can be improved, and power consumption can be reduced.

[0228] <3. Third Implementation Plan>

[0229] Although the first embodiment described above arranges current source transistors (316 and 326) for each pixel, there is a possibility that pixel miniaturization becomes difficult in this configuration. The solid-state imaging element 200 of the third embodiment differs from the first embodiment in that multiple pixels share a current source transistor.

[0230] Figure 23 This is a circuit diagram illustrating a construction example of pixel block 300 according to a third embodiment of the present technology. The pixel block 300 of the third embodiment differs from that of the first embodiment in that it further includes upstream selection transistors 317 and 327, and does not include current source transistor 316.

[0231] Upstream selection transistor 317 outputs the voltage amplified by upstream amplification transistor 315 to upstream node 338 based on the upstream selection signal sel1 from vertical scan circuit 211. Upstream selection transistor 327 outputs the voltage amplified by upstream amplification transistor 325 to upstream node 338 based on the upstream selection signal sel2 from vertical scan circuit 211. Furthermore, current source transistor 326 is connected to upstream node 338.

[0232] Furthermore, capacitor elements 331, 332, 336, and 337 share a common end connected to upstream node 339 and another end connected to selection circuits 350 and 355. Upstream node 339 is connected to upstream node 338.

[0233] Furthermore, the circuitry and components of the solid-state imaging element 200 are distributed across the upper pixel chip 201 and the lower pixel chip 202. For example, upstream circuitry 310 and upstream circuitry 320 are arranged on the upper pixel chip 201, and downstream circuitry is arranged on the lower pixel chip 202. Additionally, upstream nodes 338 and 339 are connected via Cu-Cu connections or similar means.

[0234] In the first embodiment where current source transistors are arranged for each pixel, when forming a stacked structure, it is necessary to... Figure 15 The diagram shows Cu-Cu connections between individual pixels. Specifically, when capacitor elements 331 with MIM structures are arranged on the lower pixel chip 202, the chip thickness increases, and the surface connecting the upper and lower chips becomes difficult to planarize, thus limiting the spacing of the Cu-Cu connections. For example, the Cu-Cu connection spacing is a few micrometers (μm), while the size of fine pixels in a moving image sensor is less than a micrometer (μm). Therefore, miniaturization becomes difficult in a structure that arranges current source transistors for each pixel.

[0235] On the other hand, in the configuration where the current source transistor 326 is shared by two pixels, the number of Cu-Cu connections can be reduced. This facilitates pixel miniaturization. Furthermore, it reduces the current during global shutter operation. Additionally, the current source transistor 326 is typically constructed in a cascaded configuration to suppress current variations caused by the channel length modulation effect of the transistor. Since the relatively large current source transistor 326 is shared, the transistor area can be reduced.

[0236] Incidentally, the current source transistor 326 is shared by two pixels, but the number of pixels that are shared is not limited to two pixels and can be more than three pixels.

[0237] Figure 24 This is a timing diagram illustrating an example of global shutter operation in the third embodiment of this technology. From moment T0 immediately before the start of exposure to moment T1 at the end of the pulse period, the vertical scan circuit 211 supplies high-level FD reset signals rst1 and rst2, as well as high-level transmission signals trg1 and trg2, to all rows. Therefore, all pixels are reset by the PD, and exposure begins simultaneously in all rows.

[0238] During the period from time T2 immediately preceding the end of exposure to time T5, the vertical scan circuit 211 sets the upstream selection signal sel1 of all rows to a high level. At time T3 within this period, in all rows, the vertical scan circuit 211 supplies a high-level FD reset signal rst1 within a pulse period, while simultaneously setting the downstream reset signal rstb and the selection signal Φr1 to a high level. Therefore, the first pixel of pixel block 300 undergoes FD reset, and the reset level is sampled and held.

[0239] At time T4, the vertical scan circuit 211 returns the selection signal Φr1 to a low level. Furthermore, from time T5 to time T8, the vertical scan circuit 211 sets the upstream selection signal sel1 of all rows to a low level and sets the upstream selection signal sel2 to a high level. At time T6 during this period, the vertical scan circuit 211 supplies a high-level FD reset signal rst2 within the pulse period, while simultaneously setting the downstream reset signal rstb and the selection signal Φr2 of all rows to a high level. Therefore, the second pixel of pixel block 300 undergoes FD reset, and the reset level is sampled and held.

[0240] Then, at time T7, the vertical scanning circuit 211 returns the selection signal Φr2 of all rows to a low level, sets the upstream selection signal sel2 to a low level, and sets the upstream selection signal sel1 to a high level at time T8.

[0241] Here, sel1_[n] and sel2_[n] in the figure represent the signals up to the nth row of pixels.

[0242] As shown in the figure, immediately before the end of exposure, the vertical scan circuit 211 sequentially sets the upstream selection transistor 317 and the upstream selection transistor 327 to the closed state. Then, when the upstream selection transistor 317 is in the closed state, the FD reset transistor 313 performs an FD reset, and when the upstream selection transistor 327 is in the closed state, the FD reset transistor 323 performs an FD reset.

[0243] Figure 25 This is a timing diagram illustrating a control example of the third embodiment of the present technology immediately following the end of exposure. At the end of exposure time T9, the vertical scan circuit 211 provides high-level transmission signals trg1 and trg2 for a pulse period in all rows.

[0244] Then, during the period from time T10 to time T11, the vertical scan circuit 211 sets the selection signal Φs1 to a high level in all rows. Therefore, the signal level of the first pixel of the pixel block 300 is sampled and held.

[0245] At time T12, the vertical scan circuit 211 sets the upstream selection signal sel1 of all rows to low level and sets the upstream selection signal sel2 to high level.

[0246] Then, during the period from time T13 to time T14, the vertical scan circuit 211 sets the selection signal Φs2 to a high level in all rows. Therefore, the signal level of the second pixel of pixel block 300 is sampled and held.

[0247] At time T15, the vertical scanning circuit 211 returns the upstream selection signal sel2 of all rows to a low level.

[0248] As shown in the figure, at the end of exposure, the vertical scanning circuit 211 sequentially sets the upstream selection transistor 317 and the upstream selection transistor 327 to the closed state. Then, at the end of exposure, the vertical scanning circuit 211 enables the transfer transistor 312 and the transfer transistor 322 to transfer charge, and then sequentially sets the upstream selection transistor 317 and the upstream selection transistor 327 to the closed state.

[0249] Incidentally, the first and third variations of the first implementation scheme and the second implementation scheme can be applied to the third implementation scheme.

[0250] In this way, since the two pixels according to the third embodiment of the present technology share the current source transistor 326, the number of Cu-Cu connections between chips can be reduced. Therefore, pixel miniaturization is facilitated.

[0251] <4. Fourth Implementation Plan>

[0252] Although a pair of capacitors is arranged for each pixel in the first embodiment described above, miniaturization of the pixels is difficult in this configuration. The solid-state imaging element 200 of the fourth embodiment differs from the first embodiment in that the number of capacitors is reduced.

[0253] Figure 26 This is a circuit diagram illustrating a construction example of pixel block 300 according to the fourth embodiment of the present technology. In pixel block 300 of the fourth embodiment, an upstream circuit block 305, capacitor elements 331 and 332, capacitor elements 531, 532 and 533, a selection unit 340, a downstream reset transistor 361, and a downstream circuit 370 are arranged. In pixel block 300 of the fourth embodiment, four pixels are arranged. For example, pixel block 300 is arranged with… Figure 17 Pixels 301 to 304.

[0254] Upstream circuit block 305 includes photoelectric conversion elements 311, 512, and 513, a transfer transistor 312, and transfer transistors 514, 515, and 516. Furthermore, upstream circuit block 305 includes FD reset transistors 313 and FD 314, upstream amplification transistor 315, and current source transistor 316. For example, nMOS transistors are used as transfer transistors 312, 514, 515, and 516.

[0255] Furthermore, the selection unit 340 includes selection transistors 351 and 352, as well as selection transistors 551, 552, and 553. For example, nMOS transistors are used as selection transistors 551, 552, and 553.

[0256] The connection configuration of the photoelectric conversion element 311, transmission transistor 312, FD reset transistor 313, FD 314, upstream amplification transistor 315, and current source transistor 316 in the fourth embodiment is similar to that in the first embodiment. However, the FD reset signal rst from the vertical scanning circuit 211 is input to the FD reset transistor 313.

[0257] Photoelectric conversion elements 511 to 513 generate charge through photoelectric conversion. Transfer transistor 514 transfers charge from photoelectric conversion element 511 to FD 314 according to the transfer signal trg2 from the vertical scanning circuit 211. Transfer transistor 515 transfers charge from photoelectric conversion element 512 to FD 314 according to the transfer signal trg3 from the vertical scanning circuit 211. Transfer transistor 516 transfers charge from photoelectric conversion element 513 to FD 314 according to the transfer signal trg4 from the vertical scanning circuit 211.

[0258] The connection configuration between capacitor elements 331 and 332, and between selection transistors 351 and 352 in the fourth embodiment is similar to that in the first embodiment. However, a selection signal Φr from the vertical scanning circuit 211 is input to selection transistor 351.

[0259] Capacitor elements 531, 532 and 533 have one end that is connected to the upstream node 330 and the other end that is connected to the selection unit 340.

[0260] Selector transistor 551 opens and closes the path between capacitor element 531 and downstream node 360 ​​according to the select signal Φs2 from vertical scan circuit 211. Selector transistor 552 opens and closes the path between capacitor element 532 and downstream node 360 ​​according to the select signal Φs3 from vertical scan circuit 211. Selector transistor 553 opens and closes the path between capacitor element 533 and downstream node 360 ​​according to the select signal Φs4 from vertical scan circuit 211.

[0261] The circuit construction of the downstream reset transistor 361 and the downstream circuit 370 in the fourth embodiment is similar to that in the first embodiment.

[0262] Furthermore, the circuitry and components of the solid-state imaging element 200 are distributed across the upper pixel chip 201 and the lower pixel chip 202. For example, the upstream circuit block 305 is disposed on the upper pixel chip 201, and its downstream circuitry is disposed on the lower pixel chip 202.

[0263] like Figure 26 As shown, the four pixels share a single FD 314, downstream reset transistor 361, and downstream circuit 370. Furthermore, the reset level of the four pixels is maintained in capacitor element 331, and the signal levels of the four pixels are maintained in capacitor elements 332, 531, 532, and 533, respectively. Although in the first embodiment, capacitors configured to maintain the reset level need to be arranged for each pixel, in the fourth embodiment, since the capacitors are shared by the four pixels, the number of capacitors can be reduced. Therefore, pixel miniaturization is facilitated compared to the case where capacitors are not shared.

[0264] Incidentally, FD 314, etc., is shared by four pixels, but the number of shared pixels is not limited to four. Furthermore, capacitor elements 331 and 332 are examples of the first and second capacitor elements as described in the claims. Capacitor elements 531, 532, and 533 are examples of the third capacitor element as described in the claims.

[0265] Figure 27 This is a timing diagram illustrating an example of global shutter operation according to the fourth embodiment of the present technology. During the period from exposure start time T0 to time T4, the vertical scan circuit 211 supplies a high-level FD reset signal rst to all rows. At times T0, T1, T2, and T3 within this period, the vertical scan circuit 211 supplies transmission signals trg1, trg2, trg3, and trg4 to all rows within a pulse period. Therefore, all pixels undergo PD reset.

[0266] Then, during the period from the end of exposure T5 to T15, the vertical scan circuit 211 supplies a high-level downstream reset signal rstb to all rows. Furthermore, at time T5, the vertical scan circuit 211 supplies an FD reset signal rst to all rows within a pulse period. Immediately following time T5, at time T6, the vertical scan circuit 211 supplies a selection signal Φr to all rows within a pulse period. Therefore, all rows are FD reset.

[0267] Furthermore, at time T7, the vertical scanning circuit 211 supplies a transmission signal trg1 to all rows within a pulse period. Immediately following time T7, at time T8, the vertical scanning circuit 211 supplies a selection signal Φs1 to all rows within a pulse period. Therefore, the signal level of the first pixel of pixel block 300 is sampled and maintained.

[0268] Furthermore, at time T9, the vertical scanning circuit 211 supplies a transmission signal trg2 to all rows within a pulse period. Immediately following time T9, at time T10, the vertical scanning circuit 211 supplies a selection signal Φs2 to all rows within a pulse period. Therefore, the sum of the signal levels of the first and second pixels of pixel block 300 is sampled and held.

[0269] Furthermore, at time T11, the vertical scanning circuit 211 supplies the transmission signal trg3 to all rows within a pulse period. Immediately following time T11, at time T12, the vertical scanning circuit 211 supplies the selection signal Φs3 to all rows within a pulse period. Therefore, the sum of the signal levels of the first to third pixels of the pixel block 300 is sampled and held.

[0270] Furthermore, at time T13, the vertical scanning circuit 211 supplies the transmission signal trg4 to all rows within a pulse period. Immediately following time T13, at time T14, the vertical scanning circuit 211 supplies the selection signal Φs4 to all rows within a pulse period. Therefore, the sum of the signal levels of the first to fourth pixels of the pixel block 300 is sampled and held.

[0271] Here, rst_[n] and Φr_[n] represent the signals for the nth row of pixels in the N rows.

[0272] Since FD 314 is shared by four pixels in the fourth embodiment, it is not possible to perform charge transfer among the four pixels simultaneously as shown in the figure. However, the four capacitors (capacitor elements 332, 531, 532, and 533) that serve as the destination for charge transfer can be sampled on the order of a few microseconds (μs), and the difference in exposure time between pixels will not become too large.

[0273] Figure 28 This is a timing diagram illustrating an operational example of reading the reset level and signal level in the fourth embodiment of this technology.

[0274] During the period from time T20 to time T26 when the nth line is read, the vertical scan circuit 211 sets the FD reset signal rst to a high level.

[0275] Furthermore, at time T20, the vertical scan circuit 211 supplies a high-level downstream reset signal rstb to the nth row within a pulse period. Then, at time T21, immediately following time T20, the vertical scan circuit 211 supplies a high-level selection signal Φr to the nth row within a pulse period. Immediately following this control, the reset level shared by the four pixels is read via the vertical signal line 309.

[0276] Then, at time T22 after reading the reset level, the vertical scan circuit 211 supplies a high-level selection signal Φs1 to the nth row within a pulse period. Immediately following this control, the signal level Vsig1 of the first pixel is read via the vertical signal line 309. The column signal processing circuit 260 obtains the difference between the reset level Vrst and the signal level Vsig1 as the net signal level of the first pixel after CDS processing.

[0277] Then, at time T23 after reading signal level Vsig1, the vertical scan circuit 211 supplies a high-level selection signal Φs2 to the nth row within a pulse period. Immediately following this control, Vsig2 is read via vertical signal line 309. This Vsig2 corresponds to the sum of the signal levels of the first and second pixels. The column signal processing circuit 260 obtains the difference between Vsig1 and Vsig2 as the signal level of the second pixel after CDS processing.

[0278] Then, at time T24 after reading Vsig2, the vertical scan circuit 211 supplies a high-level selection signal Φs3 to the nth row within a pulse period. Immediately following this control, Vsig3 is read via the vertical signal line 309. This Vsig3 corresponds to the sum of the signal levels of the first to the third pixel. The column signal processing circuit 260 obtains the difference between Vsig2 and Vsig3 as the signal level of the third pixel after CDS processing.

[0279] Then, at time T25 after reading Vsig3, the vertical scan circuit 211 supplies a high-level selection signal Φs4 to the nth row within a pulse period. Immediately following this control, Vsig4 is read via the vertical signal line 309. This Vsig4 corresponds to the sum of the signal levels of the first to fourth pixels. The column signal processing circuit 260 obtains the difference between Vsig3 and Vsig4 as the signal level of the fourth pixel after CDS processing.

[0280] Incidentally, the third variation of the first implementation scheme can also be applied to the fourth implementation scheme.

[0281] In this way, since the capacitor element 331 that maintains the reset level in the fourth embodiment of this technology is shared by four pixels, it is easier to miniaturize pixels compared to the case where the capacitor element is not shared.

[0282] <5. Application Examples for Moving Bodies>

[0283] The technology according to the present invention (the technology) can be applied to various products. For example, the technology according to embodiments of the present invention can be implemented as a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, robots, etc.

[0284] Figure 29 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present invention can be applied.

[0285] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 29 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / visual output unit 12052, and an in-vehicle network interface (I / F) 12053, which are functional components of the integrated control unit 12050, are shown.

[0286] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 is used as a control device for devices such as internal combustion engines, drive motors, etc., which generate drive force for the vehicle, drive force transmission mechanisms that transmit drive force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate vehicle braking force.

[0287] The body system control unit 12020 controls the operation of various types of devices installed on the vehicle body according to various types of programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, reversing lights, brake lights, turn signals, and fog lights. In this case, radio waves or signals from various switches sent from a keyless entry device can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signal inputs and controls the vehicle's door locks, power windows, or lights, etc.

[0288] The exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to image an image of the exterior of the vehicle and receives the image. Based on the received image, the exterior information detection unit 12030 can perform processing such as detecting objects like people, vehicles, obstacles, signs, characters on the road surface, or detecting the distance to these objects.

[0289] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or it can output the electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0290] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0291] The microcomputer 12051 can calculate control target values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, following distance-based driving, speed maintenance driving, vehicle collision warning, and lane departure warning.

[0292] Furthermore, by controlling the driving force generation device, steering mechanism, braking device, etc., based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control aimed at achieving autonomous driving, etc., which enables the vehicle to drive autonomously without relying on the driver's operation.

[0293] Furthermore, based on information about the vehicle's exterior obtained by the exterior information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, the microcomputer 12051 can, for instance, perform coordinated control aimed at preventing glare by controlling the headlights to switch from high beam to low beam, based on the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030.

[0294] The sound and image output unit 12052 sends an output signal of at least one of sound or image to an output device capable of visually or audibly notifying passengers of the vehicle or external to the vehicle. Figure 29 In the example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. Display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0295] Figure 30 This is a diagram showing an example of the mounting position of the imaging unit 12031.

[0296] exist Figure 30 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0297] Imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, and rear door of the vehicle 12100, and on the upper part of the windshield inside the vehicle. Imaging unit 12101 on the front nose and imaging unit 12105 on the upper part of the windshield inside the vehicle primarily acquire images of the front of the vehicle 12100. Imaging units 12102 and 12103 on the side mirrors primarily acquire images of the sides of the vehicle 12100. Imaging unit 12104 on the rear bumper or rear door primarily acquires images of the rear of the vehicle 12100. Imaging unit 12105 on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0298] Incidentally, Figure 30An example of the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located on the rear bumper or rear cover. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by overlaying image data captured by imaging units 12101 to 12104.

[0299] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0300] For example, based on distance information acquired from imaging units 12101 to 12104, microcomputer 12051 can determine the distances of various three-dimensional objects within imaging ranges 12111 to 12114 and the time-varying distances (relative speeds relative to vehicle 12100), and thereby extract the closest three-dimensional object, particularly on the driving path of vehicle 12100, traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in approximately the same direction as vehicle 12100, as the vehicle ahead. Furthermore, microcomputer 12051 can preset the following distance to the vehicle ahead and perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, it is possible to perform cooperative control such as autonomous driving, which aims to enable the vehicle to drive automatically without relying on driver operation.

[0301] For example, based on distance information acquired from imaging units 12101 to 12104, microcomputer 12501 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 classifies obstacles around vehicle 12100 into obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, microcomputer 12051 determines the collision risk to indicate the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is therefore a possibility of collision, microcomputer 12051 issues a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering through drive system control unit 12010. Microcomputer 12051 can thus assist driving to avoid collision.

[0302] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. The microcomputer 12051 can identify a pedestrian, for example, by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by: extracting feature points from the images captured by the imaging units 12101 to 12104 (which are infrared cameras); and performing pattern matching processing on a series of feature points representing object outlines to determine whether it is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The audio-visual output unit 12052 can also control the display unit 12062 to display icons or the like representing the pedestrian at desired locations.

[0303] Examples of vehicle control systems to which the technology according to the present invention can be applied have been described above. The technology according to the present invention can be applied to the imaging unit 12031 in the above-described configuration. Specifically, for example, Figure 1 The imaging device 100 can be applied to the imaging unit 12031. When the technology according to the present invention is applied to the imaging unit 12031, kTC noise can be reduced and an easier-to-view imaging image can be obtained, thereby reducing driver fatigue.

[0304] Incidentally, the above embodiments illustrate examples for implementing this technology, and the content of each embodiment corresponds to the content of the invention specified in the claims. Similarly, the content of the invention specified in the claims corresponds to the content with the same name in the embodiments of this technology. However, this technology is not limited to the embodiments and can be implemented by various modifications to the embodiments without departing from its spirit.

[0305] Incidentally, the effects described in this specification are merely illustrative and not limiting, and other effects may exist.

[0306] Incidentally, this technology can also have the following construction.

[0307] (1) A solid-state imaging element, comprising:

[0308] A predetermined number of capacitor components;

[0309] An upstream circuit block generates a predetermined reset level and each of a plurality of signal levels corresponding to the exposure amount, and maintains the reset level and the plurality of signal levels by the different capacitive elements;

[0310] The selection unit sequentially executes: control to connect the capacitor element that maintains the reset level among the predetermined number of capacitor elements to a predetermined downstream node, control to disconnect the predetermined number of capacitor elements from the downstream node, and control to connect the capacitor element that maintains any of the plurality of signal levels among the predetermined number of capacitor elements to the downstream node.

[0311] A downstream reset transistor initializes the voltage level of the downstream node when the predetermined number of capacitor elements are disconnected from the downstream node; and

[0312] The downstream circuit sequentially reads the reset level and each of the plurality of signal levels via the downstream node.

[0313] (2) According to the solid-state imaging element of (1) above, wherein,

[0314] The predetermined number of capacitor elements includes a first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element;

[0315] The upstream circuit block includes:

[0316] A first upstream circuit sequentially generates a first reset level and a first signal level, and maintains the first capacitor element and the second capacitor element at the first reset level and the first signal level, respectively; and

[0317] The second upstream circuit sequentially generates a second reset level and a second signal level, and maintains the second reset level and the second signal level by the third capacitor element and the fourth capacitor element; and

[0318] The selection unit includes:

[0319] A first selection circuit connects either the first capacitor element or the second capacitor element to the downstream node; and

[0320] A second selection circuit connects either the third or fourth capacitor element to the downstream node.

[0321] (3) The solid-state imaging element according to (2) above, wherein,

[0322] The first upstream circuit includes:

[0323] First photoelectric conversion element;

[0324] A first upstream transport transistor transfers charge from the first photoelectric conversion element to the first floating diffusion layer;

[0325] A first reset transistor initializes the first floating diffusion layer; and

[0326] A first upstream amplifying transistor amplifies the voltage of the first floating diffusion layer; and

[0327] The second upstream circuit includes:

[0328] Second photoelectric conversion element;

[0329] The second upstream transport transistor transfers charge from the second photoelectric conversion element to the second floating diffusion layer;

[0330] A second reset transistor initializes the second floating diffusion layer; and

[0331] The second upstream amplifying transistor amplifies the voltage of the second floating diffusion layer.

[0332] (4) The solid-state imaging element according to (3) above, wherein,

[0333] The first upstream circuit also includes a first current source transistor connected to the first upstream node;

[0334] The second upstream circuit also includes a second current source transistor connected to the second upstream node;

[0335] The first upstream amplifying transistor amplifies the voltage of the first floating diffusion layer and outputs the amplified voltage to the first upstream node;

[0336] The second upstream amplifying transistor amplifies the voltage of the second floating diffusion layer and outputs the amplified voltage to the second upstream node;

[0337] The first capacitor element and the second capacitor element each have a first terminal and a second terminal connected to the first selection circuit. The first terminal of the first capacitor element and the first terminal of the second capacitor element are both connected to the first upstream node.

[0338] The third capacitor element and the fourth capacitor element each have a first terminal and a second terminal connected to the second selection circuit. The first terminal of the third capacitor element and the first terminal of the fourth capacitor element are both connected to the second upstream node.

[0339] (5) The solid-state imaging element according to (3) or (4) above, wherein,

[0340] The first upstream transport transistor and the second upstream transport transistor transfer the charge to the first floating diffusion layer and the second floating diffusion layer at a predetermined exposure start time, and the first reset transistor and the second reset transistor, together with the first floating diffusion layer and the second floating diffusion layer, initialize the first photoelectric conversion element and the second photoelectric conversion element; and

[0341] The first upstream transport transistor and the second upstream transport transistor transfer the charge to the first floating diffusion layer and the second floating diffusion layer at a predetermined exposure end time.

[0342] (6) A solid-state imaging element according to any one of (3) to (5) above, wherein,

[0343] The selection unit sequentially executes: control to connect one of the first capacitor element and the second capacitor element to the downstream node, control to connect the other of the first capacitor element and the second capacitor element to the downstream node, control to connect one of the third capacitor element and the fourth capacitor element to the downstream node, and control to connect the other of the third capacitor element and the fourth capacitor element to the downstream node.

[0344] (7) A solid-state imaging element according to any one of (3) to (6) above, wherein,

[0345] In a predetermined addition mode, the selection unit sequentially performs: control to connect one of the first capacitor element and the second capacitor element, and one of the third capacitor element and the fourth capacitor element, to the downstream node; and control to connect the other of the first capacitor element and the second capacitor element, and the other of the third capacitor element and the fourth capacitor element, to the downstream node.

[0346] (8) The solid-state imaging element according to (3) above, wherein,

[0347] The first upstream circuit further includes a first upstream selection transistor, which outputs the voltage amplified by the first upstream amplification transistor to a predetermined upstream node according to a predetermined first selection signal;

[0348] The second upstream circuit includes:

[0349] The second upstream selection transistor outputs the voltage amplified by the second upstream amplification transistor to the upstream node according to a predetermined second selection signal; and

[0350] A current source transistor connected to the upstream node;

[0351] The first capacitor element and the second capacitor element each have a first terminal commonly connected to the upstream node and a second terminal connected to the first selection circuit; and

[0352] The third capacitor element and the fourth capacitor element each have a first terminal that is connected to the upstream node and a second terminal that is connected to the second selection circuit.

[0353] (9) The solid-state imaging element according to (8) above, wherein,

[0354] The first upstream selection transistor and the second upstream selection transistor sequentially switch to a closed state before and after the predetermined exposure end time.

[0355] When the first upstream selection transistor is in a closed state, the first reset transistor initializes the first floating diffusion layer;

[0356] When the second upstream selection transistor is in a closed state, the second reset transistor initializes the second floating diffusion layer;

[0357] The first upstream selection transistor and the second upstream selection transistor sequentially switch to a closed-circuit state immediately after the exposure ends; and

[0358] The first upstream transfer transistor and the second upstream transfer transistor transfer charge at a predetermined exposure end time.

[0359] (10) The solid-state imaging element according to (1) above further includes:

[0360] A short-circuit transistor that opens and closes the path between the first downstream node and the second downstream node.

[0361] The predetermined number of capacitor elements includes: a first capacitor element, a second capacitor element, a third capacitor element, a fourth capacitor element, a fifth capacitor element, a sixth capacitor element, a seventh capacitor element, and an eighth capacitor element; and

[0362] The selection unit includes:

[0363] A first selection circuit connects either the first capacitor element or the second capacitor element to the first downstream node;

[0364] The second selection circuit connects either the third capacitor element or the fourth capacitor element to the first downstream node;

[0365] A third selection circuit connects either the fifth or sixth capacitor element to the second downstream node; and

[0366] The fourth selection circuit connects either the seventh capacitor element or the eighth capacitor element to the second downstream node.

[0367] (11) The solid-state imaging element according to (10) above, wherein,

[0368] The short-circuit transistor is in an open-circuit state in a predetermined non-additive mode, and

[0369] In the non-additive mode, the selection unit executes the following in a predetermined order: controlling the sequential connection of each of the first and second capacitor elements to the first downstream node, controlling the sequential connection of each of the third and fourth capacitor elements to the first downstream node, controlling the sequential connection of each of the fifth and sixth capacitor elements to the second downstream node, and controlling the sequential connection of each of the seventh and eighth capacitor elements to the second downstream node.

[0370] (12) The solid-state imaging element according to (10) or (11) above, wherein,

[0371] The short-circuit transistor is in a closed-circuit state under a predetermined addition mode, and

[0372] In the addition mode, the selection unit sequentially executes: control to connect one of the fifth and sixth capacitor elements and one of the seventh and eighth capacitor elements to the second downstream node while simultaneously connecting one of the first and second capacitor elements and one of the third and fourth capacitor elements to the first downstream node; and control to connect the other of the fifth and sixth capacitor elements and the other of the seventh and eighth capacitor elements to the second downstream node while simultaneously connecting the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the first downstream node.

[0373] (13) According to the solid-state imaging element of (1) above, wherein,

[0374] The predetermined number of capacitor elements includes a first capacitor element, a second capacitor element, and a third capacitor element;

[0375] The upstream circuit block includes:

[0376] First photoelectric conversion element;

[0377] A first upstream transport transistor transfers charge from the first photoelectric conversion element to a predetermined floating diffusion layer;

[0378] Second photoelectric conversion element;

[0379] The second upstream transport transistor transfers charge from the second photoelectric conversion element to the predetermined floating diffusion layer;

[0380] Initialize the reset transistor of the floating diffusion layer; and

[0381] An upstream amplifying transistor amplifies the voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node; and

[0382] The first capacitor element, the second capacitor element, and the third capacitor element each have a first end that is connected to the upstream node and a second end that is connected to the selection section.

[0383] (14) According to the solid-state imaging element of (13) above, wherein,

[0384] The first upstream transport transistor and the second upstream transport transistor transfer the charge to the floating diffusion layer at a predetermined exposure start time, and the reset transistor, together with the floating diffusion layer, initializes the first photoelectric conversion element and the second photoelectric conversion element; and

[0385] The first upstream transport transistor and the second upstream transport transistor sequentially transport the charge to the floating diffusion layer at a predetermined exposure end time.

[0386] (15) The solid-state imaging element according to (13) or (14) above, wherein,

[0387] The selection unit sequentially performs: control to connect one of the first capacitor element and the second capacitor element to the downstream node, control to connect the other of the first capacitor element and the second capacitor element to the downstream node, and control to connect the third capacitor element to the downstream node.

[0388] (16) A solid-state imaging element according to any one of (1) to (15) above, wherein,

[0389] The upstream circuit block is located on the first chip, and

[0390] The predetermined number of capacitor elements, the selection section, the downstream reset transistor, and the downstream circuit are disposed on the second chip.

[0391] (17) The solid-state imaging element according to (16) above also includes

[0392] An analog-to-digital converter sequentially converts the output reset level and the plurality of output signal levels into digital signals.

[0393] The analog-to-digital converter is located on the second chip.

[0394] (18) The solid-state imaging element according to (16) or (17) above also includes

[0395] An analog-to-digital converter sequentially converts the output reset level and the plurality of output signal levels into digital signals.

[0396] The analog-to-digital converter is located on the third chip.

[0397] (19) An imaging device, comprising:

[0398] A predetermined number of capacitor components;

[0399] An upstream circuit block generates a predetermined reset level and each of a plurality of signal levels corresponding to the exposure amount, and maintains the reset level and the plurality of signal levels by capacitive elements that are different from each other;

[0400] The selection unit sequentially executes: control to connect the capacitor element that maintains the reset level among the predetermined number of capacitor elements to a predetermined downstream node, control to disconnect the predetermined number of capacitor elements from the downstream node, and control to connect the capacitor element that maintains any one of the plurality of signal levels among the predetermined number of capacitor elements to the downstream node.

[0401] The downstream reset transistor initializes the level of the downstream node when the predetermined number of capacitor elements are disconnected from the downstream node;

[0402] Downstream circuitry, which sequentially reads the reset level and each of the plurality of signal levels via the downstream node; and

[0403] The signal processing circuit sequentially converts the reset level and the plurality of signal levels into digital signals and processes the digital signals.

[0404] (20) A solid-state imaging element, comprising:

[0405] The first photoelectric conversion element that converts incident light into electrical charge;

[0406] A second photoelectric conversion element that converts incident light into electrical charge;

[0407] The upstream amplifying transistor converts the charge into voltage;

[0408] A predetermined number of capacitor elements, each of which has a first terminal connected to an upstream node, the upstream node being the output destination of the upstream amplifying transistor;

[0409] A predetermined number of selection transistors are inserted in the respective paths between the second terminal of each of the predetermined number of capacitor elements and a predetermined downstream node;

[0410] A reset transistor having a source or drain connected to the downstream node; and

[0411] A downstream amplifying transistor has a gate connected to the downstream node and outputs a pixel signal.

[0412] Attached Reference List

[0413] 100 imaging device

[0414] 110 imaging lens

[0415] 120 recording unit

[0416] 130 Imaging Control Unit

[0417] 200 solid-state imaging elements

[0418] 201 Upper Pixel Chip

[0419] 202 lower pixel chip

[0420] 203 circuit chip

[0421] 211 Vertical Scan Circuit

[0422] 212 timing control circuit

[0423] 213DAC

[0424] 220 pixel array

[0425] 221 Upper Pixel Array Section

[0426] 222 lower pixel array

[0427] 250 load MOS circuit block

[0428] 251 load MOS transistor

[0429] 260-column signal processing circuits

[0430] 261ADC

[0431] 262 Digital Signal Processing Department

[0432] 300 pixel blocks

[0433] 301 to 304 pixels

[0434] 305 upstream circuit block

[0435] 310, 320, 410, 420 upstream circuits

[0436] Photoelectric conversion elements 311, 321, 411, 421, 511 to 513

[0437] Transmission transistors 312, 322, 412, 422, 514 to 516

[0438] 313, 323, 413, 423FD reset transistors

[0439] 314, 324, 414, 424FD

[0440] 315, 325, 415, 425 upstream amplifier transistors

[0441] 316, 326, 416, 426 current source transistors

[0442] 317, 327 upstream selection transistors

[0443] Capacitors 331, 332, 336, 337, 431, 432, 436, 437, and 531 to 533

[0444] 340 Selection Department

[0445] 350, 355, 450, 455 selector circuit

[0446] 351, 352, 356, 357, 451, 452, 456, 457, 551 to 553 select transistors

[0447] 361, 461 downstream reset transistors

[0448] 370, 470 downstream circuits

[0449] 371, 471 downstream amplifying transistors

[0450] 372, 472 downstream selection transistors

[0451] 480 short-circuit transistor

[0452] 12031 Imaging Unit

Claims

1. A solid-state imaging element, comprising: A first photoelectric conversion element converts light incident on the first photoelectric conversion element into a first charge; A first upstream amplifying transistor converts the first charge into a first voltage; A predetermined number of first capacitor elements, each having a first end connected to a first upstream node, the first upstream node being connected to the first upstream amplifying transistor; A predetermined number of first selection transistors are inserted in the respective paths between the second terminal of each of the predetermined number of first capacitor elements and the downstream node; The second photoelectric conversion element converts light incident on it into a second charge. The second upstream amplifying transistor converts the second charge into a second voltage; A predetermined number of second capacitor elements, each having a first end connected to a second upstream node, the second upstream node being connected to a second upstream amplifying transistor; A predetermined number of second selection transistors are inserted in the respective paths between the second terminal of each of the predetermined number of second capacitor elements and the downstream node; A reset transistor having a source or drain connected to the downstream node; as well as A downstream amplifying transistor has a gate connected to the downstream node and outputs a pixel signal.

2. The solid-state imaging element according to claim 1, further comprising: A first upstream transport transistor transfers the first charge from the first photoelectric conversion element to a first floating diffusion layer, the first floating diffusion layer being connected to the first upstream amplification transistor; as well as The second upstream transport transistor transfers the second charge from the second photoelectric conversion element to the second floating diffusion layer, which is connected to the second upstream amplification transistor.

3. The solid-state imaging element according to claim 2, further comprising: A first reset transistor initializes the first floating diffusion layer; as well as The second reset transistor initializes the second floating diffusion layer.

4. The solid-state imaging element according to claim 3, wherein, The first upstream amplifying transistor converts the voltage of the first floating diffusion layer during initialization into a third voltage, and The second upstream amplifying transistor converts the voltage of the second floating diffusion layer at initialization into a fourth voltage.

5. The solid-state imaging element according to claim 4, wherein, The first and second of the predetermined number of first capacitor elements respectively maintain the third voltage and the first voltage, and The first and second of the predetermined number of second capacitor elements respectively maintain the fourth voltage and the second voltage.

6. The solid-state imaging element according to claim 5, wherein, The following steps are executed sequentially: connecting a first of the predetermined number of first capacitor elements to the downstream node; connecting a second of the predetermined number of first capacitor elements to the downstream node; connecting a first of the predetermined number of second capacitor elements to the downstream node; and connecting a second of the predetermined number of second capacitor elements to the downstream node.

7. The solid-state imaging element according to claim 5, wherein, In a predetermined addition mode, the following steps are performed sequentially: connecting the first of the predetermined number of first capacitor elements and the first of the predetermined number of second capacitor elements to the downstream node; And the control of connecting the second of the predetermined number of first capacitor elements and the second of the predetermined number of second capacitor elements to the downstream node.

8. The solid-state imaging element according to claim 5, further comprising: The first upstream selection transistor outputs the first voltage and the third voltage, converted by the first upstream amplification transistor, to the first upstream node according to a predetermined first selection signal; and The second upstream selection transistor outputs the second voltage and the fourth voltage, converted by the second upstream amplification transistor, to the second upstream node according to a predetermined second selection signal.

9. The solid-state imaging element according to claim 8, wherein, The first upstream selection transistor and the second upstream selection transistor sequentially switch to a closed state before and after the predetermined exposure end time. When the first upstream selection transistor is in a closed state, the first reset transistor initializes the first floating diffusion layer; When the second upstream selection transistor is in a closed state, the second reset transistor initializes the second floating diffusion layer; The first upstream selection transistor and the second upstream selection transistor sequentially switch to a closed-circuit state immediately after the exposure ends; and The first upstream transfer transistor and the second upstream transfer transistor transfer charge at a predetermined exposure end time.

10. The solid-state imaging element according to claim 1, further comprising: The third photoelectric conversion element converts light incident on the third photoelectric conversion element into a third charge; The third upstream amplifying transistor converts the third charge into a third voltage; A predetermined number of third capacitor elements, each of the third capacitor elements having a first terminal connected to a third upstream node, the third upstream node being connected to the third upstream amplifying transistor; A predetermined number of third selection transistors are inserted in the respective paths between the second terminal of each of the predetermined number of third capacitor elements and the second downstream node; A fourth photoelectric conversion element, which converts light incident on the fourth photoelectric conversion element into a fourth charge; A fourth upstream amplifying transistor, which converts the fourth charge into a fourth voltage; A predetermined number of fourth capacitor elements, each of the fourth capacitor elements having a first terminal connected to a fourth upstream node, the fourth upstream node being connected to the fourth upstream amplifying transistor; as well as A predetermined number of fourth selection transistors are inserted in the respective paths between the second terminal of each of the predetermined number of fourth capacitor elements and the second downstream node. The short-circuit transistor is inserted in the path between the downstream node and the second downstream node.

11. The solid-state imaging element according to claim 10, wherein, The short-circuit transistor is in an open-circuit state in a predetermined non-additive mode, and In the non-additive mode, the following are executed in a predetermined order: the control of sequentially connecting each of the predetermined number of first capacitor elements to the downstream node, the control of sequentially connecting each of the predetermined number of second capacitor elements to the downstream node, the control of sequentially connecting each of the predetermined number of third capacitor elements to the second downstream node, and the control of sequentially connecting each of the predetermined number of fourth capacitor elements to the second downstream node.

12. The solid-state imaging element according to claim 10, wherein, The short-circuit transistor is in a closed-circuit state under a predetermined addition mode, and In the addition mode, the following operations are performed sequentially: connecting the first of the predetermined number of third capacitor elements and the first of the predetermined number of fourth capacitor elements to the second downstream node, and simultaneously connecting the first of the predetermined number of first capacitor elements and the first of the predetermined number of second capacitor elements to the downstream node. The control that connects the second of the predetermined number of third capacitor elements and the second of the predetermined number of fourth capacitor elements to the second downstream node, and simultaneously connects the second of the predetermined number of first capacitor elements and the second of the predetermined number of second capacitor elements to the downstream node.

13. The solid-state imaging element according to claim 1, further comprising: A first current source transistor is connected to the first upstream node; and The second current source transistor is connected to the second upstream node.

14. The solid-state imaging element according to any one of claims 1 to 13, wherein, The first photoelectric conversion element, the second photoelectric conversion element, the first upstream amplifying transistor, and the second upstream amplifying transistor are disposed on the first chip, and The predetermined number of first capacitor elements, the predetermined number of first selection transistors, the predetermined number of second capacitor elements, the predetermined number of second selection transistors, the reset transistor, and the downstream amplification transistor are disposed on the second chip.

15. The solid-state imaging element according to claim 14, further comprising: An analog-to-digital converter converts the first voltage and the second voltage into digital signals, respectively. The analog-to-digital converter is located on the second chip.

16. The solid-state imaging element according to claim 14, further comprising: An analog-to-digital converter converts the first voltage and the second voltage into digital signals, respectively. The analog-to-digital converter is located on the third chip.

Images