Three-dimensional dynamic random access memory and manufacturing method thereof

Abstract

The invention discloses a three-dimensional dynamic random access memory and a manufacturing method thereof, relates to the technical field of memories, and aims to improve the storage density of the dynamic random access memory. The three-dimensional dynamic random access memory comprises a plurality of memory units distributed in a three-dimensional array, and a medium structure used for separating different memory units. Each storage unit comprises a transistor and a capacitor. The source electrode and the drain electrode are arranged on the two sides of the channel layer in the length direction respectively and cover the inner wall of the notch. The gate dielectric layer is located between the gate and the channel layer, between the gate and the source and between the gate and the drain. The capacitor comprises a first electrode and a second electrode which are distributed at an interval, and a dielectric layer located between the first electrode and the second electrode. One of a source electrode and a drain electrode included in the transistor is shared with the first electrode of the capacitor, and the other one is integrally continuous with the source electrode or the drain electrode located on the same side in the other transistors located on the same column in the first direction.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a three-dimensional dynamic random access memory and its manufacturing method. Background Technology

[0002] In computer systems, memory is a crucial component for storing data and programs. Dynamic Random Access Memory (DRAM), as an important type of memory, plays a key role in modern computer architecture. DRAM comprises a 1T1C memory cell structure. A memory cell in this type of DRAM consists of a transistor and a capacitor connected to either the source or drain of the transistor. The capacitor stores electrical charge, and the transistor controls access to the capacitor.

[0003] However, the existing dynamic random access memory (DRAM) has different memory cells arranged in an array along the horizontal direction of the wafer, which is a two-dimensional DRAM. Its distribution density is small and cannot meet the development requirements of computer systems. Summary of the Invention

[0004] The purpose of this invention is to provide a three-dimensional dynamic random access memory and its manufacturing method, which can improve the storage density of the dynamic random access memory; and the source and drain of the transistor are contacted by the sidewall of the channel layer along the length direction to improve the gate control capability of the transistor and improve leakage current.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a three-dimensional dynamic random access memory (DRAM), comprising: a plurality of memory cells arranged in a three-dimensional array, and a dielectric structure for isolating the different memory cells. The plurality of memory cells arranged in a three-dimensional array include multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, and each memory group including a plurality of memory cells arranged along a third direction. The first direction, the second direction, and the third direction are mutually different. Each memory cell includes: a transistor and a capacitor. The dielectric structure includes a first dielectric portion located between two transistors spaced apart along the first direction. The transistor includes: a gate, a gate dielectric layer, a channel layer, a source, and a drain. The length direction of the channel layer is parallel to the second direction, and the two sidewalls of the channel layer along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portions to form notches. The source and drain are respectively disposed on both sides of the channel layer along the length direction and cover the inner walls of the notches. The gate dielectric layer is located between the gate and the channel layer, the source, and the drain, respectively. The capacitor includes a first electrode and a second electrode spaced apart, and a dielectric layer located between the first electrode and the second electrode. The transistor includes a source and a drain, one of which is shared with the first electrode of the capacitor, and the other is integrally continuous with the source or drain of the remaining transistors located on the same side in the same column along a first direction.

[0006] With the above technical solution, the three-dimensional dynamic random access memory (DRAM) provided by the present invention not only has multiple memory groups spaced apart along the second direction in the same layer, but also includes multiple memory layers spaced apart along the first direction, in which case the multiple memory cells are arranged in a three-dimensional array. Compared with a two-dimensional DRAM with only a single memory layer, each memory layer in the present invention can form a structure analogous to the existing two-dimensional DRAM. Furthermore, the multiple memory layers stacked along the first direction in the present invention can multiply the storage density of the three-dimensional DRAM provided by the present invention, effectively solving the problem of low density in two-dimensional DRAMs.

[0007] Furthermore, in the storage cell of the three-dimensional dynamic random access memory provided by this invention, the two side walls of the channel layer of the transistor along the length direction are recessed inward relative to the side wall of the corresponding first dielectric portion, forming a notch. The source and drain are respectively disposed on both sides of the channel layer along the length direction. In other words, in the transistor provided by this invention, the contact interface between the existing source and drain and the channel layer is changed from contact with the top plane to contact with the side of the channel layer along the length direction, which is beneficial to improve integration density; at the same time, it can also improve the gate control capability of the transistor and improve leakage current. Secondly, the source and drain cover the inner wall of the notch. In the actual manufacturing process, the source and drain in contact with the side of the channel layer can be formed in the notch through the deposition process, which can reduce the manufacturing difficulty of the boundary contact source and drain, and improve the transistor yield while ensuring good transistor performance. In addition, one of the source and drain of the transistor is shared with the first electrode of the capacitor, which helps to simplify the structure of the semiconductor device. At the same time, when the source and drain cover the inner wall of the notch, the first electrode is not only located on the inner wall of the notch along the length of the channel layer, but also covers the inner wall of the notch along the first direction, which helps to increase the surface area of ​​the first electrode, thereby increasing the capacitance and improving the storage capacity of the three-dimensional dynamic random access memory.

[0008] In one example, the channel layer material includes indium gallium zinc oxide.

[0009] In one example, in the same transistor, the gate and gate dielectric layers are respectively disposed on both sides of the channel layer along a first direction.

[0010] In one example, the dielectric structure further includes a second dielectric section and a third dielectric section. The second dielectric section is located between two capacitors spaced apart along a third direction, and between the integrally continuous source or drain electrodes of two rows of transistors spaced apart along a third direction. The third dielectric section is located between two transistors spaced apart along a third direction.

[0011] In one example, the dielectric structure includes a fourth dielectric section located between integrally continuous source or drain electrodes in two rows of transistors spaced apart along a second direction.

[0012] In one example, the dielectric layers of the different capacitors spaced apart along a first direction are integrally continuous, and the second electrodes of the different capacitors spaced apart along the first direction are integrally continuous.

[0013] In a second aspect, the present invention provides a method for manufacturing a three-dimensional dynamic random access memory (DRAM), the method comprising: first, forming a plurality of memory cells arranged in a three-dimensional array. The plurality of memory cells arranged in a three-dimensional array includes multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, and each memory group including a plurality of memory cells arranged along a third direction. The first direction, the second direction, and the third direction are different from each other. Each memory cell includes a transistor and a capacitor. Next, forming a dielectric structure for isolating different memory cells. The dielectric structure includes a first dielectric portion located between two transistors spaced apart along the first direction. The transistor includes a gate, a gate dielectric layer, a channel layer, a source, and a drain. The length direction of the channel layer is parallel to the second direction, and the two sidewalls of the channel layer along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portion to form a notch. The source and drain are respectively disposed on both sides of the channel layer along the length direction and cover the inner wall of the notch. The gate dielectric layer is located between the gate and the channel layer, the source, and the drain, respectively. The capacitor includes a first electrode and a second electrode spaced apart, and a dielectric layer located between the first electrode and the second electrode. The transistor includes a source and a drain, one of which is shared with the first electrode of the capacitor, and the other is integrally continuous with the source or drain of the remaining transistors located on the same side in the same column along a first direction.

[0014] In one example, forming a plurality of memory cells arranged in a three-dimensional array and forming a dielectric structure for isolating different memory cells includes: forming a stacked structure and a second dielectric portion through the stacked structure. The stacked structure includes multiple stacked cells stacked along a first direction. Each stacked cell includes a first dielectric layer and a stack layer located on the first dielectric layer. The stack layer includes a stacked second dielectric layer and a gate. The material of the first dielectric layer is different from the material of the second dielectric layer. A first via group and a second via group spaced apart along a second direction are formed in the stacked structure. Both the first via group and the second via group include a plurality of vias spaced apart along a third direction. The second dielectric portion is disposed between two adjacent vias along the third direction in the same first via group and between two adjacent vias along the third direction in the same second via group. The first dielectric layer includes the first dielectric portion. Next, the edge portion of each gate layer is selectively removed to form a notch. Next, the second dielectric layer is selectively etched to form a third dielectric portion of the remaining second dielectric layer. The third dielectric portion is located between two transistors spaced apart along the third direction. The dielectric structure includes the first dielectric portion, the second dielectric portion, and the third dielectric portion. Next, a gate dielectric layer is deposited to cover the outer periphery of the gate. A channel layer is then deposited on the gate dielectric layer. Next, at least one of the source and drain electrodes of a transistor is formed on the sidewall of each via included in the first via group, and a capacitor is formed on the portion of the notch corresponding to each via included in the second via group.

[0015] In one example, forming a stacked structure and a second dielectric portion penetrating the stacked structure includes: forming a stacked material layer. Next, forming a third group of vias and a fourth group of vias penetrating the stacked material layer. The aperture pattern of the third group of vias is the same as the top pattern of the second dielectric layer disposed between two adjacent vias in the same first group of vias along a third direction. The aperture pattern of the fourth group of vias is the same as the top pattern of the second dielectric layer disposed between two adjacent vias in the same second group of vias along a third direction. Next, forming a second dielectric portion filling the third group of vias and the fourth group of vias. Next, forming a first group of vias and a second group of vias penetrating the stacked material layer.

[0016] In one example, the method of manufacturing a three-dimensional dynamic random access memory further includes forming a fourth dielectric portion that fills each via of a first via group. The fourth dielectric portion is located between integrally continuous source or drain electrodes in two rows of transistors spaced apart along a second direction.

[0017] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 1 ; Figure 2 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 2 ; Figure 3 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 3 ; Figure 4 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 4 ; Figure 5 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 5 ; Figure 6 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 6 ; Figure 7 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 7 ; Figure 8 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 8 ; Figure 9 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 9 ; Figure 10 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 ; Figure 11 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 one; Figure 12 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 two; Figure 13 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 three; Figure 14 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 Four; Figure 15 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 five; Figure 16 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 six; Figure 17 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 seven; Figure 18 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 eight; Figure 19 A schematic diagram of the structure of the three-dimensional dynamic random access memory provided in the embodiments of the present invention during the manufacturing process. Figure 10 Nine.

[0019] Reference numerals: 11 is a memory cell, 12 is a transistor, 13 is a capacitor, 14 is a first dielectric section, 15 is a gate, 16 is a gate dielectric layer, 17 is a channel layer, 18 is a source, 19 is a drain, 20 is a notch, 21 is a first electrode, 22 is a second electrode, 23 is a dielectric layer, 24 is a second dielectric section, 25 is a third dielectric section, 26 is a fourth dielectric section, 27 is a first dielectric layer, 28 is a second dielectric layer, 29 is a first via group, 30 is a second via group, 31 is a third via group, and 32 is a fourth via group. Detailed Implementation

[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0021] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0022] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0025] In computer systems, memory is a crucial component for storing data and programs. Dynamic Random Access Memory (DRAM), as an important type of memory, plays a key role in modern computer architecture. DRAM includes a 1T1C memory cell structure. A memory cell in this type of DRAM consists of a transistor and a capacitor connected to the source or drain of the transistor. The capacitor stores charge, and the transistor controls access to the capacitor. This type of DRAM also includes word lines connected to the gate of the transistor and bit lines connected to the source or drain of the transistor. When data is accessed in a memory cell, the word line connected to that memory cell is selected, and a voltage is input to that word line to turn on the transistor. The transistor turns on, and then the bit line connected to that memory cell is selected, allowing access to the charge in the capacitor. However, because the capacitor gradually leaks current, causing the stored charge to decrease, DRAM needs to be refreshed periodically (usually every few milliseconds) to maintain data validity. The refresh operation reads the data in each storage cell and rewrites it, thereby replenishing the charge lost from the capacitor.

[0026] In existing technologies, the memory cells of dynamic random access memory (DRAM) are arrayed along the horizontal direction of the wafer, which is called two-dimensional DRAM. However, the development of computer systems has placed higher demands on the density of DRAM, and the density of two-dimensional DRAM is limited by the manufacturing process and cannot meet the density requirements.

[0027] To address the aforementioned technical problems, embodiments of the present invention provide a three-dimensional dynamic random access memory (DRAM) and a method for manufacturing the same. The DRAM provided in this embodiment includes multiple memory cells arranged in a three-dimensional array to improve device integration. Furthermore, the source and drain of the transistors are contacted by sidewalls of the channel layer along its length to improve gate control capability and reduce leakage current.

[0028] In a first aspect, embodiments of the present invention provide a three-dimensional dynamic random access memory. For example... Figures 16 to 19 As shown, the three-dimensional dynamic random access memory includes: a plurality of memory cells 11 arranged in a three-dimensional array, and a dielectric structure for isolating the different memory cells 11. The plurality of memory cells 11 arranged in a three-dimensional array includes multiple memory layers spaced apart along a first direction, each memory layer including a plurality of memory groups spaced apart along a second direction, and each memory group including a plurality of memory cells 11 arranged along a third direction. The first direction, the second direction, and the third direction are different from each other. Each memory cell 11 includes: a transistor 12 and a capacitor 13. The dielectric structure includes a first dielectric portion 14 located between two transistors 12 spaced apart along the first direction. The transistor 12 includes: a gate 15, a gate dielectric layer 16, a channel layer 17, a source 18, and a drain 19. The length direction of the channel layer 17 is parallel to the second direction, and the two sidewalls of the channel layer 17 along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portion 14 to form a notch 20. The source 18 and drain 19 are respectively disposed on both sides of the channel layer 17 along its length and cover the inner wall of the notch 20. The gate dielectric layer 16 is located between the gate 15 and the channel layer 17, the source 18, and the drain 19. The capacitor 13 includes a first electrode 21 and a second electrode 22 spaced apart, and a dielectric layer 23 located between the first electrode 21 and the second electrode 22. One of the source 18 and drain 19 of the transistor 12 is shared with the first electrode 21 of the capacitor 13, and the other is integrally continuous with the source 18 or drain 19 located on the same side of the other transistors 12 located in the same column along the first direction.

[0029] When the above technical solution is adopted, such as Figures 16 to 19As shown, the three-dimensional dynamic random access memory (DRAM) provided in this embodiment of the invention not only has multiple memory groups spaced apart along a second direction in the same layer, but also includes multiple memory layers spaced apart along a first direction. In this case, the multiple memory cells 11 are arranged in a three-dimensional array. Compared to a two-dimensional DRAM with only a single memory layer, each memory layer in this embodiment can form a structure analogous to the existing two-dimensional DRAM. Furthermore, the multiple memory layers stacked along the first direction in this embodiment can significantly increase the storage density of the three-dimensional DRAM, effectively solving the problem of low density in two-dimensional DRAMs. In addition, in the memory cells 11 included in the three-dimensional DRAM provided in this embodiment, the channel layer 17 of the transistor 12 has its two sidewalls recessed inward relative to the sidewall of the corresponding first dielectric portion 14 along its length, forming a notch 20. The source 18 and drain 19 are respectively disposed on both sides of the channel layer 17 along its length. In other words, in the transistor 12 provided in this embodiment of the invention, the contact interface between the existing source 18 and drain 19 and the channel layer 17 is changed from contact with the top plane to contact with the side of the channel layer 17 along the length direction. This is beneficial for improving integration density and making electron injection more efficient; at the same time, it can also improve the gate control capability of the transistor 12 and improve leakage current. Secondly, as Figures 16 to 19 As shown, the source 18 and drain 19 cover the inner wall of the recess 20. In the actual manufacturing process, the source 18 and drain 19, which are in contact with the side of the channel layer 17, can be formed in the recess 20 through a deposition process. This reduces the manufacturing difficulty of the boundary contact source 18 and drain 19, and can also improve the yield of the transistor 12 if the transistor 12 has good working performance. In addition, one of the source 18 and drain 19 of the transistor 12 is shared with the first electrode 21 of the capacitor 13, which helps to simplify the structure of the semiconductor device. At the same time, when the source 18 and drain 19 cover the inner wall of the recess 20, the first electrode 21 is not only disposed on the inner wall of the recess 20 along the length direction of the channel layer 17, but also covers the inner wall of the recess 20 along the first direction. This helps to increase the surface area of ​​the first electrode 21, thereby increasing the capacitance and improving the storage capacity of the three-dimensional dynamic random access memory.

[0030] In practical applications, the embodiments of the present invention do not specifically limit the specific arrangement direction and distribution of different storage units, as long as the different storage units are distributed in a three-dimensional array. As for the specific directions referred to by the first direction, the second direction and the third direction, no specific limitation is made here, as long as any two of the above three directions are different.

[0031] For example, the first direction can be the height direction of the three-dimensional dynamic random access memory provided in the embodiments of the present invention. Secondly, the second and third directions can be determined based on the distribution of different memory cells in the same memory layer. Optionally, the second and third directions can be perpendicular.

[0032] For example: Figures 16 to 19 As shown, when different storage cells 11 in the same storage layer are distributed in a rectangular array, the second direction and the third direction can be the length and width directions of the rectangular array, respectively.

[0033] For example, when different memory cells in the same memory layer are distributed in a parallelogram array, the second direction and the third direction can be the directions of two adjacent sides of the parallelogram array, respectively.

[0034] For example, when different memory cells in the same memory layer are distributed in a concentric circle array, the second direction and the third direction can be the radial and circumferential directions of the concentric circle array, respectively.

[0035] It is understandable that when the distribution of storage cells in the same storage layer is different, the second and third directions can be changed according to their distribution.

[0036] For storage units, such as Figures 16 to 19 As shown, each storage cell 11 of the three-dimensional dynamic random access memory includes a transistor 12 and a capacitor 13 to form a 1T1C dynamic random access memory structure.

[0037] In practical applications, the embodiments of the present invention do not specifically limit the connection relationship between the transistors and capacitors included in the memory cell, and can determine it according to the conductivity type of the transistors and actual needs. For example, the source of the transistor may share the same electrode as the first electrode of the capacitor (i.e., the same conductive structure can be used as both the source of the transistor and the first electrode of the capacitor), in which case the drain is electrically connected to the bit line (either the drain and the bit line are shared, or the drain and the bit line are manufactured separately and electrically connected). Alternatively, as... Figures 16 to 19 As shown, it is also possible that when the source 18 and drain 19 of transistor 12 are electrically connected to the first electrode 21 of capacitor 13, the source 18 is electrically connected to the bit line.

[0038] It should be noted that the accompanying drawings provided in the embodiments of the present invention only illustrate the case where the drain is electrically connected to the first electrode of the capacitor, and the source is electrically connected to the bit line, but do not represent that the connection relationship can only be as described above. For the specific connection relationships between the source and drain of the transistor and the capacitor and bit line, respectively, please refer to the preceding text.

[0039] From a structural perspective, such as Figures 16 to 19 As shown, transistor 12 includes a gate 15, a gate dielectric layer 16, a channel layer 17, a source 18, and a drain 19. The channel layer 17 has its length direction parallel to the second direction, and its two sidewalls along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portion 14 to form a notch 20. The source 18 and drain 19 are respectively disposed on both sides of the channel layer 17 along the length direction and cover the inner wall of the notch 20; the gate dielectric layer 16 is located between the gate 15 and the channel layer 17, source 18, and drain 19. Since the channel layer 17, source 18, and drain 19 are formed after the gate 15, they will not be suspended during the manufacturing of the three-dimensional dynamic random access memory provided in this embodiment of the invention. This helps to prevent collapse due to the low structural strength of the channel layer 17, source 18, and drain 19, thereby ensuring the regularity of the transistor 12 structure. This ensures the normal operation and stable performance of the memory cell 11 manufactured by the manufacturing method of the three-dimensional dynamic random access memory provided in this embodiment of the invention, thereby improving the yield.

[0040] In practical applications, the embodiments of the present invention do not specifically limit the gate structure of the transistor, but can determine it according to the performance requirements of the three-dimensional dynamic random access memory of the embodiments of the present invention. The gate structure of the transistor can be a conventional single-gate transistor or a dual-gate transistor, or other possible gate structures.

[0041] For example, the transistor is a conventional single-gate transistor. Along a first direction, a gate is disposed on a first dielectric portion, a gate dielectric layer is disposed on the gate, and a channel layer is disposed on the gate and the first dielectric portion.

[0042] For example, the transistor is a dual-gate transistor. (e.g.) Figures 16 to 19As shown, in the same transistor 12, the gate 15 and the gate dielectric layer 16 are respectively disposed on both sides of the channel layer 17 along the first direction. The transistor 12 provided in this embodiment of the invention has two gates 15. The dual-gate transistor can have a larger gate control area with the same channel layer 17 area, which can effectively improve the control capability of the gate 15 over the channel layer 17, thereby improving the switching performance of the transistor 12 provided in this embodiment of the invention. For example, under low voltage operation, the dual-gate transistor can control the current more precisely and achieve faster switching, which is beneficial to reducing the power consumption of the three-dimensional dynamic random access memory provided in this embodiment of the invention. Furthermore, the dual-gate transistor 12 provided in this embodiment of the invention can effectively suppress the short-channel effect, which is beneficial to further reduce the size of the transistor 12 provided in this embodiment of the invention, thereby improving the storage density of the three-dimensional dynamic random access memory provided in this embodiment of the invention. Specifically, in the first direction, the two gates 15 of the same transistor 12 are respectively disposed on two adjacent first dielectric layers 14, and the edges of the two gates 15 along the second direction are recessed inward relative to the edges of the first dielectric layers 14, forming notches 20. A gate dielectric layer 16 covering the outer periphery of the gate 15 is disposed on the inner wall of the notch 20, and a channel layer 17 is disposed between the upper and lower gate dielectric layers 16. The source 18 and the drain 19 are covered on the gate dielectric layer 16 located in the notch 20.

[0043] In practical applications, the embodiments of the present invention do not specifically limit the material of the channel layer, as long as the performance of the material can meet the speed requirements of the three-dimensional dynamic random access memory provided by the embodiments of the present invention. The material of the channel layer can be common silicon, or it can be a material with high electron mobility such as germanium, silicon germanium, or indium gallium zinc oxide to reduce the resistivity of the channel layer and improve the speed of the transistor.

[0044] Optionally, the channel layer material includes indium gallium zinc oxide (IGZO). In this case, IGZO has a relatively high carrier mobility, meaning that electrons move faster in the material. This allows the transistors provided in the embodiments of the present invention to have faster signal transmission and switching speeds, thereby improving the operating efficiency and response speed of the three-dimensional dynamic random access memory (DRAM) provided in the embodiments of the present invention. Furthermore, the transistors with IGZO as the channel layer material have very low current in the off state, which helps to reduce the power consumption of the three-dimensional DRAM provided in the embodiments of the present invention and improve the battery life of electronic devices using the three-dimensional DRAM provided in the embodiments of the present invention. Simultaneously, when manufacturing the three-dimensional DRAM provided in the embodiments of the present invention, the IGZO channel layer can be fabricated using a low-temperature process. Low-temperature processes reduce the need for expensive high-temperature equipment and complex process steps, thus reducing costs; they also reduce the risk of thermal damage to the three-dimensional memory, thereby improving chip yield.

[0045] In practical applications, the source and drain materials can include any conductive material. This invention does not impose specific limitations on them, as long as they meet the design and process requirements of the three-dimensional dynamic random access memory provided in this invention. For example, the source and / or drain materials can include silver, copper, aluminum, tungsten, titanium, nickel, or gold.

[0046] In practical applications, the materials of the gate dielectric layer and the gate are not specifically limited in this embodiment of the invention, as long as they can be applied to the three-dimensional dynamic random access memory provided by this embodiment. For example, high dielectric constant materials, including hafnium dioxide, can be used to reduce the thickness of the gate dielectric layer, thereby reducing the floating height during the manufacturing of the transistor provided by this embodiment and effectively avoiding structural damage caused by floating, thus improving yield; the thickness of the transistor can also be reduced to increase storage density. For example, the gate material can be copper, aluminum, or tungsten. Optionally, the gate material is tungsten because tungsten is stable, does not easily diffuse into other structures, and is not easily affected by the high-temperature process steps during the manufacturing of the three-dimensional dynamic random access memory provided by this embodiment, thus ensuring the performance of the three-dimensional dynamic random access memory provided by this embodiment.

[0047] In addition, such as Figures 16 to 19 As shown, regarding the notch 20, since the source 18 and drain 19 are disposed on the inner wall of the notch 20, the surface area of ​​the inner wall of the notch 20 is also the contact area between one of the source 18 and drain 19 and the bit line, and the other determines the area of ​​the first electrode 21 of the capacitor 13 (and thus the capacitance). Therefore, in order to reduce the contact resistance and the capacitance of the capacitor 13, the shape of the notch is limited as follows in this embodiment of the invention:

[0048] Specifically, such as Figures 16 to 19 As shown, the ratio of the height to the width of the notch 20 can be greater than or equal to 0.1 and less than or equal to 10. The height of the notch 20 is parallel to the first direction, and the width of the notch 20 is parallel to the second direction. In this case, when the height and width of the notch 20 are within the above range, the notch 20 has a larger surface area, which is beneficial to reduce the contact resistance between one of the source 18 and drain 19 and the bit line, improve the speed of transistor 12, and improve leakage current; it can also increase the capacitance of capacitor 13 and improve storage capacity. Furthermore, it also prevents the size of the notch 20 from being too large, ensuring that during the manufacturing of the three-dimensional dynamic random access memory provided in this embodiment of the invention, the lateral etching width (i.e., the width of the notch 20) of the first dielectric portion 14 and the gate layer disposed on the first dielectric portion 14 is not too large when the notch 20 is formed, reducing the difficulty of lateral etching, thereby improving the yield of the provided three-dimensional dynamic random access memory.

[0049] For the capacitors in the storage cell, such as Figures 16 to 19 As shown, the dielectric layers 23 of the different capacitors 13 spaced apart along the first direction can be integrally continuous, and the second electrodes 22 of the different capacitors 13 spaced apart along the first direction can also be integrally continuous. This configuration allows the dielectric layers 23 and second electrodes 22 of different capacitors 13 to be formed simultaneously in the same operation step, improving manufacturing efficiency and simplifying the manufacturing process of three-dimensional dynamic random access memory.

[0050] Furthermore, in practical applications, the embodiments of the present invention do not impose specific limitations on the specific shape and distribution of the media structure, as long as different storage units can be isolated.

[0051] Specifically, such as Figures 16 to 19 As shown, the dielectric structure includes a first dielectric portion 14 located between two transistors 12 spaced apart along a first direction. Along a second direction, the sidewalls of the first dielectric portion 14 protrude relative to the sidewalls of the channel layer 17 to form recesses 20 on both sides of the channel layer 17 along its length.

[0052] In practical applications, the embodiments of the present invention do not impose specific limitations on the material and thickness of the first dielectric layer, as long as it can isolate the gates of two adjacent transistors along the first direction. For example, the material of the first dielectric layer may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The first dielectric layer can be a single-layer structure or a stacked structure formed by manufacturing multiple materials, as long as it is feasible in terms of process.

[0053] For example, along the first direction, the thickness of the first dielectric portion can be greater than or equal to 10 nm and less than or equal to 1000 nm. This setting can prevent electrical interference between the gates of two adjacent transistors along the first direction due to the thickness of the first dielectric portion being too small, ensuring that the three-dimensional dynamic random access memory has high operating performance. In addition, it can also prevent material waste and low vertical integration of the device due to the thickness of the first dielectric portion being too large, which helps to reduce the manufacturing cost of the device and reduce the process difficulty of vertical operation.

[0054] The distance between two adjacent first dielectric layers can be determined based on the size of the transistor located between the two adjacent first dielectric layers along the first direction. For example, the distance between two adjacent first dielectric layers can be greater than or equal to 5 nm and less than or equal to 500 nm.

[0055] Regarding the shape and size of the notch, such as Figures 16 to 19As shown, the bottom of the notch 20 is composed of the gate 15 and the sidewalls of the channel layer 17 along the first direction. The sidewalls of the notch 20 are composed of the opposing surfaces of the protruding portions of the first dielectric portion 14 located on both sides of the transistor 12 in the first direction, and are composed of a structure disposed along the third direction that separates the two memory cells 11.

[0056] For example, such as Figure 6 , Figures 16 to 19 As shown, the dielectric structure also includes a second dielectric section 24 and a third dielectric section 25. The second dielectric section 24 is located between two capacitors 13 spaced apart along a third direction and between the integrally continuous source 18 or drain 19 of two rows of transistors 12 spaced apart along a third direction. The third dielectric section 25 is located between two transistors 12 spaced apart along a third direction. It can be understood that the second dielectric section 24 extends through the three-dimensional dynamic random access memory provided in this embodiment of the invention to completely isolate the integrally continuous source 18 or drain 19 (i.e., bit lines) of two adjacent transistors 12 along a third direction. As for the third dielectric section 25, it isolates two adjacent transistors 12 distributed along a third direction to enable separate access to two adjacent memory cells 11 including the two adjacent transistors 12. The gates 15 of the two transistors 12 spaced apart along a third direction are interconnected to form the word lines of the three-dimensional dynamic random access memory provided in this embodiment of the invention.

[0057] In practical applications, the materials of the first, second, and third dielectric portions are not specifically limited in the embodiments of the present invention, and can be set according to actual needs. The materials of the first and second dielectric portions can be the same or different, depending on the manufacturing process. The material of the third dielectric portion is different from both the materials of the first and second dielectric portions; please refer to the following content to facilitate selective etching of the third dielectric portion. For example, if the materials of the first and second dielectric portions are the same and both are silicon oxide, the third dielectric portion can be silicon nitride.

[0058] For example, such as Figures 16 to 19 As shown, the dielectric structure may include a fourth dielectric section 26, which is located between integrally continuous source 18 or drain 19 in two rows of transistors 12 spaced apart along the second direction, so as to reduce electrical interference between integrally continuous source 18 or drain 19 in different transistors 12 spaced apart along the second direction and improve the working performance of the three-dimensional dynamic random access memory.

[0059] The material of the fourth dielectric portion can be the same as the material of the dielectric layer included in the capacitor, so that the fourth dielectric portion can be formed at the same time as the dielectric layer of the capacitor, thereby improving manufacturing efficiency and reducing manufacturing costs.

[0060] Or, such as Figure 16 and Figure 17 As shown, a dielectric layer 23 and a second electrode 22 can also be provided between the integrally continuous source 18 or drain 19 of the two rows of transistors 12 spaced apart along the third direction. With this configuration, the integrally continuous source 18 or drain 19 of the two rows of transistors 12 spaced apart along the third direction can be isolated by the dielectric layer 23, and the presence of the second electrode 22 will not affect the overall operation of the memory cell 11. This configuration allows for the simultaneous formation of the capacitor 13 using the exact same process to achieve isolation between the integrally continuous source 18 or drain 19 of the two rows of transistors 12 spaced apart along the third direction, further improving manufacturing efficiency and reducing manufacturing costs.

[0061] Secondly, embodiments of the present invention provide a method for manufacturing a three-dimensional dynamic random access memory. The following will describe a method based on... Figures 1 to 19 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the manufacturing method of this three-dimensional dynamic random access memory includes the following steps: First, a plurality of memory cells are formed in a three-dimensional array. The plurality of memory cells in a three-dimensional array include multiple memory layers spaced apart along a first direction, each memory layer including multiple memory groups spaced apart along a second direction, and each memory group including multiple memory cells spaced apart along a third direction. The first direction, the second direction, and the third direction are different from each other. Each memory cell includes a transistor and a capacitor. Next, a dielectric structure for isolating different memory cells is formed. The dielectric structure includes a first dielectric portion located between two transistors spaced apart along the first direction. The transistor includes a gate, a gate dielectric layer, a channel layer, a source, and a drain. The length direction of the channel layer is parallel to the second direction, and the two sidewalls of the channel layer along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portion to form a notch. The source and drain are respectively disposed on both sides of the channel layer along the length direction and cover the inner wall of the notch. The gate dielectric layer is located between the gate and the channel layer, the source, and the drain, respectively. The capacitor includes a first electrode and a second electrode spaced apart, and a dielectric layer located between the first electrode and the second electrode. The transistor includes a source and a drain, one of which is shared with the first electrode of the capacitor, and the other is integrally continuous with the source or drain of the remaining transistors located on the same side in the same column along the first direction.

[0062] It should be noted that the structure of the three-dimensional dynamic random access memory formed by the manufacturing method provided in the second aspect of the present invention is the same as the structure of the three-dimensional dynamic random access memory provided in the first aspect. Therefore, the specific structure and materials of the three-dimensional dynamic random access memory formed in the second aspect can be referred to the preceding text and will not be repeated here. In addition, in the manufacturing method provided in the embodiments of the present invention, there is no specific limitation on the order of forming the memory cells and the medium structure, and the two can be formed simultaneously.

[0063] In an actual manufacturing process, for example, forming multiple memory cells arranged in a three-dimensional array and forming a media structure for isolating the different memory cells may include the following steps: like Figures 1 to 4 As shown, a stacked structure is formed, and a second dielectric portion 24 penetrates the stacked structure. The stacked structure includes multiple stacked units stacked along a first direction. Each stacked unit includes a first dielectric layer 27 and a stacked layer located on the first dielectric layer 27. The stacked layer includes a stacked second dielectric layer 28 and a gate 15. The material of the first dielectric layer 27 is different from the material of the second dielectric layer 28. A first via group 29 and a second via group 30 are provided in the stacked structure and spaced apart along a second direction. Both the first via group 29 and the second via group 30 include a plurality of vias spaced apart along a third direction. The second dielectric portion 24 is disposed between two adjacent vias in the same first via group 29 along a third direction and between two adjacent vias in the same second via group 30 along a third direction. The first dielectric layer 27 includes a first dielectric portion 14.

[0064] It is understood that the first dielectric layer is used to form the first dielectric portion, isolating the memory cells along the first direction. For information regarding the material and thickness of the first dielectric layer, please refer to the relevant description of the first dielectric portion; it will not be repeated here.

[0065] Regarding the stacked structure, the stack includes a second dielectric layer and a gate. The second dielectric layer acts as a sacrificial layer, pre-positioning the channel layer and gate dielectric layer to facilitate their subsequent formation. Additionally, the second dielectric layer also serves as an isolation layer for the subsequent formation of the third dielectric portion. Therefore, the material and thickness of the second dielectric layer can refer to the material and thickness of the third dielectric portion described above. As for the gate material and the distribution of the gate and second dielectric layer in the stack, please refer to the relevant description in the first aspect; it will not be repeated here.

[0066] For example, such as Figures 16 to 19 As shown, in the fabricated three-dimensional dynamic random access memory, when the gate 15 and the gate dielectric layer 16 are disposed on both sides of the channel layer 17 along the first direction, as... Figure 4As shown, the stack may include two gate layers 15 spaced apart along a first direction, and a second dielectric layer 28 located between the two gate layers 15.

[0067] If the gate and gate dielectric layer in the manufactured three-dimensional dynamic random access memory are disposed on one side of the channel layer along the first direction, the stack may also consist of only a gate layer and a second dielectric layer stacked along the first direction to form a conventional transistor or a back-gate transistor. The specific structure of the stack can be formed according to the requirements of the transistor structure in the first aspect, and will not be elaborated here.

[0068] It should be noted that, along the first direction, the two outermost layers of the stacked structure are the first dielectric layers, and the thickness of the two outermost first dielectric layers of the stacked structure can be greater than that of the first dielectric layer located inside the stacked structure, so as to protect the stacked structure and other structures formed subsequently.

[0069] The first via group includes vias for forming at least one integral continuous source or source in a transistor within the via, and for isolating integral continuous sources or source in different transistors spaced apart along a third direction. The second via group includes vias for forming a capacitor within the via.

[0070] This invention does not impose specific limitations on the shape and size of the through holes included in the first and second through hole groups. The shape of each through hole in the first and / or second through hole groups can be a cylindrical hole, a prism hole, or other possible shapes. As for the size of each through hole in the first through hole group, it can be determined based on the thickness of the integral continuous source or drain electrode formed in each through hole in the first through hole group, and the isolation requirements for different source or drain electrodes.

[0071] Optionally, the aperture of each via in the first via group can be greater than or equal to 30 nm and less than or equal to 3000 nm. In this case, it avoids the excessively high cost caused by excessively small apertures due to the high requirements of etching and photolithography processes, thus helping to reduce costs; it also avoids the difficulty in uniformly forming or forming continuous source or drain electrodes on the via walls due to small apertures, or the poor isolation effect between continuous source or drain electrodes in adjacent transistors. It also avoids the excessive area occupied by large apertures, thereby reducing the storage density of the three-dimensional dynamic random access memory manufactured in the embodiments of the present invention.

[0072] Optionally, the aperture of each via in the second via group can be greater than or equal to 50 nm and less than or equal to 5000 nm. In this case, it avoids the excessively high cost caused by excessively small apertures due to high requirements for etching and photolithography processes, thus helping to reduce costs; it also avoids the reduced capacitor area resulting from small apertures, which would lead to a shorter capacitor hold time and consequently a higher refresh rate and increased power consumption, thereby reducing the power consumption of the three-dimensional dynamic random access memory manufactured in this embodiment of the invention. It also avoids the excessive area occupied by large apertures, thus reducing the storage density of the three-dimensional dynamic random access memory manufactured in this embodiment of the invention.

[0073] It should be noted that the dielectric layer and the second electrode formed in each through hole of the second through hole group can both be disposed in a barrel shape on the inner wall of the through hole; or the dielectric layer can be disposed in a barrel shape on the inner wall of the through hole, and the second electrode can be disposed in a column shape to fill each through hole of the second through hole group.

[0074] In the actual manufacturing process, such as Figure 1 As shown, processes such as deposition can be used to form stacked material layers.

[0075] Next, as Figure 2 As shown, photolithography and etching processes can be used to form a third via group 31 and a fourth via group 32 that penetrate the stacked material layers. The aperture pattern of the third via group 31 is the same as the top pattern of the second dielectric layer 28 disposed between two adjacent vias in the third direction in the same first via group 29. The aperture pattern of the fourth via group 32 is the same as the top pattern of the second dielectric layer 28 disposed between two adjacent vias in the third direction in the same second via group 30.

[0076] Next, as Figure 3 As shown, processes such as deposition and planarization can be used to form the second dielectric portion 24 filling the third through-hole group 31 and the fourth through-hole group 32. The material of the second dielectric portion 24 can be referred to above.

[0077] Next, as Figure 4 As shown, photolithography and etching processes can be used to form a first through-hole group 29 and a second through-hole group 30 that penetrate the stacked material layers.

[0078] Next, as Figure 5 As shown, dry etching or wet etching processes can be used to selectively remove the edge portion of each gate layer 15 to form a notch 20.

[0079] Next, as Figure 6 As shown, the second dielectric layer 28 can be selectively etched using processes such as dry etching or wet etching, so that the remaining second dielectric layer 28 forms the third dielectric portion 25. The third dielectric portion 25 is located between two transistors 12 spaced apart along a third direction.

[0080] Next, as Figure 7 As shown, a gate dielectric layer 16 covering the outer periphery of the gate 15 can be formed using processes such as atomic layer deposition.

[0081] Next, as Figures 8 to 11 As shown, the channel layer 17 can be deposited on the gate dielectric layer 16 using processes such as deposition and etching. Specifically, a channel layer can be formed first, and then the channel layer can be etched using processes such as sidewall etching to disconnect the interlayer channel interconnections.

[0082] Next, as Figures 12 to 15 As shown, processes such as deposition and etching can be used to form at least one of the source 18 and drain 19 of the transistor 12 on the sidewall of each via included in the first via group 29, and to form a capacitor 13 on the portion of the notch 20 corresponding to each via included in the second via group 30.

[0083] For example, a deposition process can be used to first form a first electrode layer on the sidewall of each via in the second via group. Then, under the protection of the first dielectric portion, a wet etching process can be used to selectively etch the first electrode layer, retaining only the first electrode located within the notch. Then, a dielectric layer and a second dielectric layer can be sequentially formed within each via in the second via group using deposition and etching processes.

[0084] In practical applications, the dielectric structure may include a first dielectric section, a second dielectric section, and a third dielectric section. In some cases, such as... Figures 16 to 19 As shown, a fourth dielectric portion 26 can be formed by processes such as deposition and etching, filling each via of the first via group 29. The fourth dielectric portion 26 is located between the integrally continuous source 18 or drain 19 of two rows of transistors 12 spaced apart along the second direction. The dielectric structure also includes the fourth dielectric portion 26.

[0085] It should be noted that the fourth dielectric portion can be formed simultaneously with the dielectric layer included in the capacitor, or it can be formed separately before or after the capacitor is formed in the second via (if the fourth dielectric portion is formed later, when forming the capacitor in each via of the second via group, photolithography or other processes can be used to form a mask structure filling the first via group. Alternatively, if the fourth dielectric portion is formed first, during the formation of the fourth dielectric portion, photolithography or other processes can be used to form a mask structure filling the second via group). Wherein, for example... Figure 16 and Figure 17As shown, when the fourth dielectric portion 26 is formed simultaneously with the dielectric layer 23 included in the capacitor 13, each via of the first via group 29 may include a second electrode 22 in addition to the integrally continuous source electrode 18 or drain electrode 19 and the fourth dielectric portion 26. The presence of the second electrode 22 will not significantly affect the operation of the transistor 12. Furthermore, there is no need to additionally form a filler material such as photoresist in order to avoid forming the second electrode 22 in the vias included in the first via group 29, which simplifies the manufacturing process of the three-dimensional dynamic random access memory.

[0086] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0087] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0088] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A three-dimensional dynamic random access memory, characterized in that, include: A plurality of storage cells arranged in a three-dimensional array, and a medium structure for isolating different storage cells; the plurality of storage cells arranged in a three-dimensional array includes multiple storage layers spaced apart along a first direction, each storage layer including a plurality of storage groups spaced apart along a second direction, and each storage group including a plurality of storage cells arranged along a third direction. The first direction, the second direction, and the third direction are all different from each other; Each of the memory cells includes a transistor and a capacitor; the dielectric structure includes a first dielectric portion located between two of the transistors at intervals along the first direction; The transistor includes: a gate, a gate dielectric layer, a channel layer, a source, and a drain; the length direction of the channel layer is parallel to the second direction, and the two sidewalls of the channel layer along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portion to form a notch; the source and the drain are respectively disposed on both sides of the channel layer along the length direction and cover the inner wall of the notch; the gate dielectric layer is located between the gate and the channel layer, the source, and the drain respectively; The capacitor includes a first electrode and a second electrode spaced apart, and a dielectric layer located between the first electrode and the second electrode; one of the source and drain of the transistor is shared with the first electrode of the capacitor, and the other is integrally continuous with the source or drain of the remaining transistors located on the same side in the same column along the first direction.

2. The three-dimensional dynamic random access memory according to claim 1, characterized in that, The channel layer is made of indium gallium zinc oxide.

3. The three-dimensional dynamic random access memory according to claim 1, characterized in that, In the same transistor, the gate and the gate dielectric layer are respectively disposed on both sides of the channel layer along the first direction.

4. The three-dimensional dynamic random access memory according to claim 1, characterized in that, The dielectric structure further includes a second dielectric section and a third dielectric section; the second dielectric section is located between two capacitors spaced apart along the third direction and between the source or drain of two rows of transistors spaced apart along the third direction; the third dielectric section is located between two transistors spaced apart along the third direction.

5. The three-dimensional dynamic random access memory according to claim 1, characterized in that, The dielectric structure includes a fourth dielectric section located between two columns of transistors spaced apart along the second direction, which are integrally continuous sources or drains.

6. The three-dimensional dynamic random access memory according to claim 1, characterized in that, The dielectric layers of the different capacitors distributed at intervals along the first direction are integrally continuous, and the second electrodes of the different capacitors distributed at intervals along the first direction are integrally continuous.

7. A method for manufacturing a three-dimensional dynamic random access memory, characterized in that, include: Multiple storage cells are formed in a three-dimensional array; the multiple storage cells in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer includes multiple storage groups spaced apart along a second direction, and each storage group includes multiple storage cells distributed along a third direction. The first direction, the second direction, and the third direction are all different from each other; each memory cell includes a transistor and a capacitor; A dielectric structure is formed to isolate different memory cells; the dielectric structure includes a first dielectric portion located between two transistors spaced apart along a first direction; the transistor includes a gate, a gate dielectric layer, a channel layer, a source, and a drain; the length direction of the channel layer is parallel to the second direction, and the two sidewalls of the channel layer along the length direction are recessed inward relative to the sidewalls of the corresponding first dielectric portion to form a notch; the source and the drain are respectively disposed on both sides of the channel layer along the length direction and cover the inner wall of the notch; the gate dielectric layer is located between the gate and the channel layer, the source, and the drain; the capacitor includes a first electrode and a second electrode spaced apart, and a dielectric layer located between the first electrode and the second electrode; one of the source and drain of the transistor is shared with the first electrode of the capacitor, and the other is integrally continuous with the source or drain of the remaining transistors located on the same side in the same column along the first direction.

8. The method for manufacturing a three-dimensional dynamic random access memory according to claim 7, characterized in that, The formation of a plurality of said memory cells arranged in a three-dimensional array, and the formation of said media structure for isolating the different said memory cells, include: A stacked structure is formed, and a second dielectric portion penetrates the stacked structure; the stacked structure includes multiple stacked units stacked along a first direction; each stacked unit includes a first dielectric layer and a stacked layer located on the first dielectric layer; the stacked layer includes a stacked second dielectric layer and a gate; the material of the first dielectric layer is different from the material of the second dielectric layer; the stacked structure has a first via group and a second via group spaced apart along the second direction; both the first via group and the second via group include a plurality of vias spaced apart along the third direction; the second dielectric portion is disposed between two adjacent vias along the third direction in the same first via group and between two adjacent vias along the third direction in the same second via group; the first dielectric layer includes the first dielectric portion; The edge portions of each of the gate layers are selectively removed to form the notch; The second dielectric layer is selectively etched to form a third dielectric portion with the remaining second dielectric layer; the third dielectric portion is located between two transistors spaced apart along the third direction; the dielectric structure includes the first dielectric portion, the second dielectric portion, and the third dielectric portion. A gate dielectric layer is deposited to cover the outer periphery of the gate; and a channel layer is deposited on the gate dielectric layer; At least one of the source and drain of the transistor is formed on the sidewall of each via included in the first via group, and the capacitor is formed on the portion of the notch corresponding to each via included in the second via group.

9. The method for manufacturing a three-dimensional dynamic random access memory according to claim 8, characterized in that, The stacked structure and the second dielectric portion extending through the stacked structure include: Forming stacked material layers; A third and fourth through-hole group are formed through the stacked material layer; the aperture pattern of the third through-hole group is the same as the top pattern of the second dielectric layer disposed between two adjacent through-holes in the same first through-hole group along the third direction; the aperture pattern of the fourth through-hole group is the same as the top pattern of the second dielectric layer disposed between two adjacent through-holes in the same second through-hole group along the third direction. A second medium portion is formed that fills the third and fourth through-hole groups; The first and second through-hole groups are formed through the stacked material layers.

10. The method for manufacturing a three-dimensional dynamic random access memory according to claim 8, characterized in that, The method for manufacturing the three-dimensional dynamic random access memory further includes: A fourth dielectric portion is formed and filled within each of the vias included in the first via group; the fourth dielectric portion is located between the source or drain of two columns of transistors that are integrally continuous and spaced apart along the second direction.

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