Processing method of deep groove capacitor and capacitor
By employing simultaneous etching and laser-induced etching methods on glass substrates, combined with MIM multilayer capacitor structures, the processing challenges of deep trench capacitors on glass substrates have been solved, achieving efficient and uniform capacitor processing and improving capacitor density and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAMEN UNIV
- Filing Date
- 2026-01-16
- Publication Date
- 2026-04-21
AI Technical Summary
Existing technologies for processing deep trench capacitors on glass substrates suffer from problems such as slow etching rate, large bottom roughness, poor trench depth consistency, small feature size, and difficulty in achieving high verticality and aspect ratio, resulting in limited capacitor density and yield loss.
By employing a simultaneous etching process combined with laser-induced etching and wet etching, a high aspect ratio through-groove structure is formed on a glass substrate. The etching rate is increased through glass modification regions, and then the structure is bonded to a semiconductor substrate to form a MIM multilayer capacitor structure, thus realizing the fabrication of deep trench capacitors.
It improves the processing efficiency and bottom consistency of glass-based deep trench capacitors, optimizes capacitance uniformity and breakdown voltage, enhances capacitance density and yield, is applicable to a wide variety of glass types, is compatible with semiconductor processes, and possesses high flexibility and high capacitance density.
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Abstract
Description
Technical Field
[0001] This invention belongs to the technical field of semiconductor processing, specifically relating to a method for processing deep trench capacitors and the capacitor itself. Background Technology
[0002] Deep trench capacitors are widely used in various integrated circuits because they can achieve high capacitance density integration within a small area. Deep trench capacitors are usually processed on semiconductor substrates such as silicon, silicon-on-insulator, or III / V compound semiconductors. The deep trench structure is formed by processes such as dry etching, and metal-dielectric-metal is deposited in the trench until the capacitor structure is completed.
[0003] Glass, with its advantages of high-frequency performance, easy availability of large-size wafers, good surface flatness, and short processing flow, is an ideal substrate material for integrating passive devices and has broad application prospects in fields such as radio frequency, artificial intelligence, Internet of Things, and cloud computing. Using glass as a substrate, blind trenches are fabricated inside the glass using dry etching or laser-induced etching to create the structure of deep trench capacitors. However, fabricating deep trench capacitors on glass substrates presents several challenges: 1. Dry etching of glass has a slow rate, making deep trench etching uneconomical; 2. While induced etching can achieve efficient deep trench fabrication, it suffers from problems such as large trench bottom roughness and poor trench depth consistency, leading to large capacitance deviations, susceptibility to breakdown and short circuits, and high yield losses; 3. For different glass types, it is difficult to fabricate deep trenches with small feature dimensions, high verticality, and aspect ratios, limiting the capacitance density of glass-based integrated capacitors. These problems restrict the development of device integration technology such as deep trench capacitors using glass as a substrate. Summary of the Invention
[0004] This invention addresses the shortcomings of existing technologies by providing a method for processing deep trench capacitors and a capacitor in general.
[0005] To achieve the above objectives, the technical solution of the present invention is as follows:
[0006] A method for fabricating a deep trench capacitor includes the following steps:
[0007] 1) Provide a first substrate, the first substrate being a glass substrate having opposing first and second sides, and form a first through-groove in the first substrate by employing a process of simultaneous etching from the first and second sides of the first substrate; provide a second substrate, the second substrate having opposing bonding and non-bonding sides;
[0008] 2) Bond the second side of the first substrate to the bonding side of the second substrate;
[0009] 3) A first capacitor is formed by depositing a MIM multilayer covering the first through-hole on the first side of the first substrate;
[0010] In any of the above steps, there is also a step of fabricating a connection via on the first substrate, and a step of fabricating a connection line on the second substrate;
[0011] 4) A first wiring layer is formed on a first side of the first substrate and the connection via is formed into a first metallized via; the first capacitor is connected to the connection line through the first wiring layer and the first metallized via.
[0012] Optionally, the process of simultaneously etching from the first and second sides of the first substrate employs laser-induced etching, using a picosecond or femtosecond laser to irradiate and focus inside the glass, modifying it through the nonlinear absorption and thermal effects of the glass, and then performing wet etching on the glass. This significantly increases the etching rate in the modified glass region, allowing for the fabrication of blind holes / through holes / through grooves / blind groove structures on the glass.
[0013] Optionally, the glass substrate is a silicate glass substrate or a quartz glass substrate, and the thickness between the first side and the second side is 30µm-500µm; the first through-groove extends through the thickness direction; the characteristic dimension of the first through-groove is 1µm-20µm, and the aspect ratio is 10-200. The first through-groove can be elongated, hexagonal, or a circular structure with through holes. When it is elongated, the characteristic dimension refers to its width.
[0014] Optionally, in step 1), a plurality of first through slots are etched to form a first through slot array, and the distance between adjacent first through slots is 1um-20um; the MIM multilayer covers the through slot array area.
[0015] Optionally, the MIM multilayer comprises a first metal layer, a dielectric layer, and a second metal layer deposited sequentially; the thicknesses of the first metal layer and the second metal layer are 10 nm to 500 nm, respectively, and the thickness of the dielectric layer is 5 nm to 50 nm.
[0016] Optionally, the connection line includes a second metallized via and a second wiring layer, the second wiring layer being disposed on the non-bonded side, and the second metallized via penetrating the bonded side and the non-bonded side; the first metallized via is connected to the second metallized via.
[0017] Optionally, it further includes fabricating a second capacitor in the second substrate:
[0018] A second through-groove is formed in the second substrate. After bonding, a second capacitor is formed by depositing a MIM multilayer covering the second through-groove on the non-bonded surface of the second substrate. The second capacitor is connected to the connection line.
[0019] Optionally, a plurality of the first through slots are arranged to form a first through slot array; a plurality of the second through slots are arranged to form a second through slot array, wherein the extending directions of the first through slots and the second through slots are perpendicular to each other.
[0020] A capacitor is obtained by the above-described preparation method; the capacitor includes a first substrate and a second substrate bonded together, wherein the first substrate has a first through-slot, and a multilayer MIM covering the first through-slot forms a first capacitor; the first substrate also has metallized vias and a first wiring layer; the second substrate has connection lines; the first capacitor is connected to the connection lines through the first wiring layer and the metallized vias.
[0021] Optionally, the second substrate is further provided with a second through-slot, the surface of which is covered with a multilayer MIM to form a second capacitor, which is connected to the connection line.
[0022] In a preferred embodiment, a method for fabricating a glass-based deep trench capacitor is based on glass etching processes (such as laser-induced etching) and glass bonding processes. The two bonded substrates are defined as a first substrate supporting the main body of the deep trench capacitor and a second substrate providing the bottom of the capacitor. The first substrate is made of materials such as silicate glass or quartz glass. High-density first through-grooves and connecting vias are fabricated using laser-induced etching or dry etching processes. The surface roughness and thickness uniformity of the first substrate are controlled to meet bonding requirements by controlling the etching process and post-processing (such as CMP, polishing). The second substrate is made of semiconductor substrates (silicon, silicon-on-insulator, III / V compound semiconductors) or quartz glass, silicate glass, etc., and has opposing bonding and non-bonding surfaces. The bonding surface needs to be deposited with or have a material that can bond with the first substrate and must meet the surface roughness and thickness uniformity requirements for bonding. The unbonded surface can be fabricated with any structure as needed, such as a redistribution layer, pad, bump, or a high-density trench structure identical to the substrate, and includes a second metallized via penetrating both the bonded and unbonded surfaces. The first and second substrates are bonded to complete the deep trench structure fabrication. Atomic layer deposition (ALD) and etching processes are then used to fabricate a deep trench capacitor on the first substrate to form the first capacitor. After fabricating the deep trench capacitor, the connecting vias can be metallized to interconnect with the second metallized via, and the remaining structures, such as the wiring layer on the surface of the first substrate, can be fabricated, ultimately realizing the fabrication of the deep trench capacitor testing, interconnection, and integration structure.
[0023] The beneficial effects of this invention are as follows:
[0024] (1) The glass-based deep trench capacitor structure has high processing efficiency and excellent consistency between the bottom roughness and depth of the trench, which improves the uniformity of capacitance value, optimizes the breakdown voltage and leakage current, and improves the yield and process stability.
[0025] (2) It is applicable to a wide variety of glass types, has few restrictions on substrate structure and size, is compatible with semiconductor processes and has flexible process routes, and has small deep trench feature size, high verticality and high aspect ratio, which can greatly improve capacitance density.
[0026] (3) It can be integrated into glass-based filters, glass substrates and other structures, and has high flexibility. It can also be used to process three-dimensional deep trench capacitors by bonding two glass with groove structures, thereby further improving capacitance density and device performance.
[0027] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description
[0028] Figure 1a This is a schematic cross-sectional view of the first substrate in Example 1. Figure 1b This is a top view schematic diagram of the first substrate in Example 1;
[0029] Figure 2 This is a cross-sectional schematic diagram of the second substrate with fabricated connection lines in Example 1;
[0030] Figure 3 This is a schematic diagram of the bonding between the first substrate and the second substrate in Example 1;
[0031] Figure 4 This is a schematic diagram of depositing a first capacitor on a first substrate after bonding, as shown in Example 1.
[0032] Figure 5 This is a partially enlarged schematic diagram of the first capacitor in Example 1;
[0033] Figure 6 A schematic diagram of the connection circuit is made for the bonding structure of Example 1, thus obtaining the capacitor structure of Example 1;
[0034] Figure 7a This is a schematic cross-sectional view of the second substrate in Example 2. Figure 7b This is a top view of the second substrate in Example 2;
[0035] Figure 8 This is a schematic diagram of a capacitor with a double deep-groove capacitor structure according to Example 2. Detailed Implementation
[0036] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments. The accompanying drawings are merely illustrative to facilitate a better understanding of the invention, and their specific proportions can be adjusted according to design requirements. The "upper" and "lower" relationships of relative elements and the definitions of "front" and "back" in the graphics described herein should be understood by those skilled in the art to refer to the relative positions of the components; therefore, they can all be flipped to present the same component, and all of this should fall within the scope disclosed in this specification.
[0037] Furthermore, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof mean "at least comprising."
[0038] Example 1
[0039] like Figure 1a This is a cross-sectional view of the first substrate 101 used to support the deep trench capacitor body. Figure 1b This is a top view of the first substrate 101. The first substrate 101 is mainly made of materials such as silicate glass and quartz glass, and its main component is silicon dioxide. The first substrate 101 has opposing first sides 101a and second sides 101b, with a thickness between the first sides 101a and second sides 101b ranging from 30 to 500 μm, preferably 200 μm; the lateral dimension is not limited and can be a 1×1 cm square, a 4, 6, or 8-inch wafer, or a glass square plate from 510×515 mm to 600×600 mm. A high aspect ratio, high density array of first through-slots 102 is fabricated on the first substrate 101 using a laser-induced etching process. The feature size of the first through-slots 102 ranges from 1 μm to 20 μm, and the aspect ratio of the deep slots ranges from 10 to 200, depending on the glass material, process parameters, and design; the preferred feature size is 10 μm, and the aspect ratio is 20. The morphology of the first through-slots 102 can be as follows, depending on the design. Figure 1b The first through-slot 102, which is a long strip or other shape arranged parallel to each other along the X direction, extends along the Y direction and is perpendicular to the X and Y directions. In the formed through-slot array, the spacing between adjacent first through-slots 102 is 1µm-20µm. In addition to the through-slot array serving as the sidewall of the deep trench capacitor, first connection vias 103a for vertical interconnection can be simultaneously fabricated on the first substrate 101.
[0040] Specifically, laser-induced etching utilizes a high-energy femtosecond laser to create induced regions inside the glass, altering the local chemical structure and stress state, thus significantly increasing the etching rate in those areas. Subsequent wet etching, performed in a chemical etching solution, preferentially dissolves these induced regions due to changes in their physicochemical properties, achieving anisotropic etching and ultimately forming trenches or conical structures.
[0041] After the fabrication of the structure on the first substrate 101 is completed, the surface roughness of the second side 101b and the thickness uniformity of the first substrate 101 need to be controlled to meet the bonding requirements. This can be achieved through physical polishing or chemical mechanical polishing. Typical values required for optical contact between the two planar plates are a surface roughness of less than 0.5 nm, a total thickness variation (TTV) of less than 5 µm, and a flatness of less than 30 µm.
[0042] Figure 2 This diagram provides a cross-sectional example of the second substrate 201 at the bottom of the capacitor. The main body of the second substrate 201 can be any material that can be bonded to the first substrate 101, typically a semiconductor substrate (silicon, silicon-on-insulator, III / V compound semiconductor) or quartz glass, silicate glass, etc. The second substrate 201 has opposing bonding sides 201a and non-bonding sides 201b. For the second substrate 201, which is made of a different material than the first substrate 101, a layer of metal or inorganic material (such as silicon, silicon dioxide) is typically deposited on the surface of the bonding side 201a. The thickness and size of the second substrate 201 are not limited; as a support, the second substrate 201 is typically thicker and larger than the first substrate 101. The surface roughness and thickness uniformity of the bonding side 201a must meet the bonding requirements. In this embodiment, a second metallized via 202 is pre-fabricated on the second substrate 201, penetrating the bonding side 201a and the non-bonding side 201b. A second wiring layer 203 and a second dielectric layer 204 are formed on the non-bonding side 201b to create connection lines. After bonding with the first substrate 101, this structure can be ultimately fabricated into a device with deep trench capacitors for testing, interconnection, and integration.
[0043] like Figure 3 The second side 101b of the first substrate 101 is bonded to the bonding side 201a of the second substrate 201. The bonding process can use one or more methods, such as hydrophilic bonding, thermoforming, anodic bonding, or laser bonding, depending on the material, thickness, and size of the first and second substrates. Annealing can be performed on the bonded structure to eliminate internal stress and enhance reliability. Thus, the bottom of the first through-hole 102 is closed by the bonding side 201a of the second substrate 201, forming a deep trench structure; the first connecting via 103a is vertically connected to the second metallized via 202.
[0044] refer to Figure 4 and Figure 5A first capacitor 104 is formed by depositing a multilayer MIM (Metal Injection Molding) on the first side 101a of the bonded first substrate 101 using atomic layer deposition (ALD). Specifically, this includes a first metal layer 1041, a dielectric layer 1042, and a second metal layer 1043 arranged sequentially. The MIM multilayer is deposited on the surface of the array region of the first through-hole 102, enabling high capacitance density integration. Commonly used metal layer materials are titanium nitride, ruthenium, and ruthenium oxide, with thicknesses ranging from 10 to 500 nm. Commonly used dielectric layer materials are high-k dielectric materials or ultra-high-k dielectric materials such as hafnium oxide, titanium oxide, and aluminum oxide, with thicknesses ranging from 5 to 50 nm. The number of MIM layers can be flexibly adjusted according to design and requirements. After the deposition of the multilayer structure is completed, etching is required to expose each metal layer for interconnection and testing.
[0045] After completing the deep trench capacitor machining, refer to Figure 6 Metal is deposited in the first connecting via 103a to form a first metallized via 103, thereby achieving vertical interconnection with the second metallized via 202. A first wiring layer 105 and a first dielectric layer 106 are fabricated on the first side 101a of the first substrate 101, and the first capacitor 104 is led out through the first wiring layer 105 and the first metallized via 103. Solder balls 205 for surface mounting are fabricated on the second wiring layer 203 of the second substrate 201. Before metallization, the first connecting via 103a may require etching, laser ablation, or other processes to remove any residues of dielectric material deposited inside the glass via after the first metallized via 103a, thus avoiding interference with the electrical connection between the first metallized via 103 and the second metallized via 202.
[0046] In addition, in other embodiments, if the first connecting via 103a is not pre-processed, the vias for vertical connection of the first substrate and the second substrate can be simultaneously processed using processes such as laser ablation after bonding, and connection lines can be fabricated.
[0047] This embodiment uses a glass laser-induced etching process to fabricate high aspect ratio through-grooves within the glass. The etching of the through-grooves begins from both sides of the glass, allowing for faster etching through the induced region and enabling the fabrication of structures with higher verticality and aspect ratio. The glass with the through-grooves is then bonded to blank glass to achieve the deep groove structure. Deep grooves achieved using this method exhibit high verticality, a flat groove bottom, and uniform groove depth, significantly improving capacitance density, yield, and process stability.
[0048] Example 2
[0049] The first through-groove 102 and the first connecting through-hole 103a of the first substrate 101 in Embodiment 2 are configured and processed in the same way as in Embodiment 1, and are similarly formed as shown in the figure. Figure 1a and 1b The structure shown.
[0050] In this embodiment, the second substrate 301 is a glass substrate, having opposing bonding sides 301a and non-bonding sides 301b. An array of second through-holes 302 and a second connecting via 303a are formed using a processing method similar to that of the first substrate. Figure 7a As shown. Reference Figure 7b The second through slot 302 is set perpendicular to the first through slot 102, that is, the second through slot 302 is arranged along the Y direction in the array, and the long strip-shaped second through slot 302 extends along the X direction.
[0051] The first substrate 101 and the second substrate 301 are bonded together on their bonding sides 301a, so that the first through-hole 102 and the second through-hole 302 intersect and are arranged with the first connecting via 103a and the second connecting via 303a corresponding vertically. Then, through atomic layer deposition, electroplating, photolithography, etching, and other processes, the first connecting via 103a of the first substrate 101 is metallized to form a first metallized via 103, and a first wiring layer 105 and a first dielectric layer 106 are fabricated; and the second connecting via 303a of the second substrate 301 is metallized to form a second metallized via 303, and a second wiring layer 305 and a second dielectric layer 306 are fabricated, along with solder balls 307 for surface mounting. Before metallization, the connecting vias may require etching, laser ablation, or other processes to remove any residue inside the glass vias after dielectric material deposition, to avoid affecting their electrical connection. Figure 8 As shown, the final product can be fabricated into a dual deep-groove capacitor structure interconnected via metallized vias, enabling the fabrication of deep-groove capacitors with dual devices or double the capacitance density. This embodiment achieves the fabrication of a three-dimensional deep-groove capacitor by bonding two glass elements with groove structures, further improving capacitance density and device performance.
[0052] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of this application can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.
[0053] The above embodiments are only used to further illustrate a deep trench capacitor processing method and capacitor of the present invention. However, the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A method for processing a deep trench capacitor, characterized in that, Includes the following steps: 1) A first substrate is provided, the first substrate being a glass substrate having opposing first and second sides, and a first through-groove is formed in the first substrate by a process of simultaneous etching from the first and second sides of the first substrate; A second substrate is provided, the second substrate having opposing bonded sides and unbonded sides; 2) Bond the second side of the first substrate to the bonding side of the second substrate; 3) A first capacitor is formed by depositing a MIM multilayer covering the first through-hole on the first side of the first substrate; In any of the above steps, there is also a step of fabricating a connection via on the first substrate, and a step of fabricating a connection line on the second substrate; 4) A first wiring layer is formed on a first side of the first substrate and the connection via is formed into a first metallized via; the first capacitor is connected to the connection line through the first wiring layer and the first metallized via.
2. The method for processing a deep trench capacitor according to claim 1, characterized in that: The process of synchronous etching from the first and second sides of the first substrate is a laser-induced etching process, which uses picosecond or femtosecond lasers to irradiate and focus on the interior of the glass substrate to modify it, and then performs wet etching.
3. The method for processing a deep trench capacitor according to claim 1, characterized in that: The glass substrate is a silicate glass substrate or a quartz glass substrate, and the thickness between the first side and the second side is 30um-500um; the first through groove extends through the thickness direction; the characteristic size of the first through groove is 1um-20um, and the aspect ratio is 10-200.
4. The method for processing a deep trench capacitor according to claim 1, characterized in that: In step 1), multiple first through slots are etched to form a first through slot array, and the distance between adjacent first through slots is 1um-20um; the MIM multilayer covers the through slot array area.
5. The processing method for a deep trench capacitor according to claim 1, characterized in that: The MIM multilayer comprises a first metal layer, a dielectric layer, and a second metal layer deposited sequentially; the thicknesses of the first metal layer and the second metal layer are 10 nm to 500 nm, respectively, and the thickness of the dielectric layer is 5 nm to 50 nm.
6. The method for processing a deep trench capacitor according to claim 1, characterized in that: The connection line includes a second metallized via and a second wiring layer, the second wiring layer is disposed on the non-bonded side, and the second metallized via penetrates the bonded side and the non-bonded side; the first metallized via is connected to the second metallized via.
7. The method for processing a deep trench capacitor according to claim 1, characterized in that: This also includes fabricating a second capacitor in the second substrate: A second through-groove is formed in the second substrate. After bonding, a second capacitor is formed by depositing a MIM multilayer covering the second through-groove on the non-bonded surface of the second substrate. The second capacitor is connected to the connection line.
8. The method for processing a deep trench capacitor according to claim 7, characterized in that: Multiple first through slots are arranged to form a first through slot array; multiple second through slots are arranged to form a second through slot array, and the extension directions of the first through slots and the second through slots are perpendicular to each other.
9. A capacitor, characterized in that: The capacitor is obtained by the preparation method according to any one of claims 1 to 8; the capacitor includes a first substrate and a second substrate bonded together, wherein the first substrate has a first through-slot, and the first through-slot is covered by a multilayer MIM to form a first capacitor; the first substrate also has metallized vias and a first wiring layer; the second substrate has connection lines; the first capacitor is connected to the connection lines through the first wiring layer and the metallized vias.
10. The capacitor according to claim 9, characterized in that: The second substrate is further provided with a second through-slot, and the surface of the second through-slot is covered with MIM multilayer to form a second capacitor, which is connected to the connection line.