Nitride semiconductor transistor

Abstract

The present disclosure provides a nitride semiconductor transistor capable of improving current density. The nitride semiconductor transistor includes: a first channel layer having a first upper surface having nitrogen polarity; the ferroelectric nitride semiconductor layer is positioned on the first upper surface and is provided with a second upper surface with metal polarity; the second channel layer is positioned on the second upper surface and is provided with a third upper surface with metal polarity; and the first barrier layer is positioned on the third upper surface and is provided with a fourth upper surface with metal polarity.

Description

Technical Field

[0001] This disclosure relates to nitride semiconductor transistors. Background Technology

[0002] A high electron mobility transistor (HEMT) with multiple channels has been proposed in the past.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-183311

[0006] In recent years, the requirements for further increases in current density have become increasingly stringent. Summary of the Invention

[0007] The purpose of this disclosure is to provide a nitride semiconductor transistor that can improve current density.

[0008] The nitride semiconductor transistor disclosed herein has: a first channel layer having a first upper surface having nitrogen polarity; a ferroelectric nitride semiconductor layer having a second upper surface having metal polarity above the first upper surface; a second channel layer having a third upper surface having metal polarity above the second upper surface; and a first barrier layer having a fourth upper surface having metal polarity above the third upper surface.

[0009] Invention Effects

[0010] According to this disclosure, current density can be increased. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view showing the nitride semiconductor transistor of the first embodiment.

[0012] Figure 2 This is a diagram illustrating an example of the band structure of a nitride semiconductor transistor according to the first embodiment.

[0013] Figure 3 This is a cross-sectional view (one of) showing a method for manufacturing a nitride semiconductor transistor according to the first embodiment.

[0014] Figure 4 This is a cross-sectional view (part two) showing the manufacturing method of the nitride semiconductor transistor according to the first embodiment.

[0015] Figure 5 This is a cross-sectional view (part 3) showing the manufacturing method of the nitride semiconductor transistor according to the first embodiment.

[0016] Figure 6 This is a cross-sectional view (fourth in a series) showing the manufacturing method of the nitride semiconductor transistor according to the first embodiment.

[0017] Figure 7 This is a cross-sectional view (part 5) showing the manufacturing method of the nitride semiconductor transistor according to the first embodiment.

[0018] Figure 8 This is a cross-sectional view (sixth in a series) showing a method for manufacturing a nitride semiconductor transistor according to the first embodiment.

[0019] Figure 9 This is a cross-sectional view showing the nitride semiconductor transistor of the second embodiment.

[0020] Figure 10 This is a diagram illustrating an example of the band structure of the nitride semiconductor transistor according to the second embodiment.

[0021] Explanation of reference numerals in the attached figures:

[0022] 1, 2: Nitride semiconductor transistors;

[0023] 10: Substrate;

[0024] 21: Buffer layer;

[0025] 21A, 22A, 23A, 24A, 25A, 26A: Upper surface;

[0026] 22: Barrier layer;

[0027] 23: Channel layer;

[0028] 23B, 24B, 25B: Lower surface;

[0029] 24: Ferroelectric nitride semiconductor layer;

[0030] 25: Channel layer;

[0031] 26: Barrier layer;

[0032] 30: Insulating film;

[0033] 30D, 30G, 30S: Opening;

[0034] 40D, 40S: concave part;

[0035] 41D, 41S: Regeneration layer;

[0036] 42D: Drain electrode;

[0037] 42S: Source electrode;

[0038] 43: Gate electrode;

[0039] 120, 220: Nitride semiconductor layers;

[0040] 121, 122, 221, 222: Two-dimensional electron gas;

[0041] E: Electric field. Detailed Implementation

[0042] [Description of embodiments of this disclosure]

[0043] First, the implementation plan disclosed herein will be listed for illustration.

[0044] (1) A nitride semiconductor transistor of one embodiment of the present disclosure has: a first channel layer having a first upper surface having nitrogen polarity; a ferroelectric nitride semiconductor layer having a second upper surface having metal polarity above the first upper surface; a second channel layer having a third upper surface having metal polarity above the second upper surface; and a first barrier layer having a fourth upper surface having metal polarity above the third upper surface.

[0045] The first upper surface of the first channel layer has nitrogen polarity, the second upper surface of the ferroelectric nitride semiconductor layer has metallic polarity, the third upper surface of the second channel layer has metallic polarity, and the fourth upper surface of the first barrier layer has metallic polarity. Therefore, the first and second channel layers can each contain a two-dimensional electron gas. This increases the current density.

[0046] (2) In (1), the ferroelectric nitride semiconductor layer may also comprise aluminum and at least one selected from the group consisting of scandium and yttrium. In this case, large remanent polarization is readily obtained in the ferroelectric nitride semiconductor layer.

[0047] (3) In (1) or (2), the first channel layer may have a first lower surface opposite to the first upper surface, and the second channel layer may have a second lower surface opposite to the third upper surface. The first channel layer contains a first two-dimensional electron gas at a position closer to the first upper surface than the first lower surface, and the second channel layer contains a second two-dimensional electron gas at a position closer to the third upper surface than the second lower surface. In this case, the first two-dimensional electron gas is mainly generated by the spontaneous polarization of the ferroelectric nitride semiconductor layer, and the second two-dimensional electron gas is generated by the spontaneous polarization of the first barrier layer.

[0048] (4) Alternatively, in (1) or (2), the nitride semiconductor transistor may have a second barrier layer having a fifth upper surface with nitrogen polarity, and the first channel layer is situated above the second barrier layer. In this case, a two-dimensional electron gas is generated in the first channel layer through the second barrier layer.

[0049] (5) In (4), the first channel layer may have a first lower surface opposite to the first upper surface, and the second channel layer may have a second lower surface opposite to the third upper surface. The first channel layer contains a first two-dimensional electron gas at a position closer to the first lower surface than the first upper surface, and the second channel layer contains a second two-dimensional electron gas at a position closer to the third upper surface than the second lower surface. In this case, the first two-dimensional electron gas is mainly generated by the spontaneous polarization of the second barrier layer, and the second two-dimensional electron gas is generated by the spontaneous polarization of the first barrier layer.

[0050] (6) In any of (1) to (5), the ferroelectric nitride semiconductor layer may be lattice-matched with the second channel layer. In this case, no compressive strain is generated in the second channel layer due to lattice mismatch between the ferroelectric nitride semiconductor layer and the second channel layer, thereby avoiding the decrease in electron mobility associated with compressive strain.

[0051] (7) In any of (1) to (6), the ferroelectric nitride semiconductor layer may comprise a first nitride having a first lattice constant, and the second channel layer may comprise a second nitride having a second lattice constant, wherein the ratio of the first lattice constant to the second lattice constant is greater than or equal to 99%. In this case, compressive strain on the second channel layer that accompanies lattice mismatch between the ferroelectric nitride semiconductor layer and the second channel layer is less likely to occur, thereby easily avoiding a decrease in electron mobility associated with compressive strain.

[0052] (8) In any of (1) to (7), the ferroelectric nitride semiconductor layer may be an aluminum scandium nitride layer, wherein the ratio of the number of scandium atoms to the total number of aluminum atoms and the scandium atoms in the aluminum scandium nitride layer is less than or equal to 40%. In this case, the aluminum scandium nitride layer is likely to have a wurtzite-type crystal structure.

[0053] (9) In (8), it is also possible that the number of scandium atoms in the aluminum scandium nitride layer is greater than or equal to 10% and less than or equal to 40% of the total number of aluminum atoms and the scandium atoms. In this case, it is less likely to generate compressive strain in the second channel layer that accompanies the lattice mismatch between the ferroelectric nitride semiconductor layer and the second channel layer, thereby easily avoiding the decrease in electron mobility accompanied by compressive strain.

[0054] (10) In any of (1) to (7), the ferroelectric nitride semiconductor layer may also be an aluminum yttrium nitride layer, wherein the ratio of the number of yttrium atoms to the total number of aluminum atoms and the total number of yttrium atoms in the aluminum yttrium nitride layer is less than or equal to 80%. In this case, the aluminum yttrium nitride layer is likely to have a wurtzite-type crystal structure.

[0055] (11) In (10), it is also possible that the number of yttrium atoms in the aluminum yttrium nitride layer is greater than or equal to 10% and less than or equal to 80% of the total number of aluminum atoms and the total number of yttrium atoms.

[0056] [Details of the embodiments disclosed herein]

[0057] The embodiments of this disclosure will now be described in detail, but this disclosure is not limited thereto. It should be noted that in this specification and accompanying drawings, sometimes repeated descriptions are omitted by using the same reference numerals to denote constituent elements having substantially the same functional configuration. In this disclosure, "top view" refers to viewing an object from above. In this disclosure, the direction in which the nitride semiconductor layer is located when viewed from the substrate is defined as upward.

[0058] (First Implementation)

[0059] The first embodiment relates to a nitride semiconductor transistor. A nitride semiconductor transistor is, for example, a gallium nitride-based high electron mobility transistor (HEMT). Figure 1 This is a cross-sectional view showing the nitride semiconductor transistor of the first embodiment.

[0060] like Figure 1 As shown, the nitride semiconductor transistor 1 of the first embodiment has a substrate 10, a nitride semiconductor layer 120, an insulating film 30, a regenerated layer 41S, a regenerated layer 41D, a gate electrode 43, a source electrode 42S, and a drain electrode 42D.

[0061] The substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the substrate 10 is a SiC substrate, the upper surface of the substrate 10 is a carbon (C) polar surface.

[0062] The nitride semiconductor layer 120 has a buffer layer 21, a channel layer 23, a ferroelectric nitride semiconductor layer 24, a channel layer 25, and a barrier layer 26. The nitride semiconductor layer 120 may also have a nucleation layer between the substrate 10 and the buffer layer 21.

[0063] A buffer layer 21 is disposed on the substrate 10. The buffer layer 21 has a nitrogen-polarized upper surface 21A. The buffer layer 21 is, for example, a gallium nitride (GaN) layer. The thickness of the buffer layer 21 is, for example, greater than or equal to 100 nm and less than or equal to 2000 nm.

[0064] The channel layer 23 is situated above the upper surface 21A of the buffer layer 21. The channel layer 23 has a nitrogen-polarized upper surface 23A and a lower surface 23B opposite to the upper surface 23A. The channel layer 23 exhibits polarization extending from the lower surface 23B towards the upper surface 23A. The channel layer 23 is, for example, a gallium nitride (GaN) layer. The thickness of the channel layer 23 is, for example, greater than or equal to 5 nm and less than or equal to 40 nm. The conductivity type of the channel layer 23 is, for example, n-type or undoped (i-type). The channel layer 23 is an example of a first channel layer. The upper surface 23A is an example of a first upper surface, and the lower surface 23B is an example of a first lower surface. Alternatively, the buffer layer 21 and the channel layer 23 may not be distinguished.

[0065] A ferroelectric nitride semiconductor layer 24 is situated above the upper surface 23A of the channel layer 23. The ferroelectric nitride semiconductor layer 24 has an upper surface 24A and a lower surface 24B opposite to the upper surface 24A. The upper surface 24A has metallic polarity, and the lower surface 24B has nitrogen polarity. The ferroelectric nitride semiconductor layer 24 exhibits polarization from the upper surface 24A to the lower surface 24B. The ferroelectric nitride semiconductor layer 24 is, for example, a scandium aluminum nitride (ScAlN) layer. The thickness of the ferroelectric nitride semiconductor layer 24 is, for example, greater than or equal to 5 nm and less than or equal to 40 nm. The composition of the ferroelectric nitride semiconductor layer 24 is, for example, Sc... X Al 1－X N (0 < X ​​≤ 0.4). That is, in the ScAlN layer, the ratio of the number of Sc atoms to the total number of Al atoms and Sc atoms (Sc composition ratio) is greater than 0% and less than or equal to 40%. Upper surface 24A is an example of the second upper surface.

[0066] The channel layer 25 is situated above the upper surface 24A of the ferroelectric nitride semiconductor layer 24. The channel layer 25 has an upper surface 25A with metallic polarity and a lower surface 25B opposite to the upper surface 25A. The channel layer 25 has polarization extending from the upper surface 25A to the lower surface 25B. The channel layer 25 is, for example, a gallium nitride (GaN) layer. The thickness of the channel layer 25 is, for example, greater than or equal to 5 nm and less than or equal to 40 nm. The conductivity type of the channel layer 25 is, for example, n-type or undoped (i-type). The channel layer 25 is an example of a second channel layer. The upper surface 25A is an example of a third upper surface, and the lower surface 25B is an example of a second lower surface.

[0067] A barrier layer 26 is situated above the upper surface 25A of the channel layer 25. The barrier layer 26 has an upper surface 26A with metallic polarity. The barrier layer 26 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron affinity of the barrier layer 26 is less than that of the channel layer 25. The band gap of the barrier layer 26 is larger than that of the channel layer 25. The thickness of the barrier layer 26 is, for example, greater than or equal to 5 nm and less than or equal to 40 nm. The composition of the barrier layer 26 is, for example, Al. Y Ga 1－Y N (0.15 ≤ Y ≤ 0.55). That is, in the AlGaN layer, the ratio of the number of Al atoms to the total number of Al and Ga atoms (Al composition ratio) is greater than or equal to 15% and less than or equal to 55%. The conductivity type of the barrier layer 26 is, for example, n-type or undoped (i-type). The barrier layer 26 is an example of a first barrier layer. The upper surface 26A is an example of a fourth upper surface.

[0068] A recess 40S for the active electrode and a recess 40D for the drain electrode are formed in the nitride semiconductor layer 120. The recesses 40S and 40D penetrate the barrier layer 26, the channel layer 25, and the ferroelectric nitride semiconductor layer 24. The bottom of the recesses 40S and 40D is closer to the lower surface of the nitride semiconductor layer 120 than the upper surface 23A of the channel layer 23. That is, the recesses 40S and 40D are formed deeper than the upper surface 23A of the channel layer 23. The recesses 40S and 40D may also further penetrate the channel layer 23. The bottom of the recesses 40S and 40D may be located in the channel layer 23 or in the buffer layer 21.

[0069] An insulating film 30 is situated on the upper surface 26A of the barrier layer 26. The insulating film 30 is, for example, a silicon nitride (SiN) film. The thickness of the insulating film 30 is, for example, greater than or equal to 5 nm and less than or equal to 100 nm. An opening 30S for the active electrode, an opening 30D for the drain electrode, and an opening 30G for the gate electrode are formed on the insulating film 30. Opening 30S is connected to a recess 40S, and opening 30D is connected to a recess 40D. When viewed from above, opening 30G is located between openings 30S and 30D. Opening 30G extends to the barrier layer 26.

[0070] The regenerated layer 41S is located above the buffer layer 21 or the channel layer 23 within the recess 40S. The regenerated layer 41D is located above the buffer layer 21 or the channel layer 23 within the recess 40D. The regenerated layers 41S and 41D are, for example, n-type GaN layers. The regenerated layers 41S and 41D contain germanium (Ge) or silicon (Si) as n-type impurities.

[0071] The source electrode 42S is located above the regenerated layer 41S, and the drain electrode 42D is located above the regenerated layer 41D. The source electrode 42S is in contact with the regenerated layer 41S, and the drain electrode 42D is in contact with the regenerated layer 41D. The source electrode 42S and the regenerated layer 41S are in ohmic contact, and the drain electrode 42D and the regenerated layer 41D are in ohmic contact.

[0072] When viewed from above, the gate electrode 43 is positioned between the source electrode 42S and the drain electrode 42D. The gate electrode 43 rests on the insulating film 30 and contacts the barrier layer 26 through the opening 30G.

[0073] Here, an example of the band structure of a nitride semiconductor transistor 1 is described. Figure 2 This is a diagram showing an example of the band structure of the nitride semiconductor transistor 1 according to the first embodiment. Figure 2 The image shows the Fermi level EF and the lower end of the conduction band EC. In Figure 2 In the diagram, the horizontal axis represents the depth relative to the upper surface 26A of the barrier layer 26, and the vertical axis represents the energy relative to the Fermi level EF. Figure 2 In the example shown, the buffer layer 21 and the channel layer 23 are assumed to be GaN layers with a combined thickness of 20 nm or more, and the ferroelectric nitride semiconductor layer 24 is a Sc with a thickness of 5 nm. 0.2 Al 0.8 The N-layer, channel layer 25 is a 15nm thick GaN layer, and barrier layer 26 is a 10nm thick Al layer. 0.3 Ga 0.7 N layers.

[0074] In the nitride semiconductor transistor 1, the upper surface 23A of the channel layer 23 has nitrogen polarity, the upper surface 24A of the ferroelectric nitride semiconductor layer 24 has metallic polarity, and the lower surface 24B has nitrogen polarity. Therefore, as Figure 1 and Figure 2 As shown, a two-dimensional electron gas (2DEG) 121 is generated near the upper surface 23A of the channel layer 23. That is, the channel layer 23 contains the two-dimensional electron gas 121 at a position closer to the upper surface 23A than the lower surface 23B. Furthermore, the upper surface 25A of the channel layer 25 has metallic polarity, and the upper surface 26A of the barrier layer 26 also has metallic polarity. Therefore, as... Figure 1 and Figure 2As shown, a two-dimensional electron gas 122 is generated near the upper surface 25A of the channel layer 25. That is, the channel layer 25 contains the two-dimensional electron gas 122 at a position closer to the upper surface 25A than the lower surface 25B. The two-dimensional electron gas 121 is mainly generated by the spontaneous polarization of the ferroelectric nitride semiconductor layer 24, and the two-dimensional electron gas 122 is generated by the spontaneous polarization of the barrier layer 26. The two-dimensional electron gas 121 is an example of a first two-dimensional electron gas, and the two-dimensional electron gas 122 is an example of a second two-dimensional electron gas.

[0075] It should be noted that the polarity of the nitride semiconductor layer can be determined, for example, using an annular bright-field scanning transmission electron microscope (ABF-STEM).

[0076] Next, the manufacturing method of the nitride semiconductor transistor 1 according to the first embodiment will be described. Figures 3-8 This is a cross-sectional view showing a method for manufacturing the nitride semiconductor transistor 1 according to the first embodiment.

[0077] First, such as Figure 3 As shown, for example, a buffer layer 21, a channel layer 23, and a ferroelectric nitride semiconductor layer 24 are sequentially formed on a substrate 10 using metal-organic chemical vapor deposition (MOCVD). Alternatively, after forming the buffer layer 21 and the channel layer 23 using MOCVD, the ferroelectric nitride semiconductor layer 24 can be formed, for example, by sputtering or molecular beam epitaxy (MBE). At this point, the upper surface 21A of the buffer layer 21, the upper surface 23A of the channel layer 23, and the upper surface 24A of the ferroelectric nitride semiconductor layer 24 possess nitrogen polarity.

[0078] Next, as Figure 4As shown, the polarization orientation of the ferroelectric nitride semiconductor layer 24 is reversed by applying an electric field E, greater than or equal to the coercive electric field of the ferroelectric nitride semiconductor layer 24. As a result, the arrangement of atoms in the ferroelectric nitride semiconductor layer 24 changes, with the upper surface 24A of the ferroelectric nitride semiconductor layer 24 exhibiting metallic polarity and the lower surface 24B exhibiting nitrogen polarity. Furthermore, a two-dimensional electron gas 121 is generated near the upper surface 23A of the channel layer 23. The electric field E can be applied, for example, by corona discharge or by applying a voltage between the two electrodes (not shown). Alternatively, the ferroelectric nitride semiconductor layer 24 can be heated to a temperature of approximately 500°C or less when reversing the polarization orientation. It should be noted that regions where the polarization is not reversed may exist within a portion of the ferroelectric nitride semiconductor layer 24.

[0079] Next, as Figure 5 As shown, for example, a channel layer 25 and a barrier layer 26 are sequentially formed on a ferroelectric nitride semiconductor layer 24 using MOCVD. Then, an insulating film 30 is formed on the barrier layer 26.

[0080] Next, as Figure 6 As shown, an opening 30S for the source and an opening 30D for the drain are formed in the insulating film 30, and a recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 120. The opening 30S, opening 30D, recess 40S, and recess 40D can be formed, for example, by using reactive ion etching (RIE) or ion milling with a mask (not shown).

[0081] Next, as Figure 7 As shown, a regenerated layer 41S is formed on the buffer layer 21 or the channel layer 23 within the recess 40S, and a regenerated layer 41D is formed on the buffer layer 21 or the channel layer 23 within the recess 40D. The regenerated layer 41S and the regenerated layer 41D can be formed, for example, by physical vapor deposition (PVD) methods such as evaporation, sputtering, or MBE, or by MOCVD methods.

[0082] Next, as Figure 8 As shown, a source electrode 42S is formed on the regenerated layer 41S, and a drain electrode 42D is formed on the regenerated layer 41D. In the formation of the source electrode 42S and the drain electrode 42D, firstly, a metal layer (not shown) constituting the source electrode 42S and the drain electrode 42D is formed. During the formation of the metal layer, for example, a film is formed using a growth mask (not shown) with openings in the region where the metal layer is formed, and then the growth mask and the metal layer (not shown) formed thereon are removed together. That is, a stripping process is performed.

[0083] Next, an opening 30G for the gate is formed in the insulating film 30 (see reference). Figure 1 The opening 30G can be formed, for example, using a RIE with a mask (not shown). Next, a gate electrode 43 is formed on the insulating film 30, contacting the barrier layer 26 via the opening 30G (see reference). Figure 1 During the formation of the gate electrode 43, for example, a metal layer is formed using a growth mask (not shown) with an opening in the region where the gate electrode 43 is formed, and then the growth mask and the metal layer (not shown) formed thereon are removed together. That is, a stripping process is performed.

[0084] In this way, nitride semiconductor transistors can be manufactured.

[0085] It should be noted that there are no particular limitations on the method and timing for reversing the polarization of the ferroelectric nitride semiconductor layer 24.

[0086] (Second Implementation)

[0087] The second embodiment differs from the first embodiment mainly in the composition of the nitride semiconductor layer. Figure 9 This is a cross-sectional view showing the nitride semiconductor transistor of the second embodiment.

[0088] like Figure 9 As shown, the nitride semiconductor transistor 2 of the second embodiment has a nitride semiconductor layer 220 instead of a nitride semiconductor layer 120.

[0089] The nitride semiconductor layer 220 has a buffer layer 21, a barrier layer 22, a channel layer 23, a ferroelectric nitride semiconductor layer 24, a channel layer 25, and a barrier layer 26. The nitride semiconductor layer 220 may also have a nucleation layer between the substrate 10 and the buffer layer 21.

[0090] A barrier layer 22 is situated on the upper surface 21A of the buffer layer 21. The barrier layer 22 has a nitrogen-polarized upper surface 22A. A channel layer 23 is situated on the upper surface 22A of the barrier layer 22. The barrier layer 22 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron affinity of the barrier layer 22 is less than that of the channel layer 23. The band gap of the barrier layer 22 is larger than that of the channel layer 23. The thickness of the barrier layer 22 is, for example, greater than or equal to 5 nm and less than or equal to 40 nm. The composition of the barrier layer 22 is, for example, Al. Z Ga 1－ZN (0.15 ≤ Z ≤ 0.55). That is, in the AlGaN layer, the ratio of the number of Al atoms to the total number of Al and Ga atoms (Al composition ratio) is greater than or equal to 15% and less than or equal to 55%. The conductivity type of the barrier layer 22 is, for example, n-type or undoped (i-type). The barrier layer 22 is an example of a second barrier layer. The upper surface 22A is an example of a fifth upper surface.

[0091] Recesses 40S and 40D penetrate the barrier layer 26, the channel layer 25, the ferroelectric nitride semiconductor layer 24, and the channel layer 23. Recesses 40S and 40D may also further penetrate the barrier layer 22. The bottom of recesses 40S and 40D may be located within the barrier layer 22 or within the buffer layer 21. A regenerated layer 41S is located within recesses 40S above either the barrier layer 22 or the buffer layer 21. A regenerated layer 41D is located within recesses 40D above either the barrier layer 22 or the buffer layer 21.

[0092] The other configurations of the nitride semiconductor transistor 2 are the same as those of the nitride semiconductor transistor 1.

[0093] Here, an example of the band structure of the nitride semiconductor transistor 2 is described. Figure 10 This is a diagram showing an example of the band structure of the nitride semiconductor transistor 2 according to the second embodiment. Figure 10 The image shows the Fermi level EF and the lower end of the conduction band EC. In Figure 10 In the diagram, the horizontal axis represents the depth relative to the upper surface 26A of the barrier layer 26, and the vertical axis represents the energy relative to the Fermi level EF. Figure 10 In the example shown, buffer layer 21 is assumed to be a GaN layer with a thickness greater than or equal to 10 nm, and barrier layer 22 is an Al layer with a thickness of 30 nm. 0.3 Ga 0.7 The N-layer, channel layer 23 is a 10nm thick GaN layer, and ferroelectric nitride semiconductor layer 24 is a 5nm thick Sc 0.2 Al 0.8 The N-layer, channel layer 25 is a 15nm thick GaN layer, and barrier layer 26 is a 10nm thick Al layer. 0.3 Ga 0.7 N layers.

[0094] In the nitride semiconductor transistor 2, the upper surface 22A of the barrier layer 22 is nitrogen-polarized, and the upper surface 23A of the channel layer 23 is also nitrogen-polarized. Therefore, as... Figure 9 and Figure 10As shown, a two-dimensional electron gas 221 is generated near the lower surface 23B of the channel layer 23. That is, the channel layer 23 contains the two-dimensional electron gas 221 at a position closer to the lower surface 23B than the upper surface 23A. Furthermore, the upper surface 25A of the channel layer 25 has metallic polarity, and the upper surface 26A of the barrier layer 26 also has metallic polarity. Therefore, as... Figure 9 and Figure 10 As shown, a two-dimensional electron gas 222 is generated near the upper surface 25A of the channel layer 25. That is, the channel layer 25 contains the two-dimensional electron gas 222 at a position closer to the upper surface 25A than the lower surface 25B. The two-dimensional electron gas 221 is mainly generated by the spontaneous polarization of the barrier layer 22, and the two-dimensional electron gas 222 is generated by the spontaneous polarization of the barrier layer 26. The two-dimensional electron gas 221 is an example of a first two-dimensional electron gas, and the two-dimensional electron gas 222 is an example of a second two-dimensional electron gas.

[0095] It should be noted that the composition of the ferroelectric nitride semiconductor layer 24 is not limited. When the ferroelectric nitride semiconductor layer 24 and the channel layer 25 are lattice-matched, no compressive strain is generated in the channel layer 25 due to lattice mismatch between the ferroelectric nitride semiconductor layer 24 and the channel layer 25, thereby avoiding the reduction in electron mobility in the two-dimensional electron gas 122 or the two-dimensional electron gas 222 accompanied by compressive strain.

[0096] The ferroelectric nitride semiconductor layer 24 may also contain yttrium (Y) instead of scandium (Sc), or both scandium and yttrium. That is, the ferroelectric nitride semiconductor layer 24 may also contain aluminum and at least one selected from the group consisting of scandium and yttrium. In this case, a large remanent polarization is easily obtained in the ferroelectric nitride semiconductor layer 24. The ferroelectric nitride semiconductor layer 24 may further contain gallium (Ga), or indium (In). When the ferroelectric nitride semiconductor layer 24 contains gallium, the coercive electric field of the ferroelectric nitride semiconductor layer 24 can be reduced. The lattice constants along the a-axis of various nitrides are shown in Table 1.

[0097] [Table 1]

[0098]

[0099] The Sc contained in the ferroelectric nitride semiconductor layer 24 X Al 1－X N is an example of a first nitride, Sc X Al 1－XThe lattice constant of N is an example of a first lattice constant. The GaN contained in the channel layer 25 is an example of a second nitride, and the lattice constant of GaN is an example of a second lattice constant. When the ratio of the first lattice constant to the second lattice constant is greater than or equal to 99%, compressive strain on the channel layer 25 associated with lattice mismatch between the ferroelectric nitride semiconductor layer 24 and the channel layer 25 is less likely to occur, thereby easily avoiding the reduction in electron mobility in the two-dimensional electron gas 122 or the two-dimensional electron gas 222 associated with compressive strain.

[0100] It should be noted that even if the lattice constants of the channel layer 23 and the ferroelectric nitride semiconductor layer 24 are different, if the thickness of the ferroelectric nitride semiconductor layer 24 is less than or equal to the critical film thickness, the interatomic spacing in the ferroelectric nitride semiconductor layer 24 becomes the same as the interatomic spacing in the channel layer 23. Therefore, if both the channel layer 23 and the channel layer 25 are GaN layers, the interatomic spacing in the channel layer 25 becomes the same as the interatomic spacing in the ferroelectric nitride semiconductor layer 24, and thus the stress associated with lattice strain hardly acts on the channel layer 25.

[0101] When the ferroelectric nitride semiconductor layer 24 is an aluminum scandium nitride layer, the aluminum scandium nitride layer tends to have a wurtzite-type crystal structure when the ratio of the number of Sc atoms to the total number of Al atoms and Sc atoms (Sc composition ratio) in the aluminum scandium nitride layer is less than or equal to 40%. When the ratio of the number of Sc atoms to the total number of Al atoms and Sc atoms is greater than or equal to 10% and less than or equal to 40%, compressive strain towards the channel layer 25 associated with lattice mismatch between the ferroelectric nitride semiconductor layer 24 and the channel layer 25 is less likely to occur, thus easily avoiding the decrease in electron mobility in the two-dimensional electron gas 122 or two-dimensional electron gas 222 associated with compressive strain.

[0102] When the ferroelectric nitride semiconductor layer 24 is an aluminum yttrium nitride layer, the aluminum yttrium nitride layer tends to have a wurtzite-type crystal structure when the ratio of the number of Y atoms in the aluminum yttrium nitride layer to the total number of Al atoms and Y atoms (Y composition ratio) is less than or equal to 80%. When the ratio of the number of Y atoms to the total number of Al atoms and Y atoms is greater than or equal to 10% and less than or equal to 80%, compressive strain on the channel layer 25 associated with lattice mismatch between the ferroelectric nitride semiconductor layer 24 and the channel layer 25 is less likely to occur, thus easily avoiding the decrease in electron mobility in the two-dimensional electron gas 122 or two-dimensional electron gas 222 associated with compressive strain.

[0103] The Sc and Y composition ratios can be determined, for example, by transmission electron microscope-energy dispersive X-ray spectroscopy (TEM-EDX), secondary ion mass spectrometry (SIMS), or X-ray photoelectron spectroscopy.

[0104] The embodiments have been described in detail above, but this disclosure is not limited to specific embodiments, and various modifications and alterations can be made within the scope of the claims.

Claims

1. A nitride semiconductor transistor, comprising: The first channel layer has a first upper surface that is nitrogen polar; A ferroelectric nitride semiconductor layer is located above the first upper surface and has a second upper surface with metallic polarity; The second channel layer is located above the second upper surface and has a third upper surface with metallic polarity; as well as The first barrier layer is located above the third upper surface and has a fourth upper surface with metallic polarity.

2. The nitride semiconductor transistor according to claim 1, wherein, The ferroelectric nitride semiconductor layer comprises aluminum and at least one selected from the group consisting of scandium and yttrium.

3. The nitride semiconductor transistor according to claim 1 or 2, wherein, The first channel layer has a first lower surface opposite to the first upper surface. The second channel layer has a second lower surface opposite to the third upper surface. The first channel layer contains a first two-dimensional electron gas at a location closer to the first upper surface than the first lower surface. The second channel layer contains a second two-dimensional electron gas at a location closer to the third upper surface than the second lower surface.

4. The nitride semiconductor transistor according to claim 1 or 2, wherein, The nitride semiconductor transistor has a second barrier layer, which has a fifth upper surface with nitrogen polarity. The first channel layer is located above the second barrier layer.

5. The nitride semiconductor transistor according to claim 4, wherein, The first channel layer has a first lower surface opposite to the first upper surface. The second channel layer has a second lower surface opposite to the third upper surface. The first channel layer contains a first two-dimensional electron gas at a position closer to the first lower surface than the first upper surface. The second channel layer contains a second two-dimensional electron gas at a location closer to the third upper surface than the second lower surface.

6. The nitride semiconductor transistor according to claim 1 or 2, wherein, The ferroelectric nitride semiconductor layer is lattice-matched with the second channel layer.

7. The nitride semiconductor transistor according to claim 1 or 2, wherein, The ferroelectric nitride semiconductor layer comprises a first nitride having a first lattice constant. The second channel layer contains a second nitride having a second lattice constant. The ratio of the first lattice constant to the second lattice constant is greater than or equal to 99%.

8. The nitride semiconductor transistor according to claim 1 or 2, wherein, The ferroelectric nitride semiconductor layer is an aluminum scandium nitride layer. In the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and the scandium atoms is less than or equal to 40%.

9. The nitride semiconductor transistor according to claim 8, wherein, In the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and the scandium atoms is greater than or equal to 10% and less than or equal to 40%.

10. The nitride semiconductor transistor according to claim 1 or 2, wherein, The ferroelectric nitride semiconductor layer is an aluminum yttrium nitride layer. In the aluminum yttrium nitride layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and the total number of yttrium atoms is less than or equal to 80%.

11. The nitride semiconductor transistor according to claim 10, wherein, In the aluminum yttrium nitride layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and the total number of yttrium atoms is greater than or equal to 10% and less than or equal to 80%.

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