Semiconductor device and electronic equipment

Abstract

According to the semiconductor device and the electronic equipment provided by the invention, because the interface of the grid electrode has Schottky contact and ohmic contact at the same time, the advantages of low grid leakage of a Schottky contact type P-GaN grid device and stable threshold voltage of an ohmic contact type P-GaN grid device can be combined; the problem that the threshold voltage is unstable due to the fact that the potential of the P-GaN cap layer in a traditional Schottky contact type P-GaN gate relatively floats is solved. Moreover, the P-type doped GaN structure with the P-type lightly doped GaN layer and the P-type heavily doped GaN layer can achieve the self-clamping of the leakage current of the grid electrode, and solves a problem that the leakage current of the ohmic contact type P-GaN grid device is too large. The P-type extension layer is arranged on the side, close to the drain electrode, of the P-GaN cap layer, so that the 2DEG concentration in a channel between a gate and a drain can be modulated, off-state peak electric field distribution, located on the side, close to the drain electrode, of the P-GaN cap layer under high-voltage bias, of the device is optimized, and the dynamic on-resistance characteristic of the device is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and electronic device. Background Technology

[0002] High Electron Mobility Transistors (HEMTs) based on AlGaN / GaN heterostructures can meet the requirements of power electronic systems in terms of high temperature, high voltage, high frequency and miniaturization, and have become one of the best candidates for realizing next-generation high power density power systems.

[0003] During switching operations, GaN devices may exhibit dynamic instabilities in parameters such as on-resistance, threshold voltage, and output capacitance due to changes in time or voltage. These dynamic changes can affect the overall performance and efficiency of the device, leading to issues such as current collapse and threshold voltage drift. th shift), degradation of dynamic on-resistance (R) ON Issues such as these can ultimately lead to device and even system reliability failures. Mitigating these dynamic effects is crucial for ensuring device reliability. As the mainstream solution for realizing enhancement-mode GaN HEMT power devices, P-GaN gates have seen a surge in research on their stability, reliability, and robustness in recent years. Analyzing the relevant mechanisms and considering how to improve the stability and reliability of P-GaN HEMT power devices has become the main motivation for proposing various optimized processes or device structures. The stability issues of P-GaN HEMT power devices can be mainly divided into two major problems: threshold voltage instability introduced by the P-GaN gate and dynamic on-resistance degradation. Summary of the Invention

[0004] This disclosure provides a semiconductor device and electronic device that optimizes gate leakage current and threshold voltage stability issues, and improves the dynamic conduction characteristics of the device.

[0005] The specific plan disclosed herein is as follows: On one hand, embodiments of this disclosure provide a semiconductor device, including: A substrate, a channel layer, and a barrier layer are stacked sequentially. The source and drain are spaced apart on the side of the barrier layer and / or the channel layer away from the substrate; A P-GaN cap layer is located on the side of the barrier layer away from the substrate and between the source and the drain. The source, the P-GaN cap layer and the drain are arranged sequentially along a first direction, which is parallel to the substrate. A p-type doped GaN structure is located on the side of the P-GaN cap layer away from the substrate; the p-type doped GaN structure includes: a lightly doped p-type GaN layer on the P-GaN cap layer, and a heavily doped p-type GaN layer on the lightly doped p-type GaN layer; wherein the cross-sectional widths of the heavily doped p-type GaN layer and the lightly doped p-type GaN layer along the first direction are both smaller than the cross-sectional width of the P-GaN cap layer along the first direction. The gate is located on the side of the P-GaN cap layer away from the substrate and covers the P-type doped GaN structure. The interface between the gate and the P-GaN cap layer and the lightly doped P-type GaN layer is a Schottky contact, and the interface between the gate and the heavily doped P-type GaN layer is an ohmic contact. A P-type extension layer is located on the side of the barrier layer away from the substrate and on the side of the P-GaN cap layer near the drain. The P-type extension layer is connected to the P-GaN cap layer.

[0006] In some embodiments, in the semiconductor device provided in the present disclosure, the thickness of the P-type extension layer is less than the thickness of the P-GaN cap layer.

[0007] In some embodiments, in the semiconductor device provided in the present disclosure, the P-type heavily doped GaN layer, the P-type lightly doped GaN layer and the P-type extended layer are all strip-shaped structures extending along a second direction, which is perpendicular to the first direction and parallel to the substrate.

[0008] In some embodiments, in the semiconductor device provided in the present disclosure, the P-type heavily doped GaN layer includes a row of P-type heavily doped GaN portions spaced apart along a second direction, and the P-type lightly doped GaN layer includes a row of P-type lightly doped GaN portions spaced apart along the second direction. The P-type heavily doped GaN portions and the P-type lightly doped GaN portions are in one-to-one contact to form a columnar structure; wherein, the second direction is perpendicular to the first direction and parallel to the substrate.

[0009] In some embodiments, in the semiconductor device provided in the present disclosure, the P-type heavily doped GaN layer includes multiple rows of P-type heavily doped GaN portions spaced apart along a second direction, each of the P-type heavily doped GaN portions being distributed in a lattice; the P-type lightly doped GaN layer includes multiple rows of P-type lightly doped GaN portions spaced apart along the second direction, each of the P-type lightly doped GaN portions being distributed in a lattice; the P-type heavily doped GaN portions and the P-type lightly doped GaN portions are in one-to-one contact to form a columnar structure; wherein, the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

[0010] In some embodiments, in the semiconductor device provided in the present disclosure, the P-type extension layer includes a plurality of P-type extensions spaced apart along the second direction, and the P-type extensions are aligned one-to-one with a row of columnar structures arranged along the first direction.

[0011] In some embodiments, in the semiconductor device provided in the present disclosure, the orthographic projection shape of the columnar structure on the substrate includes at least one of a circle, a square, and a hexagon.

[0012] In some embodiments, in the semiconductor device provided in the present disclosure, the cross-sectional widths of the heavily doped P-type GaN layer and the lightly doped P-type GaN layer are equal along the first direction.

[0013] In some embodiments, in the semiconductor device provided in the present disclosure, the gate completely encapsulates the P-type doped GaN structure, and the cross-sectional width of the gate along the first direction is smaller than the cross-sectional width of the P-GaN cap layer along the first direction.

[0014] Accordingly, this disclosure also provides an electronic device, including any of the semiconductor devices described above in this disclosure.

[0015] The beneficial effects of this disclosure are as follows: This disclosure provides a semiconductor device and electronic device with a P-type doped GaN structure forming an ohmic island. Because the gate interface contains both Schottky and ohmic contacts, a JFET-like equivalent structure is formed at the gate. This combines the advantages of low gate leakage current of Schottky contact P-GaN gate devices and stable threshold voltage of ohmic contact P-GaN gate devices, solving the problem of unstable threshold voltage caused by the relatively fluctuating potential of the P-GaN cap layer in traditional Schottky contact P-GaN gates. By adding a lightly doped P-type GaN layer between the heavily doped P-type GaN layer and the P-GaN cap layer, a lower hole density distribution is achieved from the heavily doped P-type GaN layer to the P-GaN cap layer with weaker doping, adjusting the size of the "leakage path" and making the JFET-like structure easier to turn off under high gate voltage conditions, effectively "pinching off" the "leakage path" of the ohmic island. Devices with an ohmic island structure address the threshold instability issue caused by net charge accumulation in Schottky contact P-GaN gate devices at lower gate voltages due to the presence of a "discharge" channel. Simultaneously, at higher gate voltages, the "discharge" channel of this type of JFET is "pinched off," clamping the gate leakage current and resolving the problem of excessive gate leakage in ohmic contact P-GaN gate devices. Furthermore, by placing a P-type extension layer on the drain side of the P-GaN cap layer, the 2DEG concentration in the gate-drain channel can be modulated, optimizing the off-state peak electric field distribution on the drain side of the P-GaN cap layer under high-voltage bias, thus improving the device's dynamic on-resistance characteristics. Therefore, this disclosure achieves a synergistic optimization effect by combining the ohmic island structure and the P-type extension layer, simultaneously improving threshold voltage stability, reducing gate leakage current, and enhancing the device's dynamic conduction characteristics, significantly improving the stability and reliability of P-GaN HEMT devices. Attached Figure Description

[0016] Figure 1 This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure; Figure 2 for Figure 1 A cross-sectional schematic diagram; Figure 3 for Figure 1 A top-view plan view; Figure 4 A three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure; Figure 5 for Figure 4 A cross-sectional schematic diagram; Figure 6 for Figure 4 A top-view plan view; Figure 7 A three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure; Figure 8 for Figure 7 A cross-sectional schematic diagram; Figure 9 for Figure 7 A top-view plan view. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes do not represent the precise shape of the illustrated regions or reflect true proportions; they are only intended to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0018] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0019] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0020] This disclosure provides a semiconductor device, such as... Figures 1-3 As shown, Figure 1 This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure. Figure 2 for Figure 1 A cross-sectional schematic diagram, Figure 3 for Figure 1 The schematic diagram is shown in the top view. The semiconductor device includes: a substrate 1, a channel layer 2, and a barrier layer 3 stacked sequentially. Specifically, the channel layer 2 and the barrier layer 3 form a heterojunction. The heterojunction forms a high-density two-dimensional electron gas (2DEG) at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects, that is, a 2DEG channel is formed. The source electrode 4 and the drain electrode 5 are spaced apart and located on the side of the barrier layer 3 and / or the channel layer 2 away from the substrate 1. For example, the source electrode 4 and the drain electrode 5 may both be located on the side of the barrier layer 3 away from the substrate 1, or the source electrode 4 and the drain electrode 5 may both be in contact with the channel layer 2 through vias penetrating the barrier layer 3 (i.e., the source electrode 4 and the drain electrode 5 may both be located on the side of the channel layer 2 away from the substrate 1), or a portion of the source electrode 4 and the drain electrode 5 may be located on the side of the barrier layer 3 away from the substrate 1, and the other portion may be in contact with the channel layer 2 through vias penetrating the barrier layer 3. Specifically, the source electrode 4 and the drain electrode 5 form an ohmic contact with the barrier layer 3 and the channel layer 2. The P-GaN cap layer 6 is located on the side of the barrier layer 3 away from the substrate 1, and is situated between the source 4 and the drain 5. The source 4, the P-GaN cap layer 6, and the drain 5 are arranged sequentially along the first direction X, which is parallel to the substrate 1. The P-GaN cap layer 6 is used to ensure the threshold stability of the device. A p-type doped GaN structure 7 is located on the side of the p-GaN cap layer 6 away from the substrate 1. The p-type doped GaN structure 7 includes a p-type lightly doped GaN layer 71 on the p-GaN cap layer 6 and a p-type heavily doped GaN layer 72 on the p-type lightly doped GaN layer 71. The cross-sectional widths of the p-type heavily doped GaN layer 72 and the p-type lightly doped GaN layer 71 along the first direction X are both smaller than the cross-sectional width of the p-GaN cap layer 6 along the first direction X. Gate 8 is located on the side of P-GaN cap layer 6 away from substrate 1 and covers P-type doped GaN structure 7. The interface between gate 8 and P-GaN cap layer 6 and P-type lightly doped GaN layer 71 is a Schottky contact, and the interface between gate 8 and P-type heavily doped GaN layer 72 is an ohmic contact, which is a P-type ohmic contact. The P-type extension layer 9 is located on the side of the barrier layer 3 away from the substrate 1 and on the side of the P-GaN cap layer 6 near the drain 5. The P-type extension layer 9 is connected to the P-GaN cap layer 6.

[0021] The semiconductor device provided in this disclosure has an ohmic island structure for the P-type doped GaN. Since the gate interface contains both Schottky and ohmic contacts, forming a JFET-like structure on the gate, it combines the advantages of low gate leakage current of Schottky contact P-GaN gate devices and stable threshold voltage of ohmic contact P-GaN gate devices. This solves the problem of unstable threshold voltage caused by the relatively fluctuating potential of the P-GaN cap layer in traditional Schottky contact P-GaN gates. By adding a lightly doped P-type GaN layer between the heavily doped P-type GaN layer and the P-GaN cap layer, a lower hole density distribution is achieved from the heavily doped P-type GaN layer to the P-GaN cap layer with weaker doping. This adjusts the size of the "leakage path," making the JFET-like structure easier to turn off under high gate voltage conditions, effectively "pinching off" the "leakage path" of the ohmic island. Devices with an ohmic island structure, due to the presence of a "discharge" channel at lower gate voltages, solve the threshold instability problem caused by net charge accumulation in Schottky contact P-GaN gate devices. Simultaneously, at higher gate voltages, the "discharge" channel of this type of JFET is "pinched off," clamping the gate leakage current. That is, once the gate voltage is sufficiently high, the gate leakage current is clamped and no longer increases, solving the problem of excessive gate leakage current in ohmic contact P-GaN gate devices. Furthermore, by setting a P-type extension layer on the drain side of the P-GaN cap layer, the 2DEG concentration in the gate-drain channel can be modulated, optimizing the off-state peak electric field distribution on the drain side of the P-GaN cap layer under high-voltage bias, thus improving the device's dynamic on-resistance characteristics. Therefore, this disclosure, by combining the ohmic island structure and the P-type extension layer, achieves a superimposed optimization effect, improving both threshold voltage stability and reducing gate leakage current, while also enhancing the device's dynamic conduction characteristics, significantly improving the stability and reliability of P-GaN HEMT devices.

[0022] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the thickness of the P-type extension layer 9 is less than the thickness of the P-GaN cap layer 6. Thus, by setting a thin P-type extension layer 9 on the side of the P-GaN cap layer 6 near the drain 5, and since the P-type extension layer 9 is connected to the P-GaN cap layer 6, the potential of the P-type extension layer 9 is controlled by the gate 7. When the device is in the on state, the 2DEG concentration in the channel below the P-type extension layer 9 can be restored by the gate voltage control. Therefore, the P-type extension layer 9 can modulate the 2DEG concentration in the channel between the gate and drain, optimize the distribution of the peak electric field in the off state of the device, suppress leakage current, and improve the breakdown voltage.

[0023] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3As shown, the P-type heavily doped GaN layer 72 includes a row of P-type heavily doped GaN portions 721 spaced apart along the second direction Y, and the P-type lightly doped GaN layer 71 includes a row of P-type lightly doped GaN portions 711 spaced apart along the second direction Y. The P-type heavily doped GaN portions 721 and P-type lightly doped GaN portions 711 are in one-to-one contact to form a columnar structure M. The second direction Y is perpendicular to the first direction X and parallel to the substrate 1. This disclosure optimizes the channel pinch-off effect into a two-dimensional pinch-off effect by setting a row of dispersed columnar structures M with P-type heavily doped GaN portions 721 and P-type lightly doped GaN portions 711 along the second direction Y and utilizing the curvature effect. Therefore, the dispersed columnar structure M can achieve the gate leakage self-clamping effect of the device with a wider range of P-GaN ohm island sizes, and the hole injection channels introduced by the ohm islands may be beneficial to the control of the P-type extension layer.

[0024] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the P-type extension layer 9 includes multiple P-type extensions 91 spaced apart along the second direction Y. The P-type extensions 91 are aligned with a row of columnar structures M arranged along the first direction X. By providing multiple segmented P-type extensions 91 on the side of the P-GaN cap layer 6 near the drain 5, the multiple P-type extensions 91 form a comb-like structure, which can selectively modulate the 2DEG concentration in the gate-drain channel, optimize the off-state peak electric field distribution of the device on the side of the P-GaN cap layer 6 near the drain 5 under high voltage bias, and the segmented P-type extensions 91 can reduce the parasitic capacitance and resistance effects they introduce, improving the dynamic on-resistance characteristics of the device. Therefore, by combining the Ohm island of the columnar structure M with the segmented P-type extensions, a P-GaN gate enhancement HEMT device with high threshold stability, low gate leakage current, and excellent dynamic on-resistance characteristics can be realized, greatly improving the stability and reliability of the P-GaN HEMT device.

[0025] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the orthographic projection shape of the columnar structure M on the substrate 1 includes at least one of a circle, a square, and a hexagon. In this embodiment, a circle is used as an example.

[0026] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3As shown, the cross-sectional widths of the heavily doped P-type GaN layer 72 and the lightly doped P-type GaN layer 71 along the first direction X are equal, that is, the cross-sectional widths of the heavily doped P-type GaN portion 721 and the lightly doped P-type GaN portion 711 along the first direction X are equal. This simplifies the fabrication process and improves the gate reliability of P-GaN gate enhancement type HEMT power devices. Of course, the cross-sectional widths of the heavily doped P-type GaN layer 72 and the lightly doped P-type GaN layer 71 are not limited to being equal; for example, the cross-sectional width of the lightly doped P-type GaN layer 71 can be greater than the cross-sectional width of the heavily doped P-type GaN layer 72.

[0027] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the orthographic projections of the lightly doped P-type GaN portion 711 and the heavily doped P-type GaN portion 721 on substrate 1 coincide. This further simplifies the fabrication process and improves the gate reliability of P-GaN gate enhancement-type HEMT power devices. Of course, the orthographic projections of the lightly doped P-type GaN portion 711 and the heavily doped P-type GaN portion 721 on substrate 1 are not limited to coinciding; for example, the orthographic projection area of ​​the lightly doped P-type GaN portion 711 on substrate 1 can be larger than that of the heavily doped P-type GaN portion 721 on substrate 1.

[0028] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 and Figure 2 As shown, in implementing both ohmic and Schottky contacts between the gate 8 and the P-type doped GaN structure 7, after forming the P-type doped GaN structure 7, a low work function metal can be directly used to form the gate, followed by high-temperature annealing. The portion contacting the heavily doped P-type GaN layer 72 in the P-type doped GaN structure 7 forms an ohmic contact, while the portion contacting the lightly doped P-type GaN layer 71 in the P-type doped GaN structure 7 forms a Schottky contact. Of course, other methods can also be used, and this disclosure does not limit this approach.

[0029] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-3 As shown, the gate 8 completely encapsulates the P-type doped GaN structure 7, and the cross-sectional width of the gate 8 along the first direction X is smaller than the cross-sectional width of the P-GaN cap layer 6 along the first direction X. This can further improve device performance.

[0030] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 4-6 As shown, Figure 4 This is a three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure. Figure 5 for Figure 4A cross-sectional schematic diagram, Figure 6 for Figure 4 A top-view plan view, this embodiment and Figures 1-3 The difference is as follows: the P-type heavily doped GaN layer 72 includes multiple rows of P-type heavily doped GaN portions 721 spaced apart along the second direction Y, with each P-type heavily doped GaN portion 721 arranged in a lattice pattern; the P-type lightly doped GaN layer 71 includes multiple rows of P-type lightly doped GaN portions 711 spaced apart along the second direction Y, with each P-type lightly doped GaN portion 711 arranged in a lattice pattern; the P-type heavily doped GaN portions 721 and the P-type lightly doped GaN portions 711 are in one-to-one contact to form a columnar structure M. This embodiment takes three rows of P-type doped GaN portions 721 spaced apart along the second direction Y and multiple rows of P-type lightly doped GaN portions 711 spaced apart along the second direction Y as an example, but it is not limited to this, for example, it can also be two rows, four rows, etc.; each columnar structure M is arranged in a lattice pattern, and through the lattice structure design, the curvature effect is utilized to further optimize the gate leakage self-clamping effect. Specifically, the dot matrix distribution can be orthogonal, hexagonal, or other distribution methods. This embodiment takes an orthogonal distribution as an example, that is, it is distributed in an array along the first direction X and the second direction Y. The distribution density and size of each columnar structure M can be designed as needed, and this disclosure does not limit it.

[0031] In some embodiments, such as Figures 1-6 As shown, the area of ​​the P-type ohmic contact of the entire device can be adjusted by adjusting the size of the columnar structure M, further balancing the problems of large gate leakage current and unstable threshold of traditional P-GaN gate device ohmic contacts and Schottky contacts.

[0032] In some embodiments, such as Figures 1-6 As shown, by adjusting parameters such as the height, radius, and doping concentration of the columnar structure M, the columnar structure can more easily achieve gate leakage self-clamping effect, enabling the device to achieve lower gate leakage under the effect of threshold stability.

[0033] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-6 As shown, the width w1 of the gap between two adjacent P-type extensions 91 along the second direction Y is the same as the width w2 of the P-type extension 91 along the second direction Y, i.e., w1 = w2. This improves the effect of optimizing the distribution of the peak electric field in the off-state of the device. Of course, w1 and w2 can also be different.

[0034] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-6As shown, the orthographic projection shape of the P-type extension 91 on the substrate 1 is square, and the width of the P-type extension 91 along the second Y direction is greater than or equal to 50 nm. This can reduce the concentration of the fabrication process. Of course, the orthographic projection shape of the P-type extension 91 on the substrate 1 is not limited to square.

[0035] In some embodiments, such as Figures 1-6 As shown, through process and layout pattern control, the dimensions of the P-type extension 91 on the side of the P-GaN cap layer 6 near the drain 5 can be adjusted, including length, width, height, segment size / duty cycle, etc., to achieve optimal improvement of the device's dynamic on-resistance characteristics.

[0036] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 7-9 As shown, Figure 7 This is a three-dimensional schematic diagram of another semiconductor device provided in the embodiments of this disclosure. Figure 8 for Figure 7 A cross-sectional schematic diagram, Figure 9 for Figure 7 A top-view plan view, this embodiment and Figures 1-3 The difference is that the P-type heavily doped GaN layer 72, the P-type lightly doped GaN layer 71, and the P-type extended layer 9 are all strip-shaped structures extending along the second direction Y. In this embodiment, by setting fin-shaped ohmic islands (P-type doped GaN structure 7) + strip-shaped P-type extended layer 9, it is possible to achieve lower gate leakage current, stable threshold voltage, improved off-state characteristics, and reduce the difficulty of fabrication process.

[0037] In some embodiments, such as Figures 1-9 As shown, the columnar P-type doped GaN structure 7 of this disclosure, compared with the conventional Schottky P-type gate GaN device, has a P-type ohmic contact formed between the gate 8 and the heavily P-type doped GaN layer 72, which provides a discharge channel for holes generated by the irradiation effect. Therefore, the semiconductor device of this disclosure has an irradiation hardening effect.

[0038] In some embodiments, such as Figures 1-9 As shown, the P-type extension layer 9 of this disclosure can effectively suppress the electric field in the radiation-sensitive region, and has a radiation hardening effect compared with traditional P-type gate GaN devices.

[0039] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-9 As shown, the doping concentration of the P-GaN cap layer 6 can be between the doping concentration of the lightly doped P-type GaN layer 71 and the doping concentration of the heavily doped P-type GaN layer 72. In some embodiments, the doping concentration of the heavily doped P-type GaN layer 72 is 1 × 10⁻⁶. 20 ~5×10 20 cm-3 For example, 1×10 20 cm -3 2×10 20 cm -3 3×10 20 cm -3 4×10 20 cm -3 and 5×10 20 cm -3 The doping concentration of the lightly doped p-type GaN layer 71 is 1 × 10⁻⁶. 17 ~5×10 18 cm -3 For example, 1×10 17 cm -3 2×10 17 cm -3 3×10 17 cm -3 4×10 17 cm -3 5×10 17 cm -3 6×10 17 cm -3 7×10 17 cm -3 8×10 17 cm -3 9×10 17 cm -3 1×10 18 cm -3 2×10 18 cm -3 3×10 18 cm -3 4×10 18 cm -3 and 5×10 18 cm -3 etc.; the doping concentration of P-GaN cap layer 6 is 5×10⁶. 18 ~5×10 19 cm -3 For example, 5×10 18 cm -3 6×10 18 cm -3 7×10 18 cm -3 8×10 18 cm -3 9×10 18 cm -3 1×10 19 cm -3 2×1019 cm -3 3×10 19 cm -3 4×10 19 cm -3 and 5×10 19 cm -3 The doping concentration of the lightly doped P-type GaN layer 71 and the doping concentration of the P-GaN cap layer 6 can be the same or different.

[0040] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-9 As shown, the doping concentration of the P-type extension layer 9 can be the same as that of the P-GaN cap layer 6.

[0041] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-9 As shown, the thickness of the heavily doped P-type GaN layer 72 can be 5~30 nm, such as 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, etc.; the thickness of the lightly doped P-type GaN layer 71 can be 10~200 nm, such as 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.; and the thickness of the P-GaN cap layer 6 can be 50~120 nm, such as 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, etc. This can further improve the problem of threshold instability caused by the relatively fluctuating potential of the P-GaN cap layer in traditional Schottky contact P-GaN gates, and further optimize the gate leakage self-clamping effect.

[0042] In some embodiments, such as Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 7 and Figure 8 As shown, the semiconductor device provided in this embodiment of the present disclosure further includes a dielectric layer (not shown in this disclosure) filled between the source 4, the drain 5 and the gate 8. The material of the dielectric layer may be SiO2, SiNx, AlN, etc.

[0043] In some embodiments, the substrate 1 of this disclosure may be a Si, SiC, GaN, sapphire, diamond, SOI, QST composite substrate, etc., and this disclosure does not limit it.

[0044] In some embodiments, the channel layer 2 of this disclosure may be made of GaN; the barrier layer 3 may be made of Al(In,Ga)N. For example, the barrier layer 3 may be an AlN binary alloy layer, an AlGaN, AlInN, or InGaN ternary alloy layer, or an AlInGaN quaternary alloy layer.

[0045] In some embodiments, the P-GaN cap layer 6 of this disclosure may be GaN doped with at least one of magnesium (Mg), iron (Fe), zinc (Zn) and carbon (C).

[0046] In some embodiments, the material of the source 4 of this disclosure may be one or more combinations of Ti, Al, TiN, and Au; the material of the drain 5 of this disclosure may be one or more combinations of Ti, Al, TiN, and Au; and the material of the gate 8 of this disclosure may be one or more combinations of Ti, Al, Ni, and Au.

[0047] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 7 and Figure 8 As shown, it also includes a buffer layer 10 located between the substrate 1 and the channel layer 2, and the material of the buffer layer 10 includes at least one of AlN, AlGaN and GaN.

[0048] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 7 and Figure 8 As shown, it may also include a nucleation layer 11 located between the substrate 1 and the buffer layer 10. The nucleation layer 11 can avoid the problem of cracks in the buffer layer 10 caused by lattice mismatch and thermal mismatch when the buffer layer 10 is formed directly on the substrate 1, which would lead to a decrease in crystal quality. The material of the nucleation layer 11 can be one or more combinations of AlN, GaN, and AlGaN.

[0049] To better understand the semiconductor devices provided in the embodiments of this disclosure, the fabrication process of the semiconductor devices is described in detail.

[0050] In some embodiments, the fabrication process of the semiconductor device disclosed herein may specifically include the following steps: (1) Using methods such as MOCVD, nucleation layer, buffer layer, channel layer and barrier layer are grown on the substrate.

[0051] (2) A P-type material layer is formed on the barrier layer. According to the strength of P-type doping, it is divided into three layers, from bottom to top: a P-GaN cap layer, a lightly doped P-type GaN layer, and a heavily doped P-type GaN layer, which are used to form the threshold voltage of the device.

[0052] (3) Partially etch the P-type material layer to the P-GaN cap layer, defining a P-type doped GaN structure including multiple columnar structures; then partially etch the P-GaN cap layer, defining the width of the P-GaN cap layer and the thickness of the P-type extension layer; wherein, the distribution area of ​​the ohm islands of the columnar structure is smaller than the distribution area of ​​the P-GaN cap layer.

[0053] (4) Completely etch the remaining P-type material layers, except for the P-type extension layer and the P-GaN cap layer, to the barrier layer.

[0054] (5) A source and a drain are formed on the barrier layer and the channel layer, wherein the source and the drain are in ohmic contact with the barrier layer and the channel layer.

[0055] (6) A gate is formed on the barrier layer and around the P-type doped GaN structure, wherein the gate forms a Schottky contact with the P-GaN cap layer and the lightly doped P-type GaN layer, and an Ohmic contact with the heavily doped P-type GaN layer. The cross-sectional width of the gate along the first direction (i.e., the arrangement direction of the source, P-GaN cap layer and drain) is smaller than the cross-sectional width of the P-GaN cap layer along the first direction, and the gate completely encloses the P-type doped GaN structure.

[0056] (7) A dielectric layer is formed between the source and the gate and between the drain and the gate, located above the barrier layer.

[0057] Based on the same inventive concept, this disclosure provides an electronic device including the semiconductor device described above. Since the principle by which this electronic device solves the problem is similar to that of the semiconductor device described above, the implementation of the electronic device provided in this disclosure can refer to the implementation of the semiconductor device described above, and repeated details will not be elaborated further.

[0058] In some embodiments, the electronic device provided in this disclosure can be a power supply, a photovoltaic system, an industrial motor, or an electric vehicle, etc. The disclosed embodiments do not impose any special limitations on the specific form of the electronic device.

[0059] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0060] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: A substrate, a channel layer, and a barrier layer are stacked sequentially. The source and drain are spaced apart on the side of the barrier layer and / or the channel layer away from the substrate; A P-GaN cap layer is located on the side of the barrier layer away from the substrate and between the source and the drain. The source, the P-GaN cap layer and the drain are arranged sequentially along a first direction, which is parallel to the substrate. A p-type doped GaN structure is located on the side of the P-GaN cap layer away from the substrate; The P-type doped GaN structure includes: a lightly doped P-type GaN layer on the P-GaN cap layer, and a heavily doped P-type GaN layer on the lightly doped P-type GaN layer; wherein the cross-sectional width of the heavily doped P-type GaN layer and the lightly doped P-type GaN layer along the first direction is smaller than the cross-sectional width of the P-GaN cap layer along the first direction. The gate is located on the side of the P-GaN cap layer away from the substrate and covers the P-type doped GaN structure. The interface between the gate and the P-GaN cap layer and the lightly doped P-type GaN layer is a Schottky contact, and the interface between the gate and the heavily doped P-type GaN layer is an ohmic contact. A P-type extension layer is located on the side of the barrier layer away from the substrate and on the side of the P-GaN cap layer near the drain. The P-type extension layer is connected to the P-GaN cap layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the P-type extension layer is less than the thickness of the P-GaN cap layer.

3. The semiconductor device as described in claim 1, characterized in that, The P-type heavily doped GaN layer, the P-type lightly doped GaN layer, and the P-type extended layer are all strip-shaped structures extending along a second direction, which is perpendicular to the first direction and parallel to the substrate.

4. The semiconductor device as claimed in claim 1, characterized in that, The heavily doped P-type GaN layer includes a row of heavily doped P-type GaN portions spaced apart along a second direction, and the lightly doped P-type GaN layer includes a row of lightly doped P-type GaN portions spaced apart along the second direction. The heavily doped P-type GaN portions and the lightly doped P-type GaN portions are in one-to-one contact to form a columnar structure; wherein, the second direction is perpendicular to the first direction and parallel to the substrate.

5. The semiconductor device as claimed in claim 1, characterized in that, The heavily doped P-type GaN layer includes multiple rows of heavily doped P-type GaN portions spaced apart along a second direction, each of the heavily doped P-type GaN portions being distributed in a lattice; the lightly doped P-type GaN layer includes multiple rows of lightly doped P-type GaN portions spaced apart along the second direction, each of the lightly doped P-type GaN portions being distributed in a lattice; the heavily doped P-type GaN portions and the lightly doped P-type GaN portions are in one-to-one contact to form a columnar structure; wherein, the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

6. The semiconductor device as claimed in claim 4 or 5, characterized in that, The P-type extension layer includes a plurality of P-type extensions spaced apart along the second direction, and the P-type extensions are aligned one-to-one with a row of columnar structures arranged along the first direction.

7. The semiconductor device as claimed in claim 4 or 5, characterized in that, The orthographic projection shape of the columnar structure on the substrate includes at least one of a circle, a square, and a hexagon.

8. The semiconductor device as claimed in claim 1, characterized in that, The cross-sectional widths of the heavily doped P-type GaN layer and the lightly doped P-type GaN layer are equal along the first direction.

9. The semiconductor device as claimed in claim 1, characterized in that, The gate completely encloses the P-type doped GaN structure, and the cross-sectional width of the gate along the first direction is smaller than the cross-sectional width of the P-GaN cap layer along the first direction.

10. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1-9.

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