LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure with trench drain electrode and preparation method
By introducing a trench drain electrode structure and an inner oxide liner into LDMOS devices, a capacitive coupling effect and a high conductivity current channel are formed, solving the problem of balancing breakdown voltage and specific on-resistance, and achieving better device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGZHOU CANSEMI TECH INC
- Filing Date
- 2026-01-21
- Publication Date
- 2026-04-21
AI Technical Summary
Existing LDMOS devices cannot avoid increasing the specific on-resistance while improving the breakdown voltage, or they cannot avoid degrading the breakdown voltage while reducing the specific on-resistance, resulting in a trade-off between device performance.
A trench drain electrode structure is adopted, in which the drain electrode is integrated into the trench of the drift region. Combined with the inner oxide liner and heavily doped polysilicon, a capacitor structure and a high conductivity current channel are formed, which disperses the electric field peak and enhances the carrier aggregation effect.
This improves the breakdown voltage of LDMOS devices while significantly reducing specific on-resistance, thereby enhancing the device's withstand voltage and reliability, and improving miniaturization and integration.
Smart Images
Figure CN121908590A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device design and manufacturing technology, and in particular to an LDMOS device structure and fabrication method with a trench drain electrode. Background Technology
[0002] In the field of semiconductor device design and manufacturing technology, BCD (Bipolar-CMOS-DMOS) technology, as a key integrated circuit manufacturing technology, can integrate bipolar devices, CMOS devices, and DMOS devices on the same chip. This combines the high transconductance and strong load driving capability of bipolar devices with the high integration and low power consumption of CMOS devices, achieving complementary performance advantages of each type of device. In the field of high-voltage power integrated circuits, laterally diffused metal-oxide-semiconductor (LDMOS) devices are often used in BCD processes because of their excellent compatibility with CMOS processes and the fact that their drain, source, and gate are all located on the chip surface, facilitating internal interconnection with low-voltage signal circuits. This allows them to meet the system's requirements for high voltage withstand and power control.
[0003] To improve the breakdown voltage of LDMOS devices, various structures have been proposed in existing technologies. For example, the traditional shallow trench isolation (STI) field plate LDMOS structure modulates the current path on the device surface and reduces the surface electric field by etching and filling oxide on the bulk silicon surface, thereby increasing the breakdown voltage. However, this structure is prone to current concentration at the STI corners, leading to reliability issues such as hot carrier injection (HCI), which limits the synergistic optimization of its breakdown voltage and specific on-resistance performance. Another traditional structure uses local silicon oxide (LOCOS) to form the field plate to modulate the surface electric field of the device. Given the high compatibility of LOCOS with CMOS processes, this method has been widely used in BCD process LDMOS devices. However, this structure is also prone to electric field concentration at the LOCOS corners under the gate polysilicon, leading to premature breakdown of the semiconductor device.
[0004] Therefore, although the above structure improves device performance to some extent, there is still a difficulty in achieving a balance between breakdown voltage and specific on-resistance in power integrated circuits, which is crucial for achieving superior performance. How to increase breakdown voltage while suppressing the increase in specific on-resistance, or how to reduce specific on-resistance while avoiding breakdown voltage degradation, are pressing technical problems that need to be solved in this field. Summary of the Invention
[0005] The present invention aims to provide an LDMOS device structure and fabrication method with a trench drain electrode, so as to improve the breakdown voltage of LDMOS, reduce the specific on-resistance of LDMOS, and enhance device performance.
[0006] To achieve the above objectives, a first aspect of the present invention provides an LDMOS device structure having a trench drain electrode, comprising: A substrate having a drift region and a channel region therein, a contact surface between the drift region and the channel region, and a gate oxide layer covering the surfaces of the drift region and the channel region; An active region is provided in the channel region, and a gate is provided on the surface of the gate oxide layer. The gate intersects with the vertical extension surface of the contact surface. The source region surface is provided with a first contact hole, and the gate surface is provided with a second contact hole, the first contact hole and the second contact hole penetrating the gate oxide layer; The drift zone is provided with grooves, and the walls of the grooves are covered with an inner oxide lining. A trench drain electrode structure is provided in the trench, one end of which is in contact with the drift region, and the other end of which penetrates the gate oxide layer.
[0007] The aforementioned LDMOS device structure integrates the drain electrode within the trench of the drift region, forming a trench drain electrode structure with trench geometry characteristics. This fundamentally alters the electric field distribution and current path of traditional planar LDMOS devices. Utilizing its trench structure and inner oxide liner, the device guides the high electric field region during breakdown voltage to the trench sidewalls and bottom region, effectively dispersing the electric field peak and avoiding premature breakdown caused by excessive electric field concentration. This trench drain electrode thus improves the LDMOS breakdown voltage.
[0008] Simultaneously, in the LDMOS device's on-state, the bottom surface of the trench drain electrode structure is connected to the drift region and energized. The side surface of the trench drain electrode structure is separated from the drift region by the inner oxide liner, thus forming a capacitor structure. When a voltage is applied to the trench drain electrode structure and the gate, this capacitor structure generates a capacitive coupling effect, causing the drift region near the inner oxide liner to act as the negative electrode relative to the trench drain electrode structure. Electrons accumulate on the surface of the drift region near the inner oxide liner, significantly increasing the carrier concentration in this region and forming a high-conductivity current channel. This high-conductivity current channel significantly reduces the total resistance when current flows through the drift region, thereby significantly reducing the device's specific on-resistance.
[0009] Furthermore, by adjusting the ion concentration gradient along the trench wall in the drift region, combined with adjusting the depth of the trench drain electrode structure, higher withstand voltage can be achieved within a limited device volume. This is beneficial for the miniaturization and integration of LDMOS devices, ultimately increasing the breakdown voltage of LDMOS while reducing its specific on-resistance, resulting in superior device performance compared to traditional structures.
[0010] Furthermore, a drain region is provided in the drift region, the drain region being located at the bottom of the trench; a third contact hole is filled in the trench, one end of the third contact hole contacting the drain region, and the other end of the third contact hole penetrating the gate oxide layer; wherein: The drain area and the third contact hole together form the trench drain electrode structure.
[0011] In this implementation, the drain region is formed by high-concentration ion implantation into the drift region at the bottom of the trench. When the LDMOS device is in the on state, the drain region and the rest of the drift region are conductive. The third contact hole is directly connected to the drain region at the bottom of the trench and extends through the entire trench, forming a vertical structure that extends to the surface of the gate oxide layer.
[0012] This trench drain electrode structure is based on a third contact hole. When the LDMOS device is in the on state, the third contact hole filled in the trench is separated from the drift region by an inner oxide layer, thus forming a capacitor structure. The metal structure of the third contact hole serves as an electrode of this capacitor structure. When a voltage is applied to the trench drain electrode structure and the gate, it can effectively enhance the carrier aggregation effect near the trench surface in the drift region, forming a high-conductivity current channel on the trench sidewall, thereby reducing the specific on-resistance.
[0013] Meanwhile, the third contact hole metal structure also acts as an electric field plate, which helps to further homogenize the electric field distribution in the drift region and improve the reliability of LDMOS devices.
[0014] Furthermore, the trench is filled with heavily doped polysilicon, the bottom of which contacts the drift region; the top of the heavily doped polysilicon is connected to a third contact hole, which penetrates the gate oxide layer; wherein: The heavily doped polycrystalline silicon and the third contact hole combine to form the trench drain electrode structure.
[0015] In this implementation, heavily doped polysilicon possesses excellent conductivity, and its coefficient of thermal expansion is closer to that of the silicon substrate, effectively reducing thermal stress and improving the long-term stability of the device. This heavily doped polysilicon directly contacts the drift region at the bottom of the trench, forming the main conductive part of the trench drain electrode structure. When the LDMOS device is in the on-state, the bottom of the heavily doped polysilicon is connected to the drift region and energized. The sidewalls of the heavily doped polysilicon are separated from the drift region by an inner oxide layer, forming a stable capacitor structure with the drift region through the inner oxide layer. This ensures that the carrier aggregation effect near the trench surface in the drift region is effectively enhanced when the device is on, forming a high-conductivity current channel on the trench sidewall, thereby reducing the specific on-resistance.
[0016] It should also be noted that, since this implementation fills the trench with heavily doped polysilicon as the main body of the trench drain electrode structure, only a third contact hole needs to be formed on the heavily doped polysilicon at the top of the trench to electrically lead it out to the external metal layer. Compared with the above implementation method that uses the third contact hole as the main body, this structure relaxes the process requirements for contact hole photolithographic alignment and etching depth, increases the process window, and reduces manufacturing difficulty. While achieving technical effects such as optimizing electric field distribution, improving breakdown voltage, and reducing specific on-resistance, it also improves the production yield of LDMOS devices and the consistency of device performance.
[0017] A second aspect of this invention provides a method for fabricating an LDMOS device structure with a trench drain electrode, applicable to fabricating the LDMOS device structure with a trench drain electrode described in the first aspect; the method includes the following steps: Provide substrate; A drift region and a channel region are formed in the substrate, and a contact surface is formed between the drift region and the channel region; A trench is formed in the drift zone, and then an inner oxide lining layer is grown on the trench wall; A first drain electrode structure is formed based on the trench, so that the first drain electrode structure contacts the drift region; A source region is formed in the channel region; A gate oxide layer is formed on the surface of the channel region and the drift region, and then a gate is formed on the surface of the gate oxide layer, such that the gate intersects with the vertical extension surface of the contact surface; A first contact hole is formed on the surface of the source region, and a second contact hole is formed on the surface of the gate. A second drain electrode structure is formed on the surface of the first drain electrode structure, so that the first drain electrode structure and the second drain electrode structure are combined into a trench drain electrode structure.
[0018] The aforementioned method for fabricating an LDMOS device structure with a trench drain electrode first constructs a drift region and a channel region in a substrate, and then forms a trench with an inner oxide liner within the drift region. Subsequently, by constructing a drain electrode structure within this trench, the method integrates the drain electrode within the trench of the drift region, forming a trench drain electrode structure with trench geometry characteristics. This alters the electric field distribution and current path of traditional planar LDMOS devices. Utilizing its trench structure and inner oxide liner, the device guides the high electric field region during breakdown voltage to the trench sidewalls and bottom region, effectively dispersing the electric field peak and avoiding premature breakdown caused by excessive electric field concentration. Thus, the trench drain electrode improves the LDMOS breakdown voltage.
[0019] Simultaneously, in the LDMOS device's on-state, the bottom surface of the trench drain electrode structure is connected to the drift region and energized. The side surface of the trench drain electrode structure is separated from the drift region by the inner oxide liner, thus forming a capacitor structure. When a voltage is applied to the trench drain electrode structure and the gate, this capacitor structure generates a capacitive coupling effect, causing the drift region near the inner oxide liner to act as the negative electrode relative to the trench drain electrode structure. Electrons accumulate on the surface of the drift region near the inner oxide liner, significantly increasing the carrier concentration in this region and forming a high-conductivity current channel. This high-conductivity current channel significantly reduces the total resistance when current flows through the drift region, thereby significantly reducing the device's specific on-resistance.
[0020] Further, the process of forming trenches in the drift region and then growing an inner oxide lining layer on the trench walls includes: The drift region is etched to form trenches in the drift region; A first oxide layer is grown and filled in the trench; The first oxide layer is etched to form the inner oxide layer on the trench wall and expose the drift region at the bottom of the trench.
[0021] In this implementation, a uniform and reliable inner oxide liner layer can be formed on the sidewalls of the trench by first filling the entire structure and then selectively etching. This inner oxide liner layer serves as a key dielectric layer between the subsequently formed trench drain electrode structure and the drift region. Its uniformity and integrity improve the stability of the low-impedance carrier channels formed by the capacitive coupling effect between the trench drain electrode structure and the drift region.
[0022] Meanwhile, by precisely controlling the etching process, the drift region is exposed at the bottom of the trench, creating the necessary conditions for the subsequent formation of the trench drain electrode structure and the conductive channel of the drift region, ensuring that the drain current can be effectively collected.
[0023] Further, the step of forming a first drain electrode structure based on the trench, so that the first drain electrode structure contacts the drift region, includes: Ion implantation is performed on the drift region exposed at the bottom of the trench to form a drain region in the drift region, and the drain region is located at the bottom of the trench; The drain region is used as the first drain electrode structure.
[0024] In this implementation, a high-concentration drain region is formed by ion implantation into the drift region exposed at the bottom of the trench. This drain region serves as the first drain electrode structure, providing a low-resistance, highly reliable ohmic contact interface for the subsequently filled metal contact holes. Together, they act as the drain of the LDMOS device, ensuring smooth transport of carriers from the trench drain electrode structure to the drift region when the LDMOS device is turned on. This also ensures the formation of a high-conductivity current channel on the surface of the drift region near the inner oxide liner.
[0025] Further, the first contact hole is formed on the surface of the source region, and a second contact hole is formed on the surface of the gate; a second drain electrode structure is formed on the surface of the first drain electrode structure, so that the first drain electrode structure and the second drain electrode structure are combined into a trench drain electrode structure, including: An interlayer dielectric layer is grown in the drift region, the channel region, and the gate surface; The interlayer dielectric layer and the gate oxide layer are etched to form a first contact hole extending to the surface of the source region, a second contact hole extending to the surface of the gate region, and a third contact hole extending to the surface of the drain region in the interlayer dielectric layer; A metal mixture is filled into the first contact hole, the second contact hole, and the third contact hole, respectively; The drain area and the third contact hole are combined to form the trench drain electrode structure.
[0026] In this implementation, three contact holes are formed, penetrating to the source, gate, and drain regions, respectively, through the deposition and selective etching of the interlayer dielectric layer. In particular, the third contact hole, which directly penetrates the drain region, constitutes the main body of the trench drain electrode structure and is directly combined with the drain region as the second drain electrode structure. This process not only achieves effective lead-out of the device's electrodes but also fully utilizes the metal contact holes filled in the trench as capacitor plates, enhancing the capacitive coupling effect that reduces specific on-resistance.
[0027] Meanwhile, the metal contact hole structure also functions as an electric field plate, further optimizing the electric field distribution on the device surface and improving the device's withstand voltage and reliability.
[0028] Further, the step of forming a first drain electrode structure based on the trench, so that the first drain electrode structure contacts the drift region, includes: The trench is filled with heavily doped polysilicon so that the bottom of the heavily doped polysilicon contacts the drift region; The heavily doped polycrystalline silicon is used as the first drain electrode structure.
[0029] In this implementation, heavily doped polysilicon is filled into the trench, serving as the first drain electrode structure. This heavily doped polysilicon directly contacts the drift region at the bottom of the trench, forming the main conductive portion of the trench drain electrode structure and acting as an effective channel for drain current. The heavily doped polysilicon filled in the trench acts as a single electrode, with its bottom connected to the drift region and energized. The sides of the heavily doped polysilicon are separated from the drift region by an inner oxide layer, forming a stable capacitance structure with the drift region through the inner oxide layer. This ensures that when the device is turned on, the carrier aggregation effect near the trench surface in the drift region is effectively enhanced, forming a high-conductivity current channel on the trench sidewall, thereby reducing the specific on-resistance.
[0030] Because this implementation fills the trench with heavily doped polysilicon as the main body of the trench drain electrode structure, it simplifies the etching difficulty of the subsequent third contact hole. The third contact hole only needs to be etched to the surface of the heavily doped polysilicon at the top of the trench, which relaxes the process requirements for contact hole photolithography alignment and etching depth, increases the process window, and reduces manufacturing difficulty. While achieving technical effects such as optimizing electric field distribution, improving breakdown voltage and reducing specific on-resistance, it also improves the production yield of LDMOS devices and the consistency of device performance.
[0031] Further, the first contact hole is formed on the surface of the source region, and a second contact hole is formed on the surface of the gate; a second drain electrode structure is formed on the surface of the first drain electrode structure, so that the first drain electrode structure and the second drain electrode structure are combined into a trench drain electrode structure, including: An interlayer dielectric layer is grown in the drift region, the channel region, and the gate surface; The interlayer dielectric layer and the gate oxide layer are etched to form a first contact hole extending to the surface of the source region, a second contact hole extending to the surface of the gate region, and a third contact hole extending to the surface of the heavily doped polysilicon in the interlayer dielectric layer. A metal mixture is filled into the first contact hole, the second contact hole, and the third contact hole, respectively; The heavily doped polysilicon and the third contact hole are combined to form the trench drain electrode structure.
[0032] In this implementation, contact holes are also formed through the deposition and etching of the interlayer dielectric layer. The difference is that the third contact hole only needs to penetrate to the surface of the heavily doped polysilicon. This third contact hole serves as the second drain electrode structure, and its function is to lead the heavily doped polysilicon to the external metal wiring layer. Because the third contact hole no longer needs to be precisely aligned and etched to the semiconductor region at the bottom of the trench, this design significantly reduces the precision requirements for contact hole photolithographic alignment and etching depth. This not only simplifies process control and improves production yield but also ensures the consistency of device performance. While achieving technical effects such as optimized electric field distribution, improved breakdown voltage, and reduced specific on-resistance, it also improves the production yield of LDMOS devices and the consistency of device performance.
[0033] Further, the step of forming a drift region and a channel region in the substrate, and forming a contact surface between the drift region and the channel region, includes: A first photoresist pattern is formed on the substrate; Based on the first photoresist pattern, the substrate is doped with a first type of ion to form a drift region in the substrate; The first photoresist pattern is cleaned and removed; A second photoresist pattern is formed on the substrate; The substrate is doped with a second type of ion based on the second photoresist pattern to form a channel region in the substrate; The second photoresist pattern is cleaned and removed.
[0034] In this implementation, the substrate is subjected to first-type and second-type doping through two independent photolithography and ion implantation processes, respectively, thereby precisely forming the drift region and the channel region. This step-by-step formation method allows for independent and precise control of the doping concentration, junction depth, and lateral position of the two key regions, ensuring that the drift region has ideal breakdown voltage characteristics and that the channel region can form an effective conductive channel. This is the foundation for achieving the expected electrical performance of the device and ensuring the stability of key parameters such as breakdown voltage and threshold voltage. Attached Figure Description
[0035] Figure 1 This is a schematic diagram of an LDMOS device structure with a trench drain electrode provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a trench drain electrode structure formed by combining a drain region with a third contact hole. Figure 3 This is a schematic diagram of a trench drain electrode structure consisting of heavily doped polysilicon and a third contact hole. Figure 4 This is a doping distribution diagram of a conventional LDMOS device provided in an embodiment of the present invention; Figure 5 This is a doping distribution diagram of a device with a trench drain electrode structure formed by combining a drain region and a third contact hole, according to an embodiment of the present invention. Figure 6 This is a doping distribution diagram of a device with a trench drain electrode structure formed by combining heavily doped polysilicon and a third contact hole, provided in an embodiment of the present invention. Figure 7 This is an electric field distribution diagram of a conventional LDMOS device in a breakdown state provided by an embodiment of the present invention; Figure 8 This is an electric field distribution diagram of the breakdown state of a trench drain electrode structure formed by combining the drain region and the third contact hole, provided by an embodiment of the present invention. Figure 9 This is an electric field distribution diagram of the breakdown state of a trench drain electrode structure composed of heavily doped polycrystalline silicon and a third contact hole, provided by an embodiment of the present invention. Figures 10-13 This is a schematic diagram of the fabrication process of an LDMOS device structure with a trench drain electrode provided in an embodiment of the present invention; Wherein: 1. Substrate; 2. Channel region; 3. Drift region; 4. Trench; 41. First oxide layer; 42. Inner oxide liner; 5. Trench drain electrode structure; 51. Drain region; 52. Heavily doped polysilicon; 6. Source region; 7. Gate oxide layer; 8. Gate; 9. Interlayer dielectric layer; 91. First contact hole; 92. Second contact hole; 93. Third contact hole. Detailed Implementation
[0036] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that the following detailed descriptions are exemplary and intended to provide further detailed explanation of the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order.
[0037] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0038] The present invention aims to provide an LDMOS device structure and fabrication method with a trench drain electrode, so as to improve the breakdown voltage of LDMOS, reduce the specific on-resistance of LDMOS, and enhance device performance.
[0039] Please refer to Figure 1 To achieve the above objectives, the first embodiment of the present invention provides an LDMOS device structure with a trench drain electrode, comprising: Substrate 1, wherein a drift region 3 and a channel region 2 are disposed in the substrate 1, and a contact surface is provided between the drift region 3 and the channel region 2, and a gate oxide layer 7 is covered on the surface of the drift region 3 and the channel region 2; The channel region 2 is provided with an active region 6, and the gate oxide layer 7 is provided with a gate 8 on its surface. The gate 8 intersects with the vertical extension surface of the contact surface. The source region 6 has a first contact hole 91 on its surface and the gate 8 has a second contact hole 92 on its surface. The first contact hole 91 and the second contact hole 92 penetrate the gate oxide layer 7. The drift zone 3 is provided with a groove 4, and the groove 4 is covered with an inner oxide layer 42. A trench drain electrode structure 5 is provided in the trench 4. One end of the trench drain electrode structure 5 is in contact with the drift region 3, and the other end of the trench drain electrode structure 5 penetrates the gate oxide layer 7.
[0040] The aforementioned LDMOS device structure integrates the drain electrode within the trench 4 of the drift region 3, forming a trench drain electrode structure 5 with the geometric characteristics of trench 4. This fundamentally alters the electric field distribution and current path of traditional planar LDMOS devices. Utilizing its trench 4 structure and inner oxide layer 42, the device guides the high electric field region during breakdown voltage to the sidewalls and bottom of the trench 4, effectively dispersing the electric field peak and avoiding premature breakdown caused by excessive electric field concentration. This trench drain electrode thus improves the LDMOS breakdown voltage.
[0041] Simultaneously, when the LDMOS device is in the ON state, the bottom surface of the trench drain electrode structure 5 is connected to the drift region 3 and energized. The side surface of the trench drain electrode structure 5 and the drift region 3 are separated by the inner oxide layer 42, thus forming a capacitor structure. When a voltage is applied to the trench drain electrode structure 5 and the gate 8, the capacitor structure generates a capacitive coupling effect, causing the drift region 3 near the inner oxide layer 42 to act as the negative electrode relative to the trench drain electrode structure 5. Electrons accumulate on the surface of the drift region 3 near the inner oxide layer 42, thereby significantly increasing the carrier concentration in this region and forming a high-conductivity current channel. This high-conductivity current channel significantly reduces the total resistance when current flows through the drift region 3, and thus significantly reduces the specific on-resistance of the device.
[0042] Furthermore, by adjusting the ion concentration gradient along the trench wall of the drift region 3 and combining it with the adjustment of the depth of the trench drain electrode structure 5, higher withstand voltage can be achieved within a limited device volume, which is beneficial to the miniaturization and integration of LDMOS devices. Ultimately, this improves the breakdown voltage of LDMOS while reducing the specific on-resistance of LDMOS, resulting in superior device performance compared to traditional structures.
[0043] Specifically, the breakdown voltage drift region (DRFT) of the aforementioned LDMOS device structure mainly follows... Figure 1 The distribution is shown in the direction of the arrows, and the electric field distribution of the device can be adjusted by adjusting the longitudinal doping concentration of the drift region 3.
[0044] Please refer to Figure 2 Furthermore, a drain area 51 is provided in the drift region 3, and the drain area 51 is located at the bottom of the trench 4; a third contact hole 93 is filled in the trench 4, one end of the third contact hole 93 contacts the drain area 51, and the other end of the third contact hole 93 penetrates the gate oxide layer 7; wherein: The drain area 51 and the third contact hole 93 are combined to form the trench drain electrode structure 5.
[0045] In this implementation, the drain region 51 is formed by high-concentration ion implantation into the drift region 3 at the bottom of the trench 4. When the LDMOS device is in the on state, the drain region 51 and the rest of the drift region 3 are conductive. The third contact hole 93 is directly connected to the drain region 51 at the bottom of the trench 4 and penetrates the entire trench 4, forming a vertical structure that extends to the surface of the gate oxide layer 7.
[0046] This trench drain electrode structure 5 is based on the third contact hole 93. When the LDMOS device is in the on state, the third contact hole 93 filled in the trench 4 is separated from the drift region 3 by the inner oxide layer 42, thus forming a capacitor structure. The metal structure of the third contact hole 93 serves as an electrode of this capacitor structure. When a voltage is applied to the trench drain electrode structure 5 and the gate 8, it can effectively enhance the carrier aggregation effect near the surface of the trench 4 in the drift region 3, forming a high conductivity current channel on the sidewall of the trench 4, thereby reducing the specific on-resistance.
[0047] Meanwhile, the metal structure of the third contact hole 93 also acts as a field plate, which helps to further homogenize the electric field distribution in the drift region 3 and improve the reliability of the LDMOS device.
[0048] Specifically, the breakdown voltage drift region (DRFT) of the aforementioned LDMOS device structure mainly follows... Figure 2 The distribution is shown in the direction of the arrows, and the electric field distribution of the device can be adjusted by adjusting the longitudinal doping concentration of the drift region 3.
[0049] Please refer to Figure 3 Furthermore, the trench 4 is filled with heavily doped polysilicon 52, the bottom end of which contacts the drift region 3; the top end of the heavily doped polysilicon 52 is connected to a third contact hole 93, which penetrates the gate oxide layer 7; wherein: The heavily doped polycrystalline silicon 52 and the third contact hole 93 are combined to form the trench drain electrode structure 5.
[0050] In this implementation, the heavily doped polysilicon 52 possesses excellent conductivity, and its coefficient of thermal expansion is closer to that of the silicon substrate 1, effectively reducing thermal stress and improving the long-term stability of the device. This heavily doped polysilicon 52 directly contacts the drift region 3 at the bottom of the trench 4, forming the main conductive part of the trench drain electrode structure 5. When the LDMOS device is on, the bottom of the heavily doped polysilicon 52 is connected to the drift region 3 and energized. The side of the heavily doped polysilicon 52 is separated from the drift region 3 by an inner oxide layer 42, forming a stable capacitor structure with the drift region 3 through the inner oxide layer 42. This ensures that when the device is on, the carrier aggregation effect near the surface of the trench 4 in the drift region 3 is effectively enhanced, forming a high-conductivity current channel on the sidewall of the trench 4, thereby reducing the specific on-resistance.
[0051] It should also be noted that, since this implementation fills the trench 4 with heavily doped polysilicon 52 as the main body of the trench drain electrode structure 5, only a third contact hole 93 needs to be formed on the heavily doped polysilicon 52 at the top of the trench 4 to electrically lead it out to the external metal layer. Compared with the above implementation with the third contact hole 93 as the main body, this structure relaxes the process requirements for contact hole photolithography alignment and etching depth, increases the process window, reduces manufacturing difficulty, and improves the yield and performance consistency of LDMOS devices while achieving technical effects such as optimized electric field distribution, improved breakdown voltage, and reduced specific on-resistance.
[0052] Specifically, the breakdown voltage drift region (DRFT) of the aforementioned LDMOS device structure mainly follows... Figure 3 The distribution is shown in the direction of the arrows, and the electric field distribution of the device can be adjusted by adjusting the longitudinal doping concentration of the drift region 3.
[0053] The trade-off between breakdown voltage (BV) and specific on-resistance (Ron, RSP) in laterally diffused metal-oxide-semiconductor (LDMOS) has been a key research focus, as the two are mutually exclusive. How to increase the breakdown voltage while suppressing the increase in specific on-resistance, or how to decrease the specific on-resistance while avoiding the degradation of the breakdown voltage, is a pressing technical problem to be solved in this field.
[0054] For high-voltage switching devices, the performance index that evaluates the device's performance through its withstand voltage capability and conduction loss is called the quality factor (FOM). The higher the FOM value, the better the device's performance.
[0055] Please refer to Figures 4-9 To specifically illustrate the device performance of the two LDMOS device structures with trench drain electrodes provided in the first embodiment of the present invention, the present invention conducted tests on a conventional LDMOS device, an LDMOS device with a trench drain electrode structure 5 formed by combining drain region 51 and third contact hole 93, and an LDMOS device with a trench drain electrode structure 5 formed by combining heavily doped polysilicon 52 and third contact hole 93 in the following specific embodiment. Figures 4-9 The test results are shown in Table 1 below.
[0056] Table 1 Test Results in, Figure 4 This is a doping distribution diagram of a conventional LDMOS device provided in an embodiment of the present invention; Figure 5 This is a doping distribution diagram of a trench drain electrode structure 5 formed by combining a drain region 51 and a third contact hole 93, according to an embodiment of the present invention. Figure 6This is a doping distribution diagram of a device in which a heavily doped polysilicon 52 and a third contact hole 93 are combined to form a trench drain electrode structure 5, according to an embodiment of the present invention. Figure 7 This is an electric field distribution diagram of a conventional LDMOS device in a breakdown state provided by an embodiment of the present invention; Figure 8 This is an electric field distribution diagram of the breakdown state of a trench drain electrode structure 5 formed by combining a drain region 51 and a third contact hole 93, according to an embodiment of the present invention. Figure 9 This is an electric field distribution diagram of the breakdown state of a trench drain electrode structure 5 composed of heavily doped polycrystalline silicon 52 and a third contact hole 93, provided in an embodiment of the present invention.
[0057] The above experimental results show that the LDMOS device with trench drain electrode structure 5 provided in this embodiment of the invention, whether the trench drain electrode structure 5 is composed of drain region 51 and third contact hole 93 or heavily doped polysilicon 52 and third contact hole 93, has a higher breakdown voltage and a lower specific on-resistance than traditional LDMOS devices. Therefore, its quality factor (FOM) is higher than that of traditional LDMOS devices, resulting in superior device performance. Thus, this invention achieves both increased LDMOS breakdown voltage and reduced LDMOS specific on-resistance, resulting in superior device performance compared to traditional structures.
[0058] A second aspect of this invention provides a method for fabricating an LDMOS device structure with a trench drain electrode, applicable to fabricating the LDMOS device structure with a trench drain electrode described in the first aspect; the method includes the following steps: Substrate 1 is provided; A drift region 3 and a channel region 2 are formed in the substrate 1, and a contact surface is formed between the drift region 3 and the channel region 2; A trench 4 is formed in the drift zone 3, and then an inner oxide layer 42 is grown on the wall of the trench 4; A first drain electrode structure is formed based on the trench 4, so that the first drain electrode structure contacts the drift region 3; A source region 6 is formed in the channel region 2; A gate oxide layer 7 is formed on the surface of the channel region 2 and the drift region 3, and then a gate 8 is formed on the surface of the gate oxide layer 7, such that the gate 8 intersects with the vertical extension surface of the contact surface; A first contact hole 91 is formed on the surface of the source region 6, and a second contact hole 92 is formed on the surface of the gate 8; A second drain electrode structure is formed on the surface of the first drain electrode structure, so that the first drain electrode structure and the second drain electrode structure are combined to form a trench drain electrode structure 5.
[0059] The above-described method for fabricating an LDMOS device structure with a trench drain electrode first constructs a drift region 3 and a channel region 2 in a substrate 1, and then forms a trench 4 with an inner oxide liner 42 within the drift region 3. Subsequently, by constructing a drain electrode structure within this trench 4, the method integrates the drain electrode into the trench 4 of the drift region 3, forming a trench drain electrode structure 5 with the geometric characteristics of trench 4. This alters the electric field distribution and current path of traditional planar LDMOS devices. Utilizing its trench 4 structure and inner oxide liner 42, the device guides the high electric field region during breakdown voltage to the sidewalls and bottom of the trench 4, effectively dispersing the electric field peak and avoiding premature breakdown caused by excessive electric field concentration. Thus, the trench drain electrode improves the LDMOS breakdown voltage.
[0060] Simultaneously, when the LDMOS device is in the ON state, the bottom surface of the trench drain electrode structure 5 is connected to the drift region 3 and energized. The side surface of the trench drain electrode structure 5 and the drift region 3 are separated by the inner oxide layer 42, thus forming a capacitor structure. When a voltage is applied to the trench drain electrode structure 5 and the gate 8, the capacitor structure generates a capacitive coupling effect, causing the drift region 3 near the inner oxide layer 42 to act as the negative electrode relative to the trench drain electrode structure 5. Electrons accumulate on the surface of the drift region 3 near the inner oxide layer 42, thereby significantly increasing the carrier concentration in this region and forming a high-conductivity current channel. This high-conductivity current channel significantly reduces the total resistance when current flows through the drift region 3, and thus significantly reduces the specific on-resistance of the device.
[0061] Please refer to Figure 10 Furthermore, the formation of a trench 4 in the drift region 3, and the subsequent growth of an inner oxide lining layer 42 on the wall of the trench 4, includes: like Figure 10 (a) to Figure 10 As shown in (b), the drift region 3 is etched to form a trench 4 in the drift region 3; a first oxide layer 41 is grown and filled in the trench 4; like Figure 10 (b) to Figure 10 As shown in (c), the first oxide layer 41 is etched to form the inner oxide layer 42 on the wall of the trench 4 and expose the drift region 3 at the bottom of the trench 4.
[0062] In this implementation, a uniform and reliable inner oxide layer 42 can be formed on the sidewall of the trench 4 by first filling the entire structure and then selectively etching. This inner oxide layer 42 serves as a key dielectric layer between the subsequently formed trench drain electrode structure 5 and the drift region 3. Its uniformity and integrity improve the stability of the low-impedance carrier channel formed by the capacitive coupling effect between the trench drain electrode structure 5 and the drift region 3.
[0063] Meanwhile, by precisely controlling the etching process, the drift region 3 is exposed at the bottom of the trench 4, which creates the necessary conditions for the subsequent formation of the trench drain electrode structure 5 and the conductive channel of the drift region 3, ensuring that the drain current can be effectively collected.
[0064] Please refer to Figure 11 (a) Further, the step of forming a first drain electrode structure based on the trench 4, so that the first drain electrode structure contacts the drift region 3, includes: Ion implantation is performed on the drift region 3 exposed at the bottom of the trench 4 to form a drain region 51 in the drift region 3, and the drain region 51 is located at the bottom of the trench 4. The drain region 51 is used as the first drain electrode structure.
[0065] In this implementation, a high-concentration drain region 51 is formed by ion implantation into the drift region 3 exposed at the bottom of the trench 4. This drain region 51 serves as the first drain electrode structure, providing a low-resistance, highly reliable ohmic contact interface for the subsequently filled metal contact holes. Together, they act as the drain of the LDMOS device. When the LDMOS device is turned on, it ensures the smooth transport of carriers from the trench drain electrode structure 5 to the drift region 3, ensuring the formation of a high-conductivity current channel on the surface of the drift region 3 near the inner oxide layer 42.
[0066] Please refer to Figure 12 (a) A gate oxide layer 7 is formed on the surface of the channel region 2 and the drift region 3, and then a gate 8 is formed on the surface of the gate oxide layer 7, such that the gate 8 intersects with the vertical extension surface of the contact surface.
[0067] Please refer to Figure 13 (a) Further, the formation of a first contact hole 91 on the surface of the source region 6 and a second contact hole 92 on the surface of the gate 8; and the formation of a second drain electrode structure on the surface of the first drain electrode structure, so that the first drain electrode structure and the second drain electrode structure are combined to form a trench drain electrode structure 5, including: An interlayer dielectric layer 9 is grown on the surfaces of the drift region 3, the channel region 2, and the gate 8. The interlayer dielectric layer 9 and the gate oxide layer 7 are etched to form a first contact hole 91 extending to the surface of the source region 6, a second contact hole 92 extending to the surface of the gate 8, and a third contact hole 93 extending to the surface of the drain region 51 in the interlayer dielectric layer 9. A metal mixture is filled into the first contact hole 91, the second contact hole 92 and the third contact hole 93 respectively; The drain area 51 and the third contact hole 93 are combined to form the trench drain electrode structure 5.
[0068] In this implementation, three contact holes are formed through the deposition and selective etching of the interlayer dielectric layer 9, respectively, penetrating to the source region 6, the gate region 8, and the drain region 51. In particular, the third contact hole 93, which directly penetrates to the drain region 51, constitutes the main body of the trench drain electrode structure 5 and is directly combined with the drain region 51 as the second drain electrode structure. This process not only achieves effective lead-out of each electrode of the device but also fully utilizes the metal contact holes filled in the trench 4 as capacitor plates, enhancing the capacitive coupling effect that reduces specific on-resistance.
[0069] Meanwhile, the metal contact hole structure also functions as an electric field plate, further optimizing the electric field distribution on the device surface and improving the device's withstand voltage and reliability.
[0070] Please refer to Figure 11 (b) Further, the formation of the first drain electrode structure based on the trench 4, so that the first drain electrode structure contacts the drift region 3, includes: The trench 4 is filled with heavily doped polysilicon 52 so that the bottom end of the heavily doped polysilicon 52 contacts the drift region 3; The heavily doped polycrystalline silicon 52 is used as the first drain electrode structure.
[0071] In this implementation, heavily doped polysilicon 52 is filled into the trench 4, serving as the first drain electrode structure. This heavily doped polysilicon 52 directly contacts the drift region 3 at the bottom of the trench 4, forming the main conductive portion of the trench drain electrode structure 5, and can serve as an effective channel for drain current. The heavily doped polysilicon 52 filled in the trench 4 acts as a single electrode. The bottom of the heavily doped polysilicon 52 is connected to and energized by the drift region 3. The sides of the heavily doped polysilicon 52 are separated from the drift region 3 by an inner oxide layer 42, forming a stable capacitor structure with the drift region 3 through the inner oxide layer 42. This ensures that when the device is turned on, the carrier aggregation effect near the surface of the trench 4 in the drift region 3 is effectively enhanced, forming a high-conductivity current channel on the sidewall of the trench 4, thereby reducing the specific on-resistance.
[0072] Since this implementation fills the trench 4 with heavily doped polysilicon 52 as the main body of the trench drain electrode structure 5, it simplifies the etching difficulty of the subsequent third contact hole 93. The third contact hole 93 only needs to be etched to the surface of the heavily doped polysilicon 52 at the top of the trench 4, which relaxes the process requirements for contact hole photolithography alignment and etching depth, increases the process window, and reduces the manufacturing difficulty. While achieving technical effects such as optimizing electric field distribution, improving breakdown voltage and reducing specific on-resistance, it also improves the production yield of LDMOS devices and the consistency of device performance.
[0073] Please refer to Figure 12 (b) A gate oxide layer 7 is formed on the surface of the channel region 2 and the drift region 3, and then a gate 8 is formed on the surface of the gate oxide layer 7, such that the gate 8 intersects with the vertical extension surface of the contact surface.
[0074] Please refer to Figure 13 (b) Further, the formation of a first contact hole 91 on the surface of the source region 6 and a second contact hole 92 on the surface of the gate 8; and the formation of a second drain electrode structure on the surface of the first drain electrode structure, so that the first drain electrode structure and the second drain electrode structure are combined to form a trench drain electrode structure 5, including: An interlayer dielectric layer 9 is grown on the surfaces of the drift region 3, the channel region 2, and the gate 8. The interlayer dielectric layer 9 and the gate oxide layer 7 are etched to form a first contact hole 91 extending to the surface of the source region 6, a second contact hole 92 extending to the surface of the gate 8, and a third contact hole 93 extending to the surface of the heavily doped polysilicon 52 in the interlayer dielectric layer 9. A metal mixture is filled into the first contact hole 91, the second contact hole 92 and the third contact hole 93 respectively; The heavily doped polysilicon 52 and the third contact hole 93 are combined to form the trench drain electrode structure 5.
[0075] In this implementation, contact holes are also formed through the deposition and etching of the interlayer dielectric layer 9. The difference is that the third contact hole 93 only needs to penetrate to the surface of the heavily doped polysilicon 52. This third contact hole 93 serves as the second drain electrode structure, and its function is to lead the heavily doped polysilicon 52 to the external metal wiring layer. Because the third contact hole 93 no longer needs to be precisely aligned and etched to the semiconductor region at the bottom of the trench 4, this design significantly reduces the precision requirements for contact hole photolithographic alignment and etching depth. This not only simplifies process control and improves production yield, but also ensures the consistency of device performance. While achieving technical effects such as optimizing electric field distribution, improving breakdown voltage, and reducing specific on-resistance, it also improves the production yield of LDMOS devices and the consistency of device performance.
[0076] Further, the step of forming a drift region 3 and a channel region 2 in the substrate 1, and forming a contact surface between the drift region 3 and the channel region 2, includes: A first photoresist pattern is formed on the substrate 1; Based on the first photoresist pattern, the substrate 1 is doped with a first type of ion to form a drift region 3 in the substrate 1; The first photoresist pattern is cleaned and removed; A second photoresist pattern is formed on the substrate 1; The substrate 1 is subjected to second type ion doping based on the second photoresist pattern, thereby forming a channel region 2 in the substrate 1; The second photoresist pattern is cleaned and removed.
[0077] In this implementation, substrate 1 is doped with first-type and second-type doping through two independent photolithography and ion implantation processes, respectively, thereby precisely forming drift region 3 and channel region 2. This step-by-step formation method allows for independent and precise control of the doping concentration, junction depth, and lateral position of the two key regions, ensuring that drift region 3 has ideal breakdown voltage characteristics, while ensuring that channel region 2 can form an effective conductive channel. This is the foundation for achieving the expected electrical performance of the device and ensuring the stability of key parameters such as breakdown voltage and threshold voltage.
[0078] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; however, any combination of these technical features that does not contradict each other should be considered within the scope of this specification.
[0079] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the concept of this application, and these improvements and substitutions should also be considered within the scope of protection of this invention. Therefore, the scope of protection of this application should be determined by the appended claims.
Claims
1. An LDMOS device structure with a trench drain electrode, characterized in that, include: A substrate having a drift region and a channel region therein, a contact surface between the drift region and the channel region, and a gate oxide layer covering the surfaces of the drift region and the channel region; An active region is provided in the channel region, and a gate is provided on the surface of the gate oxide layer. The gate intersects with the vertical extension surface of the contact surface. The source region surface is provided with a first contact hole, and the gate surface is provided with a second contact hole, the first contact hole and the second contact hole penetrating the gate oxide layer; The drift zone is provided with grooves, and the walls of the grooves are covered with an inner oxide lining. A trench drain electrode structure is provided in the trench, one end of which is in contact with the drift region, and the other end of which penetrates the gate oxide layer.
2. The LDMOS device structure with a trench drain electrode according to claim 1, characterized in that, A drain region is provided in the drift region, and the drain region is located at the bottom of the trench; a third contact hole is filled in the trench, one end of the third contact hole contacts the drain region, and the other end of the third contact hole penetrates the gate oxide layer; wherein: The drain area and the third contact hole together form the trench drain electrode structure.
3. The LDMOS device structure with a trench drain electrode according to claim 1, characterized in that, The trench is filled with heavily doped polysilicon, the bottom of which is in contact with the drift region; the top of the heavily doped polysilicon is connected to a third contact hole, which penetrates the gate oxide layer; wherein: The heavily doped polycrystalline silicon and the third contact hole combine to form the trench drain electrode structure.
4. A method for fabricating an LDMOS device structure with a trench drain electrode, characterized in that, This method is applicable to fabricating an LDMOS device structure with a trench drain electrode as described in claim 1; the method includes the following steps: Provide substrate; A drift region and a channel region are formed in the substrate, and a contact surface is formed between the drift region and the channel region; A trench is formed in the drift zone, and then an inner oxide lining layer is grown on the trench wall; A first drain electrode structure is formed based on the trench, so that the first drain electrode structure contacts the drift region; A source region is formed in the channel region; A gate oxide layer is formed on the surface of the channel region and the drift region, and then a gate is formed on the surface of the gate oxide layer, such that the gate intersects with the vertical extension surface of the contact surface; A first contact hole is formed on the surface of the source region, and a second contact hole is formed on the surface of the gate. A second drain electrode structure is formed on the surface of the first drain electrode structure, so that the first drain electrode structure and the second drain electrode structure are combined into a trench drain electrode structure.
5. The method for fabricating an LDMOS device structure with a trench drain electrode according to claim 4, characterized in that, The process of forming trenches in the drift region and then growing an inner oxide lining layer on the trench walls includes: The drift region is etched to form trenches in the drift region; A first oxide layer is grown and filled in the trench; The first oxide layer is etched to form the inner oxide layer on the trench wall and expose the drift region at the bottom of the trench.
6. The method for fabricating an LDMOS device structure with a channel drain electrode according to claim 5, characterized in that, The step of forming a first drain electrode structure based on the trench, so that the first drain electrode structure contacts the drift region, includes: Ion implantation is performed on the drift region exposed at the bottom of the trench to form a drain region in the drift region, and the drain region is located at the bottom of the trench; The drain region is used as the first drain electrode structure.
7. The method for fabricating an LDMOS device structure with a trench drain electrode according to claim 6, characterized in that, A first contact hole is formed on the surface of the source region, and a second contact hole is formed on the surface of the gate. A second drain electrode structure is formed on the surface of the first drain electrode structure, so that the first drain electrode structure and the second drain electrode structure are combined into a trench drain electrode structure, including: An interlayer dielectric layer is grown in the drift region, the channel region, and the gate surface; The interlayer dielectric layer and the gate oxide layer are etched to form a first contact hole extending to the surface of the source region, a second contact hole extending to the surface of the gate region, and a third contact hole extending to the surface of the drain region in the interlayer dielectric layer; A metal mixture is filled into the first contact hole, the second contact hole, and the third contact hole, respectively; The drain area and the third contact hole are combined to form the trench drain electrode structure.
8. The method for fabricating an LDMOS device structure with a trench drain electrode according to claim 5, characterized in that, The step of forming a first drain electrode structure based on the trench, so that the first drain electrode structure contacts the drift region, includes: The trench is filled with heavily doped polysilicon so that the bottom of the heavily doped polysilicon contacts the drift region; The heavily doped polycrystalline silicon is used as the first drain electrode structure.
9. The method for fabricating an LDMOS device structure with a trench drain electrode according to claim 8, characterized in that, A first contact hole is formed on the surface of the source region, and a second contact hole is formed on the surface of the gate. A second drain electrode structure is formed on the surface of the first drain electrode structure, so that the first drain electrode structure and the second drain electrode structure are combined into a trench drain electrode structure, including: An interlayer dielectric layer is grown in the drift region, the channel region, and the gate surface; The interlayer dielectric layer and the gate oxide layer are etched to form a first contact hole extending to the surface of the source region, a second contact hole extending to the surface of the gate region, and a third contact hole extending to the surface of the heavily doped polysilicon in the interlayer dielectric layer. A metal mixture is filled into the first contact hole, the second contact hole, and the third contact hole, respectively; The heavily doped polysilicon and the third contact hole are combined to form the trench drain electrode structure.
10. The method for fabricating an LDMOS device structure with a trench drain electrode according to claim 4, characterized in that, The step of forming a drift region and a channel region in the substrate, and forming a contact surface between the drift region and the channel region, includes: A first photoresist pattern is formed on the substrate; Based on the first photoresist pattern, the substrate is doped with a first type of ion to form a drift region in the substrate; The first photoresist pattern is cleaned and removed; A second photoresist pattern is formed on the substrate; The substrate is doped with a second type of ion based on the second photoresist pattern to form a channel region in the substrate; The second photoresist pattern is cleaned and removed.