Semiconductor device

Abstract

A semiconductor device includes: a semiconductor pattern; a plurality of channel structures including a plurality of channel patterns; a plurality of gate structures; a source / drain pattern on the semiconductor pattern and on side surfaces of the plurality of channel patterns; a dielectric isolation layer; a plurality of dielectric isolation patterns; a plurality of contact blocks; at least one contact via extending from the at least one contact block into the dielectric isolation layer to contact at least one of the source / drain patterns, respectively; a conductive barrier between the dielectric isolation layer and the plurality of contact blocks and contacting the at least one contact via; and an interconnection structure on a lower surface of the plurality of contact blocks, on the plurality of dielectric isolation patterns, and electrically connected to the at least one contact block.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0140577, filed on October 15, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device. Background Technology

[0003] With the increasing demand for high performance, high speed, and / or versatility in semiconductor devices, the integration density of semiconductor devices has also increased. In line with this trend towards higher integration, semiconductor devices with back-side power delivery network (BSPDN) structures, where power rails are located on the back side of the wafer, have been developed. Furthermore, efforts have been made to develop semiconductor devices with three-dimensional channel structures to overcome the limitations in operating characteristics caused by the reduction in size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs). Summary of the Invention

[0004] One aspect of this disclosure is to provide a semiconductor device with improved electrical characteristics and reliability.

[0005] According to one aspect of this disclosure, a semiconductor device includes: a semiconductor pattern extending in a first direction; a plurality of channel structures spaced apart from each other in the first direction and on the semiconductor pattern, wherein each of the plurality of channel structures includes a plurality of channel patterns; a plurality of gate structures extending in the plurality of channel structures in a second direction intersecting the first direction and extending around the plurality of channel patterns; source / drain patterns on the semiconductor pattern and on side surfaces of the plurality of channel patterns; a dielectric isolation layer on a lower surface of the semiconductor pattern; a plurality of dielectric isolation patterns extending toward the plurality of gate structures in a third direction perpendicular to the first direction; and a plurality of contact blocks. The plurality of contact blocks are respectively located between adjacent dielectric isolation patterns in the plurality of dielectric isolation patterns and on the lower surface of the dielectric isolation layer; at least one contact via extends from at least one of the plurality of contact blocks into the dielectric isolation layer to respectively contact at least one source / drain pattern in the source / drain pattern; a conductive barrier is located between the dielectric isolation layer and the plurality of contact blocks and contacts the at least one contact via, wherein each of the plurality of contact blocks includes a side surface that respectively contacts the sidewalls of the plurality of dielectric isolation patterns; and an interconnection structure is located on the lower surface of the plurality of contact blocks, on the plurality of dielectric isolation patterns, and electrically connected to the at least one contact block.

[0006] According to another aspect of this disclosure, a semiconductor device includes: a semiconductor pattern extending in a first direction; a device isolation layer on opposite side surfaces of the semiconductor pattern and extending in the first direction; a plurality of channel structures spaced apart from each other in the first direction and on the semiconductor pattern; a plurality of gate structures on the plurality of channel structures and extending in a second direction intersecting the first direction; source / drain patterns respectively between the plurality of channel structures and on the semiconductor pattern; a dielectric isolation layer on a lower surface of the semiconductor pattern; a plurality of dielectric isolation patterns extending toward the plurality of gate structures in a third direction perpendicular to the first direction; and a plurality of contact blocks respectively on the plurality of channel structures. Between adjacent dielectric isolation patterns in a plurality of dielectric isolation patterns, and on the lower surface of the dielectric isolation layer; at least one contact via extending from at least one of the plurality of contact blocks into the dielectric isolation layer to contact at least one source / drain pattern in the source / drain patterns respectively; a conductive barrier between the dielectric isolation layer and the plurality of contact blocks and contacting the at least one contact via, wherein each of the plurality of contact blocks includes a side surface that contacts the sidewalls of the plurality of dielectric isolation patterns respectively; and an interconnection structure on the lower surface of the plurality of contact blocks, on the plurality of dielectric isolation patterns, on the device isolation layer, and electrically connected to the at least one contact block.

[0007] According to another aspect of this disclosure, a semiconductor device includes: a semiconductor pattern extending in a first direction; a device isolation layer extending in the first direction on opposite side surfaces of the semiconductor pattern; a plurality of channel structures spaced apart from each other in the first direction and on the semiconductor pattern; a plurality of gate structures extending in the plurality of channel structures and in a second direction intersecting the first direction; a first source / drain pattern and a second source / drain pattern on the semiconductor pattern; an interlayer insulating layer extending on the device isolation layer and surrounding the plurality of gate structures, the first source / drain pattern, and the second source / drain pattern; a dielectric isolation layer on a lower surface of the semiconductor pattern; and a plurality of dielectric isolation patterns extending in a third direction toward the plurality of gate structures and into the dielectric isolation layer, wherein the third direction is perpendicular to the first direction. A contact element electrically connected to a first source / drain pattern and extending into an interlayer insulating layer; a plurality of contact blocks, respectively between adjacent dielectric isolation patterns in the plurality of dielectric isolation patterns, and on the lower surface of the dielectric isolation layer; a contact via extending from a first contact block adjacent to a second source / drain pattern in the plurality of contact blocks to a second source / drain pattern and into the dielectric isolation layer; a conductive barrier element between the dielectric isolation layer and the plurality of contact blocks and contacting the contact via, wherein each of the plurality of contact blocks includes a side surface that respectively contacts a sidewall of the plurality of dielectric isolation patterns; a first interconnect structure on the interlayer insulating layer and electrically connected to the upper contact element; and a second interconnect structure on the lower surface of the plurality of contact blocks, on the plurality of dielectric isolation patterns, on the device isolation layer, and electrically connected to the first contact block. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure; Figure 2 yes Figure 1 A cross-sectional view of a semiconductor device taken along line I-I'; Figure 3A and Figure 3B They are Figure 1 A cross-sectional view of a semiconductor device taken along lines II1-II1' and II2-II2'; Figure 4A yes Figure 2 A partial enlarged view of part "A1" of the semiconductor device, and Figure 4B yes Figure 3A A partial enlarged view of part "B" of the semiconductor device; Figure 5 and Figure 6This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure; Figure 7 yes Figure 5 A partial enlarged view of part "A2" of the semiconductor device; Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F This is a cross-sectional view illustrating an example dielectric isolation patterning process for manufacturing a semiconductor device according to an embodiment of the present disclosure; Figure 9A , Figure 9B , Figure 9C and Figure 9D They are respectively with Figure 8A , Figure 8B , Figure 8C and Figure 8F A side view of the semiconductor device; Figure 10A , Figure 10B , Figure 10C and Figure 10D This is a cross-sectional view illustrating an example back contact formation process for a method of manufacturing a semiconductor device according to an embodiment of the present disclosure; and Figure 11A , Figure 11B , Figure 11C and Figure 11D They are respectively with Figures 10A to 10D The side view of the semiconductor device. Detailed Implementation

[0009] To clarify this disclosure, the same elements or equivalents are designated by the same reference numerals throughout the specification. Furthermore, since the dimensions and thicknesses of the constituent components shown in the drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are overstated for better understanding and ease of description.

[0010] It will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being “on” another element, the element may be directly on said other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly” on another element, there are no intermediate elements present. Furthermore, for ease of description, spatial relative terms (such as “below,” “under,” “lower,” “above,” “upper,” etc.) are used herein to describe the relationship of one element or feature as shown in the accompanying drawings to another element or feature (or other elements). It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as being “below” or “under” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the term “below” can cover both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0011] Furthermore, unless explicitly stated otherwise, the words “comprising” and variations thereof (such as “including” or “contains”) shall be understood to imply inclusion of the stated element but not exclusion of any other element. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. The term “and / or” includes any and all combinations of one or more of the associated listed items. The term “connected” may be used herein to mean a physical and / or electrical connection, and may mean a direct or indirect physical and / or electrical connection. The term “exposed” may be used to define the relationship between a particular layer or surface, but it does not require that the layer or surface be free of other elements or layers in the finished device. When viewed along a line extending in a particular direction or in a plane perpendicular to the particular direction, components or layers described by reference to “overlapping” in a particular direction may at least partially obscure each other. The terms “first,” “second,” etc., may be used herein only to distinguish one component, element, etc., from another component, element, etc.

[0012] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0013] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2 yes Figure 1 A cross-sectional view of the semiconductor device taken along line I-I', and Figure 3A and Figure 3B They are Figure 1 A cross-sectional view of the semiconductor device taken along lines II1-II1' and II2-II2'.

[0014] Reference Figure 1 , Figure 2 , Figure 3A and Figure 3B According to some embodiments, a semiconductor device 100 may include a semiconductor pattern 105 extending in a first direction (e.g., the X direction), a plurality of channel structures CH arranged on the semiconductor pattern 105 spaced apart from each other in the first direction (e.g., the X direction), a plurality of gate structures GS intersecting the plurality of channel structures CH or extending on the plurality of channel structures CH in a second direction (e.g., the Y direction) intersecting the first direction (e.g., the X direction), and a source / drain pattern 150 arranged between the plurality of channel structures CH.

[0015] According to some embodiments, a semiconductor device 100 may include a semiconductor pattern 105 as a substrate structure, the semiconductor pattern 105 being disposed on the lower surfaces of a gate structure GS, a first source / drain pattern 150A, and a second source / drain pattern 150B. In some embodiments, the semiconductor pattern 105 may be on a polished substrate 101 (see...). Figure 8A and Figure 9A A portion of an “active pattern” that previously protruded or extended from the substrate 101 and extended in a first direction (e.g., the X direction).

[0016] Reference Figure 3A Device isolation layers 110 may be disposed between semiconductor patterns 105. Device isolation layers 110 may be disposed on opposite side surfaces of semiconductor patterns 105 extending along a first direction. Upper regions of semiconductor patterns 105 may be exposed from the upper surface of device isolation layers 110.

[0017] like Figure 2 and Figure 3B As shown, the channel structure CH can be arranged at regular intervals along a first direction (e.g., the X direction) on the semiconductor pattern 105. In some embodiments, the channel structure CH may include a plurality of channel patterns 130 stacked and spaced apart from each other in a vertical direction (e.g., in the Z direction) on the semiconductor pattern 105. The plurality of channel patterns 130 are configured as the channel structure of a transistor and may include at least one of, for example, silicon (Si), silicon germanium (SiGe), and germanium (Ge). In some embodiments, the plurality of channel patterns 130 may be silicon semiconductors. In some embodiments, the plurality of channel patterns 130 includes three channel patterns 130, but the number and shape of the plurality of channel patterns 130 may vary.

[0018] like Figure 1 , Figure 2 and Figure 3BAs shown, the gate structure GS may include a gate electrode 145 extending in a second direction (e.g., the Y direction) and surrounding or surrounding a plurality of channel patterns 130, a gate insulating film 142 disposed between the gate electrode 145 and the plurality of channel patterns 130, gate spacers 141 disposed on opposite side surfaces of the gate electrode 145 portion located on the uppermost channel pattern, and a gate capping layer 147 disposed on the gate electrode 145 between the gate spacers 141.

[0019] The gate electrode 145 may include a conductive material. For example, the gate electrode 145 may include at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and TaAlC. In some embodiments, the gate electrode 145 may include a semiconductor material (such as doped polycrystalline silicon). At least one of the gate electrodes 145 may include a multilayer structure comprising different materials.

[0020] The gate insulating film 142 may include a dielectric material. For example, the gate insulating film 142 may include an oxide, a nitride, or a high-k material. A high-k material is a dielectric material having a higher dielectric constant than silicon oxide (SiO2), and the high-k material may be, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), or titanium oxide (TiO2). i O2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi) x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O y It is one of praseodymium oxide (Pr2O3) and praseodymium oxide (Pr2O3). In some embodiments, the gate insulating film 142 may include two or more different dielectric films.

[0021] Gate spacer 141 may include an insulating material. For example, gate spacer 141 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, gate spacer 141 may include a multilayer structure comprising different materials. Gate capping layer 147 may include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride.

[0022] Reference Figure 2According to some embodiments, a semiconductor device 100 may include source / drain patterns 150 on opposite sides of a gate structure GS, respectively connected to opposite sides of a plurality of channel patterns 130 (channel regions). In some embodiments, a portion of a semiconductor pattern 105 located on opposite sides of the gate structure GS has a recessed region, and the source / drain patterns 150 may be arranged in the recessed region of the semiconductor pattern 105.

[0023] Reference Figure 2 and Figure 3A In some embodiments, the source / drain pattern 150 includes a first epitaxial layer 151 and a second epitaxial layer 152 disposed on the first epitaxial layer 151. In some embodiments, the first epitaxial layer 151 may directly contact the side surfaces of the plurality of channel patterns 130. In some embodiments, the first epitaxial layer 151 and the second epitaxial layer 152 may include different materials. For example, in the case of a P-type MOSFET, the first epitaxial layer 151 and the second epitaxial layer 152 may include SiGe with different Ge compositions (e.g., the second epitaxial layer 152 may have a higher Ge content), or the first epitaxial layer 151 and the second epitaxial layer 152 may include Si and SiGe, respectively. In some embodiments, the first epitaxial layer 151 and the second epitaxial layer 152 may include different types of impurities or include the same impurities at different concentrations. In the case of an N-type MOSFET, the first epitaxial layer 151 and the second epitaxial layer 152 may both include Si, but the first epitaxial layer 151 and the second epitaxial layer 152 may include different types of impurities or include the same impurities at different concentrations.

[0024] According to some embodiments, a semiconductor device 100 may include an upper contact structure 180 connected to a first interconnect structure 190 on the front side and a lower contact structure 280 connected to a second interconnect structure 290 on the back side. For example, the first interconnect structure 190 may include signal lines connected to a second source / drain pattern 150B of the semiconductor device 100 via the upper contact structure 180, and the second interconnect structure 290 may include power lines connected to a first source / drain pattern 150A of the semiconductor device 100 via the lower contact structure 280.

[0025] In some embodiments, the upper contact structure 180 may be connected to the second source / drain pattern 150B between adjacent gate structures GS, and the lower contact structure 280 may be connected to the first source / drain pattern 150A between adjacent dielectric isolation patterns 230. The upper and lower contact structures will be described in more detail below.

[0026] like Figure 2 and Figure 3BAs shown, the semiconductor device 100 according to some embodiments may further include a first interlayer insulating layer 161 and a second interlayer insulating layer 162. The first interlayer insulating layer 161 is disposed on the device isolation layer 110 to cover the source / drain pattern 150 (i.e., the first source / drain pattern 150A and the second source / drain pattern 150B) or at least partially superimposed with the source / drain pattern 150 (i.e., the first source / drain pattern 150A and the second source / drain pattern 150B). The second interlayer insulating layer 162 covers the gate structure GS on the first interlayer insulating layer 161 or at least partially superimposed with the gate structure GS. For example, the first interlayer insulating layer 161 and the second interlayer insulating layer 162 may include spin-coated hard masks (SOH), flowable oxide (FOX), Tonen silazane (TOSZ), undoped silicon glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), flowable CVD (FCVD) oxide, or combinations thereof. The first interlayer insulating layer 161 and the second interlayer insulating layer 162 may be formed using chemical vapor deposition, flowable CVD processes, or spin-coating processes.

[0027] In some embodiments, the upper contact structure 180 may be connected to the second source / drain pattern 150B through the first interlayer insulating layer 161. The upper contact structure 180 may extend from the upper surface of the second source / drain pattern 150B into the interior of the second source / drain pattern 150B.

[0028] Each of the upper contact structures 180 may include a contact plug and a conductive barrier extending around or around the contact plug. For example, the contact plug may include Cu, Co, Mo, Ru, W, or alloys thereof. For example, the conductive barrier may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or combinations thereof.

[0029] like Figure 2As shown, a dielectric isolation layer 210 may be disposed on the lower surface of the semiconductor pattern 105. A plurality of dielectric isolation patterns 230 may be disposed in regions on the lower surface of the dielectric isolation layer 210 corresponding to a plurality of gate structures GS. The plurality of dielectric isolation patterns 230 may have a structure extending in a vertical direction (e.g., in the Z direction). The plurality of dielectric isolation patterns 230 may define spaces for contact blocks 285 on the lower surface of the dielectric isolation layer 210. Each of the plurality of dielectric isolation patterns 230 may extend through or into the dielectric isolation layer 210 toward each of the plurality of gate structures GS. The semiconductor pattern 105 may be separated into a plurality of patterns by the extended portions of the dielectric isolation patterns 230. For example, at least one of the dielectric isolation layer 210 and the dielectric isolation patterns 230 may include silicon nitride, silicon oxynitride, aluminum nitride, or aluminum oxynitride. In some embodiments, the dielectric isolation layer 210 and the dielectric isolation patterns 230 may include the same insulating material.

[0030] Multiple contact blocks 285 may be arranged in the space between multiple dielectric isolation patterns 230 on the lower surface of the dielectric isolation layer 210. Each of the multiple contact blocks 285 may be located below a source / drain pattern 150 and may serve as part of a potential lower contact structure for a corresponding source / drain pattern 150. As described below, in some embodiments, the contact block 285 may be used together with a contact via 286 extending therefrom as a lower contact structure 280. The contact blocks 285 used in some embodiments may be individually referred to as "active contact block 285A" and "dummy contact block 285B," with "active contact block 285A" participating in transistor operation and "dummy contact block 285B" not participating in transistor operation.

[0031] In some embodiments, the lower contact structure 280 may include at least one contact block 285A among the contact blocks 285 and a contact via 286 extending from the at least one contact block 285A to a first source / drain pattern 150A. The contact via 286 may extend from the at least one contact block 285A through the dielectric isolation layer 210 to an adjacent first source / drain pattern 150A within the source / drain pattern 150. The contact via 286 may be connected to a second epitaxial layer 152 by passing through or extending through the first epitaxial layer 151 to reduce contact resistance (see...). Figure 4A ).

[0032] In some embodiments, a cross-section of the semiconductor device 100 in a first direction (see...) Figure 2In the plurality of dielectric isolation patterns 230, each may have a shape in which the width Wb of the portion adjacent to the second interconnect structure 290 is larger than the width Wa of the portion adjacent to the plurality of gate structures GS. This is because the etching process for the dielectric isolation patterns 230 is performed at a relatively low temperature (e.g., 400°C or less) so as not to adversely affect the metal composition (assembly) of the first interconnect structure 190; therefore, the plurality of dielectric isolation patterns 230 may each have a tapered structure. Thus, each of the contact blocks 285 defined by the plurality of dielectric isolation patterns 230 may have a shape in which the width W2 of the portion adjacent to the second interconnect structure 290 is smaller than the width W1 of the portion adjacent to the dielectric isolation layer 210.

[0033] In some embodiments, the semiconductor device 100 may further include a conductive barrier 282 disposed between the dielectric isolation layer 210 and a plurality of contact blocks 285. In the lower contact structure 280, the conductive barrier 282 may extend to the surface of at least one contact via 286. A portion of the conductive barrier 282 that does not extend is present on the side surface of the contact blocks 285. Each of the plurality of contact blocks 285 may have a side surface portion that contacts the sidewalls of a plurality of dielectric isolation patterns 230 (e.g., adjacent or adjacent to each other).

[0034] Figure 4A yes Figure 2 A partial enlarged view of part "A1" of the semiconductor device, and Figure 4B yes Figure 3A A magnified view of part "B" of the semiconductor device.

[0035] and Figure 2 and Figure 3A Refer to together Figure 4A and Figure 4B The conductive barrier 282 may have a portion (i.e., an extension portion) 282E extending from the sidewalls of the plurality of dielectric isolation patterns 230 to a portion adjacent to the dielectric isolation layer 210. Based on the extension portion 282E of the conductive barrier 282, each of the plurality of contact blocks 285 may be divided or partitioned into two portions 285a and 285b. Each of the plurality of contact blocks 285 may include a first portion 285a that overlaps with the extension portion 282E in the horizontal direction and a second portion 285b that contacts the plurality of dielectric isolation patterns 230 (e.g., adjacent or adjacent to each other).

[0036] In some embodiments, the first portion 285a and the second portion 285b of the contact block 285 may comprise the same metallic material. However, the first portion 285a and the second portion 285b may be formed by different deposition processes (see [link to documentation]). Figure 10B and Figure 10DThe first portion 285a can be used as a seed layer in the deposition process for the second portion 285b. Multiple contact blocks 285 (particularly the second portion 285b) may comprise metal having a substantially single-crystal structure without grain boundaries. For example, the first portion 285a may be executed by a non-selective deposition process (e.g., physical vapor deposition (PVD) or chemical vapor deposition (CVD)), and the second portion 285b may be executed by a selective deposition process (e.g., selective CVD or atomic layer deposition (ALD)).

[0037] In some embodiments, the thickness of the first portion 285a may be based on the extension portion 282E of the conductive barrier 282. The first portion 285a may have an appropriate thickness for the seed layer. For example, the length d of the extension portion 282E (e.g., in the third direction (Z direction)) may be 1 nm or greater, but is not limited thereto.

[0038] In some embodiments, the contact via 286 may include the same metal material as the metal material of the first portion 285a of the plurality of contact blocks 285. Each of the plurality of contact blocks 285 may include the same metal material as the contact via 286.

[0039] In some embodiments, the contact vias and contact blocks may comprise molybdenum (Mo) or tungsten (W). For example, when molybdenum is used to form contact block 285, voids may occur. For example, conductive barrier 282 may comprise Ta, TaN, Mn, MnN, WN, Ti, TiN, or combinations thereof.

[0040] In some embodiments, the lower contact structure 280 not only forms a high-quality contact block 285A, but also allows the material of the contact block 285A to replace the conductive barrier 282, which has relatively high resistance. Therefore, the lower contact structure 280 can improve the electrical characteristics of the semiconductor device 100 (such as reducing contact resistance and improving reliability). In some embodiments, the lower contact structure 280 may have sufficient length to adequately remove the conductive barrier. For example, the length d of the extension 282E may be 10 nm or less, but is not limited thereto.

[0041] According to some embodiments, a semiconductor device 100 may have a dual-sided interconnect structure including a first interconnect structure 190 and a second interconnect structure 290. The first interconnect structure 190 may be disposed on the upper surface of the semiconductor device 100, and the second interconnect structure 290 may be disposed on the lower surface of the semiconductor device 100.

[0042] The first interconnect structure 190 may include a first interconnect insulating layer 191 and a first interconnect line M1 disposed within the first interconnect insulating layer 191. The first interconnect line M1 may be connected to the upper contact structure 180 via a first via V1 extending through the second interlayer insulating layer 162 or into the second interlayer insulating layer 162.

[0043] Similarly, the second interconnect structure 290 may include second interconnect insulating layers 291 and 292, and a second via V2 and a second interconnect line M2 disposed in the second interconnect insulating layers 291 and 292. In some embodiments, the second interconnect line M2 may be electrically insulated from the dummy contact block 285B through the second interconnect insulating layer 291, while being connected to the active contact block 285A of the lower contact structure 280 through the second via V2 extending through the second interconnect insulating layer 291 or into the second interconnect insulating layer 291.

[0044] In some embodiments, power for device operation can be supplied to the first source / drain pattern 150A via the second interconnect M2 and the lower contact structure 280 connected thereto, thereby simplifying the first interconnect M1.

[0045] For example, the first interconnect insulating layer 191 and the second interconnect insulating layers 291 and 292 may comprise a low-k material (such as silicon oxide, silicon oxynitride, SiOC, or SiCOH). For example, the first interconnect M1 and the second interconnect M2, as well as the first via V1 and the second via V2, may comprise copper or a copper-containing alloy.

[0046] Figure 5 and Figure 6 This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0047] Reference Figure 5 and Figure 6 Except that the lower contact structure 280' includes different metal materials and the metal-semiconductor compound film SC is disposed between the contact via 286 and the first source / drain pattern 150A, the semiconductor device 100A according to some embodiments can be understood as being related to... Figures 1 to 4B The semiconductor device 100 shown is similar. Furthermore, unless otherwise specifically described, it can be understood through... Figures 1 to 4B The components are understood by referring to the description of the same or similar components of the semiconductor device 100 shown.

[0048] Similar to the semiconductor device 100, each of the plurality of contact blocks 285' employed in some embodiments may include a first portion 285a horizontally superimposed with an extension 282E of the conductive barrier 282 and a second portion 285b' contacting the plurality of dielectric isolation patterns 230. However, in some embodiments, the first portion 285a may include a first metal material, and the second portion 285b' may include a second metal material different from the first metal material.

[0049] Figure 7 yes Figure 5 An enlarged view of part "A2" of the semiconductor device.

[0050] Reference Figures 5 to 7 In some embodiments, the first portion 285a and the second portion 285b' of the contact block 285' may each comprise different first and second metallic materials. For example, the first metallic material may comprise W, Mo, Co, or Ru, and the second metallic material may comprise W or Mo. Since the first and second metallic materials have the same or similar crystal structures, even if the first portion 285a and the second portion 285b' are different metals, the first portion 285a can be used as a seed layer for the second portion 285b'. Furthermore, in some embodiments, the second portion 285b' of the contact block 285' may comprise a metal having an almost (or essentially) single-crystal structure without grain boundaries. For example, the first portion 285a may be formed by a non-selective deposition process (e.g., PVD or CVD), and the second portion 285b' may be formed by a selective deposition process (e.g., selective CVD or ALD).

[0051] In some embodiments, the distance by which the extension portion 282E of the conductive blocking member 282 extends may be relatively reduced within the range of providing the seed layer, in order to improve or reduce resistance. For example, the length d of the extension portion 282E may be from 1 nm to 10 nm, but is not limited thereto.

[0052] In this way, the lower contact structure 280' used in some embodiments can not only form a high-quality second portion 285b', but also replace the conductive barrier 282 with a relatively high resistance using the material of the contact block 285'. Therefore, the lower contact structure 280' can improve the electrical characteristics of the semiconductor device 100A (such as reducing contact resistance and improving reliability).

[0053] In some embodiments, a metal-semiconductor compound film SC may be disposed between the contact via 286 and the first source / drain pattern 150A. (Refer to...) Figure 5The metal-semiconductor compound film SC may extend toward the surface region of the semiconductor pattern 105 that contacts the contact via 286. The metal-semiconductor compound film SC may include a metal-silicide. For example, the metal-semiconductor compound film SC may include at least one metal selected from Ti, Co, Ni, Pt, Zr, Mo, and Sc.

[0054] The features, functions, and effects of the embodiments can be understood in more detail as the methods for manufacturing semiconductor devices are described below.

[0055] Figures 8A to 8F as well as Figures 9A to 9D This is a cross-sectional view illustrating key processes in a method for manufacturing a semiconductor device according to embodiments of the present disclosure, and can be understood as being used for manufacturing... Figures 1 to 4B The process of the semiconductor device 100 shown in the figure.

[0056] here, Figures 8A to 8F They are respectively with Figure 2 The corresponding sectional view, and Figures 9A to 9D Is with Figure 3A The corresponding sectional views, and respectively represent Figure 8A , Figure 8B , Figure 8C and Figure 8F The process.

[0057] Reference Figure 8A and Figure 9A A gate all around transistor device, including multiple channel structures CH, multiple gate structures GS, and a first source / drain pattern 150A and a second source / drain pattern 150B, can be formed on the substrate 101.

[0058] Substrate 101 may include a semiconductor material (e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI semiconductor). For example, a group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Substrate 101 may include a bulk wafer, an epitaxial layer, or a silicon-on-insulator (SOI) layer.

[0059] Multiple channel structures CH may include multiple channel patterns 130, which are stacked and spaced apart from each other in a direction perpendicular to the first direction (e.g., the X direction) (e.g., a third direction (e.g., the Z direction)) on a semiconductor pattern 105 extending along a first direction (e.g., the X direction). Multiple gate structures GS may be formed to intersect with the multiple channel structures CH in a second direction (e.g., the Y direction) while extending around or around the multiple channel patterns 130. A first source / drain pattern 150A and a second source / drain pattern 150B may be arranged in recessed regions extending into a portion of the semiconductor pattern 105 between the multiple channel structures CH and may be respectively connected to opposite side surfaces of the multiple channel patterns 130 in the first direction (e.g., the X direction). Furthermore, a first interlayer insulating layer 161, covering or at least partially stacked with the first source / drain pattern 150A and the second source / drain pattern 150B, may be formed between the plurality of gate structures GS, and an upper contact structure 180 connected to the first source / drain pattern 150A may be formed by penetrating the first interlayer insulating layer 161. Additionally, a second interlayer insulating layer 162 may be formed on the first interlayer insulating layer 161 to cover or at least partially stack with the plurality of gate structures GS, and a first interconnect structure 190 connected to the upper contact structure 180 may be formed. Because the first interconnect structure is pre-formed, the following limitation may exist: subsequent processes may need to be performed at relatively low temperatures (e.g., 400°C or less) so as not to adversely affect the metal composition (assemblies) of the first interconnect structure 190. For example, along with the process of forming the first opening TH for dielectric isolation patterns (see... Figure 8D ), forming a conductive barrier with sufficient thickness (see Figure 10B This is desirable for preventing pinhole defects.

[0060] Subsequently, refer to Figure 8B and Figure 9B The substrate 101 can be removed to partially leave or expose the semiconductor pattern 105.

[0061] This process can be performed sequentially as a process for removing the substrate 101 and a process for partially removing the semiconductor pattern 105. First, the substrate 101 can be removed via a polishing process and / or an etching process. The removal process can be performed until the device isolation layer 110 is exposed. Furthermore, the semiconductor pattern 105 can be partially removed using a selective etching process to retain a semiconductor pattern 105 with a predetermined thickness. The retained semiconductor pattern 105 can extend in a first direction, and as... Figure 9BThe diagram shows a lower surface that is recessed relative to the exposed lower surface of the device isolation layer 110. The device isolation layer 110 may define a space FH from which the semiconductor pattern 105 is removed.

[0062] Next, refer to Figure 8C and Figure 9C A dielectric isolation layer 210 can be formed on the lower surface of the retained semiconductor pattern 105, and a dielectric substrate layer 220 can be formed on the dielectric isolation layer 210.

[0063] First, a dielectric isolation layer 210 can be formed on the semiconductor pattern 105 and the device isolation layer 110. For example... Figure 9C As shown, dielectric isolation layer 210 may be formed on the lower surface of the recess in semiconductor pattern 105, at least partially exposed to the sidewalls of space FH, and on the lower surface of device isolation layer 110. Dielectric isolation layer 210 may be conformally formed on semiconductor pattern 105 and device isolation layer 110 using a deposition process (such as CVD). For example, dielectric isolation layer 210 may include silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or aluminum oxynitride.

[0064] The dielectric substrate layer 220 may be formed to at least partially fill the spaces FH on the dielectric isolation layer 210 where the semiconductor pattern 105 has been partially removed. The dielectric substrate layer 220 may include, for example, SOH, FOX, TOSZ, USG, BSG, PSG, BPSG, PETEOS, FSG, HDP oxide, PEOX, FCVD oxide, or combinations thereof. For example, the dielectric substrate layer 220 may be formed using CVD, fluid CVD, or spin coating processes. In some embodiments, a planarization process may be additionally performed on the lower surface of the dielectric substrate layer 220.

[0065] Next, refer to Figure 8D Multiple first openings TH can be formed by partially removing the dielectric substrate layer 220 and the dielectric isolation layer 210.

[0066] A plurality of first openings TH can be formed in regions of the dielectric substrate layer 220 corresponding to the plurality of gate structures GS, respectively, using a selective etching process. The plurality of first openings TH can extend through the dielectric isolation layer 210 to the gate structures GS. In some embodiments, the semiconductor pattern 105 may be formed as a plurality of portions separated by the plurality of first openings TH.

[0067] Because the etching process for the multiple first openings TH is performed at relatively low temperatures (e.g., 400°C or less) to avoid adversely affecting the metal composition (assembly) of the first interconnect structure 190, it may be difficult to form the multiple first openings TH with a nearly vertical structure. Therefore, the first openings TH may have a tapered structure. Figure 8DAs shown, each of the plurality of first openings TH may have a shape in which the width Wb' of the portion adjacent to the lower surface of the dielectric substrate layer 220 is larger than the width Wa of the portion adjacent to the plurality of gate structures GS. Furthermore, due to differences in etching rates, the inner sidewalls of the semiconductor pattern 105 and the inner sidewalls of the dielectric substrate layer 220 may have different profiles (e.g., tilt angles).

[0068] Next, refer to Figure 8E Dielectric isolation patterns 230 can be formed in multiple first openings TH respectively.

[0069] In some embodiments, a deposition process may be performed to form dielectric isolation patterns 230 in a plurality of first openings TH. The first openings TH may be at least partially filled during the deposition process of the insulating material. For example, the dielectric isolation patterns 230 may comprise silicon nitride or silicon oxynitride. In the insulating material deposition process for forming the plurality of dielectric isolation patterns 230, the plurality of dielectric isolation patterns 230 are formed to cover or at least partially overlap with the lower surface of the dielectric substrate layer 220, and furthermore, by a polishing process, such as... Figure 8E As shown, the lower surface of the dielectric substrate layer 220 may be at least partially exposed and may have a substantially flat surface coplanar with the lower surface of the dielectric isolation pattern 230.

[0070] Next, refer to Figure 8F and Figure 9D The dielectric substrate layer 220 can be removed to form the second opening CS.

[0071] The second opening CS substantially corresponds to the space FH beneath each of the first source / drain patterns 150A and the second source / drain patterns 150B, where the semiconductor pattern 105 has been partially removed therefrom. A dielectric isolation layer 210 may be formed (e.g., retained) on the inner surface of the second opening CS and on the lower surface of the device isolation layer 110. In the removal process, the dielectric isolation layer 210 may serve as an etch stop layer. The width of each of the second openings CS in a first direction (e.g., the X direction) may be defined by a plurality of dielectric isolation patterns 230, and the width of each of the second openings CS in a second direction (e.g., the Y direction) may be defined by the space FH beneath which the semiconductor pattern 105 on which the dielectric isolation layer 210 is formed is partially removed (see [reference]). Figure 9B )limited.

[0072] Figures 10A to 10D and Figures 11A to 11D This is a cross-sectional view illustrating key processes in a method for manufacturing a semiconductor device according to embodiments of the present disclosure (back contact formation process). Here, Figures 10A to 10D They are respectively with Figure 2 The corresponding sectional view, and Figures 11A to 11DThey are respectively with Figure 3A The corresponding sectional views, and respectively represent Figures 10A to 10D The process.

[0073] Reference Figure 10A and Figure 11A A third opening CH' connected to the first source / drain pattern 150A may be additionally formed in at least one of the second openings CS.

[0074] A selective removal process can be applied to the second opening CS located below the first source / drain pattern 150A. A third opening CH' connected to the first source / drain pattern 150A can be formed by removing a portion of the dielectric isolation layer 210 exposed to the second opening CS and removing the semiconductor pattern 105 via the removal region. The second opening CS with the third opening CH' formed can then be connected to the first source / drain pattern 150A.

[0075] Subsequently, referring to Figure 10B and Figure 11B The second opening CS and the third opening CH' can be at least partially filled by the conductive blocking element 282 and the first conductive material MP1 (or contact plug).

[0076] Prior to depositing the first conductive material MP1, a conductive barrier 282 may be conformally formed on the surface exposed by the second opening CS and the third opening CH'. Since the conductive barrier 282 is formed at a relatively low temperature (e.g., 400°C or less) so as not to adversely affect the metal composition (assembly) of the first interconnect structure 190, it is desirable to form the conductive barrier 282 with sufficient thickness to prevent or suppress pinhole defects. Therefore, the second opening CS and the third opening CH' may be at least partially filled to a certain level by the conductive barrier 282, which has a relatively high resistance.

[0077] Next, a first conductive material MP1 can be formed in the second opening CS, such that the third opening CH' on the conductive barrier 282 is at least partially filled. The deposition process of the first conductive material MP1 can be performed by a non-selective deposition process (e.g., CVD or PVD). Since the deposited first conductive material MP1 grows from almost the entire surface of the conductive barrier 282, the deposited first conductive material MP1 can be a polycrystalline metal. Therefore, since the deposited first conductive material MP1 is distributed on multiple grain boundaries, the deposited first conductive material MP1 can have a high resistance compared to a single-crystal metal. The first conductive material MP1 can at least partially fill the third opening CH' to form a contact via 286 connected to at least partially exposed areas of the first source / drain pattern 150A.

[0078] Next, refer to Figure 10C and Figure 11C It can perform a back-etching process on the deposited first conductive material MP1.

[0079] The etching process can be performed under conditions where not only the first conductive material MP1 but also the conductive blocking element 282 is removed. An etching process can be performed to remove the first conductive material MP1 and the conductive blocking element 282 located in the second opening CS', but leaving at least a portion of the first conductive material MP1 such that this at least portion has a certain thickness. The retained first conductive material 285a can be used as a seed layer and can be the first part of the contact block. Here, the retained first conductive material 285a can be retained with a thickness of almost no pinholes and can have, for example, a thickness of 1 nm or greater, but is not limited thereto. In this etching process, the conductive blocking element 282 can be removed together from most of the sidewalls of the dielectric isolation pattern 230 defining the second opening CS'. As a result, the volume of the conductive blocking element 282, which has relatively high resistance, can be significantly reduced, thereby improving the electrical characteristics of the final lower contact structure 280.

[0080] Next, refer to Figure 10D and Figure 11D A second conductive material MP2 can be deposited on the retained first portion 285a.

[0081] In some embodiments, the second conductive material MP2 may be the same material as the first conductive material MP1. For example, the first conductive material MP1 may be molybdenum, and the second conductive material MP2 may also be the same molybdenum. However, this disclosure is not limited thereto, and the first conductive material MP1 and the second conductive material MP2 may be different conductive materials having substantially the same or similar crystal structures. The second conductive material MP2 may be formed by selective deposition. The second conductive material MP2 may be grown in a bottom-up manner using the retained first portion 285a as a seed layer, resulting in the second conductive material MP2 having an almost single-crystal structure. For example, when the second conductive material MP2 is grown by atomic layer deposition (ALD) process, MoCl5, which can be selectively deposited, may be used as a precursor.

[0082] In some embodiments, the first conductive material MP1 (see...) Figure 10B ) and the second conductive material MP2 (see Figure 10D Both materials can be deposited using the ALD process, or they can be deposited separately using non-selective deposition (i.e., conformal filling) and selective deposition (i.e., bottom-up growth) by selecting different precursors. For example, when both the first conductive material MP1 and the second conductive material MP2 are molybdenum (Mo), the deposition of the first conductive material MP1 can use MoO2Cl2 as a precursor, and the deposition of the second conductive material MP2 can use MoCl5 as a precursor.

[0083] In this way, by etching back the contact block 285 together with the conductive barrier 282 so that only the first grown portion 285a of the first conductive material MP1 is retained, the volume of the conductive barrier with high resistance in the final lower contact structure can be reduced, and the retained portion 285a can be used as a seed to regrow the second conductive material, thereby providing a high-quality contact block 285 (a contact block 285 with minimized grain boundaries).

[0084] Subsequently, a polishing process can be performed to remove the second conductive material MP2 and at least partially expose the lower surface of the dielectric isolation pattern 230. As a result, the contact blocks 285 can be separated from each other through the dielectric isolation pattern 230. This polishing process can be performed to reduce the semiconductor device 100 to a desired thickness. For example, as Figure 10D and Figure 11D As shown, the polishing process can be performed until a predetermined polishing stop line PL is reached, but is not limited to this. Afterwards, return to the reference. Figures 1 to 3B A second interconnect structure 290 can be formed on the dielectric isolation pattern 230 and the contact block 285.

[0085] According to the above embodiment, the contact block and the conductive barrier are etched back together so that only a portion of the contact block is retained. Then, the retained area is used as a seed to regrow the contact block, thereby minimizing the conductive barrier to improve or reduce contact resistance and provide a high-quality contact block (a contact block with minimized grain boundaries).

[0086] While embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The semiconductor pattern extends in the first direction; Multiple channel structures are spaced apart from each other in a first direction and are on a semiconductor pattern, wherein each of the multiple channel structures includes multiple channel patterns; Multiple gate structures extend over the multiple channel structures in a second direction intersecting the first direction and around the multiple channel patterns; Source / drain patterns, on the semiconductor pattern and on the side surfaces of the plurality of channel patterns; A dielectric isolation layer is placed on the lower surface of the semiconductor pattern. Multiple dielectric isolation patterns extend upward toward the multiple gate structures in a third direction perpendicular to the first direction; Multiple contact blocks are respectively located between adjacent dielectric isolation patterns in the multiple dielectric isolation patterns, and on the lower surface of the dielectric isolation layer; At least one contact via extends from at least one of the plurality of contact blocks into the dielectric isolation layer to contact at least one of the source / drain patterns, respectively. A conductive blocking element is positioned between the dielectric isolation layer and the plurality of contact blocks and contacts the at least one contact via, wherein each of the plurality of contact blocks includes a side surface that contacts a sidewall of an adjacent dielectric isolation pattern in the plurality of dielectric isolation patterns; and An interconnection structure is located on the lower surface of the plurality of contact blocks, on the plurality of dielectric isolation patterns, and electrically connected to the at least one contact block.

2. The semiconductor device according to claim 1, wherein, In the cross-sectional view, each of the plurality of dielectric isolation patterns has a shape in which the width of a first portion adjacent to the interconnect structure in a first direction is greater than the width of a second portion adjacent to the plurality of gate structures in the first direction.

3. The semiconductor device according to claim 1, wherein, In the cross-sectional view, each of the plurality of contact blocks has a shape in which the width of a first portion adjacent to the interconnect structure in a first direction is smaller than the width of a second portion adjacent to the dielectric isolation layer in the first direction.

4. The semiconductor device according to claim 1, wherein, The conductive barrier has an extension portion that extends upward in a third direction and contacts the first dielectric isolation pattern among the plurality of dielectric isolation patterns.

5. The semiconductor device according to claim 4, wherein, The length of the extended portion of the conductive barrier in the third direction is in the range of 1 nm to 10 nm.

6. The semiconductor device according to claim 4, wherein, Each of the plurality of contact blocks comprises the same metal material as the metal material of the at least one contact via.

7. The semiconductor device according to claim 4, wherein, Each of the plurality of contact blocks comprises a metal having a single-crystal structure.

8. The semiconductor device according to claim 4, wherein: Each of the plurality of contact blocks includes a first portion and a second portion, the first portion at least partially overlapping with an extension of the conductive barrier in a first direction, and the second portion contacting an adjacent dielectric isolation pattern among the plurality of dielectric isolation patterns. Part One and Part Two consist of different metallic materials.

9. The semiconductor device according to claim 8, wherein, The at least one contact via comprises the same metal material as the first portion of the plurality of contact blocks.

10. The semiconductor device according to claim 1, wherein, The plurality of contact blocks and the at least one contact via comprise tungsten or molybdenum.

11. The semiconductor device according to claim 1, wherein, Conductive blocking elements include Ta, TaN, Mn, MnN, WN, Ti, TiN, or combinations thereof.

12. The semiconductor device according to claim 1, further comprising: A metal-semiconductor compound film, between a first contact via in the at least one contact via and a first source / drain pattern in the at least one source / drain pattern.

13. The semiconductor device according to claim 12, wherein, Metal-semiconductor compound films include at least one of Ti, Co, Ni, Pt, Zr, Mo, and Sc.

14. A semiconductor device, comprising: The semiconductor pattern extends in the first direction; Device isolation layer, extending on opposite side surfaces of a semiconductor pattern and in a first direction; Multiple channel structures are spaced apart from each other in a first direction and are on a semiconductor pattern; Multiple gate structures are provided on the multiple channel structures and extend in a second direction intersecting the first direction; Source / drain patterns are respectively located between the plurality of channel structures and on the semiconductor pattern; A dielectric isolation layer is placed on the lower surface of the semiconductor pattern. Multiple dielectric isolation patterns extend upward toward the multiple gate structures in a third direction perpendicular to the first direction; Multiple contact blocks are respectively located between adjacent dielectric isolation patterns in the multiple dielectric isolation patterns, and on the lower surface of the dielectric isolation layer; At least one contact via extends from at least one of the plurality of contact blocks into the dielectric isolation layer to contact at least one of the source / drain patterns, respectively. A conductive blocking element is located between the dielectric isolation layer and the plurality of contact blocks and contacts the at least one contact via, wherein each of the plurality of contact blocks includes a side surface that contacts a sidewall of an adjacent dielectric isolation pattern in the plurality of dielectric isolation patterns. as well as An interconnection structure is provided on the lower surface of the plurality of contact blocks, on the plurality of dielectric isolation patterns, on the device isolation layer, and electrically connected to the at least one contact block.

15. The semiconductor device according to claim 14, wherein, The conductive barrier has an extension that extends in a third-order direction from the sidewall of the plurality of dielectric isolation patterns into the dielectric isolation layer.

16. The semiconductor device according to claim 15, wherein, Each of the plurality of contact blocks comprises the same metal material as the metal material of the contact via, and wherein the metal material has a single crystal structure.

17. The semiconductor device according to claim 16, wherein, Metallic materials include molybdenum or tungsten.

18. The semiconductor device according to claim 15, wherein: Each of the plurality of contact blocks includes a first portion and a second portion, the first portion being at least partially overlapping with an extension of a conductive barrier in a first direction, and the second portion contacting an adjacent dielectric isolation pattern among the plurality of dielectric isolation patterns. The contact via and the first part include a first metallic material, and The second part includes a second metallic material that is different from the first metallic material.

19. The semiconductor device according to claim 18, wherein, The first metallic material includes W, Mo, Co, or Ru.

20. A semiconductor device, comprising: The semiconductor pattern extends in the first direction; Device isolation layer, extending on opposite side surfaces of a semiconductor pattern and in a first direction; Multiple channel structures are spaced apart from each other in a first direction and are on a semiconductor pattern; Multiple gate structures are provided on the multiple channel structures and extend in a second direction intersecting the first direction; First source / drain pattern and second source / drain pattern on semiconductor pattern; An interlayer insulating layer extends on the device isolation layer and around the plurality of gate structures, the first source / drain pattern, and the second source / drain pattern; A dielectric isolation layer is placed on the lower surface of the semiconductor pattern. Multiple dielectric isolation patterns extend toward the multiple gate structures in a third direction and into the dielectric isolation layer, wherein the third direction is perpendicular to the first direction; The upper contact is electrically connected to the first source / drain pattern and extends into the interlayer insulating layer; Multiple contact blocks are respectively located between adjacent dielectric isolation patterns in the multiple dielectric isolation patterns, and on the lower surface of the dielectric isolation layer; A contact via extends from the first contact block, which is adjacent to the second source / drain pattern, to the second source / drain pattern and into the dielectric isolation layer; A conductive blocking element is located between the dielectric isolation layer and the plurality of contact blocks and in contact with a contact via, wherein each of the plurality of contact blocks includes a side surface that contacts a sidewall of an adjacent dielectric isolation pattern in the plurality of dielectric isolation patterns. A first interconnect structure is on the interlayer insulating layer and electrically connected to the upper contact; and The second interconnect structure is located on the lower surface of the plurality of contact blocks, on the plurality of dielectric isolation patterns, on the device isolation layer, and is electrically connected to the first contact block.

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