Semiconductor structure with occupying position margin

Abstract

A semiconductor structure having an improved footprint margin is provided. In an embodiment, a semiconductor structure includes a nanosheet transistor, the nanosheet transistor includes a plurality of spaced apart and vertically stacked nanosheets of semiconductor channel material, a gate structure surrounding each of the nanosheets of semiconductor channel material, a first source / drain region on a first side of the gate structure, and a second source / drain region on a second side of the gate structure. The gate structure has a first gate thickness underlying a bottommost semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets, the first gate thickness is greater than a second gate thickness between a bottommost semiconductor channel material nanosheet and a nearest overlying semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and more specifically, to a semiconductor structure having improved site margin. Background Technology

[0002] In recent years, the semiconductor industry has transitioned from FinFETs to gate-all-around stacked nanosheet transistor architectures. Compared to FinFETs, nanosheet transistors deliver more drive current by increasing the channel width within the same circuit footprint. The gate-all-around design improves channel control and minimizes short-channel effects. Summary of the Invention

[0003] A semiconductor structure with improved footprint margin without including a bottom dielectric isolation layer is provided.

[0004] In one embodiment of the present invention, the semiconductor structure includes a nanosheet transistor comprising a plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, a gate structure surrounding the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, a first source / drain region located on a first side of the gate structure, and a second source / drain region located on a second side of the gate structure. The gate structure has a first gate thickness below the bottommost semiconductor channel material nanosheet of the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, the first gate thickness being greater than the second gate thickness between the bottommost semiconductor channel material nanosheet and the nearest overlying semiconductor channel material nanosheet of the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets. The structure also includes a back-side source / drain contact structure that electrically contacts the second source / drain region of the nanosheet transistor.

[0005] In another embodiment of the invention, the semiconductor structure includes a nanosheet transistor comprising a plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, a gate structure surrounding the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, a first source / drain region located on a first side of the gate structure, and a second source / drain region located on a second side of the gate structure, wherein the gate structure has a first gate thickness below the bottommost semiconductor channel material nanosheet of the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, the first gate thickness being greater than a second gate thickness located between the bottommost semiconductor channel material nanosheet of the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets and the nearest overlying semiconductor channel material nanosheet. The structure of this embodiment also includes a bottom internal spacer structure located laterally adjacent to the first gate thickness of the gate structure, an upper internal spacer located above the bottom internal spacer structure and laterally adjacent to the second gate thickness of the gate structure, a back-side source / drain contact structure for the second source / drain region of the nanosheet transistor, and a back-side source / drain contact occupancy structure located below the first source / drain region, wherein the semiconductor buffer layer is located between the first source / drain region and the back-side source / drain contact occupancy structure.

[0006] In another embodiment of the invention, the semiconductor structure includes a nanosheet transistor comprising a plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, a gate structure surrounding the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, a first source / drain region located on a first side of the gate structure, and a second source / drain region located on a second side of the gate structure, wherein the gate structure has a first gate thickness below the bottommost semiconductor channel material nanosheet of the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, the first gate thickness being greater than a second gate thickness located between the bottommost semiconductor channel material nanosheet of the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets and the nearest overlying semiconductor channel material nanosheet. In this embodiment, the structure further includes: a bottom internal spacer structure having a first vertical height and positioned laterally adjacent to a first gate thickness of the gate structure, the bottom internal spacer structure including a first internal spacer and a second internal spacer vertically spaced apart by a semiconductor material liner; and an upper internal spacer having a second vertical height and located above the bottom internal spacer structure and positioned laterally adjacent to a second gate thickness of the gate structure, wherein the first vertical height is greater than the second vertical height. Attached Figure Description

[0007] Figure 1This is a top view of an exemplary semiconductor device layout that can be adopted according to an embodiment of the present invention, the semiconductor device layout including a plurality of active regions oriented along a first direction and a plurality of functional gate structures oriented in a second direction perpendicular to the first direction; cross-sections AA and BB are shown in the figure.

[0008] Figure 2A and 2B The methods that can be used in this invention are respectively corresponding to Figure 1 The cross-sectional view of the exemplary semiconductor structure shown in sections AA and BB includes a first semiconductor layer, an etch stop layer, a second semiconductor layer, and a stack of alternating sacrificial semiconductor material layers and semiconductor channel material layers, wherein the bottommost semiconductor channel material layer has a thickness less than the thickness of the other semiconductor channel material layers in the stack.

[0009] Figure 3A and 3B They are Figure 2A and 2B The exemplary semiconductor structure shown is a cross-sectional view after patterned materials are stacked and a shallow trench isolation structure is formed.

[0010] Figure 4A and Figure 4B These are respectively after the formation of the sacrificial gate structure, hard mask cap, and gate spacer. Figure 3A and Figure 3B A cross-sectional view of an exemplary semiconductor structure is shown.

[0011] Figure 5A and 5B These are respectively patterned nanosheets formed after previously patterned material stacks. Figure 4A and 4B The cross-sectional view of the exemplary semiconductor structure shown indicates that the previously patterned nanosheet stacks of material are patterned to form at least one nanosheet stack of alternating sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets, and each sacrificial semiconductor material nanosheet of the at least one nanosheet stack is recessed, i.e. indented.

[0012] Figure 6A and 6B They are Figure 5A and 5B The exemplary semiconductor structure shown is a cross-sectional view after the formation of the conformal internal dielectric spacer layer.

[0013] Figure 7A and 7B They are Figure 6A and 6BThe exemplary semiconductor structure shown is a cross-sectional view after an isotropic etching process is performed on the conformal internal dielectric spacer layer to form the internal spacers.

[0014] Figure 8A and Figure 8B These are after the protective layer has been formed. Figure 7A and Figure 7B A cross-sectional view of an exemplary semiconductor structure is shown.

[0015] Figure 9A and 9B These steps involve removing the protective layer from all horizontal surfaces of the structure to provide a protective liner and forming a spacer cavity in the second semiconductor layer. Figure 8A and 8B A cross-sectional view of an exemplary semiconductor structure is shown.

[0016] Figure 10A and 10B This involves forming a back-side source / drain contact occupant structure within the cavity and then forming a semiconductor buffer layer on the source / drain contact occupant structure. Figure 9A and 9B A cross-sectional view of an exemplary semiconductor structure is shown.

[0017] Figure 11A and Figure 11B These steps involve removing the protective liner and forming source / drain regions on the semiconductor buffer layer, followed by forming a first front-side interlayer dielectric (ILD) layer on the source / drain regions. Figure 10A and Figure 10B A cross-sectional view of an exemplary semiconductor structure is shown in the figure.

[0018] Figure 12A and 12B These steps involve removing the sacrificial gate structure to expose the underlying nanosheet stack, and then removing each sacrificial semiconductor nanosheet from the exposed nanosheet stack. Figure 11A and 11B A cross-sectional view of an exemplary semiconductor structure is shown.

[0019] Figure 13A and 13B These are respectively after performing the nanosheet trimming process. Figure 12A and 12B The cross-sectional view of the exemplary semiconductor structure shown illustrates that a nanosheet trimming process removes the exposed portion of the bottom semiconductor channel material nanosheet of the nanosheet stack.

[0020] Figure 14A and Figure 14BThese steps are: forming the second front-side ILD layer (where the first and second front-side ILD layers together form a mid-stage (MOL) dielectric multilayer structure), forming the front-side contact structure within the MOL dielectric multilayer structure, forming the front-side back-end (BEOL) structure, and then forming the carrier wafer. Figure 13A and Figure 13B A cross-sectional view of an exemplary semiconductor structure is shown.

[0021] Figure 15A and 15B They are Figure 14A and 14B The exemplary semiconductor structure shown is a cross-sectional view after the first semiconductor layer has been removed to expose the etch stop layer.

[0022] Figure 16A and Figure 16B These are respectively after removing the etch stop layer and the second semiconductor layer. Figure 15A and Figure 15B A cross-sectional view of an exemplary semiconductor structure is shown.

[0023] Figure 17A and Figure 17B These are after the formation of the dorsal ILD layer. Figure 16A and Figure 16B A cross-sectional view of an exemplary semiconductor structure is shown.

[0024] Figure 18A and 18B They are Figure 17A and 17B The exemplary semiconductor structure shown is a cross-sectional view after back-side contact patterning, which exposes at least one of the back-side source / drain contact berth structures.

[0025] Figure 19A and 19B These refer to the removal of at least one exposed back-side source / drain contact berth structure and semiconductor buffer layer to physically expose one of the source / drain regions. Figure 18A and 18B A cross-sectional view of an exemplary semiconductor structure is shown.

[0026] Figure 20A and 20B These are, respectively, after the formation of the back-side source / drain contact structure and the formation of the back-side interconnect structure. Figure 19A and 19B A cross-sectional view of an exemplary semiconductor structure is shown.

[0027] Figures 21A-21B These are respectively patterned nanosheets formed after previously patterned material stacks. Figure 3A and 3BThe exemplary semiconductor structure shown is a cross-sectional view, wherein the previously patterned nanosheet stacks of material are patterned to form at least one nanosheet stack of alternating sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets, and an opening is formed in the second semiconductor layer, and each sacrificial semiconductor material nanosheet of the at least one nanosheet stack is recessed.

[0028] Figures 22A-22B They are respectively in the execution such as Figure 6A and 6B to Figure 20A and 20B The following further anterior and dorsal treatments are shown Figure 21A and 21B A cross-sectional view of an exemplary semiconductor structure is shown. Detailed Implementation

[0029] Embodiments of the invention will now be described in more detail with reference to the following discussion and accompanying drawings. It should be noted that the drawings are provided for illustrative purposes only, and therefore are not drawn to scale. It should also be noted that identical and corresponding elements are indicated by the same reference numerals.

[0030] In the following description, numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, are set forth in order to provide an understanding of various embodiments of the invention. However, those skilled in the art will understand that various embodiments of the invention can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the invention.

[0031] It should be understood that when an element that is a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intermediate elements present. It will also be understood that when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly below" or "directly under" another element, there are no intermediate elements present.

[0032] In this specification, a semiconductor structure is described and shown as comprising at least one nanosheet transistor. The transistor (or field-effect transistor (FET)) includes a source region, a drain region, a semiconductor channel region located between the source and drain regions, and a gate structure located above the semiconductor channel region. Commonly, the source and drain regions may be referred to as source / drain regions. A nanosheet transistor is a non-planar transistor comprising a vertically stacked arrangement of spaced-apart nanosheets of semiconductor channel material as the semiconductor channel region, with a pair of source / drain regions located at each end of the vertically stacked arrangement of the spaced-apart semiconductor channel material nanosheets. The gate structure includes a gate dielectric and a gate electrode. The gate structure surrounds each of the plurality of spaced-apart semiconductor channel material nanosheets. In some cases, the nanosheet transistor is therefore referred to as a gate-all-around (GAA) transistor. Nanosheet transistors offer considerable scaling with high drive current capability. Compared to FinFET technology, nanosheet transistors provide a greater drive current for a given footprint.

[0033] In one embodiment of the present invention, the semiconductor structure includes a front side and a back side. The front side includes one side of the structure comprising at least one nanosheet transistor, a front contact structure, and a front BEOL structure. The back side is the side of the structure opposite to the front side. The back side includes a back contact structure and a back interconnect structure.

[0034] In conventional nanosheet transistor processes where a bottom dielectric isolation layer exists beneath the nanosheet transistor, there are challenges in controlling the level of the back-side source / drain contact berth and the source / drain region formed above it; in such processes, a semiconductor buffer layer is typically formed between the back-side source / drain contact berth and the source / drain region. If the level of the back-side source / drain contact berth is too low, exposing the semiconductor buffer layer, there is a high risk of damaging the source / drain region during back-side source / drain contact berth removal. If the level of the back-side source / drain contact berth is too high, causing the semiconductor buffer layer to contact one of the semiconductor channel material nanosheets, it can lead to locally high on-resistance.

[0035] In other conventional nanosheet transistor processes that do not use a bottom dielectric isolation layer, the process window is even smaller than when a bottom dielectric isolation layer is used. This means that without a bottom dielectric isolation layer, there is a greater risk of damaging the source / drain regions and a greater likelihood of high on-resistance.

[0036] This invention overcomes the aforementioned processing challenges of existing nanosheet transistor devices lacking a bottom dielectric isolation layer. In one embodiment of the invention, the risk of damage to the source / drain regions and high on-resistance during removal of the back-side source / drain contact footprint is mitigated. Therefore, this invention provides a semiconductor structure with improved footprint margin. These and other aspects of the invention will now be described in more detail below.

[0037] In one embodiment of the invention (see, for example) Figures 20A-20B or Figures 22A-22B Semiconductor structures include nanosheet transistors, which comprise multiple spaced and vertically stacked semiconductor channel material nanosheets (i.e., Figures 20A-20B And the stacking of semiconductor channel material nanosheets 18NS shown in 22A-22B). A gate structure 40 surrounding a plurality of spaced and vertically stacked semiconductor channel material nanosheets, with a first source / drain region located on a first side of the gate structure 40 (e.g., in Figure 20A and 22A The source / drain region 36 found on the left-hand side and the second source / drain region located on the second side of the gate structure 40 (e.g., in Figure 20A and 22A The source / drain region 36 is found on the right side of the structure, wherein the gate structure 40 has a first gate thickness TG1 below the bottommost semiconductor channel material nanosheet of a plurality of spaced and vertically stacked semiconductor channel material nanosheets, which is greater than the second gate thickness TG2 located between the bottommost semiconductor channel material nanosheet and the nearest overlying semiconductor channel material nanosheet of the plurality of spaced and vertically stacked semiconductor channel material nanosheets. The structure also includes a back-side source / drain contact structure 52 for electrically contacting the second source / drain region of the nanosheet transistor. Forming TG1 with a thickness greater than TG2 allows for a wider process window during the formation of the back-side source / drain contact berth structure 32, which will be explained in detail below.

[0038] In one embodiment of the invention (see, for example) Figures 20A-20B or Figures 22A-22B The structure may further include a bottom internal spacer structure 28S located laterally adjacent to the first gate thickness TG1 of the gate structure 40, and an upper internal spacer located above the bottom internal spacer structure 28S and laterally adjacent to the second gate thickness TG2 of the gate structure 40. The upper internal spacer may include an internal spacer 28 located directly above the bottom internal spacer structure 28S.

[0039] In such embodiments (see, for example) Figures 20A to 20B or Figures 22A to 22B), the bottom internal spacer structure 28S includes a first internal spacer and a second internal spacer, wherein the first internal spacer is vertically spaced apart from the second internal spacer by a semiconductor material liner 18L.

[0040] In one embodiment of the present invention (see, for example Figures 20A-20B or Figures 22A-22B ), each semiconductor channel material nanosheet 18NS of the plurality of spaced and vertically stacked semiconductor channel material nanosheets and the semiconductor material liner 18L are made of the same semiconductor material.

[0041] In one embodiment of the present invention, the bottom internal spacer structure 28S has a first vertical height, and the upper internal spacer (i.e., the internal spacer 28 located directly above the bottom internal spacer structure 28S) has a second vertical height, wherein the first vertical height is greater than the second vertical height.

[0042] In one embodiment of the present invention (see, for example Figures 20A-20B or Figures 22A-22B ), the first source / drain region of the nanosheet transistor is located on the backside source / drain contact placeholder structure 32.

[0043] In one embodiment of the present invention (see, for example Figures 20A-20B or Figures 22A-22B ), the structure may further include a semiconductor buffer layer 34 located between the first source / drain region and the backside source / drain contact placeholder structure 32.

[0044] In one embodiment of the present invention (see, for example Figures 20A-20B or Figures 22A-22B ), the structure may further include a frontside BEOL structure 44 electrically connected to the first source / drain region through the frontside source / drain contact structure 42A.

[0045] In one embodiment of the present invention, the structure may further include a semiconductor buffer layer located between the second source / drain region and the backside source / drain contact structure 52.

[0046] In one embodiment of the present invention, each semiconductor channel material nanosheet 18NS of the plurality of spaced and vertically stacked semiconductor channel material nanosheets is dumbbell-shaped, having a middle portion and two end portions, the middle portion having a first thickness, and the two end portions having a second thickness greater than the first thickness.

[0047] In one embodiment of the present invention, the backside source / drain contact structure 52 has a first portion and a second portion, wherein the second portion of the backside source / drain contact structure is closer to the second source / drain region than the first portion, and wherein the uppermost segment of the second portion is restricted by a protective liner 30L.

[0048] In one embodiment of the present invention, the first portion has a first critical size CD1, and the second portion has a second critical size CD2, wherein CD2 is smaller than CD1.

[0049] In one embodiment of the present invention, a first portion of the back-side source / drain contact structure 52 contacts the back-side interconnect structure 54.

[0050] In another embodiment of the invention (see, for example) Figures 20A-20B or Figures 22A-22B Semiconductor structures include nanosheet transistors, which comprise multiple spaced and vertically stacked semiconductor channel material nanosheets (i.e., Figures 20A-20B And the stacking of semiconductor channel material nanosheets 18NS shown in 22A-22B). A gate structure 40 surrounding a plurality of spaced and vertically stacked semiconductor channel material nanosheets, with a first source / drain region located on a first side of the gate structure 40 (i.e., Figure 20A and 22A The source / drain region 36 on the left-hand side and the second source / drain region on the second side of the gate structure 40 (i.e., Figure 20A and 22A The source / drain region 36 on the left side), wherein the gate structure 40 has a first gate thickness TG1 below the bottom semiconductor channel material nanosheet of a plurality of spaced and vertically stacked semiconductor channel material nanosheets, which is greater than the second gate thickness TG2 between the bottom semiconductor channel material nanosheet and the nearest overlying semiconductor channel material nanosheet of the plurality of spaced and vertically stacked semiconductor channel material nanosheets. The structure of this embodiment also includes a bottom internal spacer structure 28S located laterally adjacent to the first gate thickness TG1 of the gate structure 40, an upper internal spacer located above the bottom internal spacer structure 28S and laterally adjacent to the second gate thickness TG2 of the gate structure 40 (i.e., the internal spacer 28 located directly above the bottom internal spacer structure 28S), a back-side source / drain contact structure 52 electrically contacting the second source / drain region of the nanosheet transistor; and a back-side source / drain contact occupancy structure 32 located below the first source / drain region, wherein the semiconductor buffer layer 34 is located between the first source / drain region and the back-side source / drain contact occupancy structure 32.

[0051] In one embodiment of the invention (see, for example) Figures 20A-20B or Figures 22A-22B The bottom internal spacer structure 28S includes a first internal spacer and a second internal spacer, wherein the first internal spacer is vertically spaced from the second internal spacer by a semiconductor material liner 18L.

[0052] In one embodiment of the invention, each of the plurality of spaced and vertically stacked semiconductor channel material nanosheets 18NS and semiconductor material liner 18L is composed of the same semiconductor material.

[0053] In one embodiment of the invention (see, for example) Figure 10A and Figures 20A-20B or Figures 22A-22B The top surface of the bottom internal spacer structure 28S is located at a first level, the top surface of the semiconductor buffer layer 34 is located at a second level, the top surface of the back-side source / drain contact occupancy structure 32 is located at a third level, and the bottom surface of the bottom internal spacer structure 28S is located at a fourth level, wherein the first level is greater than the second level and the third level is greater than the fourth level.

[0054] In the embodiments (see, for example) Figures 20A-20B or Figures 22A-22B The back-side source / drain contact structure 52 has a first portion and a second portion, wherein the second portion of the back-side source / drain contact structure 52 is closest to the second source / drain region than the first portion, and wherein the uppermost section of the second portion is limited by a protective liner 30L.

[0055] In one embodiment of the present invention, the first portion has a first critical size and the second portion has a second critical size, wherein the second critical size is smaller than the first critical size.

[0056] In one embodiment of the present invention, a first portion of the back-side source / drain contact structure 52 contacts the back-side interconnect structure 54.

[0057] In an embodiment, the structure also includes a front BEOL structure 44 electrically connected to the first source / drain region via a front source / drain contact structure 42A.

[0058] In another embodiment of the invention (see, for example) Figures 20A-20B or Figures 22A-22B The semiconductor structure includes a nanosheet transistor comprising a plurality of spaced and vertically stacked semiconductor channel material nanosheets (i.e., semiconductor channel material nanosheets 18NS). A gate structure 40 surrounds the plurality of spaced and vertically stacked semiconductor channel material nanosheets, and a first source / drain region is located on a first side of the gate structure 40 (i.e., Figure 20A and 22B The source / drain region 36 on the left-hand side and the second source / drain region on the second side of the gate structure 40 (i.e., located on the left-hand side) ... Figure 20A and 20BThe source / drain region 36 on the right side of the gate structure 40 has a first gate thickness TG1 below the bottommost semiconductor channel material nanosheet of a plurality of spaced and vertically stacked semiconductor channel material nanosheets, which is greater than the second gate thickness TG2 between the bottommost semiconductor channel material nanosheet and the nearest overlying semiconductor channel material nanosheet of the plurality of spaced and vertically stacked semiconductor channel material nanosheets. In this embodiment, the structure also includes a bottom internal spacer structure 28S having a first vertical height and laterally adjacent to the first gate thickness TG1 of the gate structure 40. The bottom internal spacer structure 28S includes a first internal spacer and a second internal spacer vertically spaced by a semiconductor material liner 18L, and an upper internal spacer having a second vertical height and located above the bottom internal spacer structure 28S and laterally adjacent to the second gate thickness TG2 of the gate structure 40 (i.e., an internal spacer 28 located directly above the bottom internal spacer structure 28S), wherein the first vertical height is greater than the second vertical height.

[0059] In one embodiment of the invention, the first vertical height is substantially equal to the first gate thickness, and the second vertical height is substantially equal to the second gate thickness.

[0060] In one embodiment of the invention, each of the plurality of spaced and vertically stacked semiconductor channel material nanosheets 18NS and the semiconductor material liner is composed of the same semiconductor material.

[0061] Now for reference Figure 1 The figure illustrates an exemplary semiconductor device layout that can be employed according to embodiments of the present invention. The semiconductor device layout includes a plurality of active regions oriented along a first direction, such as a first active region AA1 and a second active region AA2, and a plurality of functional gate structures, such as GS1, GS2, and GS3, oriented in a second direction perpendicular to the first direction; cutouts AA and BB are shown in the figure. As an example, three functional gate structures GS1, GS2, and GS3 and two active regions AA1 and AA2 are shown. Cutout AA passes through the length direction of AA1 and through each of GS1, GS2, and GS3, and cutout BB passes through the length direction of GS2 and through AA1 and AA2.

[0062] Now for reference Figure 2A and 2B This illustrates the respective corresponding [models] that can be used in one embodiment of the invention. Figure 1The exemplary semiconductor structure shown is illustrated by cross-sections AA and BB. The semiconductor structure includes a first semiconductor layer 10, an etch stop layer 12, a second semiconductor layer 14, and an alternating stack of sacrificial semiconductor material layers 16 and semiconductor channel material layers 18, 18b, wherein element 18b represents the bottommost semiconductor channel material layer, and element 18 represents other semiconductor channel material layers within the material stack. In one embodiment of the invention, the bottommost semiconductor channel material layer 18b is intentionally designed to have a thickness less than the other semiconductor channel material layers 18 in the material stack. Due to variations in site location, the bottommost nanosheet is unsuitable as a channel nanosheet, as it may sometimes be attached to the S / D epi (i.e., source / drain region 36), or sometimes not if the back-side source / drain contact site structure 32 grows too high. Therefore, forming a thinner bottommost nanosheet makes it easier to remove it later as a sacrificial nanosheet.

[0063] In one embodiment of the present invention, the first semiconductor layer 10, the etch stop layer 12, and the second semiconductor layer 14 may be components of a substrate. The first semiconductor layer 10 is made of a first semiconductor material, and the second semiconductor layer 14 is made of a second semiconductor material. The term "semiconductor material" is used throughout the specification to refer to a material having semiconductor properties. Examples of semiconductor materials that may be used to provide the first and second semiconductor materials in one embodiment of the present invention include, but are not limited to, silicon (Si), silicon-germanium (SiGe) alloys, silicon-germanium carbide (SiGeC) alloys, germanium (Ge), group III / V compound semiconductors, or group II / VI compound semiconductors. The second semiconductor material providing the second semiconductor layer 14 may be compositionally the same as or different from the first semiconductor material providing the first semiconductor layer 10.

[0064] In some embodiments of the present invention, the etch stop layer 12 may be made of a dielectric material, such as silicon dioxide and / or boron nitride. In other embodiments of the present invention, the etch stop layer 12 is made of a semiconductor material that is compositionally different from the first semiconductor material providing the first semiconductor layer 10 and the second semiconductor material providing the second semiconductor layer 14. In one example, the first semiconductor layer 10 is made of silicon, the etch stop layer 12 is made of silicon dioxide, and the second semiconductor layer 14 is made of silicon. In another example, the first semiconductor layer 10 is made of silicon, the etch stop layer 12 is made of silicon-germanium, and the second semiconductor layer 14 is made of silicon.

[0065] The substrate comprising a first semiconductor layer 10, an etch stop layer 12, and a second semiconductor layer 14 can be formed using techniques known to those skilled in the art. For example, the substrate comprising the first semiconductor layer 10, the etch stop layer 12, and the second semiconductor layer 14 can be formed by oxygen ion implantation or by separation of wafer bonding. Alternatively, the substrate comprising the first semiconductor layer 10, the etch stop layer 12, and the second semiconductor layer 14 can be formed by depositing various substrate layers one on top of another. Depositions used to form various substrate layers may include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or epitaxial growth. The term “epitaxygmal growth” or “epitaxially growing” refers to the growth of a semiconductor material on the growth surface of another semiconductor material, wherein the grown semiconductor material has the same crystal properties as the growth surface of the other semiconductor material. During epitaxial deposition, the chemical reactants supplied by the source gas are controlled, and system parameters are set such that the deposited atoms reach the growth surface of the other semiconductor material and have sufficient energy to move on the growth surface and adapt themselves to the crystal arrangement of the atoms on the growth surface. Examples of various epitaxial growth process apparatuses that can be employed in one embodiment of the invention include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Epitaxial deposition temperatures are typically in the range of 550°C to 900°C. While higher temperatures generally result in faster deposition, faster deposition can lead to crystal defects and film rupture.

[0066] As described above, the material stack includes alternating sacrificial semiconductor material layers 16 and semiconductor channel material layers 18, 18b. In some embodiments and as... Figure 2A and Figure 2BAs shown, there are an equal number of sacrificial semiconductor material layers 16 and semiconductor channel material layers 18, 18b. That is, the material stack may include "n" semiconductor channel material layers 18, 18b and "n" sacrificial semiconductor material layers 16, where n is an integer greater than one. As an example, the material stack includes four sacrificial semiconductor material layers 16 and four semiconductor channel material layers 18, 18b. Each sacrificial semiconductor material layer 16 is composed of a third semiconductor material, while each semiconductor channel material layer 18, 18b is composed of a fourth semiconductor material that is different in composition from the third semiconductor material. In some embodiments, the fourth semiconductor material providing each semiconductor channel material layer 18, 18b can provide high channel mobility for an n-type field-effect transistor (FET) device. In other embodiments, the fourth semiconductor material providing each semiconductor channel material layer 18, 18b can provide high channel mobility for a p-type FET device. The third semiconductor material providing each sacrificial semiconductor material layer 16 and the fourth semiconductor material providing each semiconductor channel material layer 18, 18b may include one of the aforementioned semiconductor materials. In one example, the third semiconductor material providing each sacrificial semiconductor material layer 16 is composed of a silicon-germanium alloy with a germanium content of 20 to 40 atomic percent, and the fourth semiconductor material providing each semiconductor channel material layer 18, 18b is composed of silicon. Other combinations of semiconductor materials are possible as long as the third semiconductor material providing each sacrificial semiconductor material layer 16 is composed differently from the fourth semiconductor material providing each semiconductor channel material layer 18, 18b.

[0067] The material stack, including alternating sacrificial semiconductor material layers 16 and semiconductor channel material layers 18, 18b, can be formed by any combination of CVD, PECVD, epitaxial growth, or such deposition processes.

[0068] Now for reference Figure 3A and 3B The images show the results after the patterned material is stacked and forms a shallow trench isolation structure 20. Figure 2A and 2B The exemplary semiconductor structure shown is illustrated. Patterning of the material stack includes photolithography and etching. Photolithography includes forming a photoresist material on the layer or stack of layers to be patterned, exposing the photoresist material to an illumination pattern, and developing the exposed photoresist material. Etching may include reactive ion etching (RIE), ion beam etching (IBE), plasma etching, or any combination thereof. The etching etches through the entire material stack and stops at the surface of the second semiconductor layer 14. After etching, any remaining photoresist material can be removed using conventional photoresist removal processes.

[0069] Following this patterning process, at least one patterned material stack is formed. In the example shown, and as... Figure 2B As shown, two patterned material stacks are formed. Each patterned material structure includes a remaining (i.e., unetched) portion of each sacrificial semiconductor layer 16 and a remaining (i.e., unetched) portion of each semiconductor channel material layer 18, 18b. In one embodiment of the invention, each remaining (i.e., unetched) portion of the sacrificial semiconductor layer 16 in the patterned material stack may be referred to as a patterned sacrificial semiconductor layer, and each remaining (i.e., unetched) portion of the semiconductor channel material layers 18, 18b in the patterned material stack may be referred to as a patterned semiconductor channel material layer.

[0070] The shallow trench isolation structure 20 is made of any trench dielectric material, such as silicon oxide. In some embodiments, a trench dielectric liner composed of, for example, SiN may be present along the sidewalls and bottomwalls of the trench dielectric material. The shallow trench isolation structure 20 has a top surface that is coplanar with or slightly below the top surface of the second semiconductor layer 14. The shallow trench isolation structure 20 can be formed by forming trenches in the second semiconductor layer 14, depositing optional trench dielectric liner material and trench dielectric material in the trenches, and then performing an etch-back process. The shallow trench isolation structure 20 is formed on a sub-surface of the second semiconductor layer 14 and along the sidewalls of the unetched portion of the second semiconductor layer 14.

[0071] Now for reference Figure 4A and 4B The diagrams show the results after the formation of the sacrificial gate structure 22, the hard mask cap 24, and the gate spacer 26. Figure 3A and 3B The exemplary semiconductor structure is shown. In some embodiments, the hard mask cover 24 can be omitted from the structure. In the illustrated embodiment, Figure 4A Three sacrificial gate structures 22 are shown, and each sacrificial gate structure 22 spans at least one of the patterned material stacks. The term "spans" means that one material layer is located on the topmost surface and the opposite sidewall surface of another material layer; Figure 4B The diagram shows the cross-sectional aspect, where the sacrificial gate structure 22 is located on top of each patterned material stack and along the sidewalls.

[0072] The sacrificial gate structure 22 includes at least a sacrificial gate material. In some embodiments, the sacrificial gate structure 22 may also include a sacrificial gate dielectric material. In such embodiments, the sacrificial gate dielectric material is located below the sacrificial gate material. The optional sacrificial gate dielectric material may be made of a dielectric material such as, for example, silicon dioxide. The sacrificial gate material may be composed of, for example, polycrystalline silicon, amorphous silicon, amorphous silicon germanium, or amorphous germanium. The hard mask cap 24 is made of a hard mask material such as, for example, silicon nitride.

[0073] The sacrificial gate structure 22 and the hard mask cap 24 (if present) can be formed by depositing an optional sacrificial gate dielectric material, depositing a sacrificial gate material, and depositing a hard mask material (if the hard mask cap 24 is present), and then subjecting the deposited material layers to a patterning process. Patterning includes photolithography and etching as defined above.

[0074] The gate spacer 26, which exists along the opposing sidewalls of the sacrificial gate structure 22 and the hard mask cap 24 (if present), can be made of a dielectric spacer material, including but not limited to silicon dioxide, SiN, SiBCN, SiOCN, or SiOC. The gate spacer 28 can be formed by depositing the dielectric spacer material and then etching the spacer.

[0075] Now for reference Figure 5A and 5B The figures show the patterning of nanosheets after the previous patterning of the material stacks. Figure 4A and 4B The exemplary semiconductor structure shown depicts a previously patterned stack of nanosheets patterned to form at least one stack of alternating sacrificial semiconductor material nanosheets 16NS and semiconductor channel material nanosheets 18NS, 18bNS, with each sacrificial semiconductor material nanosheet 16NS of the at least one nanosheet stack recessed, i.e., retracted. In one embodiment of the invention, the semiconductor channel material nanosheet 18bNS represents the bottommost semiconductor channel material nanosheet of the nanosheet stack. The bottommost semiconductor channel material nanosheet 18bNS has a thickness less than the thickness of the other semiconductor channel material nanosheet 18NS in the nanosheet stack.

[0076] Nanosheet patterning utilizes a sacrificial gate structure 22 (if present), a hard mask cap 24, and gate spacers 26 present along at least the sidewalls of the sacrificial gate structure 22 as a combined etch mask. Etching, such as RIE, is then employed to remove portions of the patterned material stack not protected by the combined etch mask. Immediately following nanosheet patterning and before recessing, the sacrificial semiconductor material nanosheets 16NS and 18NS, 18bNS have the same width.

[0077] The recessing (i.e., shrinkage) of the sacrificial semiconductor nanosheet 16NS involves a lateral etching process that removes the ends of each sacrificial semiconductor nanosheet 16NS. This lateral etching does not cause the semiconductor channel material nanosheets 18NS and 18bNS to be recessed.

[0078] Now for reference Figure 6A and 6B The figures show the process after the formation of the conformal internal dielectric spacer layer 28L. Figure 5A and 5B The exemplary semiconductor structure is shown. Throughout this specification, the term "conformal" is used to refer to a material layer whose thickness along a horizontal surface of another material layer or structure is the same as its thickness along a vertical surface of that other material layer or structure. The conformal internal dielectric spacer layer 28L is composed of a dielectric spacer material, such as, for example, silicon dioxide, SiN, SiBCN, SiOCN, or SiOC. The dielectric spacer material providing the conformal internal dielectric spacer layer 28L may be compositionally the same as or different from the dielectric spacer material providing the gate spacer 26.

[0079] The conformal internal dielectric spacer layer 28L is formed using any conformal deposition process, such as, for example, CVD, PECVD, or atomic layer deposition (ALD). The conformal internal dielectric spacer layer 28L does not pinch the gate-to-gate spacer, and the conformal internal dielectric spacer layer 28L has sufficient thickness to fill each recess (gap) formed by the aforementioned recess (i.e., indentation) of the sacrificial semiconductor nanosheet 16NS.

[0080] Now for reference Figure 7A and 7B The figures show the results after performing an isotropic etch-back process on the conformal internal dielectric spacer layer 28L to form the internal spacer 28. Figure 6A and 6B The exemplary semiconductor structure shown. The internal spacers 28 are laterally adjacent to each of the recessed sacrificial semiconductor nanosheets 16NS, and each of the internal spacers 28 has an outermost edge that is vertically aligned with the outermost edge (i.e., sidewall) of the semiconductor channel material nanosheets 18NS, 18bNS.

[0081] Because the bottom semiconductor channel material layer 18b is intentionally designed to have a thickness smaller than that of the other semiconductor channel material layers 18, a structure such as... Figure 7AThe bottom internal spacer structure 28S is shown. The bottom internal spacer structure 25S includes two of the internal spacers 28 (i.e., the bottommost internal spacer and an internal spacer positioned immediately above the bottommost internal spacer), which are separated by a thin layer of semiconductor channel material (i.e., the semiconductor liner 18L described below). The remaining internal spacers 28 that are not part of the bottom internal spacer structure 28S may be referred to herein as upper internal spacers.

[0082] Now for reference Figure 8A and 8B The figures show the results after the formation of the protective layer 30. Figure 7A and 7B The exemplary semiconductor structure is shown. The protective layer 30 is then processed into a protective liner 30L, and in one embodiment of the invention, the protective liner 30L is used as a structure for protecting the subsequently grown source / drain region 36 during the subsequent formation of the back-side source / drain contact. Figure 7A and 7B All physically exposed surfaces of the exemplary structure shown. The protective layer 30 is composed of a dielectric material that differs in composition from the hard mask cap 24, gate spacer 26, and internal spacer 28. The dielectric material providing the protective liner layer 30 may be, for example, AlO₂. x and TiO x Composition. The protective layer 30 can be formed by deposition (e.g., CVD, PECVD, or ALD). The protective layer 30 is typically a conformal layer as defined above.

[0083] Now for reference Figure 9A and 9B These are respectively after the protective layer 30 is removed from all horizontal surfaces of the structure to provide a protective liner 30L and a spacer cavity 31 is formed in the second semiconductor layer 14. Figure 8A and 8B The diagram shows a cross-sectional view of an exemplary semiconductor structure. Removing the protective layer 30 from all horizontal surfaces of the structure includes a directional etching process, and this step opens the protective layer 30. The unetched portions of the protective layer 30 provide a protective liner 30L. The protective liner 30L is formed along the sidewalls of the gate spacer 26, the sidewalls of the internal spacer 28 (including the bottom internal spacer structure 28S), and along the sidewalls of each semiconductor channel material nanosheet 18NS, 18bNS, as shown. Figure 9AAs shown. Forming a cavity 31 in the second semiconductor layer 14 includes recess etching, which is selective in removing the second semiconductor material providing the second semiconductor layer 14. In one example, the recess etching includes a re-evaluation (RIE). The recess etching physically exposes a sub-surface of the second semiconductor layer 14. The term "sub-surface" as used throughout the specification refers to the surface of the material layer / structure located between the topmost and bottommost surfaces of the material layer / structure.

[0084] Now for reference Figure 10A and 10B The diagrams show the formation of a back-side source / drain contact occupant structure 32 in the occupant cavity and the formation of a semiconductor buffer layer 34 on the source / drain contact occupant structure 32, respectively. Figure 9A and 9B The exemplary semiconductor structure shown is typically formed due to variations in manufacturing processes. Figure 10A The back-side source / drain contact occupancy structures 32 at different heights are shown.

[0085] The back-side source / drain contact berth structure 32 is composed of a fifth semiconductor material, which is compositionally different from the second semiconductor material providing the second semiconductor layer 14 and the sixth semiconductor material providing the semiconductor buffer layer 34. In one example, the back-side source / drain contact berth structure 32 is made of a silicon-germanium alloy, while the semiconductor buffer layer 34 is made of silicon. The back-side source / drain contact berth structure 32 can be formed by depositing (e.g., CVD, PECVD, or epitaxial growth) the fifth semiconductor material and then performing recess etching. The semiconductor buffer layer 34 can be formed by depositing (e.g., CVD, PECVD, or epitaxial growth) the sixth semiconductor material and then performing recess etching. Note that the lower portion of the protective liner 30L exists along the sidewall of the semiconductor buffer layer 34, and in some cases, along the upper portion of the sidewall of the back-side source / drain contact berth structure 32.

[0086] In one embodiment of the invention, the back-side source / drain contact berths 32 have such a height that the topmost surface of each back-side source / drain contact berth 32 is located anywhere between the topmost surface of the second semiconductor layer 14 and the topmost surface of the bottom inner spacer structure 28S. Horizontal levels 1, 2, 3, and 4 are... Figure 10A The figures are shown by dashed lines. Horizontal 1 represents the first horizontal level located at the topmost surface of the bottom inner spacer structure 28S, and horizontal 2 represents the level located at one of the semiconductor buffer layers (i.e., Figure 10A The second level at the top surface of the right-hand side semiconductor buffer layer 34, level 3 indicates one of the source / drain contact occupancy structures located on the back side (i.e., Figure 10ALevel 1 represents the third level at the top surface of the back-side source / drain contact berth structure 32 on the left side, and Level 4 represents the fourth level at the bottom surface of the bottom internal spacer structure 28S. In one embodiment of the invention, Level 1 must be higher than Level 2 to ensure that all semiconductor channel material nanosheets 18NS are connected to the S / D epi, i.e., the source / drain region 36, and Level 3 must be higher than Level 4. In one embodiment of the invention, and due to the formation of the bottom internal spacer structure 28S (which is approximately twice as thick as other (i.e., upper) internal spacers 28 not present in the bottom internal spacer structure 28S), the process window for the berth margin is sufficient, considering the 3 sigma process variation including the berth cavity 31, etching, and the formation of the back-side source / drain contact berth structure 32.

[0087] Now for reference Figure 11A and 11B The diagrams show the process after the upper portion of the protective liner 30L is removed and source / drain regions 36 are formed on the semiconductor buffer layer 34, and a first front-side interlayer dielectric (ILD) layer 38 is formed on the source / drain regions 36. Figure 10A and 10B The exemplary semiconductor structure shown is shown.

[0088] The upper portion of the protective liner 30L is removed by selective etching in the removal of the dielectric material providing the protective layer 30. The lower portion of the protective liner 30L, present along the sidewalls of the semiconductor buffer layer 34, and in some cases the upper portion of the sidewalls of the back-side source / drain contact berth structure 32, are retained, such as... Figure 11A As shown. In one embodiment of the invention, each nanosheet transistor formed will include a pair of source / drain regions 36. Due to process variations, one of the source / drain regions 36 (i.e., the first source / drain region) may have a different source / drain region than the other (i.e., the second source / drain region of the pair of source / drain regions 36, see example). Figure 10A The vertical height of ).

[0089] Source / drain regions 36 are typically formed via epitaxial growth processes, as defined above. Recessed etching may be performed after the epitaxial growth process. Source / drain regions 36 extend outward from the physically exposed sidewalls of each semiconductor channel material nanosheet 18NS and upward from the semiconductor buffer layer 34; when the bottommost semiconductor channel material nanosheet 18bNS is physically exposed, the source / drain regions 36 may grow outward from the physically exposed sidewalls of the bottommost semiconductor channel material nanosheet 18bNS. Each of the source / drain regions 36 is composed of a seventh semiconductor material and dopants. As used herein, a “source / drain” region may be a source region or a drain region, depending on subsequent wiring and voltage application during transistor operation. The seventh semiconductor material providing the source / drain regions 36 may be compositionally identical or compositionally different from the fourth semiconductor material providing each semiconductor channel material nanosheet 18NS, 18bNS. The dopants present in the source / drain regions 36 may be p-type or n-type dopants. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor that create defects that generate valence electrons. Examples of p-type dopants (i.e., impurities) in silicon-containing semiconductor materials include, but are not limited to, boron, aluminum, gallium, phosphorus, and indium. "N-type" refers to the addition of impurities that contribute free electrons to the intrinsic semiconductor. Examples of n-type dopants (i.e., impurities) in silicon-containing semiconductor materials include, but are not limited to, antimony, arsenic, and phosphorus. In one example, each source / drain region 36 can have a range from 4 × 10⁻⁶. 20 atoms / cm 3 Up to 3 × 10 21 atoms / cm 3 The dopant concentration.

[0090] Next, a first front-side ILD layer 38 is formed on top of and laterally adjacent to each source / drain region 36. The first front-side ILD layer 38 is composed of a dielectric material, including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borosilicate glass (BPSG), spin-coated low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term “low-k” as used throughout this specification refers to a dielectric material with a dielectric constant less than 4.0 (unless otherwise stated, all dielectric constants mentioned herein are relative to vacuum). The first front-side ILD layer 38 can be formed by deposition processes, including but not limited to CVD, PECVD, or spin-coating. A planarization process, such as chemical mechanical polishing (CMP), is performed after the deposition process. The planarization process removes the top portion of the gate spacer 26 and, if present, the hard mask cap 24. This planarization process exposes the sacrificial gate structure 22, as shown below. Figure 11A and 11B As shown.

[0091] Now for reference Figure 12A and 12B The figures show the results after removing the sacrificial gate structure 22 to expose the underlying nanosheet stack, and after removing each sacrificial semiconductor nanosheet 16NS of the exposed nanosheet stack. Figure 11A and 11B The exemplary semiconductor structure is shown. The sacrificial gate structure 22 can be removed from the structure using a material removal process, such as etching, which is selective in the removal of the sacrificial gate structure 22. This material removal step exposes the underlying nanosheet stack. After exposing the nanosheet stack, each sacrificial semiconductor material nanosheet 16NS is removed to suspend a portion of each semiconductor channel material nanosheet 18NS, 18bNS. Each sacrificial semiconductor material nanosheet 16NS is removed using any material removal process (e.g., etching), which is selective in the removal of the sacrificial semiconductor nanosheet 16NS.

[0092] Now for reference Figure 13A and 13B The figures show the results after performing the nanosheet trimming process. Figure 12A and 12B The exemplary semiconductor structure shown depicts a nanosheet trimming process that removes the physically exposed portion of the bottommost semiconductor channel material nanosheet 18bNS of the nanosheet stack. The nanosheet trimming process may include oxidation followed by etching. A portion of the bottommost semiconductor channel material nanosheet 18bNS remains between the two internal spacers defining the aforementioned bottom internal spacer structure 28S. The remaining bottommost semiconductor channel material nanosheet 18bNS may be referred to herein as a semiconductor material liner 18L. The semiconductor material liner 18L may have a thickness from 2 nm to 6 nm. This trimming process thins the physically exposed portion of each remaining semiconductor channel material nanosheet 18NS, thereby providing a dumbbell-shaped semiconductor channel material nanosheet having two ends with a first thickness and a middle portion with a first thickness T1 located between the two ends, the two ends having a second thickness T2 greater than the first thickness T1. The dumbbell-shaped semiconductor channel material nanosheet is depicted in... Figure 13A Note that, for clarity, the dumbbell-shaped semiconductor channel material nanosheets are not shown in the other figures, but are still present in them.

[0093] Following this thinning step, a nanosheet stack is thus provided, comprising spaced-apart and vertically stacked semiconductor channel material nanosheets 18NS (dumbbell-shaped), wherein a first distance d1, measured from the top surface of the second semiconductor layer 14 to the bottom surface of the bottom semiconductor channel material nanosheets 18NS, is greater than a second distance d2, measured from the top surface of each semiconductor channel material nanosheet 18NS. In one embodiment of the invention, d1 is substantially equal to (within ±10%) the vertical height of the bottom internal spacer structure 28S, and d2 is substantially equal to (within ±10%) the vertical height of the other (i.e., upper) internal spacers 28. In one embodiment of the invention, the vertical height of the bottom internal spacer structure 28S is greater than the vertical height of the other internal spacers 28 (i.e., upper internal spacers) not present in the bottom internal spacer structure. In subsequent processing steps, the second semiconductor layer 14 (along with the etch stop layer 12 and the first semiconductor layer 10) will be removed, and a back-side ILD layer 48 will be formed in the region previously occupied by the second semiconductor layer 14, the etch stop layer 14, and the first semiconductor layer. When this occurs, d1 will be measured from the top surface of the back-side ILD layer 48 to the bottom surface of the vertically separated and spaced semiconductor channel material nanosheets 18NS.

[0094] Now for reference Figure 14A and 14B The diagrams show the formation of the gate structure 40 and the second front-side ILD layer, respectively. Figure 13A and 13B The exemplary semiconductor structure shown includes a first front-side ILD layer 38 and a second front-side ILD layer that together form a mid-stage process (MOL) dielectric multilayer structure 39. A front-side contact structure is formed in the MOL dielectric multilayer structure 39, forming a front-side BEOL structure 44 and a carrier wafer 46.

[0095] A gate structure 40 is formed in the region previously accompanied by the sacrificial semiconductor nanosheet 16NS and the bottom semiconductor channel material nanosheet 18bNS, and on top of the top semiconductor channel material nanosheet 18NS. The gate structure 40 surrounds each semiconductor nanosheet 18NS within each nanosheet stack. The gate structure 40 includes a gate dielectric layer and a gate electrode; neither the gate dielectric layer nor the gate electrode is shown separately in the figures, but both are included in the region shown as the gate structure 40. As is known, the gate dielectric layer is formed directly around the suspended portion of each semiconductor channel material nanosheet 18NS, and the gate electrode is formed on the gate dielectric layer. The gate dielectric layer of the gate structure 40 is composed of a gate dielectric material having a dielectric constant greater than 4.0. Illustrative examples of gate dielectric materials that may be used to provide the gate dielectric layer include, but are not limited to, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon nitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), and zirconium silicon nitride (ZrSiO). x N y ), tantalum oxide (TaO) x The gate dielectric material may include dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg). Other materials include titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and / or lead zinc niobate (Pb(Zn,Nb)O).

[0096] The gate electrode of gate structure 40 is made of a gate electrode material. The gate electrode material may include a work function metal (WFM) and optionally a conductive metal. The WFM can be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM can be selected to achieve an n-type threshold voltage offset. As used herein, "n-type threshold voltage offset" means an offset of the effective work function of the work function-containing metal material toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of such materials that can achieve an n-type threshold voltage offset include, but are not limited to, aluminum titanium, aluminum titanium carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM can be selected to achieve a p-type threshold voltage offset. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" is the minimum achievable gate voltage that will turn on the device by conducting the channel of the semiconductor device (e.g., a transistor). As used herein, the term "p-type threshold voltage offset" refers to the offset of the effective work function of a metallic material toward the valence band of silicon in a silicon-containing material. Examples of materials that can achieve a p-type threshold voltage offset include, but are not limited to, titanium nitride and tantalum carbide, hafnium carbide, and combinations thereof. Optional conductive metals may include, but are not limited to, aluminum (Al), tungsten (W), or cobalt (Co). The gate structure 40 can be formed by depositing gate dielectric and gate electrode materials followed by a planarization process that removes any gate dielectric and gate electrode materials formed on top of the gate spacer 26 and the first ILD layer 38.

[0097] The second front-side ILD layer includes one of the dielectric materials described above for the first front-side ILD layer 38. The dielectric material providing the second front-side ILD layer may be compositionally the same as or different from the dielectric material providing the first front-side ILD layer 38. The second front-side ILD layer is formed on top of each of the gate structure 40, the gate spacer 28, and the first front-side ILD layer 38. The second front-side ILD layer can be formed using one of the deposition processes described above for forming the first front-side ILD layer 38. As described above, the first front-side ILD layer 38 and the second front-side ILD layer together provide the MOL dielectric multilayer structure 39, such as... Figures 14A-14B As shown.

[0098] The front contact structure is now formed as an MOL dielectric multilayer structure 39. The front contact structure includes a front source / drain contact structure 42A and a front gate contact structure 42B. The front contact structure is formed using a metallization process. The metallization process includes forming contact openings in the MOL dielectric multilayer structure 39 and then filling (including deposition and planarization) those contact openings with at least a contact conductor material. Contact conductor materials that can be used to provide the front contact structure include, for example, silicide liners (such as Ni, Pt, NiPt), adherent metal liners (such as TiN), and conductive metals (such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof). The front contact structure may also include one or more contact liners (not shown). In one or more embodiments, the contact liners (not shown) may include diffusion barrier materials. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. In one or more embodiments where a contact liner is present, the contact liner (not shown) may include a silicide liner (such as Ti, Ni, NiPt, etc.) and a diffusion barrier material as defined above.

[0099] In one embodiment of the invention, the gate structure 40 has a first thickness TG1 measured from the topmost surface of the second semiconductor layer 14 (and subsequently from the topmost surface of the back-side ILD layer 48) to the bottommost surface of the vertically separated and spaced-apart semiconductor channel material nanosheets 18NS, and a second first thickness TG2 measured from the topmost surface of each of the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets 18NS. In one embodiment of the invention, TG1 is greater than TG2. Note that TG1 is equal to d1 as described above, and TG2 is equal to d2 as described above.

[0100] Next, a front BEOL structure 44 is formed on the topmost surface of the MOL dielectric multilayer structure 39. The front BEOL structure 44 may include one or more interconnect dielectric material layers (including one of the dielectric materials described above for the first front ILD layer 38), which contain embedded front metal wires (the metal wires may be composed of any conductive metal or conductive metal alloy). Electrical contacts are formed between the front BEOL structure 44 and each front contact structure.

[0101] The carrier wafer 46 may include one of the semiconductor materials described above for the first semiconductor layer 10. After the front BEOL structure 44 is formed, the carrier wafer 46 is bonded to the front BEOL structure 44. This completes the front-side processing of the semiconductor structure.

[0102] Now for reference Figure 15A and 15BThe figures show the process after the first semiconductor layer 10 is removed to expose the etch stop layer 12. Figure 14A and 14B The exemplary semiconductor structure is shown. Removal of the first semiconductor layer 10 typically involves flipping the wafer 180° to physically expose the back side of the substrate. For clarity, this flipping step is not shown in the figures. Flipping physically exposes the first semiconductor layer 10 and allows for back-side processing of the exemplary structure. The flipping of the structure can be performed by hand or by utilizing mechanical means such as, for example, a robotic arm. In the illustrated embodiment, the removal of the physically exposed first semiconductor layer 10 physically exposes the etch stop layer 12. The removal of the first semiconductor layer 10 can be performed using a material removal process that is selective in removing the first semiconductor material providing the first semiconductor layer 10.

[0103] Now for reference Figure 16A and 16B The images show the results after the removal of the etch stop layer 12 and the second semiconductor layer 14, respectively. Figure 15A and 15B The exemplary semiconductor structure is shown. Removal of the etch stop layer 12 includes a selective material removal process in removing the etch stop layer 12. Removal of the etch stop layer 12 physically exposes the second semiconductor layer 14. The physically exposed second semiconductor layer 14 can be removed using a material removal process that is selective in removing the layer from the structure. Figures 16A-16B As shown, removing the etch stop layer 12 and the second semiconductor layer 14 exposes the surface of each back-side source / drain contact berth structure 32. Note that, as Figure 16B As shown, the removal of the second semiconductor layer 14 also exposes the surface of the shallow trench isolation structure 22.

[0104] Now for reference Figure 17A and Figure 17B The figures show the formation of the dorsal ILD layer 48 after its formation. Figure 16A and Figure 16B The exemplary semiconductor structure is shown. The back-side ILD layer 50 includes one of the dielectric materials described above for the first front-side ILD layer 38. The back-side ILD layer 48 can be formed using one of the deposition processes described above for forming the first front-side ILD layer 38. The back-side ILD layer 48 is embedded in the back-side source / drain contact berth structure 32 and the shallow trench isolation structure 20.

[0105] Now for reference Figure 18A and 18B The diagrams show the results after back-side contact patterning. Figure 17A and 17BThe exemplary semiconductor structure shown has a back-side contact patterning that exposes at least one of the back-side source / drain contact berths 32. The back-side contact patterning includes photolithography and etching, wherein etching forms an initial back-side source / drain contact opening 50 in the back-side ILD layer 48.

[0106] Now for reference Figure 19A and 19B The diagrams illustrate the removal of at least one exposed back-side source / drain contact occupant structure 32 and semiconductor buffer layer 34 to physically expose one of the source / drain regions 36. Figure 18A and 18B The exemplary semiconductor structure is shown. In some embodiments, the physically exposed semiconductor buffer layer 34 is not removed.

[0107] The removal of the back-side source / drain contact berth 32 includes a material removal process, such as etching, which is selective in removing the exposed back-side source / drain contact berth 32. This removal exposes the semiconductor buffer layer 34. No damage to the source / drain region 36 occurs during the removal of the physically exposed back-side source / drain contact berth 32. In some embodiments, the exposed semiconductor buffer layer 34 may be removed using a material removal process (e.g., etching), which is selective in removing the exposed semiconductor buffer layer 34. Figure 19A As shown, the semiconductor buffer layer 34 is removed to expose one of the source / drain regions 36. These removal steps (or simply removing the exposed back-side source / drain contact berth structure 32) form a back-side source / drain contact opening 50E in the structure. As shown, the back-side source / drain contact opening 50E has a first portion that is self-aligned relative to and closest to the exposed source / drain region 36, and is narrower than a second portion of the back-side source / drain contact opening 50E that is further away from the exposed source / drain region 36. If the semiconductor buffer layer 34 is exposed, the back-side source / drain contact opening 50E will have a similar configuration.

[0108] Now for reference Figure 20A and 20B The diagrams show the back-side source / drain contact structure 52, which is in direct physical contact with the physically exposed source / drain regions 36, and the back-side interconnect structure 54, respectively. Figure 19A and 19BThe exemplary semiconductor structure is shown. In some embodiments, the back-side source / drain contact structure 52 is in direct physical contact with the physically exposed semiconductor buffer layer 34 still located on the surface of the source / drain region 36. The back-side source / drain contact structure 52 includes a back-side source / drain contact opening 50E filled (including deposition and planarization) with at least a contact conductor material, as defined above. It is worth noting that contact conductor materials that can be used to provide the back-side source / drain contact structure 52 include, for example, silicide liners (such as Ni, Pt, NiPt), adherent metal liners (such as TiN), and conductive metals (such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof). The front-side contact structure may also include one or more contact liners (not shown). In one or more embodiments, the contact liners (not shown) may include diffusion barrier materials. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. In one or more embodiments where a contact liner is present, the contact liner (not shown) may include a silicide liner (such as Ti, Ni, NiPt, etc.) and a diffusion barrier material, as defined above. The formed back-side source / drain contact structure 52 includes a first portion having a first critical size CD1 and a second portion having a second critical size CD2, wherein CD2 is smaller than CD1. In one embodiment of the invention, the second portion of the back-side source / drain contact structure 52 having CD2 is closest to the source / drain region 36 than the first portion of the back-side source / drain contact structure 52 having CD1.

[0109] Now for reference Figures 21A-21B The figures show the patterning of nanosheets after the previous patterning of the material stacks. Figure 3A and 3B The exemplary semiconductor structure shown includes a previously patterned nanosheet stack of material stacks patterned to form at least one nanosheet stack of alternating sacrificial semiconductor material nanosheets 16NS and semiconductor channel material nanosheets 18NS, 18bNS, and an opening (or recess) 56 is formed in the second semiconductor layer 14, and each sacrificial semiconductor material nanosheet 16NS in the at least one nanosheet stack is recessed.

[0110] Nanosheet patterning utilizes a sacrificial gate structure 22 (if present), a hard mask cap 24, and gate spacers 26 existing along at least the sidewalls of the sacrificial gate structure 22 as a combined etch mask. Etching, such as RIE, is then employed to remove portions of the patterned material stack not protected by the combined etch mask. During this etching, openings 56 are formed in the second semiconductor layer 14. Immediately following nanosheet patterning, the sacrificial semiconductor material nanosheets 16NS and semiconductor channel material nanosheets 18NS, 18bNS have the same width.

[0111] The recess (i.e., shrinkage) of the sacrificial semiconductor nanosheet 16NS involves a lateral etching process that removes the ends of each sacrificial semiconductor nanosheet 16NS. This lateral etching does not cause the semiconductor channel material nanosheets 18NS and 18bNS to shrink.

[0112] Now for reference Figures 22A-22B The following shows the execution of, respectively. Figure 6A and 6B to Figure 20A and 20B The following further anterior and dorsal treatments are shown Figure 21A and 21B The exemplary semiconductor structure shown.

[0113] exist Figures 20A-20B The illustrated embodiments or Figures 22A-22B In the embodiment shown, the top surface of the bottom internal spacer structure 28S is at a first level, the top surface of the semiconductor buffer layer 34 is at a second level, the top surface of the back-side source / drain contact occupancy structure 32 is at a third level, and the bottom surface of the bottom internal spacer structure 28S is at a fourth level, wherein level 1 is greater than level 2 and level 3 is greater than level 4.

[0114] While the invention has been particularly shown and described with respect to its preferred embodiments, those skilled in the art will understand that the above and other changes in form and detail may be made without departing from the scope of the invention. Therefore, it is intended that the invention be limited to the exact forms and details described and shown, but falls within the scope of the appended claims.

[0115] In a preferred embodiment of the invention described herein, a semiconductor structure is provided, comprising: a nanosheet transistor including a plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, a gate structure surrounding the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, a first source / drain region located on a first side of the gate structure, and a second source / drain region located on a second side of the gate structure, wherein the gate structure has a first gate thickness below the bottommost semiconductor channel material nanosheet of the plurality of spaced-apart and vertically stacked semiconductor channel material nanosheets, the first gate thickness being greater than that of the bottommost semiconductor channel material nanosheet. A second gate thickness between the nearest overlying semiconductor channel material nanosheets of the plurality of spaced and vertically stacked semiconductor channel material nanosheets; a bottom internal spacer structure having a first vertical height and positioned laterally adjacent to the first gate thickness of the gate structure, the bottom internal spacer structure including a first internal spacer and a second internal spacer vertically spaced apart by a semiconductor material liner; and an upper internal spacer having a second vertical height and located above the bottom internal spacer structure and positioned laterally adjacent to the second gate thickness of the gate structure, wherein the first vertical height is greater than the second vertical height. Preferably, the first vertical height is substantially equal to the first gate thickness, and the second vertical height is substantially equal to the second gate thickness. Preferably, each of the plurality of spaced and vertically stacked semiconductor channel material nanosheets and the semiconductor material liner is composed of the same semiconductor material.

Claims

1. A semiconductor structure, comprising: A nanosheet transistor comprising a plurality of spaced and vertically stacked semiconductor channel material nanosheets, a gate structure surrounding the plurality of spaced and vertically stacked semiconductor channel material nanosheets, a first source / drain region located on a first side of the gate structure, and a second source / drain region located on a second side of the gate structure, wherein the gate structure has a first gate thickness below the bottommost semiconductor channel material nanosheet of the plurality of spaced and vertically stacked semiconductor channel material nanosheets, the first gate thickness being greater than a second gate thickness located between the bottommost semiconductor channel material nanosheet and the nearest overlying semiconductor channel material nanosheet of the plurality of spaced and vertically stacked semiconductor channel material nanosheets; and A back-side source / drain contact structure is provided, wherein the back-side source / drain contact structure electrically contacts the second source / drain region of the nanosheet transistor.

2. The semiconductor structure according to claim 1 further includes a bottom internal spacer structure located laterally adjacent to a first gate thickness of the gate structure, and an upper internal spacer located above the bottom internal spacer structure and laterally adjacent to a second gate thickness of the gate structure.

3. The semiconductor structure according to claim 2, wherein the bottom internal spacer structure includes a first internal spacer and a second internal spacer, wherein the first internal spacer is vertically spaced from the second internal spacer by a semiconductor material liner.

4. The semiconductor structure of claim 3, wherein each of the plurality of spaced and vertically stacked semiconductor channel material nanosheets and the semiconductor material liner are composed of the same semiconductor material.

5. The semiconductor structure according to claim 2, wherein the bottom internal spacer structure has a first vertical height and the upper internal spacer has a second vertical height, wherein the first vertical height is greater than the second vertical height.

6. The semiconductor structure according to claim 1, wherein the first source / drain region is located on the back-side source / drain contact occupancy structure.

7. The semiconductor structure according to claim 6 further includes a semiconductor buffer layer located between the first source / drain region and the back-side source / drain contact occupancy structure.

8. The semiconductor structure of claim 6 further includes a front-side back-end process (BEOL) structure electrically connected to the first source / drain region via a front-side source / drain contact structure.

9. The semiconductor structure according to claim 1, further comprising a semiconductor buffer layer located between the second source / drain region and the back-side source / drain contact structure.

10. The semiconductor structure of claim 1, wherein each of the plurality of spaced and vertically stacked semiconductor channel material nanosheets is dumbbell-shaped, having a middle portion and two end portions, the middle portion having a first thickness and the two end portions having a second thickness greater than the first thickness.

11. The semiconductor structure of claim 1, wherein the back-side source / drain contact structure has a first portion and a second portion, wherein the second portion of the back-side source / drain contact structure is closest to the second source / drain region than the first portion, and wherein the uppermost section of the second portion is limited by a protective liner.

12. The semiconductor structure of claim 11, wherein the first portion has a first critical dimension and the second portion has a second critical dimension, wherein the second critical dimension is smaller than the first critical dimension.

13. The semiconductor structure of claim 11, wherein a first portion of the back-side source / drain contact structure contacts the back-side interconnect structure.

14. The semiconductor structure according to claim 1, comprising: A bottom internal spacer structure, wherein the bottom internal spacer structure is located laterally adjacent to the first gate thickness of the gate structure; An upper internal spacer is located above the bottom internal spacer structure and is laterally adjacent to the second gate thickness of the gate structure; as well as, A back-side source / drain contact occupant structure is provided, wherein the back-side source / drain contact occupant structure is located below the first source / drain region, and a semiconductor buffer layer is located between the first source / drain region and the back-side source / drain contact occupant structure.

15. The semiconductor structure of claim 14, wherein the bottom internal spacer structure includes a first internal spacer and a second internal spacer, wherein the first internal spacer is vertically spaced from the second internal spacer by a semiconductor material liner.

16. The semiconductor structure of claim 15, wherein each of the plurality of spaced and vertically stacked semiconductor channel material nanosheets and the semiconductor material liner are composed of the same semiconductor material.

17. The semiconductor structure of claim 14, wherein the topmost surface of the bottom internal spacer structure is at a first level, the topmost surface of the semiconductor buffer layer is at a second level, the topmost surface of the back-side source / drain contact occupant structure is at a third level, and the bottommost surface of the bottom internal spacer structure is at a fourth level, wherein the first level is greater than the second level, and the third level is greater than the fourth level.

18. The semiconductor structure of claim 14, wherein the bottom internal spacer structure has a first vertical height and the upper internal spacer has a second vertical height, wherein the first vertical height is greater than the second vertical height.

19. The semiconductor structure of claim 14, wherein the back-side source / drain contact structure has a first portion and a second portion, wherein the second portion of the back-side source / drain contact structure is closest to the second source / drain region than the first portion, and wherein the uppermost section of the second portion is limited by a protective liner.

20. The semiconductor structure of claim 19, wherein the first portion has a first critical dimension and the second portion has a second critical dimension, wherein the second critical dimension is smaller than the first critical dimension.

21. The semiconductor structure of claim 19, wherein a first portion of the back-side source / drain contact structure contacts the back-side interconnect structure.

22. The semiconductor structure of claim 14 further includes a front-side back-end process (BEOL) structure electrically connected to the first source / drain region via a front-side source / drain contact structure.

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