Method for generating buried p-n junction in BCD process, BCD substrate and single photon avalanche diode based on BCD substrate

Abstract

The invention relates to a method for generating an embedded p-n junction in a BCD (Bipolar-Coupled Device) manufacturing process, in particular to a BCD substrate with the embedded p-n junction and a single photon avalanche diode (SPAD) based on the BCD substrate. A method of forming a buried p-n junction by introducing or diffusing dopants in a boundary region between a carrier substrate and an epitaxial layer grown on a surface of the carrier substrate. The p-n junction provided by the invention can be advantageously used as a buried p-n junction for an insulated SPAD (Single Pad Amplifier) made by a BCD (Bipolar Compact Disc) technology. The subject matter of the invention is in particular a method for producing buried p-n junctions (50, 52, 54a, 54b, 56a, 56b) in a BCD process, comprising: providing a carrier substrate (10); introducing a first dopant (20) on the surface (S) of the carrier substrate (10) to form a first region (22) of the first conductivity type; introducing a second dopant (30) to the surface (S) of the carrier substrate (10) in order to form a second region (32) of the second conductivity type, the first region (22) and the second region (32) at least partially overlapping; and growing an epitaxial layer (40) on the surface (S) of the carrier substrate (10), the first region (22) and the second region (32) expanding in the epitaxial layer (40) by diffusion of the first dopant (20) and the second dopant (30), the diffusion characteristics of the first and second dopants (20, 30) being selected such that the first and second dopants (20, 30) form a p-n junction (50, 52, 54a, 54b, 56a, 56b) in the epitaxial layer (40) by diffusion.

Description

Technical Field

[0001] This invention relates to a method for generating buried pn junctions in a BCD process, a BCD substrate having buried pn junctions, and a single-photon avalanche diode (SPAD) based thereon, particularly a method for forming buried pn junctions by introducing or diffusing dopants in the boundary region between a carrier substrate and an epitaxial layer grown on the surface of the carrier substrate. The pn junctions provided by this invention can advantageously be used as buried pn junctions in insulating SPADs fabricated using BCD technology. Background Technology

[0002] When constructing integrated circuits using bipolar CMOS-DMOS technology (BCD technology), a buried layer (BL) with a first and / or second conductivity type (NBL, PBL) is typically required on the substrate. Dopant used to create the buried layer is usually introduced into the carrier substrate via implantation. The corresponding surface is then typically covered with an epitaxial layer (EPI layer) for further processing. The buried doped layer provided in the BCD substrate can be directly used as part of the integrated circuit disposed thereon. These layers can also be used to insulate and shield the integrated circuit from the carrier substrate.

[0003] In the prior art, various techniques are known for generating buried n-type and p-type doped layers in BCD processes. Specifically, a first region of a first conductivity type can be generated by photolithography using a first mask, and then a second region of a second conductivity type can be generated using a second mask to selectively introduce corresponding dopants to form NBL and PBL layers. The distance between the NBL and PBL layers is determined by the process. The dopant is introduced planarly onto the surface of the carrier substrate through appropriately structured mask openings and then diffuses outward. During the growth of the EPI layer, the high temperatures during processing cause further dopant redistribution until it occupies a fixed position in the surrounding material, thus forming a roughly defined region. In the prior art, the NBL and PBL layers are typically generated side-by-side, and the thickness of these regions largely depends on the diffusion characteristics of the relevant dopants.

[0004] Integrated single-photon avalanche diodes (SPADs) are an application example of an integrated circuit based on a BCD substrate with buried n-type and p-type doped layers. They are photodetectors similar to photodiodes and avalanche photodiodes, but with much higher sensitivity. When this integrated circuit is photoexcited, photons entering the photosensitive active region (absorption region) of the semiconductor material from the outside generate electron-hole pairs. Under the influence of an electric field, excited electrons are attracted to the cathode, and excited holes are attracted to the anode. In this process, charge carriers also drift through the so-called avalanche region, where charge avalanche occurs due to intensified collisional ionization.

[0005] SPADs typically operate in Geiger mode, detecting individual photons using the resulting charge avalanche and recording them as single events. To minimize dead time during recording, further carrier enhancement can be actively or passively suppressed immediately after avalanche formation. In addition to SPADs, integrated circuits may also include so-called single-photon counting devices or counters, which typically perform a direct statistical evaluation of the temporal distribution of each single-photon detection event rather than outputting a single detector pulse.

[0006] There is a distinction between nSPAD and pSPAD. The terms nSPAD and pSPAD indicate which type of charge carrier is primarily responsible for creating impact ionization, i.e., avalanche formation in a SPAD. Specifically, in nSPAD, it is negatively charged electrons, while in pSPAD, positively charged holes are the primary avalanche generator. The reason for implementing pSPAD is often its ability to achieve low-side readout with simple circuitry. nSPAD is preferred because of its higher avalanche probability, and therefore typically higher photon detection efficiency (PDE). The avalanche region in nSPAD is usually close to the substrate surface, but there are also cases where the avalanche region is located deeper within the substrate. Implementing a SPAD imager (“SPAD array”) typically requires a design change from pSPAD to nSPAD, which also necessitates a shift from low-side to high-side readout. While this can be achieved with circuitry, it is far more complex for SPAD imagers.

[0007] According to existing technology, in BCD technology employing a conventional non-inverted nSPAD structure, the effective detection depth (i.e., absorption depth) of transmitted photons absorbed into the integrated circuit is relatively small. Specifically, electrons generated in the substrate below the nSPAD avalanche region cannot reach the cathode (n-type doped region) on the BCD substrate surface. This results in a smaller absorption depth, which in turn leads to a correspondingly smaller useful current or efficiency in the near-infrared (NIR) spectral range. However, by introducing a highly doped buried layer beneath the conventional nSPAD structure, the useful current can be increased by increasing the effective detection depth of photons. In particular, the region above the buried layer can provide additional separated charge carriers for avalanche generation, thereby increasing the useful current (see, for example, Gramaglia, Francesco et al., "Engineering breakdown probability profile for PDP and DCR optimization in a SPAD fabricated in a standard 55 nm BCD process." IEEE Journal of Selected Topics in Quantum Electronics 28.2: Optical Detectors (2021): 1-10).

[0008] Inverted nSPAD structures have also been implemented using BCD technology. For example, Han, Dong et al.'s "A scalable single-photon avalanche diode with improved photon detection efficiency and dark count noise." Optik 212 (2020): 164692 discloses a scalable single-photon avalanche diode (SPAD) with a virtual epitaxial guard ring based on BCD technology. In this SPAD, the deep junction between the p-well (PW) and the medium-voltage n-well (MVNW) serves as the avalanche region to improve PDE and spectral sensitivity. Furthermore, the use of buried n... +An n-type buried layer (NBL) is used to achieve substrate insulation, reducing electrical crosstalk and simplifying pixel integration. In particular, a low-doped p-type epitaxial layer is used as a virtual guard ring to effectively suppress the dark count rate (DCR) caused by interface falls. Veerappan, Chockalingam, and Edoardo Charbon's "A low dark count pin diode based SPAD in CMOS technology." IEEE Transactions on Electron Devices 63.1 (2015):65-71 and Sanzaro, Mirko, et al.'s "Single-photon avalanche diodes in a 0.16 μm BCD technology with sharp timing response and red-enhanced sensitivity." IEEE Journal of Selected Topics in Quantum Electronics 24.2 (2017):1-9 also reveal inverted nSPADs in BCD technology.

[0009] Existing inverted nSPADs implemented using BCD technology are primarily based on pn structures, employing a deep n-well (DNW) introduced from the surface of the BCD substrate as the n-layer. In this type of SPAD, photon absorption and carrier generation mainly occur in the relatively wide intrinsically conductive region between the first and second p layers. This wide intrinsic layer helps to increase the effective absorption region, thereby improving the absorption probability and PDE. It also reduces the blocking layer capacity, thus shortening the detector's dead time. Despite employing an inverted nSPAD structure, the photon absorption depth remains too low to achieve high photon capture efficiency, especially in the near-infrared (NIR) spectral range.

[0010] To further increase the absorption depth, a pn junction must be provided deeper into the BCD substrate beneath the intrinsic region. This is not straightforward for fully mature integrated circuit manufacturing processes and typically requires additional process steps. In particular, additional masking, photolithography, and epitaxial steps may be necessary. It is important to note that these additional steps must also be compatible with the process steps used to manufacture other components of the integrated circuit, such as integrated amplifiers or interconnected photon counters. High efficiency can be achieved with high penetration depths and electron-based breakdown. In conventional BCD processes using epitaxy, the deepest n-layer is the NBL layer. However, in this case, typical p-wells introduced from the surface are not suitable for providing a suitable breakdown mechanism (suitable for breakdown voltages <40 V). BD (value).

[0011] Therefore, the object of the present invention is to provide a method for generating a buried pn junction in a BCD process, a BCD substrate having a buried pn junction, and a single-photon avalanche diode based thereon. The method for generating the buried pn junction in the BCD process should minimize additional process work and should be compatible with existing BCD processes. The corresponding BCD substrate having a buried pn junction can then serve as a basis for forming a high-efficiency single-photon avalanche diode with a wide absorption region. The SPAD detector should be controllable with a simple circuit solution while exhibiting high efficiency in the NIR spectral range. Summary of the Invention

[0012] The object of this invention is achieved by means of the subject matter of the independent claims. Preferred further designs are the subject matter of the dependent claims.

[0013] The first aspect of this disclosure relates to a method for generating a buried pn junction in a BCD process, comprising: providing a carrier substrate; introducing a first dopant on the surface of the carrier substrate to form a first region of a first conductivity type; growing an epitaxial layer on the surface of the carrier substrate, wherein the first region extends in the epitaxial layer and the carrier substrate by diffusion of the first dopant; introducing a second dopant in a region of the first region to form a second region of a second conductivity type, wherein the first region and the second region at least partially overlap, and the introduction of the second dopant is selected such that the first and second dopant form a pn junction located in the epitaxial layer by introduction.

[0014] Preferably, the second dopant is introduced into a region of the first region by high-energy implantation of the second dopant to form a second region of the second conductivity type.

[0015] In a preferred embodiment of the method, a second dopant is introduced onto the surface of the carrier substrate before the epitaxial layer is grown (i.e., similar to the introduction of the first dopant). Particularly preferably, the first and second regions (after the epitaxial layer is grown) extend in the epitaxial layer and carrier substrate through diffusion of the first and second dopants, wherein the diffusion characteristics of the first and second dopants are selected such that the first and second dopants form pn junctions in the epitaxial layer through diffusion.

[0016] A second aspect of this disclosure relates to a method for generating buried pn junctions in a BCD process, comprising: providing a carrier substrate; introducing a first dopant on the surface of the carrier substrate to form a first region of a first conductivity type; introducing a second dopant on the surface of the carrier substrate to form a second region of a second conductivity type, wherein the first region and the second region at least partially overlap; growing an epitaxial layer on the surface of the carrier substrate, wherein the first region and the second region extend in the epitaxial layer and the carrier substrate by diffusion of the first dopant and the second dopant, wherein the diffusion characteristics of the first dopant and the second dopant are selected such that the first dopant and the second dopant form pn junctions located in the epitaxial layer by diffusion.

[0017] The following explanation also involves the two aspects mentioned above, so it will be addressed together.

[0018] The first and second dopant are preferably formed by introduction (particularly by introducing the second dopant, however, the spatial distribution when introducing the first dopant also has an effect) and / or by diffusion (in which case, in addition to the selected diffusion parameters, the spatial distribution when introducing the first and second dopant also has a significant effect) to form pn junctions in the epitaxial layer and in the carrier substrate, respectively. In the method of the invention according to the first aspect described above, diffusion may also occur after the dopant is introduced to form at least one pn junction.

[0019] Specifically, a pn junction can be understood as a region or area within a substrate where p-type doped semiconductor material is planarly adjacent to n-type doped semiconductor material, and a depletion region, typical for a pn junction, can be formed in the transition region between the two materials. Therefore, a pn junction is locally defined by the specific structure at the corresponding location. In this sense, the corresponding pn junction can also be called a pn junction region (or pn junction area). However, the term "pn junction" should not be understood as a general term for the electronic structure itself formed by such a pn junction region, unless otherwise stated in the description of individual cases. Therefore, two adjacent pn junction regions located in different regions (e.g., the epitaxial layer and the carrier substrate) will form separate pn junctions, although they could very well form a common, coherent structure (i.e., a common pn junction structure comprising two interconnected pn junction regions).

[0020] Therefore, the pn junction located in the epitaxial layer is characterized in that the boundary region between the p-type doped semiconductor material and the n-type doped semiconductor material is located in the epitaxial layer. Correspondingly, the pn junction located in the carrier substrate is characterized in that the boundary region between the p-type doped semiconductor material and the n-type doped semiconductor material is located in the carrier substrate.

[0021] The preferred substrate is a p-type substrate. However, an n-type substrate or an intrinsic substrate can also be used. Silicon is a particularly suitable substrate material. Boron is a typical dopant used to form the p-region. Phosphorus can be used to form the n-region. For example, boron diffuses significantly faster in silicon than phosphorus, and therefore diffuses over a greater distance. It is also determined that, at the dosages typically selected for both dopants, the resulting n-region is substantially dominant; that is, the phosphorus-doped n-region retains its existing conductivity even after further introduction of boron. Therefore, providing a buried pn junction eliminates the need for additional masking, photolithography, and epitaxial steps in conventional BCD processes.

[0022] The first and second dopants preferably have different diffusion characteristics in the carrier substrate and / or epitaxial layer. Compared with the first dopant, the second dopant preferably has a higher diffusivity (also known as diffusion mobility) in the carrier substrate and / or epitaxial layer. In particular, so-called diffusion engineering can be further performed from the surface, i.e., the dopants are introduced from the surface so that the doping profile rises substantially towards the surface. However, in general, a strictly monotonous profile is not formed, but rather a certain degree of gradual or wavy transition is often observed. The diffusion characteristics of various dopants in the epitaxial growth layer and the materials commonly used as carrier substrates are well known to those skilled in the art, or can be calculated, at least approximately, by those skilled in the art in a known manner. Therefore, those skilled in the art can easily determine the first and second dopants and the relevant parameters required to introduce them into the carrier substrate surface in order to form pn junctions in the epitaxial layer and in the carrier substrate respectively by diffusion in accordance with the present invention.

[0023] After introducing the first dopant and / or the second dopant, it is preferable to heat the carrier substrate to enhance diffusion; this can also be done during the epitaxial step, as the epitaxial step typically requires extremely high process temperatures. Similarly, after growing the epitaxial layer(s), the carrier substrate can be heated to enhance dopant diffusion.

[0024] The introduction of the first dopant and / or the second dopant is preferably achieved without a mask or by means of a mask process. For example, maskless introduction can be performed using direct ion beam writing. When using a mask process, introduction is performed using a previously provided mask, such as by chemical or physical deposition or by means of ion beam writing.

[0025] Preferably, viewed from above the surface of the carrier substrate, after the introduction of the second dopant, the first or second region immediately and completely overlaps with the other region, or the first and second regions overlap only at the edge regions. The term "edge region" refers to a main region that does not overlap with the first region but exists next to it. "Overlapping only at the edge regions" may also include a region being surrounded by another region, wherein the surrounded region does not overlap with the other region in the central region.

[0026] Preferably, viewed from above the surface of the carrier substrate, after the introduction of the second dopant, the first region immediately overlaps with the edge regions of the two second regions at the left and right edge regions, or the second region overlaps with the edge regions of the two first regions at the left and right edge regions.

[0027] Preferably, the first region is an n-type embedded layer (NBL layer) and the second region is a p-type embedded layer (PBL layer).

[0028] The method of the present invention can generate buried pn junctions in conventional BCD processes, largely eliminating the need for additional process work. In particular, the method of the present invention is also compatible with other process steps of conventional BCD techniques based on providing n-type and p-type doped buried layers. The present invention provides the possibility of directly generating buried pn junctions without a mask. A particular advantage of the method of the present invention is that, depending on the specific design of the method, multiple independent pn junctions can be implemented in a single process step at substantially the same location on the carrier substrate. In particular, in some embodiments of the method of the present invention, in addition to an upper first pn junction substantially located in the epitaxial layer, a substantially identical lower second pn junction substantially located in the carrier substrate can also be provided. The shape and number of the provided pn junctions can be determined by the dopant profile used and the desired locations of the n-type and p-type doped buried layers.

[0029] A third aspect of this disclosure relates to a BCD substrate having a buried pn junction, comprising: a carrier substrate; and an epitaxial layer grown on the carrier substrate, wherein a pn junction is formed between the carrier substrate and the epitaxial layer by means of the method of the invention according to the first aspect above, or by diffusion of a dopant introduced onto the surface of the carrier substrate below the epitaxial layer. In particular, the BCD substrate of the present invention can be provided by means of a corresponding method according to the invention. The description and explanation of the method of the invention and its preferred embodiments are accordingly applicable to the BCD substrate of the present invention. This particularly refers to the formation and arrangement of different regions.

[0030] Preferably, pn junctions are formed separately in the epitaxial layer and in the carrier substrate. In this case, the BCD substrate of the present invention thus has two jointly formed pn junctions.

[0031] Another aspect of this disclosure relates to a single-photon avalanche diode (SPAD) comprising: a BCD substrate of the present invention, wherein an avalanche region is formed in the region surrounding the pn junction; and an absorption region for converting photons into electron-hole pairs, wherein the absorption region is adjacent to the region forming the pn junction (i.e., the NBL layer and PBL layer overlapped by diffusion drive according to the present invention).

[0032] Preferably, the pn junction is at least partially formed between the n-type buried layer (NBL layer) serving as the cathode and the adjacent p-type buried layer (PBL layer). The absorption region is preferably adjacent to the p-type buried layer and formed as a p-region. More preferably, the anode, designed as a p+ region, is adjacent to the absorption region. The detector region is typically radially symmetrical, or at least obtuse-angled, or more preferably rounded, to avoid generating excessive electric fields at the corners.

[0033] The absorption region preferably includes a high-voltage p-well immediately adjacent to the p-type buried layer, and optionally includes a p-well immediately adjacent to the high-voltage p-well. The absorption region here effectively serves as the intrinsic region of the corresponding pin photodiode.

[0034] The absorption region between the p-type buried layer and the anode is preferably formed as an n-type lightly doped epitaxial region, which has a high-voltage p-well formed as a channel to serve as a nonlinear quenching resistor.

[0035] Preferably, multiple independent p-type buried layers are formed along the n-type buried layer and arranged directly above it. This configuration allows multiple identical or at least structurally similar diodes to be arranged in parallel. Thus, the single-photon avalanche diode of the present invention can form multiple active regions arranged side-by-side and largely independent of each other, which is essentially equivalent to connecting multiple substantially identical single-photon avalanche diodes in parallel. Depending on the number of integrated diodes, this overall configuration is essentially dead-time-free because one or more other photon events can be detected immediately on the other diodes that remain active after the first detection.

[0036] The typical thickness of the grown epitaxial layer (and the depth of the pn junction in the BCD substrate) is approximately 5–10 µm. This allows for particularly high breakdown voltages. In this case, the NBL layer deposited at a greater depth and the p-wells that can be introduced from the surface provide a larger intrinsic region, which also generates higher breakdown voltages and can be used as a wide absorption region for the corresponding SPAD.

[0037] Thus, a novel structure is created largely using traditional BCD technology, which is systematically different from other known SPAD structures in the prior art. The single-photon avalanche diode of this invention can be particularly an inverted nSPAD, enabling higher PDE, especially in the infrared spectral range. The detector of this invention possesses all the advantages of nSPADs and improves its characteristics with the help of a wider absorption layer, but in principle, this single-photon detector can be used like a conventional surface-correlated pSPAD. The terms nSPAD and pSPAD are used to indicate which type of charge carrier is primarily responsible for forming collisional ionization, i.e., avalanche formation in the SPAD. Specifically, in nSPADs, it is negatively charged electrons, while in pSPADs, positively charged holes are the main cause of avalanche formation.

[0038] Because the BCD technology platform can optimally integrate various applications from different fields, devices embedded in the BCD substrate, particularly the single-photon avalanche diode of this invention, can also be combined with other devices and components directly above or laterally adjacent to the embedded element. For example, in addition to analog and digital amplifier elements, digital storage elements and signal processors for statistical evaluation and for constructing single-photon counting devices or single-photon counters can also be implemented.

[0039] The method of this invention allows the pn junction associated with the function of a single-photon avalanche diode to be moved deeper, thereby enabling deliberate structuring of the surface of the BCD substrate to improve optical properties (e.g., altering the active region / STI (shallow trench isolation) and / or poly) without significantly changing or affecting the characteristics of the embedded device. Most importantly, this provides high flexibility in the design and surface structuring of the corresponding integrated circuits. Since the associated pn structure is surface-independent, known BEOL interference conditions need not be strictly considered, allowing for the reduction of spectral response fringes through simple ACTI / STI structuring or modification.

[0040] The single-photon detector of the present invention, especially when equipped with a fully integrated nonlinear quenching resistor, can be used for various purposes, such as as a single pixel in an array, or as a so-called silicon photomultiplier (SiPM). The design of the present invention allows for almost arbitrary increases in detector area (from several µm² to several mm²), with no visible pixel boundaries, while simultaneously achieving almost 100% utilization of the effective area (i.e., a high fill factor).

[0041] Another advantage of the BCD structure provided by this invention for single-photon avalanche diodes is that the breakdown voltage of the diode can be variably adjusted simply by modifying the basic structural design. For example, the breakdown voltage can be significantly influenced and adjusted by changing the size of the region through the p-type buried layer. The selected breakdown voltage can be uniform or intentionally different depending on the application requirements.

[0042] The pn junction provided by this invention is located at a lower position, which in turn allows for a lower position of the individually addressable insulated single-photon avalanche diode, making it possible to address or read out the structure in a so-called low-side configuration. This low-side readout provides greater flexibility in circuit design and the corresponding integrated circuit construction.

[0043] Using the method of this invention, two nearly identical pn junctions can be generated in a BCD substrate. This provides an ideal platform for future development of SPADs with appropriate scaling. For example, the upper pn junction formed in the epitaxial layer can provide a first SPAD, while the second pn junction in the carrier substrate, for example, helps to form a substantially identical second SPAD.

[0044] On the one hand, this allows for highly compact 3D integration of multiple detector elements; on the other hand, it significantly improves detection performance and opens up entirely new application areas. In principle, both pn junctions are suitable for both front and back illumination. In principle, the second SPAD is a standalone device, largely independent of the first SPAD, and can therefore be read out independently using corresponding contacts. In principle, this also allows for the provision of a so-called back-side imager (BSI) at the lower pn junction, or its combination with a so-called front-side imager (FSI) at the upper pn junction.

[0045] Another advantage of the buried pn junction of the present invention is its simple scaling. Adjacent diode structures can be separated simply by structuring the corresponding isolation regions on the surface of the BCD substrate.

[0046] Another aspect of this disclosure relates to an integrated circuit that includes at least one single-photon avalanche diode of the present invention.

[0047] Other aspects of the invention are disclosed in the dependent claims or in the following description of the drawings. Attached Figure Description

[0048] The present invention will now be explained with reference to relevant figures and embodiments. Wherein: Figure 1 This is a schematic diagram of a first embodiment of a method for generating buried n-type and p-type doped layers in a BCD process according to the prior art. Figure 2A schematic diagram of a second embodiment of a method for providing buried n-type and p-type doped layers in a BCD process according to the prior art; Figure 3 A schematic diagram of a first embodiment (“Saturn”) of a method for providing a buried pn junction in a BCD process according to the present invention, and a TCAD diagram of the resulting dopant distribution; Figure 4 A schematic diagram of a second embodiment (“donut”) of the method for providing a buried pn junction in a BCD process according to the present invention, and a TCAD diagram of the resulting dopant distribution; Figure 5 A schematic diagram of a third embodiment (“Pacman”) of the method for providing a buried pn junction in a BCD process according to the present invention, and a TCAD diagram of the resulting dopant distribution. Figure 6 For the cutoff direction U rev The current-voltage characteristic curve of the embedded PN junction during operation is obtained by referring to the corresponding Figure 3 The invention is made by the method of the first embodiment of the present invention, including a passive quenching resistor and without illumination; Figure 7 A schematic diagram of a single-photon avalanche diode fabricated using BCD technology according to existing techniques; Figure 8 This is a schematic diagram of the first embodiment of the single-photon avalanche diode of the present invention; Figure 9 This is a schematic diagram of a second embodiment of the single-photon avalanche diode of the present invention; and Figure 10 This is a schematic diagram of a third embodiment of the single-photon avalanche diode of the present invention. Detailed Implementation

[0049] Detailed embodiments will now be described, examples of which are shown in the accompanying drawings. The effects and features of these embodiments will be explained with reference to the accompanying drawings. In the drawings, the same symbols denote the same elements, and redundant descriptions are omitted. This disclosure may be implemented in various forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are examples provided to make this disclosure comprehensive and to fully convey to those skilled in the art aspects and features of this disclosure.

[0050] Therefore, those skilled in the art will fully understand that methods, elements, and techniques not required for the aspects and features of this disclosure will not be described at their discretion. For clarity, the relative dimensions of elements, layers, and regions may be exaggerated in the figures.

[0051] The term "and / or" as used herein includes any combination of one or more of the listed elements. Furthermore, in describing embodiments of this disclosure, the term "may" means "one or more embodiments of this disclosure." In the following description of embodiments, singular terms may also include plural terms unless the context clearly indicates otherwise.

[0052] Although the terms "first" and "second" are used to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. When a phrase such as "at least one of" is added before a list of elements, it modifies the entire list, not just individual elements in the list.

[0053] Terms such as “substantially” and “approximately” are used to indicate approximation rather than degree, and are intended to take into account the inherent biases of measured or calculated values ​​that are recognized by those skilled in the art. When the term “substantially” is used in conjunction with a feature that can be expressed numerically, the term “substantially” means a range of at least + / - 5% centered on that value.

[0054] Figure 1 A schematic diagram of a first embodiment of a method for generating buried n-type and p-type doped layers in a BCD process according to the prior art is shown. The method is generally based on the three steps illustrated in the figure, where the bar graph in the upper region of the figure is intended to illustrate the regions to be structured by a possible first mask layer ML1 and a possible second mask layer ML2 in the first and second steps. These regions correspond to the buried layers shown in the figure, where NBL represents an n-type buried layer and PBL represents a p-type buried layer.

[0055] The diagram shows a basic layout commonly used in BCD technology, consisting of a wide n-type embedded layer horizontally sandwiched between two p-type embedded layers. However, this is merely an example. The size and arrangement of each embedded layer are not specifically determined by the method used and can therefore be changed arbitrarily. The order of the first and second steps shown in the diagram can also be changed. Figure 1 In the example shown, an NBL layer is provided first, followed by two PBL layers. Therefore, the specific descriptions within parentheses following the symbols are only relevant to the case shown as an example in the figures and are not intended to limit the method in any way. Furthermore, the view of the method shows only the doping profile and the resulting diffusion profile in a highly simplified form. In particular, at the sharp edges of the doping profile, deviations in layer shape may occur due to various factors in actual implementation.

[0056] As shown in the figure, a method for generating buried n-type and p-type doped layers NBL and PBL in a BCD process includes: providing a carrier substrate 10 (this step is not explicitly shown); introducing a first dopant 20 on the surface S of the carrier substrate 10 to form a first region 22 of a first conductivity type (negative) (in the illustrated example, an NBL layer); introducing a second dopant 30 on the surface S of the carrier substrate 10 to form at least one second region 32 (PBL) of a second conductivity type (positive), wherein the first region 22 (NBL) and the second region 32 (PBL) are formed at a distance d from each other; and growing an epitaxial layer 40 on the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) are extended (diffused outward) in the epitaxial layer 40 and the carrier substrate 10 by diffusion of the first dopant 20 and the second dopant 30.

[0057] Dopant diffusion is known to those skilled in the art and can be taken into account when forming the desired layer thickness. To enhance diffusion, the carrier substrate 10 can be heated after the introduction of the first dopant 20 and / or the second dopant 30 (so-called "push-in"). Furthermore, the carrier substrate 10 can be heated after the growth of the epitaxial layer 40 to enhance dopant diffusion. The introduction of the first dopant 20 and / or the second dopant 30 can be achieved using a masking process. In particular, the corresponding structures can be defined using first and second mask layers ML1 and ML2. Alternatively, dopant can be introduced using a structuring method without using masks (e.g., direct ion beam writing). In this case, the two mask layers ML1 and ML2 in the figure will respectively represent the implantation regions. The carrier substrate 10 is preferably a p-type substrate, but an intrinsic substrate or an n-type substrate can also be used depending on specific requirements.

[0058] Figure 2 This diagram illustrates a second embodiment of a method for providing buried n-type and p-type doped layers (NBLs and PBLs) in a BCD process according to existing technology. For simplicity, this diagram and the following views will be simplified by referring to the resulting structure and its corresponding mask sequence, but... Figure 1 Steps 1 and 2 are not shown; please refer to the relevant sections for further information. Figure 2 The embodiments shown are the same as Figure 1The only difference in the illustrated embodiment is that the first and second dopants 20 and 30 have different diffusion characteristics in the carrier substrate 10 and the epitaxial layer 40. Specifically, the diffusion rate (and diffusion length) of the second dopant 30 in the second region 32 (PBL) in the carrier substrate 10 and the epitaxial layer 40 is higher than that of the first dopant 10 in the first region 22 (NBL). Therefore, in the provided BCD substrate 100, the resulting PBL layer, after complete dopant diffusion (i.e., outward diffusion), has a greater thickness than the resulting NBL layer. The diffusion characteristics in the carrier substrate 10 and the epitaxial layer 40 depend directly on the selection of the dopants 20 and 30 used, and on the specific parameters selected during application (e.g., density, energy, area, geometry). Therefore, when designing integrated circuits (e.g., SPADs), the difference in thickness between the resulting n-type buried layers and p-type buried layers NBL and PBL must be taken into account.

[0059] Figure 3 A schematic diagram of a first embodiment (“Saturn”) of the method for providing buried pn junctions 50 and 52 in a BCD process according to the present invention is shown, along with a TCAD diagram of the resulting dopant distribution. The method for generating buried pn junctions 50 and 52 in a BCD process according to the present invention includes: providing a carrier substrate 10; introducing a first dopant 20 on the surface S of the carrier substrate 10 to form a first region 22 (NBL) of a first conductivity type (donor); introducing a second dopant 30 on the surface S of the carrier substrate 10 to form a second region 32 (PBL) of a second conductivity type (acceptor), wherein the first region 22 (NBL) and the second region 32 (PBL) at least partially overlap; growing an epitaxial layer 40 on the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) are extended in the epitaxial layer 40 and the carrier substrate 10 by diffusion of the first dopant 20 and the second dopant 30, wherein the diffusion characteristics of the first and second dopant 20 and 30 are selected such that the first and second dopant 20 and 30 respectively form pn junctions 50 and 52 located in the epitaxial layer 40 and in the carrier substrate by diffusion. In the figure, the first region 22 is a buried NBL layer, and the second region 32 is a buried PBL layer. However, the order can be reversed, so the first region 22 can also be a buried PBL layer, and the second region 32 can correspondingly be a buried NBL layer. By adjusting the diffusion length of each dopant, the layer sequence at the resulting pn junctions 50 and 52 can also be reversed, for example in... Figure 3 In addition, the NBL layer and PBL layer at pn junctions 50 and 52 can be interchanged.

[0060] Therefore, the difference between this method and the aforementioned method for generating buried n-type and p-type doped layers NBL and PBL in a BCD process according to existing technology is specifically that the first region 22 (NBL) and the second region 32 (PBL) at least partially overlap. Preferably, at least two pn junctions 50 and 52 (i.e., different pn junction regions) located in different material regions (carrier substrate 10, epitaxial layer 40) can be formed. In particular, viewed from the top view of the surface S of the carrier substrate 10, after the introduction of the second dopant 30, the first region 22 or the second region 32 can immediately and completely overlap with another region 32, 22. Therefore, in the illustrated embodiment, viewed from the top view of the surface S of the carrier substrate 10, after the introduction of the second dopant 30 to form the second region 32 (PBL), the second region is immediately and completely located within the first region 22 (NBL). To enable the formation of pn junctions 50 and 52 in the epitaxial layer 40 and in the carrier substrate 10, respectively, the first and second dopants 20 and 30 preferably have different diffusion characteristics in the carrier substrate 10 and / or the epitaxial layer 40. In particular, as shown in the figure, the diffusion rate (and diffusion length) of the second dopant 30 in the second region 32 (PBL) in the carrier substrate 10 and the epitaxial layer 40 may be higher than that of the first dopant 20 in the first region 22 (NBL).

[0061] To enhance diffusion, the carrier substrate 10 may be heated after the introduction of the first dopant 20 and / or the second dopant 30. Furthermore, after the epitaxial layer 40 is grown, the carrier substrate 10 may be further heated to enhance dopant diffusion. In the method of the present invention, the first dopant 20 and / or the second dopant 30 may also be introduced without using a mask or with a mask process. This corresponds to methods in the prior art such as... Figure 2 The embodiment shown, the method of the present invention as illustrated in the first embodiment, can be understood as a complete superposition of a first region 22 (NBL) and a single second region 32 (PBL). However, in the prior art, the first and second regions 22 and 32 are typically formed spatially separate from each other. In particular, the distance d is usually chosen to be at least so large that no overlapping region is generated even after the dopants diffuse outward. Therefore, the above-described method according to the prior art cannot create buried pn junctions 50 and 52 between the NBL layer and the PBL layer.

[0062] The TCAD diagram below the schematic shows the dopant distribution inside the contact BCD substrate 100 used by the present invention to simulate the corresponding integrated diode structure. Because this embodiment has a dual structure including an upper pn junction 50 and a lower pn junction 52, in the shown side view, the n-region NBL sandwiched within the regions of pn junctions 50 and 52 is effectively contracted by the two p-regions PBL surrounding this n-region NBL. The two pn junctions 50 and 52 can be formed using doping densities and field strength distributions suitable for generating an avalanche effect, thereby enabling two independently buried SPADs to be realized particularly densely within the regions of pn junctions 50 and 52.

[0063] Figure 4 A schematic diagram (“donut”) illustrating a second embodiment of the method for providing buried pn junctions 54a, 54b, 56a, and 56b in a BCD process according to the present invention, and a TCAD diagram of the resulting dopant distribution, is shown. Basic method and Figure 3 The method described in [the original text] is consistent with this. Therefore, the symbols and their correspondence with the various features also apply here. Unlike [the original text], Figure 3 Viewed from the top of the surface S of the carrier substrate 10, after the introduction of the second dopant 30, the left and right edge regions of the second region 32 (PBL) immediately overlap or contact the edge regions of the two first regions 22 (NBL). Alternatively, the left and right edge regions of the first region 22 (NBL) may overlap or contact the edge regions of the two second regions 32 (PBL). In particular, viewed from the top of the surface S of the carrier substrate 10, after the introduction of the second dopant 30, the first region 22 or the second region 32 may immediately be completely located within another region 32 and 22, but these regions 22 and 32 do not completely overlap. For example, the first region 22 may overlap or contact the second region 32 only in a ring or box shape at its edge regions (or vice versa). The term "edge region" here refers to a "main region" that, in addition to the edge region, at least does not overlap.

[0064] Therefore, in the view shown, two first regions 22 (NBL) and a second region 32 (PBL) overlapping the two first regions 22 (NBL) in the edge region are introduced into the surface S of the carrier substrate 10 in such a way that a first right-side pn junction structure (always including two pn junctions 54a and 56a located in the epitaxial layer 40) and a second left-side pn junction structure (always including two pn junctions 54b and 56b located in the carrier substrate 10) are formed in the horizontal direction. In this respect, this embodiment is essentially equivalent to Figure 3 In the embodiment described above, the rotation is 90°. Figure 3The two pn junctions 50 and 52 generated are distributed vertically (i.e., extending along the depth of the carrier substrate 10 relative to surface S). This can also be seen from the relevant TCAD diagram, which also shows the dopant distribution after the corresponding rotation. In the side view, pn junctions 54a and 54b, and 56a and 56b, can be identified by the contraction of the two edge NBL layers over the central PBL layer.

[0065] Figure 5 A schematic diagram (“Pacman”) illustrating a third embodiment of the method for providing buried pn junctions 50, 52, 54a, and 54b in a BCD process according to the present invention, and a TCAD diagram of the resulting dopant distribution. Basic method and Figure 4 The method described in [the original text] is consistent with this. Therefore, the symbols and their correspondence with the various features also apply here. Unlike [the original text], Figure 4 However, viewed from the top of the surface S of the carrier substrate 10, after the introduction of the second dopant 30, the first region 22 (NBL) and the second region 32 (PBL) immediately overlap only at their edge regions. Therefore, the way the first region 22 (NBL) and the second region 32 (PBL) are introduced into the surface S of the carrier substrate 10 causes their distance d to become negative after the dopant diffuses outward, that is, a part of one region overlaps with a part of another region.

[0066] As shown in the schematic diagram, this embodiment forms four interconnected pn junction regions 50, 52, 54a, and 54b. These are, respectively, an upper pn junction 50 in the epitaxial layer, a lower pn junction 52 in the carrier substrate 10, and a right-side pn junction structure connecting these two pn junctions 50 and 52, which includes an upper pn junction 54a located in the epitaxial layer 40 and a lower pn junction 54b located in the carrier substrate. In the corresponding TCAD drawing, these regions can be identified by the PBL layer in the right-side shrinkage center NBL layer. Each pn junction region 50, 52, 54a, and 54b forms a single, continuous pn junction structure.

[0067] Figure 6 This invention is shown with the cutoff direction U rev Multiple current-voltage characteristic curves of the embedded PN junction during operation, which are obtained by means of corresponding Figure 3 The invention is manufactured according to the method of the first embodiment, including a passive quenching resistor and without illumination. When the breakdown voltage U BV At a breakdown voltage (BV) of approximately 18 V, the breakdown current at the pn junction increases sharply by several orders of magnitude. The curve shape is typical for the passive quenching of a SPAD pn junction, at a breakdown voltage U... BVThe so-called Geiger plateau characteristic exists in the range of approximately 25 V. The breakdown voltage itself can be changed by appropriate design adjustments without adjusting the manufacturing process! For example, values ​​from 10 V to 70 V can be used.

[0068] Figure 7 A schematic diagram of a single-photon avalanche diode 200 fabricated using BCD technology according to existing techniques is shown (see Veerappan, Chockalingam, and Edoardo Charbon, "A low dark count pin diode based SPAD in CMOS technology." IEEE Transactions on Electron Devices 63.1 (2015):65-71 and Sanzaro, Mirko, et al., "Single-photon avalanche diodes in a 0.16 μm BCD technology with sharp timing response and red-enhanced sensitivity." IEEE Journal of Selected Topics in Quantum Electronics 24.2 (2017):1-9). The detector employs a vertical structure (i.e., extending relative to the surface into the BCD substrate 100), wherein the anode A is formed by a p-type avalanche diode on the surface of the BCD substrate 100. + The region is formed, and the cathode C is formed by an n-type buried layer (NBL) or a deep n-type well (DNW). Between these two, located in p... +A pn junction 58 is formed at the boundary between the p-well (PW) acting as the absorption region directly below the n-type buried layer NBL and the lightly doped n- or p-type epitaxy (NEPI) or PEPI acting as the conductive region. The p-well PW is introduced from above by the lightly doped n- or p-type epitaxy (NEPI) or PEPI, thus the p-well PW is also laterally surrounded by the lightly doped n- or p-type epitaxy (NEPI) or PEPI, thereby separating it from other surrounding structures. Functionally, the lightly doped n- or p-type epitaxy (NEPI) or PEPI represents a wide intrinsic region, used to form a pin structure between the p-well PW and the n-type buried layer NBL or deep n-well DNW. Therefore, the pin structure associated with the illustrated single-photon avalanche diode 200 is formed in the transition region between the p-well PW, the lightly doped n- or p-type epitaxy (NEPI) or PEPI, and the n-type buried layer NBL or deep n-well DNW. In particular, lightly doped n-type or p-type epitaxial regions NEPI or PEPI help increase the distance between the p-well PW and other surrounding structures, thereby significantly weakening the parasitic pn junctions formed between these structures.

[0069] The BCD substrate 100 used can be particularly benefited from conforming to Figure 2 The embodiment shown is manufactured using a conventional method, wherein after forming spatially separated n-type and p-type buried layers NBL and PBL, an epitaxial layer 40 is grown on a carrier substrate 10. For further details regarding the method according to the prior art, please refer to [reference needed]. Figure 1 and Figure 2 The detector region is typically radially symmetrical to even out the propagation time of different avalanche propagation directions and avoid hotspots.

[0070] Contact between the detector's buried cathode C and the high-voltage n-type well (HVNW) adjacent to the absorption region and the n+ region disposed thereon on the surface of the BCD substrate 100 can be achieved. Specifically, the corresponding contact CONT can be achieved using the metallized portion MET1. The areas on the surface can be separated from each other by the isolation region STI. The incident window for the radiation to be detected is also located on the surface of the BCD substrate 100. A silicide blocking layer (SBL) can be applied to protect it. To prevent the detector from being affected by the substrate, a p-type isolation region extending from the surface to the p-type buried layer PBL can be arranged around the detector. However, this isolation region is irrelevant to the actual function of the detector and will not be described in detail below. The equivalent circuit diagram next to the view, due to its position, again illustrates the exact location of the pn junction 58 (pin structure) in the BCD substrate 100 and indicates the corresponding terminals (anode A, cathode / common n-well C / TW) on the provided diode.

[0071] The proposed single-photon avalanche diode 200 is a so-called nSPAD, with its pn junction 58 located on the n-side of the BCD substrate 100, where photon incidentness and contact with the detector both begin from the surface of the BCD substrate 100. This design is technically quite easy to implement and is favored over other SPAD designs due to its potential detection performance. However, in the prior art, n-type buried layers (NBLs) or deep n-wells (DNWs) are introduced via a surface without an epitaxial layer, and their depth is relatively shallow (approximately 2-3 µm, compared to approximately 5-10 µm in BCD technology using epitaxial layers). A drawback is the relatively shallow absorption depth of incident photons, which significantly increases the detection difficulty in the infrared spectral range and limits the PDE. If the known structures in the prior art are directly applied to BCD technology with an epitaxial step, the large drift distance leads to extremely high breakdown voltages (V0). BD (>30-40V), which is often more difficult to handle in applications.

[0072] Figure 8 A schematic diagram of a first embodiment of the single-photon avalanche diode 200 of the present invention is shown. By means of the method of the present invention for generating buried pn junctions 50, 52, 54a, 54b and 56a, 56b in a BCD process, pn junctions 50 and 52 for detection can be provided in a simple manner, and their depth is significantly greater than that of the prior art. Therefore, compared with conventional SPADs made using BCD technology, the absorption region and absorption depth can be significantly increased.

[0073] All embodiments of the single-photon avalanche diode 200 proposed within the scope of this application are constructed on a BCD substrate 100 having buried pn junctions 50, 52, 54a, 54b, 56a, and 56b. It includes a carrier substrate 10 and an epitaxial layer 40 grown on the carrier substrate 10, wherein the pn junctions 50, 52, 54a, 54b, 56a, and 56b in the epitaxial layer 40 are generated between the carrier substrate 10 and the epitaxial layer 40 by means of the method of the invention according to the first aspect described in the "Summary of the Invention" section or by diffusion of a dopant introduced onto the surface S of the carrier substrate 10 below the epitaxial layer 40, for example by means of the method of the invention. Therefore, the single-photon avalanche diode 200 of the present invention includes the BCD substrate 100 of the present invention, wherein an avalanche region is formed around the pn junctions 50, 52 (which may be formed individually or together with 54a, 54b and / or 56a and 56b), and an absorption region (PW, HPW) for converting photons into electron-hole pairs, wherein the absorption region (PW, HPW) is adjacent to the region (NBL, PBL) forming the pn junctions 50, 52 (54a, 54b and / or 56a, 56b).

[0074] In particular, in the single-photon avalanche diode 200 shown in the figure of the present invention, the upper pn junction 50 is at least partially formed between the n-type buried layer NBL, which serves as the cathode C, and the p-type buried layer PBL adjacent to the n-type buried layer NBL. The absorption region (PW, HPW) is adjacent to the p-type buried layer PBL and is formed as a p-region, and the anode A, which is designed as a p+ region, is formed adjacent to the absorption region (PW, HPW). Preferably, the absorption region (PW, HPW) includes a high-voltage p-well HPW adjacent to the p-type buried layer PBL, and optionally includes a p-well PW adjacent to the high-voltage p-well.

[0075] Therefore, the detector structure shown in the figure is similar to... Figure 7 The structures shown are basically the same. Therefore, the symbols and their correspondence with each feature also apply here. However, unlike... Figure 7 In this embodiment, the pn junction 50 on the detector is formed directly by overlapping an n-type buried layer NBL and a p-type buried layer PBL in the manner of the present invention, thus being formed significantly deeper in the BCD substrate 100. A high-voltage n-well, serving as an extended absorption region, is formed below the p-well PW, which serves as the absorption region, instead of forming an n-type lightly doped epitaxial region NEPI. The n-type lightly doped epitaxial region NEPI can be arranged around the PBL layer above the pn junction 50. Therefore, the fabrication process for manufacturing the corresponding single-photon avalanche diode 200 of the present invention is significantly improved. Figure 7The fabrication process of the single-photon avalanche diode 200 described herein differs only slightly from that of the prior art. Therefore, the advantageous nSPAD design can be maximized without altering the basic detector structure. Thus, by using the BCD substrate 100 of the present invention, which has one buried pn junction 50 (or two buried pn junctions 50, 52 parallel to the surface of the carrier substrate 10), the absorption depth can be increased in a simple manner, thereby improving the sensitivity of the provided detector.

[0076] Another advantage of using the BCD substrate 100 shown in the figure is that a separate second pn junction 52 can be provided and used on the bottom surface of the n-type buried layer NBL. This allows a second nSPAD to be used on the bottom surface of the carrier substrate 10. For example, the second nSPAD can be addressed and read out by making the PBL region and the p-type substrate laterally contacted with the anode on the top surface of the BCD substrate. On the one hand, this enables compact 3D integration of multiple detector elements; on the other hand, it significantly improves detection performance and opens up new application areas. For example, a double-sided sensitive integrated single-photon detector can detect photon flows from opposite directions, thereby determining the deviation between photon fluxes. Furthermore, the second SPAD can also be used as a reference detector to reduce detector noise from the first SPAD caused by environmental influences (e.g., cosmic radiation). Therefore, the corresponding equivalent circuit diagram also shows two diodes connected along the cutoff direction between the anode A and the cathode / common n-well C / TX. The anode terminal of the lower diode is also referred to as the common substrate SX.

[0077] Figure 9 A schematic diagram of a second embodiment of the single-photon avalanche diode 200 of the present invention is shown. The detector structure shown in the figure is similar to... Figure 8 The structures shown are basically the same. Therefore, the symbols and their correspondence with each feature also apply here. Unlike Figure 8 The corresponding absorption region (NEPI) between the p-type buried layer PBL and the anode A is completely formed as an n-type lightly doped epitaxial region NEPI, which has a high-voltage p-well HPW formed as a channel to serve as a fully integrated quenching resistor QR. The quenching resistor QR preferably has a nonlinear resistive function. After charge avalanche is triggered by photon-induced carrier generation within the absorption region (NEPI), a voltage drop appears across the quenching resistor QR. This voltage drop prevents further carrier generation by impact ionization, thereby quenching carrier avalanche. Then, a reverse voltage is formed again in the detector, but with a delay, before triggering a new charge avalanche.

[0078] In terms of process technology, integrating the quench resistor QR as a channel into the n-type lightly doped epitaxial region NEPI is relatively easy, and the required resistance characteristics can be flexibly adjusted by forming it as a high-voltage p-well HPW. Direct integration helps improve the fill factor on the BCD substrate 100. In the equivalent circuit diagram, the quench resistor QR is drawn above the internal anode of the diode. The upper terminal AQR can be further connected to another active or passive quench resistor.

[0079] Figure 10 A schematic diagram of a third embodiment of the single-photon avalanche diode 200 of the present invention is shown. The detector structure shown in the figure is similar to... Figure 9 The structures shown are basically the same. Therefore, the symbols and their correspondence with each feature also apply here. Unlike Figure 9 The key difference is that multiple p-type buried layers PBL are formed along the n-type buried layer NBL, each individually arranged directly above the n-type buried layer NBL. This allows multiple independent single-photon avalanche diodes 200 to be arranged side-by-side, thereby circumventing the effective detector dead time as much as possible during parallel operation. For example, using existing BCD technology, up to seven single-photon avalanche diodes 200 can be arranged in a pixel of a conventional SPAD array, typically about 20 µm wide. In the corresponding equivalent circuit diagram, this circuit is shown as multiple... Figure 9 Parallel connection of the single-photon avalanche diode 200 in the embodiment shown.

[0080] exist Figure 9 and Figure 10 In the embodiment shown, the corresponding lower pn junction provided in the BCD substrate 100 can also be referred to the preceding text. Figure 8 The described method is used to form more single-photon avalanche diodes 200. In this case, using existing BCD technology, up to fourteen single-photon avalanche diodes 200 can be arranged in this double-overlapping manner in a single 20 µm wide pixel of a conventional SPAD array. Due to the improvements in the BCD technology used, it is assumed that the number of single-photon avalanche diodes 200 that can be arranged in such a pixel will increase significantly in the future. The significantly increased integration density can, for example, be used to further improve the PDE or reduce the error rate during the detection process.

[0081] Appendix Label Table 10 carrier substrates 20 First Dopant 22 First District 30 Second Dopant 32 Second Region 40 epitaxial layers 50,52p-n junction ("top", "bottom") 54a, 54bp-n junctions ("top right", "bottom right") 56a, 56bp-n junction ("top left", "bottom left") 58p-n junction (existing technology) 100BCD substrate 200 Single-Photon Avalanche Diode (SPAD) NBLn type buried layer (English: "n-type buried layer") PBLp type buried layer (English: "p-type buried layer") ML1, ML2 first and second mask layers H(V)PW high-voltage p-type well H(V)NW high-voltage n-type well (English translation: "high-voltage n-type well") PWp well (also known as "p-type well") NWn well (English: "n-type well") DPW (Deep p-type well) DNW (deep n-type well) NEPIn type lightly doped epitaxy PEPIp type lightly doped epitaxy MET1 metallization part CONT contact SBL silicon blocking layer (English: "silicide blocking layer") STI (shallow trench isolation) P + p + district N + n + district Anode C cathode TW common n-well (English: "twin-well") SX bulk area or common substrate QR quenching resistor (English: "quenching resistor") Anode side terminals after the AQR quenching resistor S surface d distance

Claims

1. A method for generating embedded PN junctions (50, 52, 54a, 54b, 56a, 56b) in a BCD process, comprising: - Provide a carrier substrate (10); - A first dopant (20) is introduced on the surface (S) of the carrier substrate (10) to form a first region (22) of a first conductivity type; - An epitaxial layer (40) is grown on the surface (S) of the carrier substrate (10), wherein the first region (22) extends in the epitaxial layer (40) and the carrier substrate (10) by diffusion of the first dopant (20); - A second dopant (30) is introduced into a region of the first region (22) to form a second region (32) of a second conductivity type, wherein the first region (22) and the second region (32) at least partially overlap, and the introduction of the second dopant (20, 30) is selected such that the first and second dopant (20, 30) form pn junctions (50, 52, 54a, 54b, 56a, 56b) in the epitaxial layer (40) by means of the introduction.

2. A method for generating embedded PN junctions (50, 52, 54a, 54b, 56a, 56b) in a BCD process, comprising: - Provide a carrier substrate (10); - A first dopant (20) is introduced on the surface (S) of the carrier substrate (10) to form a first region (22) of a first conductivity type; - A second dopant (30) is introduced on the surface (S) of the carrier substrate (10) to form a second region (32) of a second conductivity type, wherein the first region (22) at least partially overlaps with the second region (32); - An epitaxial layer (40) is grown on the surface (S) of the carrier substrate (10), wherein the first region (22) and the second region (32) are extended in the epitaxial layer (40) and the carrier substrate (10) by diffusion of the first dopant (20) and the second dopant (30), wherein the diffusion characteristics of the first and second dopant (20, 30) are selected such that the first and second dopant (20, 30) form pn junctions (50, 52, 54a, 54b, 56a, 56b) in the epitaxial layer (40) by diffusion.

3. The method according to claim 1 or 2, wherein the first and second dopants (20, 30) form pn junctions (50, 52, 54a, 54b, 56a, 56b) in the epitaxial layer (40) and in the carrier substrate (10) respectively by introduction and / or diffusion.

4. The method according to any one of claims 1 to 3, wherein the first and second dopants (20, 30) have different diffusion characteristics in the carrier substrate (10) and / or the epitaxial layer (40).

5. The method according to any one of claims 1 to 4, wherein the second dopant (30) has a higher diffusion rate in the carrier substrate (10) and / or the epitaxial layer (40) compared with the first dopant (20).

6. The method according to any one of the preceding claims, wherein after the introduction of the first dopant (20) and / or the second dopant (30), the carrier substrate (10) is heated to enhance the diffusion, and / or, after the growth of the epitaxial layer (40), the carrier substrate (10) is heated to enhance the diffusion of the dopant.

7. The method according to any one of the preceding claims, wherein the first dopant (20) and / or the second dopant (30) are introduced without using a mask or by means of a mask process.

8. The method according to any one of claims 1 to 7, wherein, viewed from a top view of the surface (S) of the carrier substrate (10), after the introduction of the second dopant (30), the first region (22) or the second region (32) immediately completely overlaps with the other region (32, 22), or the first region (22) and the second region (32) overlap only at the edge regions.

9. The method according to any one of claims 1 to 7, wherein, viewed from a top view of the surface (S) of the carrier substrate (10), after the introduction of the second dopant (30), the first region (22) immediately overlaps with the edge regions of the two second regions (32) at the left and right edge regions, or the second region (32) overlaps with the edge regions of the two first regions (22) at the left and right edge regions.

10. The method according to any one of the preceding claims, wherein the first region (22) is an n-type embedded layer (NBL) and the second region (32) is a p-type embedded layer (PBL).

11. A BCD substrate (100) having buried pn junctions (50, 52, 54a, 54b, 56a, 56b), comprising: Carrier substrate (10); and An epitaxial layer (40) is grown on the carrier substrate (10), wherein pn junctions (50, 52, 54a, 54b, 56a, 56b) are generated between the carrier substrate (10) and the epitaxial layer (40) by means of the method according to claim 1, or by diffusion of a dopant introduced into the surface (S) of the carrier substrate (10) below the epitaxial layer (40).

12. The BCD substrate (100) according to claim 11, wherein pn junctions (50, 52, 54a, 54b, 56a, 56b) are respectively formed in the epitaxial layer (40) and in the carrier substrate (10).

13. A single-photon avalanche diode (200), SPAD, comprising: The BCD substrate (100) according to claim 11 or 12, wherein the region around the pn junctions (50, 52, 54a, 54b, 56a, 56b) forms an avalanche zone; and Absorption regions (PW, HPW, NEPI) for converting photons into electron-hole pairs, wherein the absorption regions (PW, HPW, NEPI) are adjacent to the regions (NBL, PBL) that form the pn junctions (50, 52, 54a, 54b, 56a, 56b).

14. The single-photon avalanche diode (200) according to claim 13, wherein The pn junctions (50, 52, 54a, 54b, 56a, 56b) are at least partially formed between the n-type buried layer (NBL) serving as the cathode (C) and the p-type buried layer (PBL) immediately adjacent to the n-type buried layer (NBL). The absorption regions (PW, HPW, NEPI) are adjacent to the p-type buried layer (PBL) and are formed as p-regions. The anode (A) designed as a p+ region is located adjacent to the absorption region (PW, HPW, NEPI).

15. The single-photon avalanche diode (200) according to claim 14, wherein the absorption region (PW, HPW, NEPI) includes a high-voltage p-well (HPW) adjacent to the p-type buried layer (PBL), and optionally includes a p-well (PW) adjacent to the high-voltage p-well.

16. The single-photon avalanche diode (200) according to claim 14 or 15, wherein the absorption region (PW, HPW, NEPI) located between the p-type buried layer (PBL) and the anode (A) is formed as an n-type lightly doped epitaxial region (NEPI) having a high-voltage p-well (HPW) formed as a channel as a nonlinear quenching resistor (QR).

17. The single-photon avalanche diode (200) according to claim 16, wherein a plurality of independent p-type buried layers (PBLs) are formed along the n-type buried layer (NBL) and disposed directly above the n-type buried layer (NBL).

18. An integrated circuit comprising at least one single-photon avalanche diode (200) according to any one of claims 13 to 17.

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