A replication system and method for replicating an area

Abstract

The present application relates to chip design technical field, especially to a kind of copy system and method of copy area, and it is obtained instruction parameter by decoding hardware copy instruction through instruction decoding unit;Splitting subunit responds to the hardware copy instruction after decoding, and the to-be-copied region defined by instruction parameter is split into N linear copy operation, and the independent source address and destination address of each linear copy operation are generated, and are assembled into operation package;Operation package is sequentially written into package cache subunit;Hardware execution unit sequentially reads operation package from package cache subunit, and initiates read operation, and reads copy data from source address and stores into data cache unit;Write processing unit is configured to obtain copy data from data cache unit and initiate write operation and write into destination address;When N linear copy operation is executed, hardware copy instruction completion flag is returned, which reduces the complexity of software and hardware cooperative processing, and significantly improves system performance.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a system and method for replicating a region. Background Technology

[0002] In modern heterogeneous accelerator chips and high-performance computing systems, memory data transfer efficiency is one of the key factors affecting overall performance. Rectangular copying, as a fundamental and frequently used operation, is widely applied in scenarios such as graphics rendering, image processing, and computational data movement. However, with the increasing complexity and processing power of heterogeneous accelerator chip architectures, traditional rectangular copying implementation methods face challenges in bandwidth bottlenecks and resource utilization efficiency.

[0003] Direct Memory Access (DMA) is another common method for implementing rectangular copying. In this approach, the DMA controller manages the entire copying process. The CPU only needs to initialize the DMA controller's parameters and can then continue executing other tasks until the DMA completes and the result is processed. However, traditional DMA controllers typically only support continuous data movement within a one-dimensional linear address space, while rectangular copying is inherently a two-dimensional or even three-dimensional non-contiguous memory access because there may be row spacing between rows, i.e., padding bytes after valid data. To perform rectangular copying using traditional DMA, the software needs to break a rectangle into multiple independent one-dimensional DMA requests, calculate the source and destination addresses for each row, and submit these requests to the DMA controller one by one. This process requires deep software involvement in coordinating control and data flows. The preprocessing operations, such as calculating the start address of each row, constructing DMA instructions, and allocating memory, incur additional time consumption, reducing the performance of single and multiple copying operations.

[0004] Therefore, there is an urgent need for a system that reduces the complexity of hardware and software co-processing and improves the performance of rectangular copying, in order to meet the development needs of heterogeneous acceleration chips in different scenarios such as graphics rendering, image processing, and computational data movement. Summary of the Invention

[0005] To address the aforementioned technical problems, the present invention adopts the following technical solution: a replication system for a replication region, the system comprising:

[0006] The instruction decoding unit is configured to decode the hardware copy instruction to extract the instruction parameters of the region to be copied in the hardware copy instruction.

[0007] The hardware decomposition unit includes a splitting subunit and a packet buffer subunit; wherein, the splitting subunit is configured to generate N linear copy operations corresponding to the region to be copied in response to receiving instruction parameters of the region to be copied, each linear copy operation corresponding to a row of data, generate its own independent source address and destination address for each linear copy operation, and assemble them into an operation packet, wherein N is greater than or equal to 1; and write the operation packets sequentially into the packet buffer subunit.

[0008] The hardware execution unit includes a read processing unit, a write processing unit, and a data cache unit; wherein, the read processing unit is configured to sequentially read the operation packet from the packet cache subunit, and initiate a read operation based on the operation packet to read copied data from the source address and store it in the data cache unit; the write processing unit is configured to obtain copied data from the data cache unit and initiate a write operation to write it to the destination address.

[0009] The instruction decoding unit, hardware decomposition unit, and hardware execution unit are all implemented in hardware.

[0010] Furthermore, the present invention also provides a method for copying a region, the method comprising:

[0011] S100, decode the hardware copy instruction to extract the instruction parameters of the region to be copied in the hardware copy instruction.

[0012] S200, in response to receiving the instruction parameter of the region to be copied, generate N linear copy operations corresponding to the region to be copied, each linear copy operation corresponds to one row of data, generate its own independent source address and destination address for each linear copy operation, and assemble them into an operation packet, where N is greater than or equal to 1; write the operation packets sequentially into the packet buffer subunit.

[0013] S300: The operation packet is read sequentially from the packet cache subunit, and a read operation is initiated based on the operation packet to read the copied data from the source address and store it in the data cache unit; and the copied data is obtained from the data cache unit and a write operation is initiated to write it to the destination address.

[0014] The instruction decoding unit, hardware decomposition unit, and hardware execution unit are all implemented in hardware.

[0015] The present invention has at least the following beneficial effects:

[0016] This invention provides a replication system and method for a replication region. Through a hardware decomposition unit, in response to a single hardware replication instruction, the region to be replicated is divided into linear replication operations, and operation packets are generated and placed into a packet buffer subunit. The hardware execution unit then executes the replication operations. The entire process requires no central processing unit (CPU) involvement; the software only needs to submit a single hardware replication instruction to achieve efficient transfer of multidimensional data. This completely transforms the control flow, originally handled by software, into automated hardware execution, reducing the complexity of software-hardware co-processing. Furthermore, the hardware execution speed is significantly higher than that of software, thus significantly improving system performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A block diagram of a copying system for a copying region provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram showing the positions of the region to be copied in the three-dimensional coordinate systems of the source and destination ends, respectively, as provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0022] Example 1

[0023] Please see Figure 1 The document illustrates a replication system for a replication region, the system comprising: an instruction decoding unit, a hardware decomposition unit, and a hardware execution unit.

[0024] Furthermore, the instruction decoding unit is configured to decode the hardware copy instruction to extract the instruction parameters of the region to be copied in the hardware copy instruction.

[0025] In one implementation, the region to be copied is a two-dimensional or three-dimensional data block that needs to be moved, defined by a single hardware copy instruction and determined by its width, height, and depth.

[0026] In one embodiment, the area to be copied is a rectangular area, a cuboid, or a hexahedron, etc. Other areas with regular polygonal cross-sections also fall within the protection scope of this invention.

[0027] The instruction decoding unit is implemented by hardware circuitry and is used to identify hardware copy instructions and extract instruction parameters.

[0028] The hardware copy instruction is an instruction executed by hardware. The instruction decoding unit, hardware decomposition unit, and hardware execution unit are all hardware components used to execute this hardware copy instruction. The copying system provided by this invention can automatically complete the transfer of all rows through hardware when executing the hardware copy instruction after configuring it once, without the need for central processing unit intervention.

[0029] The instruction parameters are a set of hardware-resolvable fields in the hardware copy instruction that characterize the geometry of the region to be copied.

[0030] In one implementation, the instruction parameters of the region to be copied include the instruction opcode, spatial coordinate units, the starting address of the source reference region, the width and area of ​​the source reference region, the starting coordinates of the region to be copied at the source, the starting address of the destination memory, the width and area of ​​the destination memory, the starting coordinates of the region to be copied at the destination, the width, height and depth of the region to be copied, and the data location exchange configuration type.

[0031] The instruction opcode differs from the data movement instruction opcode of a general-purpose processor. The instruction opcode provided in this embodiment of the invention is a unique identifier defined by a dedicated copying system, used to identify the hardware copying instruction and trigger the splitting and copying operation sequence.

[0032] The spatial coordinate unit is the measurement unit used to describe the coordinates, that is, the number of bytes occupied by each data in each coordinate, used to calculate the address offset based on the coordinate offset of the current pen operation. In one embodiment, the spatial coordinate unit is a byte, but other types of spatial coordinate units also fall within the protection scope of this invention. In one embodiment, when the spatial coordinate unit is a byte, the user-selectable byte types include 0-1 Byte, 1-2 Byte, 2-4 Byte, 3-8 Byte, and 4-16 Byte, and other byte types also fall within the protection scope of this invention.

[0033] The starting address of the source reference region is its base address in memory. Please refer to [link to relevant documentation]. Figure 2 The source reference region has a fixed physical base address and line spacing in memory, and this base address serves as the reference origin of the source three-dimensional coordinate system; the region to be copied in the copy operation is defined with respect to this reference origin at the source.

[0034] In this context, the width of the source reference region is the number of valid data entries per row, and the height is the total number of rows included in the source reference region. In physical memory, the width of the source reference region, i.e., the byte offset between the starting addresses of two adjacent rows, is the row stride. The height of the reference region itself does not directly correspond to a memory offset, but combined with the row stride, it determines the vertical coverage of the entire region in physical memory; that is, from row 0 to row (H-1), it spans a row spacing of (H-1) × Stride bytes. Therefore, the area of ​​the source reference region is the product of its width and height, representing the total number of valid data entries contained within the region. Its width and height together describe the range of data in the logical two-dimensional plane, but in physical memory, this region is stored linearly. Therefore, although logically it can be considered a rectangle, there is no corresponding rectangular structure in physical memory; instead, it is a one-dimensional storage sequence that achieves row jumps through the width of the source reference region.

[0035] The starting coordinates of the region to be copied at the source end are a set of logical offsets. Based on the source end's three-dimensional coordinate system, with the starting address of the source end's reference region as the reference origin, the coordinates describe the position of the first element of the region to be copied in the width, height, and depth directions in the three-dimensional coordinate system.

[0036] In this context, the starting address of the destination memory is its base address. Similar to the source memory's starting address, the destination memory has a fixed physical base address and line spacing. This base address serves as the reference origin of the destination's three-dimensional coordinate system. The starting coordinates of the region to be copied in the copy operation are defined relative to this reference origin on the destination side.

[0037] The width of the destination memory is the byte offset of the starting addresses of two adjacent rows in the destination display area within the memory buffer.

[0038] The area of ​​the destination memory is a two-dimensional memory coverage area determined by the width of the destination memory and the height of the destination display area. Its physical size is equal to the width × the height, representing the rectangular area occupied by the display buffer in the memory space of the destination.

[0039] Here, the starting coordinates of the region to be copied at the destination are a set of logical offsets. Similar to the starting coordinates of the region to be copied at the source, they are based on the three-dimensional coordinate system of the destination and its reference origin, describing the position of the first element of the region to be copied in the width, height, and depth directions.

[0040] The region to be copied is defined by three parameters: width, height, and depth. The width represents the size of each row of valid data in the region to be copied, the height represents the number of data rows in the region to be copied, and the depth represents the number of data layers in the region to be copied. Together, these three parameters characterize the logical size of the region to be copied.

[0041] The copy data position swap configuration type is a preset word-length granularity used to control the hardware's byte order reversal of data during copy operations. It's important to note that adjusting the byte order of copied data ensures data consistency during cross-platform data transfers or shared memory accesses, as different processor architectures may use different byte orders.

[0042] In one implementation, the exchange strategy based on the data location exchange configuration type includes: obtaining a preset word length granularity Q; when Q=0, no exchange; when Q>0, performing a byte reversal operation on every consecutive Q / 8 byte data block during the copying process. In one implementation, the preset word length granularity Q=0, 16, 32, or 64; where 0 indicates no exchange is needed. A 16-bit exchange represents a byte reversal within every 2 bytes, for example, if the source is 0xaabb, the destination is 0xbbaa. A 32-bit exchange represents a byte reversal within every 4 bytes, with the source being 0xaabbccdd and the destination being 0xddccbbaa. A 64-bit exchange represents a byte reversal within every 8 bytes, with the source being 0xaabbccddeeff0011 and the destination being 0x1100ffeeddccbbaa.

[0043] Furthermore, the hardware decomposition unit includes a splitting subunit and a packet buffer subunit; wherein, the splitting subunit is configured to generate N linear copy operations corresponding to the region to be copied in response to receiving instruction parameters of the region to be copied, each linear copy operation corresponding to a row of data, generate its own independent source address and destination address for each linear copy operation, and assemble them into an operation packet, wherein N is greater than or equal to 1; and write the operation packets sequentially into the packet buffer subunit.

[0044] The hardware decomposition unit is implemented by hardware circuitry and is used to split the area to be copied into multiple linear copy operations according to the hardware copy instruction, and assemble them into an operation package and put it into the package buffer subunit.

[0045] Each linear copy operation refers to the data copying operation that moves a continuous sequence of bytes from the source reference region to another continuous address space in the destination memory, in its original order. This continuous sequence of bytes is represented as a single line in the width direction of the region to be copied.

[0046] In one implementation, the partitioning strategy for the region to be copied is as follows: the width and height of the region to be copied form a copy surface, and the region to be copied contains multiple copy surfaces arranged sequentially; for each copy surface, according to the width of the copy surface, the region to be copied is divided into multiple linear data segments by row, wherein each linear data segment corresponds to a row of data, and each linear data segment is used as an atomic unit; each atomic unit is partitioned into a linear copy operation; after all linear data segments of the current copy surface are partitioned, the process switches to the next copy surface, and the above partitioning and partitioning steps are repeated until all copy surfaces in the region to be copied have been processed.

[0047] In this context, the source address of each linear copy operation refers to the starting physical address of the data read by the current copy operation in the source reference area, that is, the memory address of the first byte in the current consecutive byte sequence being copied.

[0048] In this context, the destination address of each linear copy operation refers to the starting physical address of the data read by the current copy operation in the destination memory.

[0049] The operation package refers to a data structure that encapsulates the parameters required for a linear copy operation and submits them to the hardware execution unit in the form of atomic units.

[0050] Among them, the packet cache subunit refers to a dedicated buffer storage structure in hardware used to temporarily store one or more operation packets and implement command queuing and pipelined execution.

[0051] It should be noted that the hardware decomposition unit responds to a single hardware copy instruction. The splitting subunit calculates the physical addresses of the source and destination ends of each line according to the width, height, and other parameters provided in the hardware copy instruction, and generates operation packets for each line in sequence and puts them into the packet buffer subunit. Then, the hardware execution unit executes the copy operation. The entire process does not require the central processing unit to participate in address calculation and loop control, nor does it generate multiple independent DMA instructions. The software only needs to submit a hardware copy instruction once to achieve efficient transfer of multidimensional data, thereby completely transforming the control flow originally undertaken by the software into automated hardware execution, significantly improving system performance and energy efficiency.

[0052] In one embodiment, the splitting subunit is further configured to: suspend the data splitting operation when the amount of cached data reaches a preset capacity threshold; and resume the data splitting operation when the amount of cached data is lower than the preset capacity threshold.

[0053] In one implementation, the splitting subunit is further configured to terminate the splitting operation on the data when the region to be copied has been completely split.

[0054] In one embodiment, the splitting subunit further includes a marking unit configured to assign a unique sequence number to the operation packet before writing it to the packet buffer subunit. It should be noted that the packet buffer subunit has limited capacity; assigning sequence numbers to operation packets allows the system to promptly detect whether there are available addresses to store new operation packets. When the splitting subunit receives completion signals for both a read and write operation of an operation packet, it releases the sequence number of that operation packet, which can then be allocated to new operation packets.

[0055] In one embodiment, the splitting subunit further includes a source address calculation unit, a destination address calculation unit, and a coordinate offset buffer unit. The splitting subunit is implemented by hardware circuitry and includes adders and multipliers, which are used to calculate the source and destination addresses.

[0056] Furthermore, the source address calculation unit is configured to: calculate the starting coordinates of the current linear copy operation at the source end based on the starting coordinates of the region to be copied at the source end, the width and area of ​​the source end reference region, and the split offsets in the height and depth directions; determine the address offset of the current linear copy operation based on the starting coordinates and spatial coordinate units of the current linear copy operation at the source end; and generate an independent source address for the current linear copy operation based on the address offset and the source end starting address.

[0057] In one implementation, the independent source address of the current pen linear copy operation satisfies: (src_x + src_z × src_area + src_y × src_wd + z_cnt × src_area + y_cnt × src_wd) × unit + src_start; where (src_x, src_y, src_z) are the starting coordinates of the source end, src_area is the area of ​​the source end reference region, src_wd is the width of the source end reference region, z_cnt is the split offset in the depth direction, y_cnt is the split offset in the height direction, unit is the spatial coordinate unit, and src_start is the starting address of the source end.

[0058] Furthermore, the destination address calculation unit is configured to: calculate the starting coordinates of the current linear copy operation at the destination based on the starting coordinates of the region to be copied at the destination, the width and area of ​​the memory at the destination, and the split offsets in the height and depth directions; determine the address offset of the current linear copy operation based on the starting coordinates and spatial coordinate units of the current linear copy operation at the destination; and generate an independent destination address for the current linear copy operation based on the address offset and the starting address at the destination.

[0059] In one implementation, the independent destination address of the current pen linear copy operation satisfies: (dst_x + dst_z × dst_area + dst_y × dst_wd + z_cnt × dst_area + y_cnt × dst_wd) × unit + dst_start; where (dst_x, dst_y, dst_z) are the starting coordinates of the destination, dst_area is the area of ​​the destination memory, dst_wd is the width of the destination memory, z_cnt is the split offset in the depth direction, y_cnt is the split offset in the height direction, unit is the spatial coordinate unit, and dst_start is the starting address of the destination.

[0060] Furthermore, the coordinate offset caching unit is configured to: after generating the independent source and destination addresses for the current linear copy operation, update the split offsets in the height and depth directions for the next linear copy operation. The update steps include: if the split offset in the height direction is less than the height of the region to be copied, keep the split offset in the depth direction unchanged and increment the split offset in the height direction by 1; if the split offset in the height direction is equal to the height of the region to be copied, reset the split offset in the height direction to 0 and increment the split offset in the depth direction by 1. That is, the current split operation needs to switch to the next copy surface in the depth direction and start splitting from the first row of data in the next copy surface. When all copy surfaces in the depth directions and the linear data segments in the copy surfaces are completely split, that is, when the split offset in the height direction is equal to the height of the region to be copied and the split offset in the depth direction is equal to the depth of the region to be copied, then all split operations in the region to be copied are completed.

[0061] Furthermore, the hardware execution unit includes a read processing unit, a write processing unit, and a data cache unit; wherein, the read processing unit is configured to sequentially read the operation packet from the packet cache subunit, and initiate a read operation based on the operation packet to read copied data from the source address and store it in the data cache unit; the write processing unit is configured to obtain copied data from the data cache unit and initiate a write operation to write it to the destination address.

[0062] The hardware execution unit is implemented by hardware circuitry and is used to perform data copying operations according to the operation package.

[0063] The operation packets stored in the packet cache subunit are read by both the read processing unit and the write processing unit. The read processing unit needs to read the copied data according to the starting address in the operation packet, while the write processing unit needs to write the copied data according to the destination address in the operation packet.

[0064] The read operation is a hardware access operation initiated by the read processing unit, used to read copied data from the storage location pointed to by the source start address, and store the read data into the data cache unit.

[0065] The write operation is a hardware access operation initiated by the write processing unit to read cached copy data from the data cache unit and write it to the storage location pointed to by the destination start address. It should be noted that due to the bus width limitation, only a fixed width of data can be written to the destination at a time. The current copy data may need to be written multiple times via the bus to complete the process. Therefore, it is necessary to calculate the destination start address for each write operation via the bus. Before initiating a write operation, the write processing unit needs to read the operation packet from the packet cache subunit and the cached copy data from the data cache unit. The starting address for the second write is obtained by adding a fixed offset to the destination start address in the operation packet. Then, the starting address for the third write is obtained by adding a fixed offset to the starting address for the second write, and so on, until the current copy data is completely written.

[0066] The copied data is payload data read from the source start address and transmitted to the destination start address; the content and format of the copied data are defined by the control information in the operation packet.

[0067] The data cache unit is a temporary storage structure located inside the hardware execution unit. It is used to temporarily store copied data read from the source until the write processing unit writes it to the destination address.

[0068] In one implementation, the hardware execution unit and the hardware decomposition unit execute in parallel.

[0069] It should be noted that by configuring independent hardware decomposition units and hardware execution units, and using a packet buffer subunit as an asynchronous communication bridge between them, a pipelined parallel processing of task decomposition and data copying execution of the region to be copied is achieved. This decouples the generation of operation packets from the execution of copying operations. The decomposition unit can generate operation packets in advance, while the execution unit processes the previously generated operation packets simultaneously, avoiding the serial bottleneck of disassembling all packets before execution. This not only significantly improves the overall throughput and hardware resource utilization of data copying but also effectively hides the latency of task splitting. Furthermore, the packet buffer subunit, acting as a bridge, ensures that if the execution unit is blocked, it will not affect the splitting of the hardware decomposition unit; similarly, if the splitting of the hardware decomposition unit is slowed down, it will not affect the execution of the hardware execution unit, resulting in strong system stability. In addition, since the operation packets are split before entering the execution unit, it ensures that each copying operation conforms to the transmission constraints of the hardware execution unit, avoiding the complex logic caused by further splitting within the hardware execution unit and simplifying hardware design.

[0070] Furthermore, after the N linear copy operations of the region to be copied are completed, the hardware copy instruction completion flag is returned.

[0071] The hardware copy instruction completion flag is used to indicate whether all N linear copy operations corresponding to the area to be copied initiated by the hardware execution unit have been completed. When all data specified by all operation packets is successfully read and written, the completion flag is set to a valid state, indicating that the current hardware copy instruction has been completed.

[0072] As an example, a user wants to transfer a small portion of a 3D image from the CPU system memory to a heterogeneous acceleration chip for rendering. The hardware copy instruction parameters include: instruction opcode "0x1"; spatial coordinate unit is "2", i.e., 4 bytes; source reference region start address "0x100100", source reference region width "0x100" and area "0x800", the start coordinates of the region to be copied at the source end (2, 4, 8), destination memory start address "0x400200", destination memory width "0x800" and area "0x1000", the start coordinates of the region to be copied at the destination end (2, 2, 4), the width "0x200", height "0x40", and depth "0x10" of the region to be copied, and the copy data location exchange configuration type is set to 16 bits. Initially, the instruction cache unit contains no hardware copy instructions. The write pointer currently points to the beginning of the instruction cache unit, which is 1 Mbyte in size. Therefore, the latest hardware copy instruction will be written to addresses 0-31 of the instruction cache unit. When the instruction cache unit is not empty, it indicates that a new instruction has been written to it. At this time, the instruction read / write module will actively send the hardware copy instruction to the instruction decoding unit. The instruction decoding unit will parse the hardware copy instruction and extract its parameters. The hardware decomposition unit will perform decomposition and splitting calculations based on the instruction parameters: the source address of the first linear copy operation is equal to: (2 + 8 × 0x800 + 4 × 0x100 + 0 × 0x800 + 0 × 0x100) × 4 + 0x100100. The destination address of the first linear copy operation is equal to: (2 + 4 × 0x1000 + 2 × 0x800 + 0 × 0x1000 + 0 × 0x800) × 4 + 0x400200. The amount of data copied is 0x200. The split offsets in the height and depth directions are recorded, and the source and destination addresses for the next split are calculated sequentially. The hardware decomposition unit assigns a unique sequence number to each linear copy operation as an operation packet and places it sequentially into the packet buffer subunit. The hardware execution unit retrieves operation packets from the packet buffer subunit in sequence. Based on the source address, a read operation is initiated to the memory unit in the CPU. The hardware decomposition unit caches the read data returned by the CPU memory unit in the data buffer unit. Simultaneously, based on the destination address, a 16-bit position swap is performed, and then the swapped data is sent to the memory unit of the heterogeneous acceleration chip. When the data in the operation packet is completely copied and transferred, the next operation packet is retrieved from the packet buffer subunit, and read, buffer, and write operations continue to be initiated. When all operation packets obtained from splitting the area to be copied have been executed, a hardware copy instruction completion flag is returned to the user. The user receiving the hardware copy instruction completion flag indicates that the copy service set by the current user has been completed.Users can utilize the heterogeneous accelerator chip to perform subsequent graphics rendering and other processing operations on the data copied to it. Users can choose to continue writing new hardware copy instructions to complete the process or stop writing.

[0073] Example 2

[0074] Embodiment 2 of the present invention provides a method for copying a region, the method comprising:

[0075] S100, decode the hardware copy instruction to extract the instruction parameters of the region to be copied in the hardware copy instruction.

[0076] S200, in response to receiving the instruction parameter of the region to be copied, generate N linear copy operations corresponding to the region to be copied, each linear copy operation corresponds to one row of data, generate its own independent source address and destination address for each linear copy operation, and assemble them into an operation packet, where N is greater than or equal to 1; write the operation packets sequentially into the packet buffer subunit.

[0077] S300: The operation packet is read sequentially from the packet cache subunit, and a read operation is initiated based on the operation packet to read the copied data from the source address and store it in the data cache unit; and the copied data is obtained from the data cache unit and a write operation is initiated to write it to the destination address.

[0078] The instruction decoding unit, hardware decomposition unit, and hardware execution unit are all implemented by hardware circuits.

[0079] It should be noted that the relevant concepts and steps in Example 1 are also applicable to Example 2, and will not be repeated here.

[0080] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0081] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0082] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0083] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0084] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A replication system for a replication region, characterized in that, The system includes: The instruction decoding unit is configured to decode the hardware copy instruction to extract the instruction parameters of the region to be copied in the hardware copy instruction; The hardware decomposition unit includes a splitting subunit and a packet buffer subunit; wherein, the splitting subunit is configured to, in response to receiving instruction parameters of the region to be copied, generate N linear copy operations corresponding to the region to be copied, each linear copy operation corresponding to one row of data, generate its own independent source address and destination address for each linear copy operation, and assemble them into an operation packet, wherein N is greater than or equal to 1; and write the operation packets sequentially into the packet buffer subunit; The hardware execution unit includes a read processing unit, a write processing unit, and a data cache unit; wherein, the read processing unit is configured to sequentially read the operation packet from the packet cache subunit, and initiate a read operation based on the operation packet to read copied data from the source address and store it in the data cache unit; the write processing unit is configured to obtain copied data from the data cache unit and initiate a write operation to write it to the destination address; The instruction decoding unit, hardware decomposition unit, and hardware execution unit are all implemented in hardware. The splitting strategy for the region to be copied is as follows: A copy surface is formed based on the width and height of the area to be copied, and the area to be copied contains multiple copy surfaces arranged in sequence; For each copy surface, the region to be copied is divided into multiple linear data segments according to the width of the copy surface, where each linear data segment corresponds to a row of data, and each linear data segment is used as an atomic unit. Each atomic unit is split into a linear copy operation; After all linear data segments of the current copy plane have been split, switch to the next copy plane and repeat the above division and splitting steps until all copy planes in the area to be copied have been processed.

2. The system according to claim 1, characterized in that, The splitting subunit is further configured to: pause the data splitting operation when the cached data volume reaches a preset capacity threshold; and resume the data splitting operation when the cached data volume is lower than the preset capacity threshold.

3. The system according to claim 1, characterized in that, The splitting subunit is further configured to terminate the splitting operation on the data when the area to be copied has been completely split.

4. The system according to claim 1, characterized in that, The splitting subunit further includes a marking unit, which is configured to assign a unique sequence number to the operation packet before writing the operation packet to the packet cache subunit.

5. The system according to claim 1, characterized in that, The instruction parameters of the region to be copied include the instruction opcode, spatial coordinate units, starting address of the source reference region, width and area of ​​the source reference region, starting coordinates of the region to be copied at the source, starting address of the destination memory, width and area of ​​the destination memory, starting coordinates of the region to be copied at the destination, width, height and depth of the region to be copied, and data location exchange configuration type.

6. The system according to claim 5, characterized in that, The splitting subunit further includes a source address calculation unit, a destination address calculation unit, and a coordinate offset buffer unit; The source address calculation unit is configured to: calculate the starting coordinates of the current linear copy operation at the source end based on the starting coordinates of the region to be copied at the source end, the width and area of ​​the source end reference region, and the split offsets in the height and depth directions; and determine the address offset of the current linear copy operation based on the starting coordinates and spatial coordinate units of the current linear copy operation at the source end. Based on the address offset and the source start address, generate an independent source address for the current pen linear copy operation; The destination address calculation unit is configured to: calculate the starting coordinates of the current linear copy operation at the destination based on the starting coordinates of the region to be copied at the destination, the width and area of ​​the memory at the destination, and the split offsets in the height and depth directions. Based on the starting coordinates and spatial coordinate units of the current linear copy operation at the destination, the address offset of the current linear copy operation is determined, and an independent destination address for the current linear copy operation is generated according to the address offset and the starting address of the destination. The coordinate offset cache unit is configured to: after generating the independent source and destination addresses for the current linear copy operation, update the split offset in the height direction and the split offset in the depth direction for the next linear copy operation. The update steps include: if the split offset in the height direction is less than the height of the area to be copied, then keep the split offset in the depth direction unchanged and increment the split offset in the height direction by 1; if the split offset in the height direction is equal to the height of the area to be copied, then reset the split offset in the height direction to 0 and increment the split offset in the depth direction by 1.

7. The system according to claim 5, characterized in that, The exchange strategy based on the data location exchange configuration type includes: obtaining the word length granularity Q; when Q=0, no exchange; when Q>0, performing a byte reversal operation on each consecutive Q / 8 byte data block during the copying process.

8. The system according to claim 1, characterized in that, The hardware execution unit and the hardware decomposition unit execute in parallel.

9. A method for copying a region, characterized in that, The method includes: S100, decode the hardware copy instruction to extract the instruction parameters of the region to be copied in the hardware copy instruction; S200, in response to receiving the instruction parameter of the region to be copied, generate N linear copy operations corresponding to the region to be copied, each linear copy operation corresponds to one row of data, generate its own independent source address and destination address for each linear copy operation, and assemble them into an operation packet, where N is greater than or equal to 1; write the operation packets sequentially into the packet buffer subunit; S300, sequentially read the operation packet from the packet cache subunit, and initiate a read operation based on the operation packet to read the copied data from the source address and store it in the data cache unit; and obtain the copied data from the data cache unit and initiate a write operation to write it to the destination address; The instruction decoding unit, hardware decomposition unit, and hardware execution unit are all implemented in hardware. The splitting strategy for the region to be copied is as follows: A copy surface is formed based on the width and height of the area to be copied, and the area to be copied contains multiple copy surfaces arranged in sequence; For each copy surface, the region to be copied is divided into multiple linear data segments according to the width of the copy surface, where each linear data segment corresponds to a row of data, and each linear data segment is used as an atomic unit. Each atomic unit is split into a linear copy operation; After all linear data segments of the current copy plane have been split, switch to the next copy plane and repeat the above division and splitting steps until all copy planes in the area to be copied have been processed.

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