Testing device and testing method for physical layer IP

Abstract

The invention relates to the technical field of integrated circuits and provides a testing device and a testing method for a physical layer IP. The method supports the composition of different physical layer intellectual property cores, supports the coverage of different hierarchies, reduces the number and overhead of hardware resources of an ATE test machine and a JTAG controller, effectively reduces the ATE test cost, can cover more complete hierarchies and circuit units of a to-be-tested design range and more complete logic chain paths, and improves the test efficiency. The completeness of the ATE test vectors and the comprehensive test items of different test dimensions of the function / performance / reliability test of the ATE test items is improved, and matching of rapid iteration and verification requirements of chip development is facilitated.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a test apparatus and test method for physical layer IP. Background Technology

[0002] Automated Test Equipment (ATE) is used for automated testing of integrated circuit chips and semiconductor devices. For example, testing the bare die (also called CP) on a chip wafer is mainly used for functional testing and performance verification of basic circuit units, testing whether the circuit and device functions and performs correctly, and eliminating faulty chips or devices. Another example is performing Function Test (FT) on packaged chips, mainly used for functional, performance, and reliability testing of analog or digital circuits, ensuring that chips and devices function correctly in the final product equipment. With the increasing integration and complexity of chips, two, four, eight, or even more Physical Layer Intellectual Property (PHY) cores are integrated on a single chip, and the integration scale has extended from the top layer of the core to the physical interface layer, such as the Physical Interface for the PCIe (PIPE) for high-speed serial peripheral interconnect buses. As the number of physical layer intellectual property cores (PIPs) expands and increases, higher demands are placed on the equipment and testing costs of ATE (Automatic Test Equipment). For example, in application scenarios integrating multiple PIPs, it may be necessary to cover different layers and adapt to different PIP compositions. In existing technologies, automated test equipment for applications integrating multiple PIPs employs two approaches: one is point-to-point parallel testing, which requires allocating a Joint Test Action Group (JTAG) interface for each PIP, resulting in a large number of hardware interfaces and resources. The other approach is to use a JTAG serial structure (Chain) to connect multiple devices in series, but this serial structure is inefficient and prolongs testing time. Chinese patent CN119716496B discloses a method to connect the test interfaces of multiple physical layer subsystems of the same type in parallel through a JTAG hub module and access the JTAG serial structure via the JTAG hub module. However, this solution requires the access logic to be determined in advance and introduces an additional hub module for parallel test control of physical layer subsystems of the same type. This increases the preparation work before each automated test and is not conducive to matching the rapid iteration and verification requirements of chip development.

[0003] To address these technical challenges, this application provides a testing apparatus and method for physical layer IP. Summary of the Invention

[0004] Firstly, this application provides a testing apparatus for physical layer IP. The testing apparatus includes a Joint Test Workgroup (JTW) bus control interface controller. The JTW bus control interface controller includes a set of JTW hardware interfaces, each of which includes a serial data input signal terminal, a serial data output signal terminal, a test clock signal terminal, and a controller state machine control signal terminal. Multiple physical layer IPs are serially cascaded according to the JTW bus standard, and these multiple physical layer IPs share the same automated testing platform and the test clock signal terminal and controller state machine control signal terminal of the JTW hardware interfaces. The JTW bus control interface controller is configured to: perform automated testing on each of the multiple physical layer IPs sequentially, or, using bypass instructions, select a specific physical layer IP from the multiple physical layer IPs as the destination to initiate a read / write access operation.

[0005] Through the first aspect of this application, a cascaded topology is constructed between a single joint test workgroup bus control interface controller and multiple physical layer IPs. Furthermore, by utilizing the shared automated test bench and the test clock signal terminal and controller state machine control signal terminal of the joint test workgroup hardware interface among the multiple physical layer IPs, automated testing of each of the multiple physical layer IPs is achieved. Alternatively, bypass instructions can be used to select a specific physical layer IP among the multiple physical layer IPs as the destination to initiate read / write access operations. This supports adaptation to different physical layer intellectual property core compositions, supports coverage of different layers, reduces the number and overhead of hardware resources for ATE test benches and JTAG controllers, effectively reduces ATE testing costs, and can cover a more complete range of layers and circuit units of the design under test, as well as a more complete logic chain path. It improves the completeness of comprehensive test items across different test dimensions of ATE test vectors and ATE test items (functionality / performance / reliability testing), which is beneficial for matching the rapid iteration and verification needs of chip development.

[0006] In one possible implementation of the first aspect of this application, the serial data output signal terminal of the preceding physical layer IP in the plurality of physical layer IPs according to the cascading order and topology routing relationship is connected to the serial data input signal terminal of the following physical layer IP. Furthermore, the serial data input signal terminal of the first physical layer IP in the plurality of physical layer IPs according to the cascading order and topology routing relationship is connected to the serial data output signal terminal of the joint test workgroup hardware interface, and the serial data output signal terminal of the last physical layer IP in the plurality of physical layer IPs according to the cascading order and topology routing relationship is connected to the serial data input signal terminal of the joint test workgroup hardware interface.

[0007] In one possible implementation of the first aspect of this application, the plurality of physical layer IPs each include at least a physical layer hard core logic processing unit top layer for first-level automated device testing.

[0008] In one possible implementation of the first aspect of this application, the plurality of physical layer IPs further include a physical layer top layer for second-level automated device testing, wherein the physical layer top layer includes the physical layer hard core logic processing unit top layer and the physical layer soft core logic processing unit.

[0009] In one possible implementation of the first aspect of this application, the plurality of physical layer IPs further include a PCIe physical interface top layer for third-level automated device testing, wherein the PCIe physical interface top layer includes the physical layer top layer and the physical coding sublayer.

[0010] In one possible implementation of the first aspect of this application, the Joint Test Workgroup Bus Control Interface Controller is configured to perform automated testing on the plurality of physical layer IPs one by one, including: a global reset followed by a release reset of the Joint Test Workgroup interface of the Joint Test Workgroup Bus Control Interface Controller; initializing the plurality of physical layer IPs and ensuring that all the plurality of physical layer IPs are powered on; according to the cascading order and topology routing relationship, starting from the first physical layer IP to the last physical layer IP, for each of the plurality of physical layer IPs, setting the power consumption state of the physical layer IP to exit from the default low power state and switch to the normal operating state, and then enabling the built-in pseudo-random binary sequence generator and verifier of the physical layer IP for the first round of detection results.

[0011] In one possible implementation of the first aspect of this application, the joint test workgroup bus control interface controller is configured to perform automated testing on the plurality of physical layer IPs one by one, and further includes: configuring the registers of each of the plurality of physical layer IPs based on the first round of detection results; enabling the built-in pseudo-random binary sequence generator and verifier of each of the plurality of physical layer IPs according to the cascading order and topology routing relationship, starting from the first physical layer IP and ending at the last physical layer IP, for the second round of detection results; and ending the automated testing based on the second round of detection results.

[0012] In one possible implementation of the first aspect of this application, the Joint Test Workgroup Bus Control Interface (JTLI) controller is configured to select a specified physical layer IP from the plurality of physical layer IPs as the destination to initiate a read / write access operation using a bypass instruction. This includes: the JTLI bus control interface controller bypassing all physical layer IPs preceding the specified physical layer IP according to the cascading order and topology routing relationship using a bypass instruction, thereby substantially connecting the serial data output signal terminal of the JTLI hardware interface to the serial data input signal terminal of the specified physical layer IP; and the JTLI bus control interface controller bypassing all physical layer IPs following the specified physical layer IP according to the cascading order and topology routing relationship using a bypass instruction, thereby substantially connecting the serial data output signal terminal of the specified physical layer IP to the serial data input signal terminal of the JTLI hardware interface.

[0013] In one possible implementation of the first aspect of this application, the Joint Test Workgroup Bus Control Interface controller is configured to bypass other Physical Layer IPs among the plurality of Physical Layer IPs except for the designated Physical Layer IP using a bypass instruction, thereby making the serial data output signal terminal of the Joint Test Workgroup Hardware Interface substantially connected to the serial data input signal terminal of the designated Physical Layer IP, and making the serial data output signal terminal of the designated Physical Layer IP substantially connected to the serial data input signal terminal of the Joint Test Workgroup Hardware Interface.

[0014] In one possible implementation of the first aspect of this application, the testing apparatus is used for wafer bare die testing or post-packaged chip completeness functional testing.

[0015] In one possible implementation of the first aspect of this application, the plurality of physical layer IPs includes one or more system-on-a-chips, and the plurality of physical layer IPs are PCIe physical layer intellectual property cores.

[0016] Secondly, this application provides a testing method for physical layer IPs. The testing method includes: resetting the joint test workgroup interface of the joint test workgroup bus control interface controller; initializing the plurality of physical layer IPs and ensuring that all the plurality of physical layer IPs are powered on; and performing automated testing on the plurality of physical layer IPs one by one through the joint test workgroup bus control interface controller, or selecting a specific physical layer IP among the plurality of physical layer IPs as the destination to initiate a read / write access operation using a bypass instruction. The joint test workgroup bus control interface controller includes a set of joint test workgroup hardware interfaces, each including a serial data input signal terminal, a serial data output signal terminal, a test clock signal terminal, and a controller state machine control signal terminal. The plurality of physical layer IPs are serially cascaded according to the joint test workgroup bus standard, and the plurality of physical layer IPs share the same automated test platform and the test clock signal terminal and controller state machine control signal terminal of the joint test workgroup hardware interface.

[0017] Through the second aspect of this application, a cascaded topology is constructed between a single joint test workgroup bus control interface controller and multiple physical layer IPs. Furthermore, by utilizing the shared automated test bench and the test clock signal terminal and controller state machine control signal terminal of the joint test workgroup hardware interface among the multiple physical layer IPs, automated testing of each of the multiple physical layer IPs is achieved. Alternatively, bypass instructions can be used to select a specific physical layer IP among the multiple physical layer IPs as the destination to initiate read / write access operations. This supports adaptation to different physical layer intellectual property core compositions, supports coverage of different layers, reduces the number and overhead of hardware resources for ATE test benches and JTAG controllers, effectively reduces ATE testing costs, and can cover a more complete range of layers and circuit units of the design under test, as well as a more complete logic chain path. It improves the completeness of comprehensive test items across different test dimensions of ATE test vectors and ATE test items (functionality / performance / reliability testing), which is beneficial for matching the rapid iteration and verification needs of chip development.

[0018] In one possible implementation of the second aspect of this application, the serial data output signal terminal of the preceding physical layer IP in the plurality of physical layer IPs according to the cascading order and topology routing relationship is connected to the serial data input signal terminal of the following physical layer IP. Furthermore, the serial data input signal terminal of the first physical layer IP in the plurality of physical layer IPs according to the cascading order and topology routing relationship is connected to the serial data output signal terminal of the joint test workgroup hardware interface, and the serial data output signal terminal of the last physical layer IP in the plurality of physical layer IPs according to the cascading order and topology routing relationship is connected to the serial data input signal terminal of the joint test workgroup hardware interface.

[0019] In one possible implementation of the second aspect of this application, the plurality of physical layer IPs respectively include: a physical layer hard core logic processing unit top layer for first-level automated device testing, a physical layer top layer for second-level automated device testing, and a PCIe physical interface top layer for third-level automated device testing, wherein the physical layer top layer includes the physical layer hard core logic processing unit top layer and the physical layer soft core logic processing unit, and the PCIe physical interface top layer includes the physical layer top layer and the physical coding sublayer.

[0020] In one possible implementation of the second aspect of this application, the joint test workgroup bus control interface controller selects a specified physical layer IP from the plurality of physical layer IPs as the destination to initiate a read / write access operation using a bypass instruction. This includes: the joint test workgroup bus control interface controller bypassing the other physical layer IPs from the plurality of physical layer IPs besides the specified physical layer IP using a bypass instruction, thereby making the serial data output signal terminal of the joint test workgroup hardware interface substantially connected to the serial data input signal terminal of the specified physical layer IP, and making the serial data output signal terminal of the specified physical layer IP substantially connected to the serial data input signal terminal of the joint test workgroup hardware interface.

[0021] Thirdly, embodiments of this application also provide a computer device, the computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a method according to any of the above-mentioned implementations.

[0022] Fourthly, embodiments of this application also provide a computer-readable storage medium storing computer instructions that, when executed on a computer device, cause the computer device to perform a method according to any of the above-described implementations.

[0023] Fifthly, embodiments of this application also provide a computer program product, the computer program product including instructions stored on a computer-readable storage medium, which, when executed on a computer device, cause the computer device to perform a method according to any of the above-described aspects. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of a test apparatus for physical layer IP provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a method for automating the testing of multiple physical layer IPs one by one, as provided in an embodiment of this application. Figure 3 A flowchart illustrating a testing method for physical layer IP provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0026] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0027] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0028] Figure 1 This is a schematic diagram of a testing apparatus for physical layer IP provided in an embodiment of this application. Figure 1As shown, the test apparatus includes a Joint Test Action Group (JTAG) bus control interface (Test Access Port, TAP) controller A110. The JTAG bus control interface controller A110 includes a set of JTAG hardware interfaces. These hardware interfaces include a serial data input signal terminal A112 (Test Data Input, TDI), a serial data output signal terminal A114 (Test Data Output, TDO), a test clock signal terminal A116 (Test Clock, TCK), and a controller state machine control signal terminal A118 (Test Mode Select, TMS). Multiple physical layer IPs are serially cascaded according to the JTAG bus standard, and these physical layer IPs share the same automated test bench and the test clock signal terminal A116 and controller state machine control signal terminal A118 of the JTAG hardware interface. The joint test workgroup bus control interface controller A110 is configured to: perform automated testing on each of the multiple physical layer IPs one by one, or, using a bypass instruction, select a specific physical layer IP from the multiple physical layer IPs as the destination to initiate a read / write access operation. This is merely for illustrative purposes. Figure 1 The diagram shows four physical layer IPs. It should be understood that... Figure 1 The test setup shown for physical layer IP can be used for automated testing of any number of physical layer IPs, which can be located at different layers. For example, the Physical Layer Media Access TOP (PMA TOP) can be used for Level 1 Automatic Test Equipment (ATE) testing, the Physical Layer TOP (PHY TOP) for Level 2 ATE testing, or the PCIe Physical Interface TOP (PIPE TOP) for Level 3 ATE testing. Generally, the Physical Layer TOP includes the Physical Layer Media Access TOP (PMA TOP) and the Physical Layer Process Unit (PPU). The PCIe Physical Interface TOP includes the Physical Layer TOP and the Physical Layer Code Sub-Layer (PCS).

[0029] See Figure 1The serial data output signal of the preceding physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the following physical layer IP. Furthermore, the serial data input signal of the first physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data output signal of the joint test workgroup hardware interface. The serial data output signal of the last physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the joint test workgroup hardware interface. Figure 1As shown, the four exemplary physical layer IPs are physical layer IP B120, physical layer IP C130, physical layer IP D140, and physical layer IP E150. Each physical layer IP has a set of hardware interfaces, such as a PMA JTAG interface, including serial data input signal terminals, serial data output signal terminals, test clock signal terminals, and controller state machine control signal terminals. Specifically, the hardware interface of physical layer IP B120 includes serial data input signal terminal B122, serial data output signal terminal B124, test clock signal terminal B126, and controller state machine control signal terminal B128. The hardware interface of physical layer IP C130 includes serial data input signal terminal C132, serial data output signal terminal C134, test clock signal terminal C136, and controller state machine control signal terminal C138. The hardware interface of physical layer IP D140 includes serial data input signal terminal D142, serial data output signal terminal D144, test clock signal terminal D146, and controller state machine control signal terminal D148. The hardware interface of physical layer IP E150 includes a serial data input signal terminal E152, a serial data output signal terminal E154, a test clock signal terminal E156, and a controller state machine control signal terminal E158. It can be seen that physical layer IPs B120, C130, D140, and E150 share the same automated test bench and the test clock signal terminal A116 and controller state machine control signal terminal A118 of the joint test workgroup hardware interface. Specifically, the test clock signal terminals B126 of physical layer IPs B120, C136 of physical layer IPs C130, D146 of physical layer IPs D140, and E156 of physical layer IPs E150 all obtain input from the test clock signal terminal A116 of the joint test workgroup bus control interface controller A110. Furthermore, the controller state machine control signal terminals B128 of physical layer IP B120, C138 of physical layer IP C130, D148 of physical layer IP D140, and E158 of physical layer IP E150 all obtain input from the controller state machine control signal terminal A118 of the joint test workgroup bus control interface controller A110. In this way, in application scenarios integrating multiple physical layer IPs, the sharing of the same board-level JTAG hardware interface among multiple physical layer IPs is achieved, thus avoiding an increase in the number of hardware interfaces and ATE testing costs as the number of physical layer IPs increases.Furthermore, by utilizing the test clock signal terminal A116 and the controller state machine control signal terminal A118 of the shared joint test workgroup bus control interface controller A110, the completeness of ATE test vectors and the functional, performance, and reliability testing of ATE test items can be realized. It can also expand the scope of the design under test covered by ATE testing, extending from the innermost physical layer hard core logic processing unit top layer (PMA TOP) outwards and to different levels such as the physical layer top layer (PHY TOP) and the PCIe physical interface top layer (PIPE TOP), thereby covering a more complete circuit unit and logic chain path of the design under test and improving the coverage of ATE testing. Additionally... Figure 1The exemplary physical layer IPs B120, C130, D140, and E150 in the example satisfy a cascaded topology, that is, they are serially cascaded according to the Joint Test Workgroup bus standard. Specifically, the serial data output signal of the preceding physical layer IP is connected to the serial data input signal of the following physical layer IP according to the cascade order and topology routing relationship. For example, the serial data output signal C134 of physical layer IP C130 is connected to the serial data input signal D142 of physical layer IP D140. Furthermore, the serial data input signal B122 of the first physical layer IP B120 is connected to the serial data output signal A114 of the Joint Test Workgroup hardware interface, and the serial data output signal E154 of the last physical layer IP E150 is connected to the serial data input signal A112 of the Joint Test Workgroup hardware interface. Thus, the data paths corresponding to the serial data input signals and serial data output signals, and the control paths corresponding to the test clock signal and the controller state machine control signals are distinguished. In terms of data path planning, a cascaded topology is constructed between the same joint test workgroup bus control interface controller A110 and multiple physical layer IPs. Furthermore, in terms of control path planning, multiple physical layer IPs share the same automated test equipment and the test clock signal terminal A116 and controller state machine control signal terminal A118 of the joint test workgroup hardware interface. This not only supports serial cascading of multiple physical layer IPs according to the JTAG serial structure, but also supports multiple physical layer IPs sharing the same ATE test equipment and JTAG hardware structure. This allows multiple physical layer IPs to specify any physical layer IP as the destination via JTAG bypass instructions, initiating read and write access operations via JTAG. This design means that by sharing the same JTAG hardware interface and ATE equipment, ATE test flows can be implemented, including initialization flows and periodic checks of initialization completion status. For example, cascaded ATE tests of multiple physical layer IPs at the PIPE TOP level can be performed, or a built-in pseudo-random binary sequence (PRBS) generator can be used.

[0030] Figure 1The test apparatus shown for physical layer IP has the following improvements and beneficial technical effects: 1) Addressing the challenge of testing chips integrating multiple physical layer IPs using automated test equipment, it supports comprehensive test coverage from the first-level automated device test at the top of the physical layer hard core logic processing unit, to the second-level automated device test at the top of the physical layer, and to the third-level automated device test at the top of the PCIe physical interface. It can continuously expand from the inside out and also supports multiple physical layer IPs sharing a single ATE test device and the same board-level JTAG hardware interface. 2) Utilizing bypass instructions from the Joint Test Workgroup bus control interface controller, it supports serial cascading of multiple physical layer IPs according to the Joint Test Workgroup bus standard, and overcomes initialization and power-on detection problems caused by cascading different physical layer IPs. 3) Improvements to the ATE test process have been provided, significantly reducing the number and overhead of hardware resources for ATE test equipment and JTAG controllers, effectively reducing ATE test costs. It can cover a more complete range of levels and circuit units of the design under test, as well as a more complete logic chain path, significantly improving the completeness of comprehensive test items for different test dimensions of ATE test vectors and ATE test items for functional / performance / reliability testing.

[0031] In short, Figure 1 The test apparatus shown for physical layer IPs constructs a cascaded topology between multiple physical layer IPs using a single joint test workgroup bus control interface controller A110. Furthermore, by sharing the same automated test bench and the test clock signal terminal A116 and controller state machine control signal terminal A118 of the joint test workgroup hardware interface, the apparatus enables automated testing of each physical layer IP. Alternatively, bypass instructions can be used to select a specific physical layer IP as the destination to initiate read / write access operations. It supports adaptation to different physical layer IP core compositions, supports coverage of different layers, reduces the number and overhead of hardware resources for ATE test benches and JTAG controllers, effectively reducing ATE testing costs. It can cover a more complete range of layers and circuit units of the design under test, as well as a more complete logic chain path, improving the completeness of comprehensive test items across different test dimensions of ATE test vectors and ATE test items (functionality, performance, reliability testing), which is beneficial for matching the rapid iteration and verification needs of chip development.

[0032] Figure 2 This is a flowchart illustrating a method for automating the testing of multiple physical layer IPs one by one, as provided in an embodiment of this application. Figure 2 As shown, the method for automating testing of multiple physical layer IPs one by one includes the following steps.

[0033] Step S201: After a global reset, release the joint test workgroup interface of the joint test workgroup bus control interface controller.

[0034] Step S203: Initialize multiple physical layer IPs and ensure that all multiple physical layer IPs are powered on.

[0035] Step S205: According to the cascading order and topology routing relationship, starting from the first physical layer IP to the last physical layer IP, for each of the multiple physical layer IPs, set the power consumption state of the physical layer IP to exit from the default low power state and switch to the normal working state. Then, enable the built-in pseudo-random binary sequence generator and verifier of the physical layer IP for the first round of detection results.

[0036] Step S207: Based on the results of the first round of detection, configure the registers of each of the multiple physical layer IPs.

[0037] Step S209: According to the cascading order and topology routing relationship, starting from the first physical layer IP and ending at the last physical layer IP, enable the built-in pseudo-random binary sequence generator and verifier of each of the multiple physical layer IPs for the second round of detection results.

[0038] Step S211: Based on the results of the second round of testing, end the automated test.

[0039] Figure 2 The method described here for automating the testing of multiple physical layer IPs one by one supports serial cascading of multiple physical layer IPs according to the Joint Test Working Group bus standard, and overcomes initialization and power-on testing issues caused by cascading different physical layer IPs. It provides improvements to the ATE testing process, significantly reducing the number and overhead of hardware resources for ATE test equipment and JTAG controllers, effectively reducing ATE testing costs. It can cover a more complete range of levels and circuit units of the design under test, as well as a more complete logic chain path, significantly improving the completeness of the comprehensive test items across different test dimensions of ATE test vectors and ATE test items for functional / performance / reliability testing.

[0040] See Figure 1 and Figure 2In one possible implementation, the serial data output signal of the preceding physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the following physical layer IP. Furthermore, the serial data input signal of the first physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data output signal of the joint test workgroup hardware interface, and the serial data output signal of the last physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the joint test workgroup hardware interface. In this way, the data paths corresponding to the serial data input signal and the serial data output signal are distinguished, as well as the control paths corresponding to the test clock signal and the controller state machine control signal. In terms of data path planning, a cascaded topology is constructed between the same joint test workgroup bus control interface controller and multiple physical layer IPs. Furthermore, in terms of control path planning, multiple physical layer IPs share the same automated test platform and the test clock signal terminal and controller state machine control signal terminal of the joint test workgroup hardware interface. This not only supports serial cascading of multiple physical layer IPs according to the JTAG serial structure, but also supports multiple physical layer IPs sharing the same ATE test platform and JTAG hardware structure. This allows multiple physical layer IPs to specify any physical layer IP as the destination via JTAG bypass instructions, initiating read and write access operations via JTAG. This design means that by sharing the same JTAG hardware interface and ATE platform, ATE test flows can be implemented, including initialization flows and periodic checks of initialization completion status. Examples include cascaded ATE tests of multiple physical layer IPs at the PIPE TOP level, and the use of a built-in pseudo-random binary sequence generator.

[0041] In one possible implementation, the plurality of physical layer IPs each include at least a top-level physical layer hard core logic processing unit for first-level automated device testing. In another possible implementation, the plurality of physical layer IPs each also include a top-level physical layer for second-level automated device testing, wherein the top-level physical layer includes the top-level physical layer hard core logic processing unit and a soft core logic processing unit. In yet another possible implementation, the plurality of physical layer IPs each also include a top-level PCIe physical interface for third-level automated device testing, wherein the top-level PCIe physical interface includes the top-level physical layer and a physical coding sublayer. Thus, addressing the challenge of testing chips integrating multiple physical layer IPs with automated testing equipment, this solution supports comprehensive test coverage from first-level automated device testing at the top-level physical layer hard core logic processing unit, to second-level automated device testing at the top-level physical layer, and to third-level automated device testing at the top-level PCIe physical interface. This allows for continuous expansion from the inside out, and also supports multiple physical layer IPs sharing a single ATE test device, enabling them to share the same board-level JTAG hardware interface.

[0042] In one possible implementation, the Joint Test Workgroup Bus Control Interface Controller is configured to perform automated testing on the plurality of physical layer IPs one by one, including: globally resetting and then releasing the Joint Test Workgroup Interface Controller's Joint Test Workgroup interface; initializing the plurality of physical layer IPs and ensuring that all the plurality of physical layer IPs are powered on; according to the cascading order and topology routing relationship, starting from the first physical layer IP to the last physical layer IP, for each of the plurality of physical layer IPs, setting the power consumption state of that physical layer IP to exit from the default low power state and switch to the normal operating state, and then enabling the built-in pseudo-random binary sequence generator and verifier of that physical layer IP for the first round of detection results. In one possible implementation, the Joint Test Workgroup Bus Control Interface controller is configured to perform automated testing on the plurality of physical layer IPs one by one, further comprising: configuring the registers of each of the plurality of physical layer IPs based on the first round of detection results; enabling the built-in pseudo-random binary sequence generator and verifier of each of the plurality of physical layer IPs according to the cascading order and topology routing relationship, starting from the first physical layer IP and ending at the last physical layer IP, for the second round of detection results; and ending the automated test based on the second round of detection results. This supports serial cascading of multiple physical layer IPs according to the Joint Test Workgroup Bus standard and overcomes the initialization and power-on detection problems caused by cascading different physical layer IPs. It provides an improvement to the ATE test process, significantly reducing the number and overhead of hardware resources for ATE test equipment and JTAG controllers, effectively reducing ATE test costs, and enabling coverage of a more complete range of levels and circuit units of the design under test, as well as a more complete logic chain path. It significantly improves the completeness of the comprehensive test items across different test dimensions of ATE test vectors and ATE test items for functional / performance / reliability testing.

[0043] In one possible implementation, the Joint Test Workgroup Bus Control Interface (JTLI) controller is configured to use a bypass instruction to select a specified physical layer IP from the plurality of physical layer IPs as the destination to initiate a read / write access operation. This includes: the JTLI bus control interface controller bypassing all physical layer IPs preceding the specified physical layer IP according to the cascading order and topology routing relationship using the bypass instruction, thereby substantially connecting the serial data output signal terminal of the JTLI hardware interface to the serial data input signal terminal of the specified physical layer IP; and the JTLI bus control interface controller bypassing all physical layer IPs following the specified physical layer IP according to the cascading order and topology routing relationship using the bypass instruction, thereby substantially connecting the serial data output signal terminal of the specified physical layer IP to the serial data input signal terminal of the JTLI hardware interface. In this way, multiple physical layer IPs can be designated as the destination by using the JTAG bypass instruction, and read and write access operations can be initiated by JTAG. This utilizes the bypass instructions of the Joint Test Workgroup bus control interface controller, supports multiple physical layer IPs to be serially cascaded according to the Joint Test Workgroup bus standard, and can overcome the problems of initialization and power-on detection caused by cascading different physical layer IPs.

[0044] In one possible implementation, the Joint Test Workgroup bus control interface controller is configured to bypass other physical layer IPs among the plurality of physical layer IPs except for the designated physical layer IP using a bypass instruction. This results in the serial data output signal of the Joint Test Workgroup hardware interface being substantially connected to the serial data input signal of the designated physical layer IP, and vice versa. This provides an improvement to the ATE test process, significantly reducing the number and overhead of hardware resources for ATE test equipment and JTAG controllers, effectively reducing ATE test costs. It can cover a more complete range of levels and circuit units within the design under test (DUT) and a more complete logic chain path, significantly improving the completeness of the comprehensive test items across different test dimensions of ATE test vectors and ATE test items for functional / performance / reliability testing.

[0045] In one possible implementation, the testing apparatus is used for wafer die testing (CP testing) or post-packaged chip functional testing (FT). This supports automated testing of integrated circuit chips and semiconductor devices.

[0046] In one possible implementation, the plurality of physical layer IPs includes one or more system-on-a-chip (SoCs), and the plurality of physical layer IPs are PCIe physical layer intellectual property cores. This supports the integration of multiple physical layer IPs on a single chip, matching the increased integration and complexity of the chip.

[0047] Figure 3 This is a flowchart illustrating a testing method for physical layer IP provided in an embodiment of this application. Figure 3 As shown, the testing method for physical layer IP includes the following steps.

[0048] Step S301: Reset the joint test workgroup interface of the joint test workgroup bus control interface controller.

[0049] Step S303: Initialize multiple physical layer IPs and ensure that all multiple physical layer IPs are powered on.

[0050] Step S305: Perform automated testing on each of the multiple physical layer IPs one by one through the joint test workgroup bus control interface controller, or use bypass instructions to select a specific physical layer IP among the multiple physical layer IPs as the destination to initiate read and write access operations.

[0051] See Figure 3 The Joint Test Workgroup Bus Control Interface Controller includes a set of Joint Test Workgroup hardware interfaces. The Joint Test Workgroup hardware interface includes a serial data input signal terminal, a serial data output signal terminal, a test clock signal terminal, and a controller state machine control signal terminal. The multiple physical layer IPs are serially cascaded according to the Joint Test Workgroup bus standard. Furthermore, the multiple physical layer IPs share the same automated test bench and the test clock signal terminal and controller state machine control signal terminal of the Joint Test Workgroup hardware interface.

[0052] Figure 3The testing method for physical layer IP shown has the following improvements and beneficial technical effects: 1) Addressing the challenge of testing chips integrating multiple physical layer IPs using automated test equipment, it supports comprehensive test coverage from the first-level automated device test at the top of the physical layer hard core logic processing unit, to the second-level automated device test at the top of the physical layer, and to the third-level automated device test at the top of the PCIe physical interface. It can continuously expand from the inside out and also supports multiple physical layer IPs sharing a single ATE test device and the same board-level JTAG hardware interface. 2) Utilizing bypass instructions from the Joint Test Workgroup bus control interface controller, it supports serial cascading of multiple physical layer IPs according to the Joint Test Workgroup bus standard, and overcomes initialization and power-on detection problems caused by cascading different physical layer IPs. 3) Improvements to the ATE test process have been provided, significantly reducing the number and overhead of hardware resources for ATE test equipment and JTAG controllers, effectively reducing ATE test costs. It can cover a more complete range of levels and circuit units of the design under test, as well as a more complete logic chain path, significantly improving the completeness of comprehensive test items for different test dimensions of ATE test vectors and ATE test items for functional / performance / reliability testing.

[0053] In short, Figure 3 The testing method for physical layer IPs shown utilizes a cascaded topology between a single joint test workgroup bus control interface controller and multiple physical layer IPs. Furthermore, by sharing the same automated test bench and the test clock signal terminal and controller state machine control signal terminal of the joint test workgroup hardware interface among the multiple physical layer IPs, automated testing of each physical layer IP can be achieved. Alternatively, bypass instructions can be used to select a specific physical layer IP among the multiple physical layer IPs as the destination to initiate read / write access operations. This method supports adaptation to different physical layer IP core compositions, supports coverage of different layers, reduces the number and overhead of hardware resources for ATE test benches and JTAG controllers, effectively reducing ATE testing costs. It can cover a more complete range of layers and circuit units of the design under test, as well as a more complete logic chain path, improving the completeness of comprehensive test items across different test dimensions of ATE test vectors and ATE test items (functionality, performance, reliability testing), which is beneficial for matching the rapid iteration and verification needs of chip development.

[0054] See Figure 3In one possible implementation, the serial data output signal of the preceding physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the following physical layer IP. Furthermore, the serial data input signal of the first physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data output signal of the joint test workgroup hardware interface, and the serial data output signal of the last physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the joint test workgroup hardware interface. In this way, the data paths corresponding to the serial data input signal and the serial data output signal are distinguished, as well as the control paths corresponding to the test clock signal and the controller state machine control signal. In terms of data path planning, a cascaded topology is constructed between the same joint test workgroup bus control interface controller and multiple physical layer IPs. Furthermore, in terms of control path planning, multiple physical layer IPs share the same automated test platform and the test clock signal terminal and controller state machine control signal terminal of the joint test workgroup hardware interface. This not only supports serial cascading of multiple physical layer IPs according to the JTAG serial structure, but also supports multiple physical layer IPs sharing the same ATE test platform and JTAG hardware structure. This allows multiple physical layer IPs to specify any physical layer IP as the destination via JTAG bypass instructions, initiating read and write access operations via JTAG. This design means that by sharing the same JTAG hardware interface and ATE platform, ATE test flows can be implemented, including initialization flows and periodic checks of initialization completion status. Examples include cascaded ATE tests of multiple physical layer IPs at the PIPE TOP level, and the use of a built-in pseudo-random binary sequence generator.

[0055] In one possible implementation, the multiple physical layer IPs respectively include: a top-level physical layer hard core logic processing unit for first-level automated device testing, a top-level physical layer for second-level automated device testing, and a top-level PCIe physical interface for third-level automated device testing. The top-level physical layer includes the top-level physical layer hard core logic processing unit and a soft-core physical layer logic processing unit, and the top-level PCIe physical interface includes the top-level physical layer and a physical coding sublayer. Thus, addressing the challenge of testing chips integrating multiple physical layer IPs with automated testing equipment, this solution supports comprehensive test coverage from first-level automated device testing at the top-level physical layer hard core logic processing unit, to second-level automated device testing at the top-level physical layer, and to third-level automated device testing at the top-level PCIe physical interface. This allows for continuous expansion from the inside out, and also supports multiple physical layer IPs sharing a single ATE test device, enabling them to share the same board-level JTAG hardware interface.

[0056] In one possible implementation, the Joint Test Workgroup Bus Control Interface (JTAG) controller uses a bypass instruction to select a designated physical layer IP (PIP) from among the plurality of physical layer IPs as the destination to initiate read / write access operations. This includes: the JTAG JTAG bus control interface controller bypassing the other physical layer IPs (excluding the designated PIP) from the plurality of physical layer IPs using the bypass instruction. This results in the serial data output signal of the JTAG hardware interface being substantially connected to the serial data input signal of the designated PIP, and vice versa. This allows multiple physical layer IPs to specify any one PIP as the destination via JTAG bypass instructions, enabling read / write access operations to be initiated via JTAG. This utilizes the bypass instructions of the JTAG JTAG bus control interface controller, supports serial cascading of multiple physical layer IPs according to the JTAG bus standard, and overcomes initialization and power-on detection issues caused by cascading different physical layer IPs.

[0057] Figure 4This is a schematic diagram of a computing device 400 provided in an embodiment of this application. The computing device 400 includes one or more processors 410, a communication interface 420, and a memory 430. The processors 410, communication interface 420, and memory 430 are interconnected via a bus 440. Optionally, the computing device 400 may further include an input / output interface 450, which is connected to input / output devices for receiving user-set parameters, etc. The computing device 400 can be used to implement some or all of the functions of the device embodiment or system embodiment described above in this application; the processor 410 can also be used to implement some or all of the operation steps of the method embodiment described above in this application. For example, the specific implementation of various operations performed by the computing device 400 can be referred to the specific details in the above embodiments, such as the processor 410 being used to execute some or all of the steps or operations in the above method embodiments. For example, in the embodiments of this application, the computing device 400 can be used to implement some or all of the functions of one or more components in the above-described device embodiments. In addition, the communication interface 420 can be used specifically for communication functions necessary to implement the functions of these devices and components, and the processor 410 can be used specifically for processing functions necessary to implement the functions of these devices and components.

[0058] It should be understood that, Figure 4 The computing device 400 may include one or more processors 410, and the multiple processors 410 may collaboratively provide processing power in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or an arbitrary connection mode; or the multiple processors 410 may form a processor sequence or a processor array; or the multiple processors 410 may be divided into a main processor and an auxiliary processor; or the multiple processors 410 may have different architectures, such as adopting a heterogeneous computing architecture. Furthermore, Figure 4 The structural and functional descriptions of the computing device 400 shown are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include... Figure 4 The diagram shows more or fewer components, or combinations of some components, or splitting of some components, or different arrangements of components.

[0059] The processor 410 can have various specific implementations. For example, it can include one or more combinations of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a tensor processing unit (TPU), or a data processing unit (DPU). This application embodiment does not impose specific limitations. The processor 410 can also be a single-core or multi-core processor. The processor 410 can be a combination of a CPU and hardware chips. The aforementioned hardware chips can be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The aforementioned PLDs can be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof. The processor 410 can also be implemented using logic devices with built-in processing logic, such as FPGAs or digital signal processors (DSPs). The communication interface 420 can be a wired interface or a wireless interface, used to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless LAN interface, etc.

[0060] Memory 430 may be non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 430 may also be volatile memory, which may be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 430 can also be used to store program code and data, so that the processor 410 can call the program code stored in the memory 430 to execute some or all of the operation steps in the above method embodiments, or to execute the corresponding functions in the above device embodiments. Furthermore, the computing device 400 may include, compared to... Figure 4 The number of components displayed may be more or less, or there may be different component configurations.

[0061] Bus 440 can be a Peripheral Component Interconnect Express (PCIe) bus, or an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. Bus 440 can be divided into address bus, data bus, control bus, etc. In addition to the data bus, bus 440 can also include a power bus, control bus, and status signal bus. However, for clarity, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0062] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computing devices, the structure of each computing device of which can refer to the structure of the computing devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0063] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0064] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless network communication, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0065] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0066] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A testing apparatus for physical layer IP, characterized in that, The testing apparatus includes a Joint Test Workgroup Bus Control Interface (JTWCI) controller. The JTWCI controller includes a set of JTWCI hardware interfaces, each including a serial data input signal terminal, a serial data output signal terminal, a test clock signal terminal, and a controller state machine control signal terminal. Multiple physical layer IPs are serially cascaded according to the JTWCI bus standard. These multiple physical layer IPs share the same automated testing platform and the test clock signal terminal and controller state machine control signal terminal of the JTWCI hardware interfaces. The JTWCI controller is configured to: perform automated testing on each of the multiple physical layer IPs one by one; or, use bypass instructions to select a specific physical layer IP from the multiple physical layer IPs as the destination to initiate read / write access operations.

2. The testing apparatus according to claim 1, characterized in that, The serial data output signal of the preceding physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the following physical layer IP. Furthermore, the serial data input signal of the first physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data output signal of the joint test workgroup hardware interface. The serial data output signal of the last physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the joint test workgroup hardware interface.

3. The testing apparatus according to claim 1, characterized in that, The plurality of physical layer IPs each include at least a physical layer hard core logic processing unit. The top layer is used for testing of the first-level automated device.

4. The testing apparatus according to claim 3, characterized in that, The plurality of physical layer IPs also include a physical layer top layer for second-level automated device testing, wherein the physical layer top layer includes the physical layer hard core logic processing unit top layer and the physical layer soft core logic processing unit.

5. The testing apparatus according to claim 4, characterized in that, The plurality of physical layer IPs also include a top-level PCIe physical interface for third-level automated device testing, wherein the top-level PCIe physical interface includes the top-level physical layer and the physical coding sublayer.

6. The testing apparatus according to claim 2, characterized in that, The joint test workgroup bus control interface controller is configured to perform automated testing on each of the multiple physical layer IPs, including: After a global reset, release the joint test workgroup interface of the joint test workgroup bus control interface controller. Initialize the plurality of physical layer IPs and ensure that all of the plurality of physical layer IPs are powered on; According to the cascading order and topology routing relationship, starting from the first physical layer IP and continuing to the last physical layer IP, for each of the multiple physical layer IPs, the power consumption state of that physical layer IP is set to exit from the default low power state and switch to the normal working state. Then, the built-in pseudo-random binary sequence generator and verifier of that physical layer IP are enabled for the first round of detection results.

7. The testing apparatus according to claim 6, characterized in that, The joint test workgroup bus control interface controller is configured to perform automated testing on each of the multiple physical layer IPs, and also includes: Based on the results of the first round of detection, configure the registers of each of the multiple physical layer IPs; According to the cascading order and topology routing relationship, starting from the first physical layer IP and ending at the last physical layer IP, for each of the multiple physical layer IPs, enable the built-in pseudo-random binary sequence generator and verifier of that physical layer IP for the second round of detection results; Based on the results of the second round of testing, the automated test ends.

8. The testing apparatus according to claim 2, characterized in that, The joint test workgroup bus control interface controller is configured to use bypass instructions to select a specified physical layer IP from the plurality of physical layer IPs as the destination to initiate read / write access operations, including: The joint test workgroup bus control interface controller uses bypass instructions to bypass all physical layer IPs before the specified physical layer IP according to the cascading order and topology routing relationship, thereby making the serial data output signal terminal of the joint test workgroup hardware interface substantially connected to the serial data input signal terminal of the specified physical layer IP. The joint test workgroup bus control interface controller uses bypass instructions to bypass all physical layer IPs following the specified physical layer IP according to the cascading order and topology routing relationship, thereby making the serial data output signal terminal of the specified physical layer IP substantially connected to the serial data input signal terminal of the joint test workgroup hardware interface.

9. The testing apparatus according to claim 2, characterized in that, The Joint Test Workgroup bus control interface controller is configured to bypass other physical layer IPs among the plurality of physical layer IPs except for the specified physical layer IP using a bypass instruction, thereby making the serial data output signal terminal of the Joint Test Workgroup hardware interface substantially connected to the serial data input signal terminal of the specified physical layer IP, and making the serial data output signal terminal of the specified physical layer IP substantially connected to the serial data input signal terminal of the Joint Test Workgroup hardware interface.

10. The testing apparatus according to claim 1, characterized in that, The testing device is used for testing bare wafer dies or for testing the complete functionality of packaged chips.

11. The testing apparatus according to claim 1, characterized in that, The plurality of physical layer IPs include one or more system-on-a-chips, and the plurality of physical layer IPs are PCIe physical layer intellectual property cores.

12. A testing method for physical layer IP, characterized in that, The testing method includes: Reset the joint test workgroup interface of the joint test workgroup bus control interface controller; Initialize multiple physical layer IPs and ensure that all of the multiple physical layer IPs are powered on; The joint test workgroup bus control interface controller can be used to perform automated testing on each of the multiple physical layer IPs, or a bypass instruction can be used to select a specific physical layer IP from the multiple physical layer IPs as the destination to initiate read / write access operations. The Joint Test Workgroup Bus Control Interface Controller includes a set of Joint Test Workgroup hardware interfaces. Each Joint Test Workgroup hardware interface includes a serial data input signal terminal, a serial data output signal terminal, a test clock signal terminal, and a controller state machine control signal terminal. The multiple physical layer IPs are serially cascaded according to the Joint Test Workgroup bus standard. Furthermore, the multiple physical layer IPs share the same automated test bench and the test clock signal terminal and controller state machine control signal terminal of the Joint Test Workgroup hardware interface.

13. The method according to claim 12, characterized in that, The serial data output signal of the preceding physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the following physical layer IP. Furthermore, the serial data input signal of the first physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data output signal of the joint test workgroup hardware interface. The serial data output signal of the last physical layer IP in the plurality of physical layer IPs, according to the cascading order and topology routing relationship, is connected to the serial data input signal of the joint test workgroup hardware interface.

14. The method according to claim 13, characterized in that, The plurality of physical layer IPs respectively include: a physical layer hard core logic processing unit top layer for first-level automated device testing, a physical layer top layer for second-level automated device testing, and a PCIe physical interface top layer for third-level automated device testing, wherein the physical layer top layer includes the physical layer hard core logic processing unit top layer and the physical layer soft core logic processing unit, and the PCIe physical interface top layer includes the physical layer top layer and the physical coding sublayer.

15. The method according to claim 13, characterized in that, Through the joint test workgroup bus control interface controller, using bypass instructions, a specified physical layer IP from among the multiple physical layer IPs is selected as the destination to initiate a read / write access operation, including: The joint test workgroup bus control interface controller uses a bypass instruction to bypass other physical layer IPs among the plurality of physical layer IPs except for the specified physical layer IP, thereby making the serial data output signal terminal of the joint test workgroup hardware interface substantially connected to the serial data input signal terminal of the specified physical layer IP, and making the serial data output signal terminal of the specified physical layer IP substantially connected to the serial data input signal terminal of the joint test workgroup hardware interface.

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