Built-in test system based on AXI interface

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a built-in test system based on an AXI interface, the system performs data path test through a test master module and a test slave module in an AXI test module, the test master module takes over a data path sent to a downstream module, and the test slave module takes over the data path sent to the downstream module. Target request information can be actively generated by the test master module, a data path sent to the upstream module is taken over by the test slave module, and target return information can be passively generated by the test slave module according to the target request information sent by the upstream module; therefore, a data path between the upstream module and the downstream module is divided into a data path from the upstream module to the test slave module and a data path from the test master module to the downstream module, the fine granularity of data path fault positioning is improved, the fault position of the data path can be quickly positioned, the transmission state information of the data stream can be monitored, and the fault positioning accuracy is improved. And the validity of the data path test is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a built-in test system based on the AXI interface. Background Technology

[0002] Currently, computing power has become a driving force for the development of the digital economy, and with the increasing demand for data computation, GPU chips have become an important component of computing infrastructure. However, due to the complexity and large scale of GPU chips, post-silicon verification of GPU chips has always been a pain point.

[0003] Existing Design for Test (DFT) technologies primarily target SRAM / DDR memory, JTAG, and SERDES high-speed interfaces, with relatively mature technologies and standards. However, testing methods for data paths are relatively outdated, making it difficult to effectively locate fault points and perform fault analysis.

[0004] Therefore, improving the effectiveness of data path testing has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows: A built-in testing system based on the AXI interface, the system comprising: an AXI testing module, wherein the AXI testing module includes a test master module and a test slave module, and the AXI testing module is connected to an upstream module and a downstream module; The main test module is used to generate target request information and send the target request information generated by the main test module to the downstream module; The main test module is also used to receive target return information sent by the downstream module; The test module is used to receive target request information sent by the upstream module; The test module is also used to generate target return information based on the target request information sent by the upstream module, and send the target return information generated by the test module to the upstream module.

[0006] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the built-in testing system based on the AXI interface provided by the present invention achieves considerable technological advancement and practicality, and has broad industrial application value. It has at least the following advantages: This invention utilizes a master test module and a slave test module within the AXI test module to perform data path testing. The master test module takes over the data path to downstream modules and can actively generate target request information. The slave test module takes over the data path to upstream modules and can passively generate target return information based on the target request information sent by the upstream modules. This divides the data path between upstream and downstream modules into a data path from the upstream module to the slave test module and a data path from the master test module to the downstream modules. This improves the granularity of data path fault location, facilitates rapid location of data path faults, and enables monitoring of data flow transmission status information, thereby enhancing the effectiveness of data path testing. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A schematic diagram of the structure of a built-in test system based on an AXI interface provided in an embodiment of the present invention; Figure 2 A schematic diagram of the architecture of the main test module in a built-in test system based on the AXI interface provided in an embodiment of the present invention; Figure 3 This is a flowchart illustrating the testing process of the main testing module in a built-in testing system based on an AXI interface, as provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the architecture of a test slave module in a built-in test system based on an AXI interface, provided in an embodiment of the present invention. Detailed Implementation

[0009] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] This embodiment provides a built-in testing system based on the AXI interface. See [link to documentation]. Figure 1This is a schematic diagram of a built-in test system based on the AXI interface provided in an embodiment of the present invention. The system includes an AXI test module, wherein the AXI test module includes a test master module and a test slave module, and the AXI test module is connected to an upstream module and a downstream module. The main test module is used to generate target request information and send the target request information generated by the main test module to the downstream module; The main test module is also used to receive target return information sent by the downstream module; The test module is used to receive target request information sent by the upstream module; The test module is also used to generate target return information based on the target request information sent by the upstream module, and send the target return information generated by the test module to the upstream module.

[0011] In this context, the upstream module can be a module that sends target request information to the downstream module, and the downstream module can be a module that sends target return information to the upstream module. In one application scenario, the upstream module and the downstream module can be two interconnected GPU chips.

[0012] The target request information is used to instruct read and write operations to be performed on the downstream module, and the target return information is used to indicate the response to the read and write operations of the upstream module.

[0013] Specifically, implementers can determine the path test results from the main test module to the downstream module based on whether the target request information generated by the main test module is received by the corresponding target return information sent by the downstream module, whether the target return information corresponding to the target request information sent by the downstream module is correct, and whether the delay in receiving the target return information corresponding to the target request information sent by the downstream module is less than a preset delay threshold.

[0014] The implementer can determine the path test results from the upstream module to the test module based on whether the target request information from the upstream module has been received by the corresponding target return information sent by the test module, whether the target return information corresponding to the target request information sent by the test module is correct, and whether the delay in receiving the target return information corresponding to the target request information sent by the test module is less than a preset delay threshold.

[0015] It should be noted that the test module can generate abnormal target return information to perform abnormal testing from the upstream module to the test module according to the implementer's needs. The test sub-module can generate abnormal target request information to perform abnormal testing from the test master module to the downstream module according to the implementer's needs. It can be seen that the functions of the AXI test module provided in this embodiment can be expanded according to the actual needs of the implementer.

[0016] In one specific implementation, the target request information includes an address write request, a data write request, and an address read request.

[0017] Among them, an address write request can refer to a request to write the currently pending data to the target address of the downstream module, a data write request can refer to a request to write the specified pending data to the downstream module, and an address read request can refer to a request to read data from the target address of the downstream module.

[0018] In one specific implementation, the test main module generates the address write request or the address read request according to the first configuration information, wherein the first configuration information includes at least address information, request identification information, continuous transmission count, transmission byte width, transmission type and user-defined information; The test main module generates the data write request based on the second configuration information, wherein the second configuration information includes at least the data to be written.

[0019] The address information can refer to the target address of the read or write operation in the downstream module. The request identifier information can be used to determine which request the current request is, in order to support application scenarios of out-of-order transmission of multiple requests. The number of consecutive transmission cycles can refer to the number of Burst transmission cycles required for the current request. The transmission byte width can refer to the number of data bytes transmitted in each Burst cycle, that is, the number of data bytes of a single data packet that needs to be transmitted continuously. The transmission type can refer to the Burst transmission type, which is used to specify the address growth mode of the Burst transmission. The Burst transmission type can include fixed address type, incremental address type and rollback address type. In the GPU chip scenario, incremental address type or rollback address type is usually used.

[0020] User-defined information can refer to a set of custom signals reserved by the AXI protocol, used to transmit additional control or status information not defined by the protocol. For example, user-defined information may include priority information, data type information, security permission information, etc.

[0021] The data to be written can be configured by the implementer to a fixed value. In one implementation, the data to be written can also be configured with a pseudo-random code seed to generate it randomly.

[0022] In one specific implementation, the target return information includes write response information and read data information.

[0023] The write response information can refer to the response information after the address write request or data write request has been processed, while the read data information can refer to the response information after reading data according to the address read request. In general, the read data information is the data read according to the address read request.

[0024] In one specific implementation, the test module generates the write response information based on the address write request or data write request received from the upstream module and the third configuration information, wherein the third configuration information includes at least response information and user-defined information; The test main module generates the read data information based on the address read request received from the upstream module and the fourth configuration information, wherein the fourth configuration information includes at least the data to be read, response information, and user-defined information.

[0025] The response information can refer to the response information after the corresponding request has been processed, and the data to be read can refer to the data corresponding to the target address in the address read request.

[0026] In one specific implementation, the test main module includes a first register submodule, an address write channel control submodule, a data write channel control submodule, an address read channel control submodule, a write response channel sampling submodule, and a read data channel sampling submodule; The address write channel control submodule is used to generate an address write request based on the first configuration information and send the generated address write request to the downstream module; The address write channel control submodule includes a first timer and a first counter. The first timer is used to count the transmission time of each address write request, and the first counter is used to count the number of address write requests sent. The data write channel control submodule is used to generate a data write request according to the second configuration information and send the generated data write request to the downstream module; The data write channel control submodule includes a second timer and a second counter. The second timer is used to count the transmission duration of each data write request, and the second counter is used to count the number of address write requests and the number of bytes sent. The address read channel control submodule is used to generate an address read request based on the first configuration information and send the generated address read request to the downstream module; The address read channel control submodule includes a third timer and a third counter. The third timer is used to count the transmission time of each address read request, and the third counter is used to count the number of address read requests sent. The write response channel sampling submodule is used to sample the response information and user-defined information sent by the downstream module to obtain the write response information; The write response channel sampling submodule includes a fourth timer and a fourth counter. The fourth timer is used to count the reception time of each write response message, and the fourth counter is used to count the number of received write response messages. The read data channel sampling submodule is used to sample the data to be read, response information and user-defined information sent by the downstream module to obtain read data information; The read data channel sampling submodule includes a fifth timer and a fifth counter. The fifth timer is used to count the reception duration of each read data message, and the fifth counter is used to count the number of read data messages received. The first register submodule is used to store statistical data of the address write channel control submodule, the data write channel control submodule, the address read channel control submodule, the write response channel sampling submodule, and the read data channel sampling submodule.

[0027] The sending duration can refer to the time elapsed from the sending of the first request or message to the sending of the last request or message.

[0028] Reception duration can refer to the time elapsed from receiving the first request or message to receiving the last request or message.

[0029] See Figure 2 This is a schematic diagram of the architecture of the main test module in a built-in test system based on the AXI interface, provided by an embodiment of the present invention.

[0030] Specifically, the test master module and the test slave module each have an enable mode. Under normal circumstances, only one of the test master module and the test slave module is enabled at any given time.

[0031] When it is necessary to test the data path from the test master module to the downstream module, the data path from the test master module to the downstream module is first initialized. For example, after the link training on the PCIe link is completed, the link is established and runs to the preset target rate.

[0032] Then enable the main test module to block the normal data flow from the upstream module to the downstream module.

[0033] Then configure the information based on the required read and write requests, as well as the number of read and write test requests.

[0034] Restart the test. During the test, poll the counters of the write response channel sampling submodule and the read data channel sampling submodule until the value of the fourth counter of the write response channel sampling submodule is the same as the configured number of write test requests, and the value of the fifth counter of the read data channel sampling submodule is the same as the configured number of read test requests. If the value of the fourth counter of the write response channel sampling submodule is not the same as the configured number of write test requests, and the value of the fifth counter of the read data channel sampling submodule is not the same as the configured number of read test requests by the target time point, it can be indicated that there is a fault in the data path from the test main module to the downstream module. The target time point can be determined based on the start time of the test and the preset duration threshold.

[0035] See Figure 3 This is a flowchart illustrating the testing process of the main testing module in a built-in testing system based on an AXI interface, as provided in an embodiment of the present invention. The information configuration in the diagram refers to configuring information based on the required read and write requests, and configuring the number of read and write test requests. Counter reading refers to polling and reading the counters of the write response channel sampling submodule and the read data channel sampling submodule. Condition judgment refers to determining whether the value of the fourth counter in the write response channel sampling submodule is the same as the configured number of write test requests, and whether the value of the fifth counter in the read data channel sampling submodule is the same as the configured number of read test requests.

[0036] It should be noted that the statistical data stored in the registers includes the timer statistics, counter statistics, and the content of specific requests or information for the corresponding submodules, that is, the transmission status information of the data stream. The transmission status information of the data stream can represent the performance information, latency information, etc. of the data stream. Implementers can analyze parameters such as bandwidth and latency based on the statistical data stored in the registers to improve the efficiency of fault analysis. For example, the ratio of the number of bytes corresponding to the write request to the final statistical value of the fourth timer can be used as the write data bandwidth, and the ratio of the number of bytes corresponding to the read request to the final statistical value of the fifth timer can be used as the read data bandwidth.

[0037] When the downstream module is a peer GPU chip, and the peer GPU chip uses a pseudo-random code seed to randomly generate the data to be read at the target address, the GPU chip deployed at the AXI test port can perform pseudo-random code verification on the data to be read. When the downstream module is a storage expansion module, and the GPU chip deployed at the AXI test port uses a pseudo-random code seed to randomly generate the data to be read and write it to the target address in the storage expansion module, the GPU chip deployed at the AXI test port can read the data at the target address and perform pseudo-random code verification.

[0038] In one specific implementation, the test module includes a second register submodule, a write response channel control submodule, a read data channel control submodule, an address write channel sampling submodule, a data write channel sampling submodule, and an address read channel sampling submodule; The write response channel control submodule is used to generate write response information based on the address write request or data write request received from the upstream module and the third configuration information, and send the generated write response information to the upstream module. The write response channel control submodule includes a sixth timer and a sixth counter. The sixth timer is used to count the transmission time of each write response message, and the sixth counter is used to count the number of write response messages sent. The read data channel control submodule is used to generate read data information based on the address write request or data write request received from the upstream module and the fourth configuration information, and send the generated read data information to the upstream module. The read data channel control submodule includes a seventh timer and a seventh counter. The seventh timer is used to count the transmission duration of each read data message, and the seventh counter is used to count the number of read data messages and the number of bytes transmitted. The address write channel sampling submodule is used to sample the address information, request identification information, number of consecutive transmissions, transmission byte width, transmission type and user-defined information sent by the upstream module to obtain the address write request; The address write channel sampling submodule includes an eighth timer and an eighth counter. The eighth timer is used to count the reception duration of each address write request, and the eighth counter is used to count the number of address write requests received. The data write channel sampling submodule is used to sample the data to be written sent by the upstream module to obtain a data write request; The data write channel sampling submodule includes a ninth timer and a ninth counter. The ninth timer is used to count the reception duration of each data write request, and the ninth counter is used to count the number of data write requests received.

[0039] The address read channel sampling submodule is used to sample the address information, request identifier information, number of consecutive transmissions, transmission byte width, transmission type and user-defined information sent by the upstream module to obtain the address read request; The address read channel sampling submodule includes a tenth timer and a tenth counter. The tenth timer is used to count the reception duration of each address read request, and the tenth counter is used to count the number of address read requests received. The second register submodule is used to store statistical data of the write response channel control submodule, the read data channel control submodule, the address write channel sampling submodule, the data write channel sampling submodule, and the address read channel sampling submodule.

[0040] See Figure 4 This is a schematic diagram of the architecture of a test slave module in a built-in test system based on an AXI interface, provided by an embodiment of the present invention.

[0041] When it is necessary to test the data path from the upstream module to the test slave module, the data path from the upstream module to the test slave module is first initialized. For example, after the link training on the PCIe link is completed, the link is established and runs to the preset target rate.

[0042] Then enable the test module to block the normal data flow from the upstream module to the downstream module.

[0043] Then, configure the information based on the read and write requests that need to be responded to from the upstream module during the test, as well as the number of read test requests and write test requests, and then start the test.

[0044] In one specific implementation, the AXI test module further includes a monitor module; The monitor module is used to monitor the data path from the upstream module to the downstream module when the test master module and the test slave module are not enabled, and to obtain the non-test path monitoring results.

[0045] When neither the test master module nor the test slave module is enabled, the data path from the upstream module to the downstream module is normal, and the monitor module can use two monitoring modes to obtain the monitoring results of the non-test path.

[0046] Specifically, the first monitoring mode is based on specific identification information. After monitoring is triggered, the communication information corresponding to the specific identification information is timed and counted. The communication information may include read / write requests and corresponding response information.

[0047] The second monitoring mode is based on the configured number of communication messages. After monitoring is triggered, it times and counts all communication messages in the data path until the configured number of communication messages is met.

[0048] Through the monitor module, the AXI test module can not only test the data path from the upstream module to the AXI test module and from the AXI test module to the downstream module in segments, but also monitor the data path from the upstream module to the downstream module. It can be seen that the AXI test module in this embodiment can be applied not only to the post-silicon testing scenario of chips after small-scale tape-out, but also to the chip application scenario after large-scale production.

[0049] In this embodiment, data path testing is performed using the test master module and test slave module in the AXI test module. The test master module takes over the data path sent to the downstream module and can actively generate target request information. The test slave module takes over the data path sent to the upstream module and can passively generate target return information based on the target request information sent by the upstream module. This divides the data path between the upstream and downstream modules into the data path from the upstream module to the test slave module and the data path from the test master module to the downstream module, improving the granularity of data path fault location, facilitating rapid location of data path faults, and enabling monitoring of data flow transmission status information, thereby improving the effectiveness of data path testing.

[0050] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A built-in testing system based on an AXI interface, characterized in that, The system includes an AXI testing module, wherein the AXI testing module includes a master testing module and a slave testing module, and the AXI testing module is connected to an upstream module and a downstream module; The main test module is used to generate target request information and send the target request information generated by the main test module to the downstream module; The main test module is also used to receive target return information sent by the downstream module; The test module is used to receive target request information sent by the upstream module; The test module is also used to generate target return information based on the target request information sent by the upstream module, and send the target return information generated by the test module to the upstream module.

2. The built-in test system based on the AXI interface according to claim 1, characterized in that, The target request information includes address write requests, data write requests, and address read requests.

3. The built-in test system based on the AXI interface according to claim 2, characterized in that, The test main module generates the address write request or the address read request according to the first configuration information, wherein the first configuration information includes at least address information, request identification information, number of consecutive transmission cycles, transmission byte width, transmission type and user-defined information; The test main module generates the data write request based on the second configuration information, wherein the second configuration information includes at least the data to be written.

4. The built-in test system based on the AXI interface according to claim 3, characterized in that, The target returned information includes write response information and read data information.

5. The built-in test system based on the AXI interface according to claim 4, characterized in that, The test module generates the write response information based on the address write request or data write request received from the upstream module and the third configuration information, wherein the third configuration information includes at least response information and user-defined information; The test main module generates the read data information based on the address read request received from the upstream module and the fourth configuration information, wherein the fourth configuration information includes at least the data to be read, response information, and user-defined information.

6. The built-in test system based on the AXI interface according to claim 5, characterized in that, The main test module includes a first register submodule, an address write channel control submodule, a data write channel control submodule, an address read channel control submodule, a write response channel sampling submodule, and a read data channel sampling submodule; The address write channel control submodule is used to generate an address write request based on the first configuration information and send the generated address write request to the downstream module; The address write channel control submodule includes a first timer and a first counter. The first timer is used to count the transmission time of each address write request, and the first counter is used to count the number of address write requests sent. The data write channel control submodule is used to generate a data write request according to the second configuration information and send the generated data write request to the downstream module; The data write channel control submodule includes a second timer and a second counter. The second timer is used to count the transmission duration of each data write request, and the second counter is used to count the number of address write requests and the number of bytes sent. The address read channel control submodule is used to generate an address read request based on the first configuration information and send the generated address read request to the downstream module; The address read channel control submodule includes a third timer and a third counter. The third timer is used to count the transmission duration of each address read request, and the third counter is used to count the number of address read requests sent. The write response channel sampling submodule is used to sample the response information and user-defined information sent by the downstream module to obtain the write response information; The write response channel sampling submodule includes a fourth timer and a fourth counter. The fourth timer is used to count the reception time of each write response message, and the fourth counter is used to count the number of received write response messages. The read data channel sampling submodule is used to sample the data to be read, response information and user-defined information sent by the downstream module to obtain read data information; The read data channel sampling submodule includes a fifth timer and a fifth counter. The fifth timer is used to count the reception duration of each read data message, and the fifth counter is used to count the number of read data messages received. The first register submodule is used to store statistical data of the address write channel control submodule, the data write channel control submodule, the address read channel control submodule, the write response channel sampling submodule, and the read data channel sampling submodule.

7. The built-in test system based on the AXI interface according to claim 5, characterized in that, The test module includes a second register submodule, a write response channel control submodule, a read data channel control submodule, an address write channel sampling submodule, a data write channel sampling submodule, and an address read channel sampling submodule; The write response channel control submodule is used to generate write response information based on the address write request or data write request received from the upstream module and the third configuration information, and send the generated write response information to the upstream module. The write response channel control submodule includes a sixth timer and a sixth counter. The sixth timer is used to count the transmission time of each write response message, and the sixth counter is used to count the number of write response messages sent. The read data channel control submodule is used to generate read data information based on the address write request or data write request received from the upstream module and the fourth configuration information, and send the generated read data information to the upstream module. The read data channel control submodule includes a seventh timer and a seventh counter. The seventh timer is used to count the transmission duration of each read data message, and the seventh counter is used to count the number of read data messages and the number of bytes transmitted. The address write channel sampling submodule is used to sample the address information, request identifier information, number of consecutive transmissions, transmission byte width, transmission type and user-defined information sent by the upstream module to obtain the address write request; The address write channel sampling submodule includes an eighth timer and an eighth counter. The eighth timer is used to count the reception duration of each address write request, and the eighth counter is used to count the number of address write requests received. The data write channel sampling submodule is used to sample the data to be written sent by the upstream module to obtain a data write request; The data write channel sampling submodule includes a ninth timer and a ninth counter. The ninth timer is used to count the reception duration of each data write request, and the ninth counter is used to count the number of data write requests received. The address read channel sampling submodule is used to sample the address information, request identifier information, number of consecutive transmissions, transmission byte width, transmission type and user-defined information sent by the upstream module to obtain the address read request; The address read channel sampling submodule includes a tenth timer and a tenth counter. The tenth timer is used to count the reception duration of each address read request, and the tenth counter is used to count the number of address read requests received. The second register submodule is used to store statistical data of the write response channel control submodule, the read data channel control submodule, the address write channel sampling submodule, the data write channel sampling submodule, and the address read channel sampling submodule.

8. The built-in test system based on the AXI interface according to claim 1, characterized in that, The AXI test module also includes a monitor module; The monitor module is used to monitor the data path from the upstream module to the downstream module when the test master module and the test slave module are not enabled, and to obtain the non-test path monitoring results.

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