Maximum delay calculation method and device and computer readable storage medium

Abstract

The invention provides a maximum delay calculation method and device and a computer readable storage medium, relates to the technical field of integrated circuits, and is used for solving the problem of how to improve the efficiency and precision of analyzing the maximum delay time of an integrated circuit. The computing method comprises: providing a circuit comprising a victim network and a plurality of aggressor networks; selecting one of a plurality of output nodes of the victim network as a representative node, and obtaining the maximum delay time of the representative node; according to the maximum delay time, obtaining initial maximum delay time of each output node except the representative node; the representative node is updated at least once, in each update, an output node is selected from the output nodes which are not used as the representative node from beginning to serve as the representative node, and the maximum delay time of the updated representative node is obtained; and according to the updated maximum delay time of the representative node, obtaining the maximum delay time of each output node which is not used as the representative node. The calculation method can be used for timing sequence verification of an integrated circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for calculating the maximum delay of a circuit, a computing device, and a computer-readable storage medium. Background Technology

[0002] In the design verification of semiconductor integrated circuits, it is necessary to verify whether the integrated circuit exhibits timing violations at a given frequency, thus preventing it from operating correctly. This is a necessary step before the integrated circuit is put into manufacturing. This verification requires analyzing the worst delay time of the relevant circuit nodes within the integrated circuit.

[0003] Maximum delay time analysis can be applied to signal integrity (SI) analysis within static timing analysis (STA). Through STA-SI analysis, optimization tools can use the results as guiding data to identify performance bottlenecks in the circuit. Through multiple rounds of analysis and optimization, they can achieve better-performing semiconductor integrated circuit designs. Furthermore, before semiconductor integrated circuits are fabricated, a full critical path analysis can be performed to ensure that the timing of each critical path meets fabrication standards, guaranteeing post-fabrication performance quality.

[0004] With the rapid development of semiconductor technology, the feature size of electronic components in semiconductor integrated circuits and the distance between adjacent electronic components have been further reduced, and the number of electronic components in semiconductor integrated circuits is also increasing. Existing technologies for analyzing maximum delay time are insufficient to meet the requirements of efficiency and accuracy, necessitating new methods for analyzing maximum delay time. Summary of the Invention

[0005] This application provides a maximum delay calculation method, computing device, computer-readable storage medium, and computer program product to address the problem of how to improve the efficiency and accuracy of maximum delay time analysis of integrated circuits.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a method for calculating the maximum delay of a circuit, the method comprising:

[0008] The system provides a circuit to be analyzed, comprising a victim network and multiple aggressor networks coupled to the victim network. The victim network includes input nodes and multiple output nodes. The system selects one of the output nodes as a representative node and obtains the maximum delay time of the representative node. Based on the maximum delay time, it obtains the initial maximum delay time of each output node other than the representative node. The system updates the representative node at least once. In each update, it selects one output node from those that were not initially designated as a representative node and obtains the maximum delay time of the updated representative node. Based on the maximum delay time of the updated representative node, it obtains the initial maximum delay time of each output node other than the current representative node. Finally, it obtains the maximum value among the multiple initial maximum delay times of each output node other than all representative nodes and uses this maximum value as the maximum delay time of the output node.

[0009] During the calculation, a representative node is selected, and its maximum latency is obtained. This maximum latency is then used to determine the initial maximum latency of all output nodes except the current representative node. Subsequently, the selected representative node is updated, and after each update, the maximum latency of the representative node and the initial maximum latency of all output nodes are obtained. Thus, by updating the representative node, the maximum latency of the representative node can be obtained. The initial maximum latency of each output node that was not initially selected as a representative node can be obtained multiple times, and the maximum value of these multiple initial maximum latency values ​​is used as the maximum latency of that output node. This allows for the calculation of only a subset of output nodes to obtain the maximum latency of all output nodes, improving the efficiency of obtaining the maximum latency. Furthermore, since the initial maximum latency of each output node that was not initially selected as a representative node is obtained multiple times, and the maximum value is selected as the maximum latency of that output node, the accuracy of obtaining the maximum latency is improved.

[0010] In one possible implementation of the first aspect, the initial maximum latency time is equal to the sum of the incremental latency time and the base latency time of the corresponding output node; the incremental latency time of the corresponding output node is equal to the difference between the maximum latency time and the base latency time of the representative node; and the base latency times of multiple output nodes are equal. Thus, the maximum latency time of an output node that has never been a representative node is obtained by adding the incremental latency time to the base latency time, while the incremental latency time is obtained by using the maximum latency time of the representative node. That is, when obtaining the maximum latency time of an output node that has never been a representative node, the incremental latency time of that output node will be the same as the incremental latency time of a representative node, meaning that the output node and that representative node are in the same category. Other output nodes that have never been representative nodes will also be in the same category as a representative node. Therefore, each category includes a representative node, through which the maximum latency time of other output nodes in that category can be obtained, improving the efficiency of obtaining the maximum latency time.

[0011] In one possible implementation of the first aspect, obtaining the maximum delay time of the representative node includes: obtaining the noise waveform V of each aggressor network at the representative node. i (t), where i represents the i-th aggressor network, and the noise waveform V i (t) is the noise waveform generated by the victim network in a silent state after the attacker network is given an attacker signal; based on the noise waveform V i (t) Obtain the peak height V of the noise waveform i (p) ; Obtain the total peak noise V ps Total peak noise V ps For each noise waveform V i Peak height V of (t) i (p) The sum, based on the total peak noise V ps Obtain the maximum latency. Thus, obtaining the maximum latency of representative nodes utilizes the crosstalk between the various aggressor networks and the victim network, which can improve the accuracy of the obtained maximum latency.

[0012] In one possible implementation of the first aspect, based on the total peak noise V ps Obtaining the maximum delay time includes: obtaining the noise-free waveform V(t) representing the node; obtaining the maximum delay time. Maximum delay time satisfy Where Vdd is the circuit supply voltage. Thus, the maximum delay time can be obtained from the noise-free waveform V(t). Simplify the process of obtaining the maximum latency time Reduce computational complexity.

[0013] In one possible implementation of the first aspect, the maximum delay calculation method further includes: based on the noise waveform V i (t) Obtain the peak time of the noise waveform Among multiple aggressor networks, one aggressor network is selected as the reference aggressor network; the peak time of the noise waveform of the reference aggressor network is...

[0014] Obtaining the maximum latency of the representative node also includes: updating the total peak noise V at least once. ps And based on the updated total noise peak value V ps Get the maximum delay time In each update: obtain the peak time t of the difference. p (s), the peak time of the difference t p (s) is

[0015]

[0016] The total peak noise V ps Updated to

[0017] V n (t p (s),s)-V(t p (s)),

[0018] Among them, V n (t,s) represents the output waveform of the output node after inputting aggressor signals into the network of n aggressors, under preset conditions; the preset conditions are that the flip time of the aggressor signal is shifted by s relative to the flip time of the victim signal. i , where s i for s is the difference between the flip time of the aggressor signal in the reference aggressor network and the flip time of the victim signal in the input node. The initial value of s is...

[0019] Update s to

[0020] Thus, through the total peak noise V ps To update, the total peak noise value V can be obtained. ps The maximum possible value, thereby improving the total peak noise V ps Get the maximum delay time The accuracy.

[0021] In one possible implementation of the first aspect, updating the total noise peak value V is stopped when the difference between the maximum delay time and the peak difference time is less than or equal to a first threshold. psThus, updates to the total noise peak V can be stopped when the victim signal's inversion moment has shifted less. ps This will improve efficiency.

[0022] In one possible implementation of the first aspect, updating the representative node includes: acquiring the noise waveform V of each aggressor network for each output node. i,j (t), where i represents the i-th aggressor network, j represents the j-th output node in the victim network, and the noise waveform V i,j (t) is the waveform of the noise signal generated by the victim network in a silent state after the attacker network inputs the attacker signal; based on the noise waveform V i,j (t) Obtain the noise waveform V i,j Peak height of (t) Peak time Obtain the maximum estimated delay time for each output node. Maximum delay estimation time Satisfy the formula

[0023]

[0024] in, V j (t) represents the noise-free waveform at the j-th output node;

[0025] Time estimation using maximum delay and peak time The feature coordinates of each output node are constructed as follows:

[0026]

[0027] Update the representative node based on the feature coordinates.

[0028] Thus, time can be estimated based on the maximum delay. and peak time The constructed feature coordinates update the representative node. Due to the maximum latency estimation time... and peak time It can detect crosstalk from intruder signals to the victim's network, thus allowing for faster acquisition of maximum latency. Improve efficiency.

[0029] In one possible implementation of the first aspect, the representative node is updated based on the Euclidean distance between the feature coordinates of the two output nodes. Thus, the representative node can be updated based on the relationships between the output nodes.

[0030] In one possible implementation of the first aspect, the representative node is updated based on the Euclidean distance from the output node to the output node that has already served as a representative node. This allows the use of the already acquired maximum latency time. Updating the information of the representative node helps improve efficiency.

[0031] In one possible implementation of the first aspect, according to the formula

[0032]

[0033] Update the representative nodes, where P is the set of output nodes that have been used as representative nodes, and dis(k,j) is the Euclidean distance between the k-th and j-th output nodes. For noise waveform V i,j The duration for which the level of (t) is greater than or equal to the threshold level. Thus, the influence of noise waveforms is considered in the update representative time, which helps to improve convergence speed and computational efficiency.

[0034] In one possible implementation of the first aspect, selecting one of multiple output nodes as a representative node includes: obtaining the geometric center or centroid of the multiple output nodes based on their feature coordinates; and selecting the output node with the smallest Euclidean distance to the geometric center or centroid as the representative node. Thus, selecting the initial representative node using feature coordinates facilitates faster convergence.

[0035] In one possible implementation of the first aspect, the number of times the representative node is updated is less than or equal to m represents the number of output nodes. Therefore, since the number of output nodes can be obtained after providing the circuit, the time to stop updating the representative nodes can be estimated.

[0036] In one possible implementation of the first aspect, the representative node is stopped from being updated if the increase in the maximum delay time of the output node after each update is less than or equal to a second threshold. Thus, when the increase in the maximum delay time is small, updating the representative node can be stopped, ensuring both computational accuracy and efficiency.

[0037] In a second aspect, this application provides a computing device including a processor for executing a maximum latency calculation method as described in any of the first aspects.

[0038] Thirdly, this application provides a computer-readable storage medium storing computer program instructions, which, when executed by a processor, perform a maximum delay calculation method as described in any of the first aspects.

[0039] Fourthly, this application provides a computer program product that, when run on a computer, causes the computer to perform the maximum delay calculation method as described in any of the first aspects.

[0040] The beneficial effects of the second and fourth aspects mentioned above can be referred to the description of the first aspect or any of the embodiments in the first aspect, and will not be repeated here. Attached Figure Description

[0041] Figure 1 A schematic diagram of an integrated circuit structure provided in an embodiment of this application;

[0042] Figure 2 A flowchart illustrating a method for calculating the maximum delay time of a circuit, as provided in an embodiment of this application;

[0043] Figure 3 A flowchart for obtaining the maximum delay time of a representative node is provided in an embodiment of this application;

[0044] Figure 4 A schematic diagram of a noise waveform provided in an embodiment of this application;

[0045] Figure 5 A schematic diagram of peak alignment provided for an embodiment of this application;

[0046] Figure 6 A signal waveform diagram showing the relative movement of the flip-off times of the aggressor signal and the victim signal, as provided in an embodiment of this application.

[0047] Figure 7 A flowchart for iterating the total peak noise level is provided as an embodiment of this application;

[0048] Figure 8 A schematic diagram of the incremental delay time of each output node in an integrated circuit victim network provided for an embodiment of this application;

[0049] Figure 9 A schematic diagram illustrating automatic classification of output nodes provided in an embodiment of this application;

[0050] Figure 10 A schematic diagram of the structure of a victim network provided in an embodiment of this application;

[0051] Figure 11 A schematic diagram of the distribution of output nodes under characteristic coordinates provided in an embodiment of this application;

[0052] Figure 12 This is a schematic diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0053] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by those skilled in the art. The terms "first," "second," "third," and similar words used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of embodiments in this application, unless otherwise stated, "a plurality of" means two or more.

[0054] The directional terms such as “left,” “right,” “up,” and “down” are defined relative to the orientation of the device shown in the accompanying drawings. It should be understood that these directional terms are relative concepts and are used for relative description and clarification. They can change accordingly depending on the orientation of the chip or semiconductor package structure.

[0055] With the rapid development of the integrated circuit industry, especially the rapid advancement of semiconductor process technology, the critical dimensions of electronic components such as transistors, registers, and conductive interconnects in integrated circuits are becoming increasingly smaller, as are the distances between adjacent electronic components. Simultaneously, as the functions of integrated circuits become increasingly rich and their functional integration density increases, the functional design of integrated circuits is becoming increasingly complex. All of these factors will affect crosstalk between circuit networks composed of different electronic components within an integrated circuit, and this crosstalk may produce delay effects. The delay effects caused by crosstalk between different circuit networks may lead to timing violations in integrated circuits. Furthermore, the clock frequency of integrated circuits is constantly increasing to improve their performance. This further increases the likelihood of timing violations in integrated circuits.

[0056] Therefore, after the integrated circuit design is completed, verification is required, including timing verification. Timing violations in the design can cause metastability during signal transmission, leading to erroneous data signals being transmitted in registers, resulting in logic errors and affecting the normal operation of the integrated circuit. Only after the integrated circuit meets timing verification requirements can it be put into production.

[0057] When performing timing verification, static timing analysis (STA) is typically used. In static timing analysis, the timing paths in the integrated circuit are analyzed. By analyzing the maximum delay time of the timing path and comparing it with the standard timing constraint settings, it is checked whether the timing path meets the timing requirements.

[0058] In static timing analysis, the signal integrity (SI) analysis takes into account the mutual influence between circuit networks in the integrated circuit.

[0059] Please see Figure 1 , Figure 1 This is a schematic diagram of the integrated circuit 100. The circuit network of the integrated circuit 100 includes a victim network 110 and an aggressor network 120 coupled to the victim network 110. The victim network 110 may include a driver 111 and a receiver 112, and the number of receivers 112 may be multiple. The end of the driver 111 facing away from the receiver 112 is an input node 113, and multiple output nodes 114 may be included between the driver 111 and the receiver 112. Figure 1 Only three output nodes 1141 to 1143 are shown in the diagram. Signals on the victim network 110 are transmitted from the input node 111 to the output nodes 1141 to 1143 via the driver 111.

[0060] Level fluctuations in the aggressor network 120 can inject noise into the victim network 110 through coupling capacitors, causing crosstalk. Coupling capacitors can include capacitance between adjacent wires placed between the aggressor network 120 and the victim network 110, or capacitance introduced by capacitors placed between the aggressor network 120 and the victim network 110. This crosstalk affects signal transmission in the victim network 110, and the more aggressor networks 120 there are, the more difficult it becomes to analyze the worst delay caused by crosstalk.

[0061] Understandably, in order to perform accurate timing verification, it is necessary to obtain the maximum delay time for the signal in the victim network 110 to be transmitted from the input node 113 to multiple output nodes 114, which can be all output nodes 114 between the driver 111 and multiple receivers 112.

[0062] Please see Figure 2 and combined Figure 1 , Figure 2 This is a flowchart illustrating a method for calculating the maximum delay time of a circuit according to an embodiment of this application. The calculation method includes the following steps:

[0063] S100 provides the circuit to be analyzed.

[0064] The circuit to be analyzed can be as follows: Figure 1The circuit 100 shown may include a victim network 110 and multiple aggressor networks 120 coupled to the victim network 110. The victim network 110 includes input nodes 113 and multiple output nodes 114. Victim signals from the victim network 110 are input from input nodes 113, transmitted through a driver 111 to the multiple output nodes 114, and can be received by a receiver 112. Understandably, the victim signals may undergo pre-processing during transmission from the driver 111 to the receiver 112.

[0065] S200, Select one of the multiple output nodes 114 as the representative node T.

[0066] The representative node T can be any one of the multiple output nodes 114. For example, in Figure 1 In this context, the output node 1141, which is directly connected to the driver 111, can be selected as the representative node T.

[0067] By selecting a suitable representative node T, the maximum delay time of each output node 114 can be obtained more quickly. In other words, selecting a suitable representative node 114 can accelerate the convergence speed of the calculation method for the maximum delay time of each output node 114, thereby improving efficiency. The selection of a representative node T among multiple output nodes 114 is explained below.

[0068] S300, Get the maximum delay time of the representative node T.

[0069] Please see Figure 3 and combined Figure 1 Obtaining the maximum delay time of the representative node T may include the following steps:

[0070] S310, Obtain the noise waveform V of each aggressor network 120 representing node T. i (t), where i represents the i-th aggressor network 120, and the noise waveform V i (t) is the noise waveform generated by the victim network 110 in a silent state after the aggressor network 120 is input with an aggressor signal.

[0071] noise waveform V i (t) represents the noise waveform generated by node T when the i-th aggressor network 120 crosstalks to the victim network 110. The aggressor signal input to the aggressor network 120 can be a signal that flips from low to high or from high to low. To obtain the noise waveform V i(t), the victim network 110 can remain in a silent state. The victim network 110 being in a silent state means that the victim signal input to the victim network 110 remains at a constant level, for example, the victim signal can be at a low level or a high level.

[0072] When the victim network is interfered with by the attacker's signal, a noise waveform will be generated at the representative node T of the attacker network. Understandably, the noise waveform V... i (t) is a function of time t, and the magnitude of the noise is the level of the signal generated by crosstalk at the representative node. The noise changes with time. Noise waveform V i (t) can be obtained through simulation or by estimating the transfer function.

[0073] S320, Based on the noise waveform V i (t) Obtain the noise waveform V i Peak height V of (t) i (p) .

[0074] Understandably, in acquiring the noise waveform V i After (t), the peak height V of the noise waveform can be obtained. i (p) Peak height V i (p) It is the level of the point where the noise waveform level is the highest.

[0075] Since the subsequent maximum delay time calculation also requires the use of the noise waveform V of each output node from each aggressor network, i,j The waveform feature data of (t), where i represents the i-th aggressor network, j represents the j-th output node in the victim network, and the noise waveform V i,j (t) is the waveform of the noise signal generated by the victim network in a silent state after the attacker network receives an attacker signal. Understandably, when the j-th output node is the representative node, the noise waveform V... i,j (t) is the noise waveform V i (t). Therefore, the noise waveform V can also be obtained simultaneously in this step. i,j Peak height of (t) Peak time and width

[0076] Please see Figure 4 , Figure 4 For noise waveform V i,j A schematic diagram of (t), where the peak height It is the noise waveform V i,j The level magnitude corresponding to the point where the level of (t) is the largest; peak time It is the noise waveform V i,j The moment corresponding to the point where the level of (t) is maximum; width For the noise waveform V i,j The time from the generation to the disappearance of the level (t), and the width This is also the noise waveform V i,j The duration for which the level of (t) is greater than or equal to the threshold level, for example, the width For the noise waveform V i,j The duration for which the level of (t) is greater than or equal to 10% of the integrated circuit supply voltage (voltage drain, Vdd).

[0077] Obtain the noise waveform V i,j Peak height of (t) Peak time and width Then, the peak height can be... Peak time and width The waveform feature data is stored in a specified location and retrieved from that location when needed.

[0078] Understandably, steps S310 and S320 can also be performed before step S200, and the noise waveform data can be acquired only when needed; this application does not impose any restrictions.

[0079] S330, Obtain the total peak noise value V ps Total peak noise V ps For each noise waveform V i Peak height V of (t) i (p) The sum, based on the total peak noise V ps Get the maximum delay time.

[0080] In step S110, the noise waveform V of each of the 120 pairs of representative nodes T in the aggressor network has been obtained. i (t), from which the various noise waveforms V can be obtained. i Peak height V of (t) i (p) By using peak height V i (p) The total peak noise V can be obtained by adding them together. ps .

[0081] Please see Figure 5 and combined Figure 1 , Figure 5 This is a schematic diagram of wave crest alignment. Figure 5Figure (a) shows the noise waveform V generated by the input aggressor signal to the same representative node T when the signal is individually crosstalked by the five aggressor networks 120a-120e. i (t). The moment the aggressor signal flips to the noise waveform V. i Peak time of (t) The peak time is The peak time corresponding to each aggressor signal is They are not the same. If the aggressor signals of multiple aggressor networks 120 flip simultaneously, the noise waveform V generated at the representative node T will be different. i (t) may undergo linear superposition. However, since the peak time corresponding to each aggressor signal is They are not the same. The maximum noise of the linearly superimposed noise waveform at node T does not represent the maximum noise that may actually occur at node T, and the noise magnitude will affect the maximum delay time.

[0082] Therefore, in order to improve the accuracy of obtaining the maximum delay time, when multiple aggressor networks 120 all generate crosstalk to the victim network 110, the flip-off time of the aggressor signals of each aggressor network 120 is shifted, so that the noise waveform V generated by multiple aggressor networks 120 to the victim network 110 is... i The noise is greatest when the peaks of (t) are superimposed.

[0083] For example, such as Figure 5 As shown in Figure (b), one of the multiple aggressor networks 120 can be selected as the reference aggressor network, for example, the first aggressor network 120a can be selected as the reference aggressor network. The peak time of the noise waveform of the reference aggressor network is... The flipping moment of the aggressor signals of other aggressor networks 120b-120e causes the noise waveform V generated by multiple aggressor networks 120 on the victim network 110 to... i The peak of (t) occurs simultaneously at node T, at which point the noise waveform V generated by the crosstalk of each aggressor network 120 is shown. i The linear superposition of the peaks of (t) is the total peak noise V. ps At this point, the noise is at its maximum. The time shift of the flip-off moment of the i-th aggressor network relative to the flip-off moment of the reference aggressor network (the first aggressor network) is:

[0084]

[0085] This achieves peak alignment of multiple noise waveforms.

[0086] Understandably, Figure 5The signal flipping moment is indicated by the moment when the signal begins to flip. The signal flipping moment can also be the 50% threshold point of the integrated circuit's power supply voltage.

[0087] Based on the total peak noise V ps The maximum delay time of the representative node T can be obtained from the noiseless waveform V(t) of the representative node T. The noiseless waveform V(t) of the representative node T is the waveform at the representative node after the victim network 110 inputs a victim signal, when none of the aggressor networks 120 have input aggressor signals or all aggressor networks 120 remain silent. The victim signal can be a low-level to high-level or a high-level to low-level transition. Understandably, the noiseless waveform V(t) is also a function of time. Therefore, when the victim signal is transmitted from the input node 113 to the output node 114, the waveform at the representative node also undergoes a high-low level transition, meaning the noiseless waveform V(t) is approximately monotonically changing. For ease of explanation, the following symbols are used... This represents the maximum delay time.

[0088] At this point, the maximum delay time Satisfy the following formula:

[0089]

[0090] Here, Vdd represents the supply voltage of the integrated circuit. The maximum delay time can be obtained from this.

[0091] Understandably, when victim network 110 also inputs victim signals, the shift in the flip times of aggressor signals input by multiple aggressor networks 120 relative to the flip times of victim signals input by victim network 110 will also affect the noise waveform at node T in victim network 110. That is, the order and degree of the flip times of aggressor signals input by multiple aggressor networks 120 and victim signals input by victim network 110 will also affect the noise waveform at node T in victim network 110. Wherein, s i A value greater than 0 indicates that the aggressor signal is flipped first.

[0092] If we take the relative shift s between the flip time of the aggressor signal of the reference aggressor network 120 and the flip time of the victim signal of the input node 113 as a reference, during peak alignment, the flip time of the aggressor signals of multiple aggressor networks 120 shifts relative to the flip time of the victim signals by s. i for:

[0093]

[0094] Where s is the difference between the flip time of the aggressor signal of the reference aggressor network 120 and the flip time of the victim signal of the input node 113, i.e., the time of relative movement.

[0095] Therefore, the maximum total noise peak value V can also be solved by iterating over s. ps Therefore, the maximum delay time can be updated using Formula 2. That is, through the total peak noise V ps Achieve maximum latency Perform iterations to obtain a more accurate maximum delay time representing node T.

[0096] Please see Figure 6 , Figure 6 This is a waveform diagram showing the relative movement of the flip times of the aggressor's signal and the victim's signal. The flip time of the victim's signal is used as a reference. Figure 6 The example uses the moment when the victim's signal begins to flip as the flip time (but other moments can also be used as the flip time), V n (t,s) represents the output waveform of node 114 after inputting aggressor signals into the n aggressor network 120, under preset conditions. For ease of description, this output waveform is referred to as the shift waveform. The preset condition is that the flip time of the aggressor signal is shifted by s relative to the flip time of the victim signal. i , where s i for s is the difference between the flip time of the aggressor signal in the reference aggressor network and the flip time of the victim signal in the input node. That is, the preset condition is that the difference between the flip time of the aggressor signal in the reference aggressor network and the flip time of the victim signal in the input node 113 is s, and the aggressor signals of other aggressor networks are shifted using Formula 3 to align the peaks of the noise waveform generated by the representative node T across multiple aggressor networks 120. Where V n Both (t,s) and the noise-free waveform V(t) can be obtained through simulation or by estimating the transfer function.

[0097] Please see Figure 7 , Figure 7 To the total peak noise V ps The iterative flowchart shows the steps involved in the iterative process:

[0098] S331. Obtain the noise waveform V generated by 120 pairs of representative nodes T in each aggressor network. i Peak height of (t) Peak time

[0099] As mentioned above, if the noise waveform V has been acquired before this step (such as step S320), i,j Peak height of (t) Peak time Then the noise waveform V corresponding to node T can be read directly. i Peak height of (t) Peak time

[0100] S332, Make the noise waveform V generated by multiple aggressor networks 120 pairs of representative nodes T. i Peak alignment of (t).

[0101] As mentioned earlier, peak alignment is performed according to Formula 1, and the relative flip times of multiple aggressor networks 120 are adjusted so that the noise waveform V generated by the multiple aggressor networks 120 representing node T is aligned with the noise waveform V generated by the node T. i The peaks of (t) occur at the same time, which will not be elaborated here.

[0102] S333. Estimate the relative movement of the aggressor signal flip-off time and the victim signal flip-off time of the reference aggressor network 120 using the fixed-point method.

[0103] When the relative shift time between the aggressor signal flip time and the victim signal flip time in aggressor network 120 is s, the flip times of other aggressor signals can be relatively shifted according to step S332. The initial value of s can be... That is, the initial value of s can be the maximum delay time obtained for the first time through formula 2. Peak time of the noise waveform representing the node difference.

[0104] Obtain the shift waveform V n (t,s) and a noise-free waveform V(t), and through the shifted waveform V n The peak time t is obtained from the difference between (t,s) and the noise-free waveform V(t). p (s) and through the shift waveform V n The updated total noise peak value V is obtained from the noiseless waveform V(t) (t,s). ps .

[0105] Please continue reading Figure 6 Using the flip time of the victim's signal as a reference, the shift waveform V is obtained. n After obtaining the peak time t of the difference between the waveforms V(t,s) and the noise-free waveform V(t), the peak time t can be obtained using the following formula. p (s):

[0106]

[0107] The total peak noise V is calculated using the following formula. ps Update:

[0108] V n (t p (s),s)-V(t p (s)) (5)

[0109] Shift waveform V n (t,s) and the noise-free waveform V(t) can be obtained through simulation or by estimation of the transfer function.

[0110] In obtaining the total noise peak value V ps s can then be updated using the following formula:

[0111]

[0112] S334. Reacquire waveform feature data based on the updated s from the previous step.

[0113] Waveform feature data may include the shifted waveform V after the update s. n (t,s) and other data required for the next step S333. In addition, waveform feature data may also include the total noise peak value V updated in step S333. ps The maximum delay time was re-acquired according to Formula 2.

[0114] S335, Determine the total peak value of the noise V ps Whether the iteration converges.

[0115] For example, convergence can be determined by the number of times s is updated. For instance, after the number of updates to s reaches a threshold, updating s is stopped, which is considered as adjusting for the total peak value V of the noise. ps The iteration has converged.

[0116] For example, it is also possible to set the maximum delay time. Peak time of difference t p When the difference between (s) and (s) is less than or equal to the first threshold, the update of the total noise peak value V is stopped. ps Furthermore, convergence can be determined and iteration can be stopped when the number of updates to s reaches the threshold number but the condition of being less than or equal to the first threshold is not met.

[0117] If the iteration converges, proceed to the next step; if it does not converge, continue with step S333.

[0118] S336, Obtain the maximum delay time

[0119] Based on the total peak noise V ps Determine the maximum delay time The total peak noise value V can be obtained from the last iteration. ps Get the maximum delay time Alternatively, in each iteration, the total peak noise value V can be used as a reference. ps Maximum latency obtained Then based on the maximum delay time obtained multiple times The maximum value in is the final maximum delay time.

[0120] S400: Obtain the initial maximum delay time for each output node other than the representative node T.

[0121] Obtain the maximum delay time of the current representative node T. After that, it is also necessary to obtain the initial maximum delay time of each output node other than the representative node T, and then obtain the maximum delay time of the output node that has not been the representative node from the beginning through the initial maximum delay time.

[0122] Please see Figure 8 , Figure 8 This diagram illustrates the incremental delay time (Δt) of each output node in an integrated circuit victim network. The incremental delay time Δt refers to the delay caused by crosstalk from the aggressor network 120 to each output node 114 of the victim network 110. The incremental delay time Δt from input node 113 to each output node 114 can be considered equal. That is, the aggressor network 120 has the same impact on the delay of each output node 114 in the victim network 110. Therefore, the maximum delay time of node T can be used to represent this delay. Obtain the incremental delay time Δt for each output node 114 in the victim network 110. For example, the incremental delay time Δt represents the maximum delay time of node T. The difference between the input node 113 and the base delay time from the input node 113 to the representative node T.

[0123] Therefore, the initial maximum delay time of each output node 114, excluding the representative node T, is equal to the sum of the incremental delay time Δt and the basic delay time of the corresponding output node 114. The basic delay time can also be obtained through simulation or estimation using a transfer function. The basic delay time is related to the flip time of the aggressor signal in the aggressor network, and the basic delay time is generally different for different aggressor signal flip times.

[0124] Understandably, this application calculates the maximum delay time. The representative node T can be updated at least once. Updating the representative node T involves selecting one output node 114 from among the output nodes 114 that have not been the representative node T from the beginning. In this way, the initial maximum delay time of each output node 114 other than the representative node T can be obtained again. That is, for an output node 114 that has not been the representative node T from the beginning, the number of initial maximum delay times obtained is at least the number of times the representative node T has been selected. Obtaining the initial maximum delay time of each output node 114 other than the representative node T again may or may not include obtaining the initial maximum delay time of the output node 114 that has already been the representative node T. This is because the maximum delay time obtained through being the representative node T... It will generally be longer than the initial maximum latency obtained when it is not a representative node T.

[0125] Obtain the maximum value among multiple initial maximum delay times for each output node 114, excluding all representative nodes T, and use this maximum value as the maximum delay time for output node 114. As described above, each output node 114, excluding all representative nodes T, acquired the initial maximum delay time multiple times, meaning it acquired multiple initial maximum delay times. Therefore, the maximum delay time of each of these output nodes 114 is... The maximum delay time of output node 114 is the maximum value among the multiple initial maximum delay times.

[0126] S500: Determine whether the iteration over the representative node T has converged.

[0127] For example, convergence can be determined based on the number of times the representative node T is updated. For instance, updating the representative node T can be stopped once a threshold is reached, which is considered convergence. Alternatively, the number of updates to the representative node can be less than or equal to... When the update of the representative node T is stopped, it is considered to be convergence, where m is the number of output nodes.

[0128] For example, the maximum delay time of node 113 can also be output after each update of representative node T. If the increase in time is less than or equal to the second threshold, updates to representative node T are stopped. For example, in the maximum delay time of output node 113. The increase in time is less than or equal to the maximum delay time already acquired by all output nodes 113 (including representative node T). When the value of the maximum value in the table reaches a certain percentage, updates to the representative node T cease. This percentage can be 1%, 3%, 5%, 10%, etc.

[0129] If the iteration converges, proceed to the next step; if it does not converge, continue with step S200.

[0130] S600, Obtain the maximum delay time of each output node 114.

[0131] Among all output nodes 114, the maximum delay time of the output node 114 that represents node T is... The maximum delay time obtained when it is used as the representative node T As the final calculation result; the maximum delay time for output node 114, which has never been used as a representative node T. The maximum delay time corresponding to the output node 114 obtained in step 400. The final calculation result is the maximum value among multiple initial maximum delay times, which is the maximum delay time of each output node.

[0132] Therefore, in obtaining the maximum latency time Then, output node 114, which had never served as a representative node T, was automatically classified. Please refer to [link / reference needed]. Figure 9 and Figure 10 and combined Figure 1 , Figure 9 This diagram illustrates the automatic classification of output nodes. Black dots represent output nodes 114 that have not been used as representative nodes T, while white dots represent output nodes 114 that have been used as representative nodes T. Figure 10 This is a schematic diagram of the structure of a victim network. The victim network 110 may include a driver 111 and multiple receivers 112 (e.g., 10 receivers, which will be further described below as 10 receivers). The input terminal of the driver 111 is an input node 113, and the input terminal of each receiver 112 is an output node 114.

[0133] Figure 9 Figure (a) shows that a representative node T has not yet been selected; Figure 9 Figure (b) shows that three output nodes have been selected as representative nodes T. The maximum delay time of output node 114, which is not selected as representative node T, is also considered. It is obtained by adding the incremental delay time to the base delay time, and the incremental delay time is obtained by using the maximum delay time representing node T. To obtain. That is, to obtain the maximum delay time of output node 114, which is not represented by node T. At that time, the incremental delay time of the output node 114 is the same as the incremental delay time of a representative node T, meaning that the two are automatically classified into the same category. Each category includes an output node 114 as a representative node T.

[0134] Calculate using the aforementioned method Figure 10 The maximum latency of output node 114 in victim network 110. If three output nodes 114 are selected as representative nodes, then the ten output nodes 114 are divided into three categories. For example, output nodes 1 and 2 belong to the first category, output nodes 3 to 5 belong to the second category, and output nodes 6 to 10 belong to the third category. Each category has the same incremental delay time, and each category includes one output node 114 as a representative node.

[0135] Understandably, the method of updating the representative node T will affect the convergence speed of the iteration.

[0136] In some implementations, feature coordinates can be constructed for each output node 114, and the representative node T can be updated using the feature coordinates of the output node 114.

[0137] For example, it can be based on the noise waveform V i,j (t) Obtain the noise waveform V i,j Peak height of (t) and peak time The noise waveform V can also be obtained after providing the circuit to be analyzed. i,j (t), noise waveform V i,j Peak height of (t) and / or noise waveform V i,j Peak time of (t) These waveform feature data are stored in a designated location, and the required waveform feature data is retrieved from that location when needed.

[0138] Understandably, in obtaining the peak height in the aforementioned characteristic waveform data... Then, the maximum delay time of each output node 114 can be obtained using the aforementioned formula 2. Among them, the total peak noise V ps For each noise waveform V i Peak height V of (t) i (p) The sum. To distinguish, the maximum delay time of each output node 114 obtained at this time is... Let this be the maximum delay estimate time. Where j represents the j-th output node (114), and the maximum estimated delay time. This represents the maximum estimated delay time for the j-th output node (114). In other words, it represents the maximum estimated delay time for each output node. Satisfy the following formula:

[0139]

[0140] in, V j (t) represents the noise-free waveform at the j-th output node.

[0141] Based on this, the feature coordinates of the j-th output node 114 can be constructed as follows:

[0142]

[0143] In this way, the representative node T can be updated using the feature information of the noise waveform and the feature information of the noise-free waveform, thereby improving the acquisition of the maximum delay time. Efficiency and accuracy.

[0144] For example, the representative node T can be updated based on the Euclidean distance between the feature coordinates of two output nodes 114, where the output nodes 114 may include output nodes 114 that have previously served as representative nodes T. For instance, with a set P of output nodes 114 that have previously served as representative nodes T, the representative node T is updated based on the distances from these nodes to the output nodes 114 in set P among the output nodes 114 that have not previously served as representative nodes T; that is, the representative node is updated based on the Euclidean distance from the output node 114 to the output node 114 that has previously served as representative nodes T.

[0145] When updating the representative node based on the Euclidean distance from output node 114 to output node 114 that has already been used as representative node T, the selection can be made by maximizing the minimum distance, i.e., according to the following formula:

[0146]

[0147] Where dis(k,j) is the Euclidean distance between the k-th output node and the j-th output node. This means that for an output node 114 that has never been a representative node T, the representative node T is updated based on the smallest distance among the distances from the output node 114 to all output nodes 114 in the set P.

[0148] Furthermore, due to the noise waveform V i,j (t) has a significant impact on crosstalk, therefore, a waveform V reflecting the noise can be added to Equation 8. i,j The weights of (t) are determined. Specifically, the representative node T can be updated according to the following formula:

[0149]

[0150] That is, when considering the minimum distance among the distances from output node 114 to all output nodes 114 in set P, the following was added. As a weight. Among them, width For noise waveform Vi,j The duration for which the level of (t) is greater than or equal to the threshold level. As mentioned earlier, the noise waveform V i,j Width of (t) You can obtain it at the start of the calculation.

[0151] Please see Figure 11 and combined Figure 2 , Figure 11 This diagram illustrates the distribution of output nodes under feature coordinates, where black dots represent output nodes 114 that have not been used as representative nodes T, and white dots represent output nodes 114 that have been used as representative nodes T. The output nodes 114 within the dashed boxes have similar minimum and maximum distances to set P, but due to the added weights... As the basis for selection, one of the output nodes 114 will be selected as the representative node T, that is, the output node 114 in the dashed box will be selected as the representative node T.

[0152] Please continue reading Figure 4 , It can reflect the noise waveform V i,j Waveform characteristics of (t). The larger the value, the higher the noise waveform V. i,j (t) The closer to the impulse noise, the greater the potential impact of that noise on the delay. Therefore, when selecting the next representative node T, it is important to consider... As part of the weighting, it can increase sensitivity to noise and improve the ability to obtain the maximum delay time. Efficiency and accuracy.

[0153] Furthermore, as mentioned earlier, the selection of the first representative node T also affects the convergence speed. Therefore, the first representative node T can also be selected based on the feature coordinates of the output node 114.

[0154] For example, the geometric center or centroid of multiple output nodes 114 can be obtained based on the feature coordinates of the output nodes 114, and the output node with the smallest Euclidean distance to the geometric center or centroid among the multiple output nodes 114 can be selected as the representative node T. This accelerates the convergence speed and improves efficiency.

[0155] Please see Figure 12 , Figure 12 This is a schematic diagram of a computing device provided in an embodiment of the present application. The computing device 200 includes a processor 210, which can be used to execute any of the maximum latency calculation methods described above.

[0156] This application also provides a computer-readable storage medium storing computer program instructions. When the computer program instructions are executed by a processor, the processor performs any of the maximum latency calculation methods described above.

[0157] This application also provides a computer program product that, when run on a computer, causes the computer to perform any of the maximum latency calculation methods described above.

[0158] The steps of the methods or algorithms described in this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a core network interface device. Of course, the processor and storage medium can also exist as discrete components in the core network interface device.

[0159] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0160] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for calculating the maximum delay of a circuit, characterized in that, The method includes: A circuit to be analyzed is provided, the circuit including a victim network and multiple aggressor networks coupled to the victim network, the victim network including input nodes and multiple output nodes; Select one of the multiple output nodes as a representative node and obtain the maximum delay time of the representative node; Based on the maximum delay time, obtain the initial maximum delay time of each of the output nodes other than the representative node; The representative node is updated at least once. In each update, an output node that has never been a representative node is selected as the representative node, and the maximum delay time of the updated representative node is obtained. Based on the updated maximum delay time of the representative node, obtain the initial maximum delay time of each of the output nodes other than the current representative node; Obtain the maximum value among the multiple initial maximum delay times for each output node other than all representative nodes, and use the maximum value as the maximum delay time of the output node.

2. The maximum delay calculation method as described in claim 1, characterized in that, The initial maximum delay time is equal to the sum of the incremental delay time and the base delay time of the corresponding output node; The incremental delay time of the corresponding output node is equal to the difference between the maximum delay time and the basic delay time of the representative node; The base delay times of the multiple output nodes are equal.

3. The maximum delay calculation method as described in claim 1 or 2, characterized in that, The process of obtaining the maximum latency time of the representative node includes: Obtain the noise waveform V of each of the aggressor networks for the representative node. i (t), where i represents the i-th aggressor network, and the noise waveform V i (t) is the noise waveform generated by the victim network in a silent state after the aggressor network is input with an aggressor signal; According to the noise waveform V i (t) Obtain the peak height V of the noise waveform. i (p) ; Obtain the total peak noise V ps The total peak noise V ps For each of the noise waveforms V i Peak height V of (t) i (p) The sum, based on the total peak noise V ps Obtain the maximum delay time.

4. The maximum delay calculation method as described in claim 3, characterized in that, The total peak noise V ps To obtain the maximum latency time, including: Obtain the noise-free waveform V(t) of the representative node; Obtain the maximum delay time The maximum delay time satisfy Where Vdd is the circuit power supply voltage.

5. The maximum delay calculation method as described in claim 4, characterized in that, The maximum delay calculation method further includes: According to the noise waveform V i (t) Obtain the peak time of the noise waveform Among the plurality of aggressor networks, one aggressor network is selected as a reference aggressor network; the peak time of the noise waveform of the reference aggressor network is... The process of obtaining the maximum delay time of the representative node also includes: At least once update the total peak noise V ps And based on the updated total noise peak value V ps Get the maximum delay time In each update: Obtain the peak time t of the difference p (s), the peak time of the difference t p (s) is The total peak noise V ps Updated to V n (t p (s),s)-V(t p (s)), Among them, V n (t,s) represents the output waveform of the output node after the aggressor signal is input to n aggressor networks, under preset conditions; the preset conditions are that the flip time of the aggressor signal is shifted by s relative to the flip time of the victim signal. i , where s i for s is the difference between the flip time of the aggressor signal in the reference aggressor network and the flip time of the victim signal in the input node, and the initial value of s is... Update s to 6. The maximum delay calculation method as described in claim 5, characterized in that, The update of the total noise peak value V is stopped when the difference between the maximum delay time and the peak value time is less than or equal to a first threshold. ps .

7. The maximum delay calculation method according to any one of claims 1 to 6, characterized in that, The updating of the representative node includes: Obtain the noise waveform V of each of the aggressor networks for each of the output nodes. i,j (t), where i represents the i-th aggressor network, j represents the j-th output node in the victim network, and the noise waveform V i,j (t) is the waveform of the noise signal generated by the victim network in a silent state after the aggressor network is input with an aggressor signal; According to the noise waveform V i,j (t) Obtain the noise waveform V i,j Peak height of (t) Peak time Obtain the maximum estimated delay time for each of the output nodes. Maximum delay estimation time Satisfy the formula in, V j (t) represents the noise-free waveform at the j-th output node; Time estimated by the maximum delay and peak time The feature coordinates of each output node are constructed as follows: The representative node is updated based on the feature coordinates.

8. The maximum delay calculation method as described in claim 7, characterized in that, The representative node is updated based on the Euclidean distance between the feature coordinates of the two output nodes.

9. The maximum delay calculation method as described in claim 8, characterized in that, The representative node is updated based on the Euclidean distance from the output node to the output node that has already served as a representative node.

10. The maximum delay calculation method as described in claim 9, characterized in that, According to the formula Update the representative node, where P is the set of output nodes that have been used as representative nodes, and dis(k,j) is the Euclidean distance between the k-th and j-th output nodes. The noise waveform V i,j The duration for which the level of (t) is greater than or equal to the threshold level.

11. The maximum delay calculation method according to any one of claims 7 to 10, characterized in that, Selecting one of the plurality of output nodes as the representative node includes: The geometric center or centroid of the plurality of output nodes is obtained based on the feature coordinates of the output nodes; The output node with the smallest Euclidean distance from the geometric center or centroid among the plurality of output nodes is selected as the representative node.

12. The maximum delay calculation method according to any one of claims 1 to 11, characterized in that, The number of times the representative node is updated is less than or equal to m is the number of output nodes.

13. The maximum delay calculation method according to any one of claims 1 to 12, characterized in that, If, after each update of the representative node, the maximum delay time of the output node increases by less than or equal to a second threshold, the update of the representative node is stopped.

14. A computing device, characterized in that, Includes a processor, the processor being configured to perform the maximum latency calculation method as described in any one of claims 1 to 13.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, perform the maximum delay calculation method as described in any one of claims 1 to 13.

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