A device main circuit parameter global optimization method based on a large model iterator

Abstract

The application relates to a large model iterator-based global optimization method for main circuit parameters of equipment, and belongs to the field of power electronic equipment design.The method comprises the following steps: generating an initial parameter set by a parameter generation LLM; performing feasibility grouping based on a feasibility flag; judging the domination relationship of data in the feasible solution pool; judging the front stability; and performing decision by the parameter optimization LLM according to a termination flag and a maximum number of iterations to obtain a final main circuit parameter set.The application can realize systematic optimization meeting physical constraints through cooperation of multiple external tools when the calculation capacity of a large model is limited.Through the construction of a closed-loop feedback iteration mechanism, the parameters are strictly checked according to physical boundaries by using a steady-state analysis tool, and the data are grouped according to the Pareto domination logic; meanwhile, the front stability judgment and the differentiated optimization strategy are introduced, so that the physical feasibility of the design scheme is ensured, and the globally optimal design considering the technical performance and the economic cost is realized.

Description

Technical Field

[0001] This invention relates to a global optimization method for device main circuit parameters based on a large model iterator, belonging to the field of power electronic equipment design and artificial intelligence application technology. Background Technology

[0002] As power electronics technology advances towards higher voltage, larger capacity, and higher frequency, the main circuit topologies of various large-scale power electronic devices are becoming increasingly complex. The parameter tuning of these devices' main circuits is a typical multi-objective, strongly coupled, and strictly physically constrained nonlinear optimization problem. Overly conservative parameter configurations can lead to redundant equipment size and soaring investment costs. Insufficient margins can induce device overvoltage, overcurrent, or even system instability. Therefore, finding the optimal solution that balances technical feasibility and economic efficiency in a multi-dimensional parameter space while satisfying multiple physical constraints is a key common challenge in power electronics engineering design. Traditional equipment parameter tuning relies heavily on expert experience and simplified formulas, exhibiting strong subjectivity and difficulty in handling complex design spaces with multiple coupled objectives. Existing mathematical programming methods are limited by model accuracy and struggle to adapt to the high nonlinearity of systems; while heuristic intelligent algorithms are essentially random searches, exhibiting slow convergence, sensitivity to initial values, and susceptibility to local extrema. Furthermore, all of these methods lack physical interpretability, and the optimization results are difficult to accept in engineering due to their opaque logic.

[0003] In recent years, Large Language Models (LLMs) have provided a new paradigm for the design of complex engineering parameters, thanks to their massive knowledge reserves and powerful data reasoning capabilities. LLMs can understand design requirements described in natural language and invoke embedded physical common sense to assist decision-making. However, directly applying a single LLM to the optimization of multidimensional, nonlinear engineering parameters still faces significant challenges. Due to the lack of precise numerical computation capabilities, LLMs often rely on semantic association rather than logical operations when handling high-precision numerical tasks, making the results prone to getting trapped in local extrema or even deviating from the feasible region. This limitation in numerical computation makes it unable to meet the stringent requirements of engineering design for globally optimal parameters. Therefore, how to construct a systematic optimization method that can leverage the semantic understanding advantages of LLMs while overcoming their weak precise numerical computation capabilities has become an urgent technical problem to be solved. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a global optimization method for device main circuit parameters based on a large model iterator. This method overcomes the limitations of large model computational capabilities by leveraging multiple external tools to achieve systematic optimization that satisfies physical constraints. The method constructs a closed-loop feedback iterative mechanism, utilizes steady-state analysis tools to rigorously verify the physical boundaries of parameters, and groups the data according to Pareto dominance logic. In implementation, this method introduces frontier stability assessment and differentiated optimization strategies to ensure the physical feasibility of the design scheme and achieve a globally optimal design that balances technical performance and economic cost.

[0005] The present invention adopts the following technical solution:

[0006] A global optimization method for device main circuit parameters based on a large model iterator includes the following steps:

[0007] S1, the user inputs operating condition information, and the parameter generation LLM generates an initial parameter set in JSON format based on the operating condition information. The initial parameter set includes m sets of main circuit parameters to be verified and is transmitted to the subsequent parameter optimization module.

[0008] S2, the steady-state analysis tool constrains and determines the parameters of the main circuit to be verified, obtaining a feasibility flag indicating whether it is feasible. ;

[0009] S3, a data grouping tool based on feasibility flags. Feasibility groups are formed, including infeasible and feasible solutions, and multiple feasible solutions form a feasible solution pool;

[0010] S4, determine the dominance relationship of the data in the feasible solution pool, further divide the feasible solutions into dominated solutions and dominant solutions, and multiple dominant solutions form the dominant solution parameter set, which constitutes the current Pareto front set;

[0011] S5. Input the dominance group parameter set into the frontier stability judgment tool, calculate the improvement magnitude, and assign a value to the termination flag based on the improvement magnitude;

[0012] S6, the parameter optimization LLM makes decisions based on the termination flag and the maximum number of iterations. If the termination flag is 0, a differentiated optimization strategy is implemented based on the feasibility grouping results, generating the parameter set for the (n+1)th round and merging it into the historical set, and then returning to step S2 for closed-loop iteration. If the system termination flag is 1 or the maximum number of iterations has been reached, the parameters are determined to converge, the iteration is terminated immediately, and the final Pareto front set is output, thus obtaining the final optimized main circuit parameter set.

[0013] Preferably, in step S2, the steady-state analysis tool has a built-in preset set of physical constraints, which includes constraints in n key dimensions. The constraint judgment logic is as follows:

[0014] (1)

[0015] in, Indicates the feasibility flag; This represents the physical constraint index of the i-th dimension. This is a binary indicator function; its value is 1 when the parameters satisfy the corresponding physical constraints, and 0 otherwise; it only evaluates when all constraints are satisfied simultaneously. A value of 1 indicates that the set of parameters is feasible; if any constraint is not met, then... The value is 0.

[0016] Preferably, in step S3, the feasibility flag bit A value of 0 indicates an infeasible solution, and the feasibility flag is set accordingly. A value of 1 indicates a feasible solution.

[0017] Preferably, in step S4, the feasible solution pool contains n sets of data, and each set of data contains m parameters to be optimized, denoted as... For any number of Group and No. The dominance relationship in the dataset is determined by Pareto dominance comparison, and the criterion is shown in equation (2):

[0018] (2)

[0019] in, Indicates the first The first set of data The values ​​of the parameters, Indicates the first The first set of data The values ​​of the parameters;

[0020] If the first The set of data satisfies formula (2) and has at least one parameter. Make That is to say, the first The values ​​of the group of data in all m parameter dimensions are better than or equal to the values ​​of the first group. If the data is in the first set, then determine the first set. Group data domination Group of data, number The set of data is the dominant solution, the first set of data is the second set of data. The set of data represents the dominated solution.

[0021] Preferably, the implementation process of step S5 is as follows:

[0022] First, extract the solution set of the nth generation. That is, the set of dominant solution parameters selected after the Pareto dominance comparison in step S4 of the current nth iteration; then, the previous generation solution set is read from the historical iteration data. That is, the set of dominant solution parameters saved in the (n-1)th iteration, and the current nth generation solution set is calculated. Relative to the solution set of generation n-1 The relative improvement As shown in formula (3):

[0023] (3)

[0024] Indicates a preset threshold;

[0025] If formula (3) is satisfied, it means that the Pareto front has stabilized and the convergence condition has been met. At this time, the termination flag F will be set. ea The value is assigned to 1; if formula (3) is not satisfied, it means that convergence has not yet been achieved, and the termination flag F will be set at this time. ea If the value is set to 0, the system does not terminate and continues to enter the next generation loop for iterative optimization.

[0026] Preferably, the differentiation optimization strategy in step S6 is as follows:

[0027] For infeasible solutions, a correction strategy is adopted to make targeted corrections to the negative correlation parameters so that they return to the feasible region.

[0028] For the dominated solution, the minimum step size is reduced by a factor of 10 in each iteration to achieve a significant adjustment.

[0029] For the dominant solution, an adaptive step size adjustment strategy is adopted. First, the index margin is used to judge. When it is in the high margin region, it indicates that the current parameter design is too conservative and there is a large redundancy space. The parameters are reduced significantly, and the minimum step unit is reduced by 10 times in each iteration. When it is in the low margin region, it indicates that the current parameters are on the edge of the feasible region and may become infeasible at any time due to the reduction of parameters. Fine adjustment is performed, and the minimum step unit is reduced by only 1 time in each iteration.

[0030] Preferably, the minimum step unit is the minimum value of each parameter change.

[0031] Preferably, a high margin region is defined as a current indicator margin greater than 20%, and a low margin region is defined as a current indicator margin less than or equal to 20%. The current indicator margin can be obtained by calculating the percentage difference between the current operating indicator and the constraint boundary value.

[0032] For any details not covered in this invention, please refer to the prior art.

[0033] The beneficial effects of this invention are as follows:

[0034] This invention proposes a global optimization method for device main circuit parameters based on a large model iterator, specifically a method that collaboratively uses a large language model and a physical constraint toolchain for global optimization of device main circuit parameters. This method effectively overcomes the illusion caused by insufficient numerical computation capabilities of a single LLM (Limited Language Model), ensuring that design parameters strictly meet engineering physical constraints, through external tool calls and a closed-loop feedback mechanism. Furthermore, this invention introduces a differentiated optimization strategy based on solution set classification, which can accurately guide the LLM to escape local extrema and quickly approach the Pareto front. This strategy effectively improves the convergence speed and optimization accuracy of multi-objective optimization problems, ultimately achieving automated device parameter design that balances technical performance and economic cost. Attached Figure Description

[0035] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.

[0036] Figure 1 This is a diagram illustrating the overall framework of the device main circuit parameter global optimization method based on a large model iterator according to the present invention.

[0037] Figure 2 This is a flowchart of the global optimization method for device main circuit parameters based on a large model iterator according to the present invention.

[0038] Figure 3 This is a schematic diagram of the data grouping strategy based on Pareto dominance comparison of the present invention;

[0039] Figure 4 A schematic diagram showing the distribution and classification of the initially generated parameter set in the target space;

[0040] Figure 5 The final Pareto front set distribution diagram after iterative convergence;

[0041] Figure 6 The waveform of the modulation signal of the upper arm of phase A and the verification diagram of modulation constraints under rated operating conditions are shown.

[0042] Figure 7 The waveform of the submodule capacitor voltage and the peak value and ripple constraint verification diagram under rated operating conditions;

[0043] Figure 8 The waveform of the interphase second harmonic circulating current and the constraint verification diagram are shown under the condition of circulating current suppression failure. Detailed Implementation

[0044] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. However, this is not the only description; all aspects not described in detail herein are based on conventional techniques in the art.

[0045] Example 1

[0046] A global optimization method for device main circuit parameters based on a large model iterator, such as... Figure 1 and Figure 2 As shown, it includes the following steps:

[0047] S1, the user inputs operating condition information, and the parameter generation LLM generates an initial parameter set in JSON format based on the operating condition information. The initial parameter set includes m sets of main circuit parameters to be verified and is transmitted to the subsequent parameter optimization module.

[0048] S2, the steady-state analysis tool constrains and determines the parameters of the main circuit to be verified, obtaining a feasibility flag indicating whether it is feasible. ;

[0049] S3, a data grouping tool based on feasibility flags. Feasibility groups are formed, including infeasible and feasible solutions, and multiple feasible solutions form a feasible solution pool;

[0050] S4, perform dominance relationship judgment on the data in the feasible solution pool, and further divide the feasible solutions into dominated solutions and dominated solutions, such as Figure 3 As shown, multiple dominant solutions form a set of dominant solution parameters, which constitute the current Pareto front set;

[0051] S5. Input the dominance group parameter set into the frontier stability judgment tool, calculate the improvement magnitude, and assign a value to the termination flag based on the improvement magnitude;

[0052] S6, the parameter optimization LLM makes decisions based on the termination flag and the maximum number of iterations. If the termination flag is 0, a differentiated optimization strategy is implemented based on the feasibility grouping results, generating the parameter set for the (n+1)th round and merging it into the historical set, and then returning to step S2 for closed-loop iteration. If the system termination flag is 1 or the maximum number of iterations has been reached, the parameters are determined to converge, the iteration is terminated immediately, and the final Pareto front set is output, thus obtaining the final optimized main circuit parameter set.

[0053] Example 2

[0054] A global optimization method for device main circuit parameters based on a large model iterator, as described in Example 1, differs in that, in step S2, the steady-state analysis tool incorporates a pre-set set of physical constraints. This set of physical constraints includes constraints in n key dimensions, and the constraint judgment logic is as follows:

[0055] (1)

[0056] in, Indicates the feasibility flag; This represents the physical constraint index of the i-th dimension. This is a binary indicator function; its value is 1 when the parameters satisfy the corresponding physical constraints, and 0 otherwise; it only evaluates when all constraints are satisfied simultaneously. A value of 1 indicates that the set of parameters is feasible; if any constraint is not met, then... The value is 0.

[0057] Example 3

[0058] A global optimization method for device main circuit parameters based on a large model iterator, as described in Example 2, differs in that, in step S3, the feasibility flag bit... A value of 0 indicates an infeasible solution, providing negative feedback to the LLM algorithm and avoiding invalid search regions; feasibility flag. A value of 1 indicates a feasible solution.

[0059] Example 4

[0060] A global optimization method for device main circuit parameters based on a large model iterator, as described in Embodiment 3, differs in that, in step S4, the feasible solution pool contains n sets of data, and each set of data contains m parameters to be optimized, denoted as... For any number of Group and No. The dominance relationship in the dataset is determined by Pareto dominance comparison, and the criterion is shown in equation (2):

[0061] (2)

[0062] in, Indicates the first The first set of data The values ​​of the parameters, Indicates the first The first set of data The values ​​of the parameters;

[0063] If the first The set of data satisfies formula (2) and has at least one parameter. Make That is to say, the first The values ​​of the group of data in all m parameter dimensions are better than or equal to the values ​​of the first group. If the data is in the first set, then determine the first set. Group data domination Group of data, number The set of data is the dominant solution, the first set of data is the second set of data. The set of data represents the dominated solution.

[0064] The dominated solution contains parameters that, while satisfying the physical constraints, are dominated by other solutions in terms of performance metrics, thus maintaining population diversity as suboptimal solutions. The dominant solution, on the other hand, contains non-dominated solutions in the current iteration that are not dominated by any other parameter set, forming the current Pareto front set.

[0065] Example 5

[0066] A global optimization method for device main circuit parameters based on a large model iterator, as described in Example 4, differs in that the implementation process of step S5 is as follows:

[0067] First, extract the solution set of the nth generation. That is, the set of dominant solution parameters selected after the Pareto dominance comparison in step S4 of the current nth iteration; then, the previous generation solution set is read from the historical iteration data. That is, the set of dominant solution parameters saved in the (n-1)th iteration, and the current nth generation solution set is calculated. Relative to the solution set of generation n-1 The relative improvement As shown in formula (3):

[0068] (3)

[0069] Indicates a preset threshold;

[0070] If formula (3) is satisfied, it means that the Pareto front has stabilized and the convergence condition has been met. At this time, the termination flag F will be set. ea The value is assigned to 1; if formula (3) is not satisfied, it means that convergence has not yet been achieved, and the termination flag F will be set at this time. ea If the value is set to 0, the system does not terminate and continues to enter the next generation loop for iterative optimization.

[0071] In this embodiment, during the iteration process, the front stability assessment tool monitors the evolution trend of the Pareto front set in real time. This tool calculates the improvement magnitude of the Pareto front set and assigns a value to the system's termination flag based on whether the improvement magnitude is lower than a preset threshold, but does not directly perform front output judgment.

[0072] Example 6

[0073] A global optimization method for device main circuit parameters based on a large model iterator, as described in Example 5, differs in that the differentiated optimization strategy in step S6 is as follows:

[0074] For infeasible solutions, a correction strategy is adopted to make targeted corrections to the negative correlation parameters so that they return to the feasible region.

[0075] For the dominated solution, the minimum step size is reduced by a factor of 10 in each iteration to achieve a significant adjustment, such as simultaneously and significantly adjusting the capacitance value C of the submodule. sm and bridge arm inductance value L m .

[0076] Because the parameters of the dominated set are designed too conservatively, there is usually a large amount of redundancy, so significant adjustments are needed. For the dominated solution, an adaptive step size adjustment strategy is adopted. First, the index margin is used to judge. When it is in the high margin region, it indicates that the current parameter design is too conservative and there is a large amount of redundancy. The parameters are significantly reduced, and the minimum step unit is reduced by 10 times in each iteration to help the population escape local extrema and enhance global exploration capabilities. The minimum step unit is the minimum value of parameter change in each iteration. When it is in the low margin region, it indicates that the current parameters are on the edge of the feasible region and may become infeasible at any time due to parameter reduction. Fine adjustment is performed, and the minimum step unit is reduced by only 1 time in each iteration.

[0077] A current indicator margin greater than 20% is considered a high margin region, while a current indicator margin less than or equal to 20% is considered a low margin region. The current indicator margin can be obtained by calculating the percentage difference between the current operating indicator and the constraint boundary value.

[0078] The final logical judgment and parameter optimization are performed by the parameter optimization LLM.

[0079] It should be noted that the parameter generation LLM in step S1 is based on pre-trained power electronics expertise, extracting key features from the input operating conditions and combining them with the basic operating principles of the target device and prior empirical formulas for logical reasoning. The physical feasible region boundary of the parameters to be optimized is initially defined, i.e., the reasonable upper and lower limits of the parameter values. After defining this feasible region, the parameter generation LLM generates an initial parameter set within this space. The parameter generation LLM is mainly responsible for initialization; it generates the first-generation initial parameter set based on initial design requirements and prior knowledge, focusing on the initial exploration of the solution space.

[0080] The parameter optimization LLM in step S6 is mainly responsible for iterative optimization and logic control. Its input is structured data that has undergone rigorous mathematical evaluation and grouping. Based on this feedback data, it executes differentiated evolutionary strategies and convergence judgments, focusing on in-depth mining and targeted correction of solutions.

[0081] To further verify the effectiveness and engineering applicability of the optimization method of this invention, the following detailed explanation is provided in conjunction with a specific MMC design example.

[0082] This embodiment selects a 500kV flexible DC transmission system as the specific design object. The user first inputs the key grid operating conditions and non-optimal system parameters required for designing the MMC (Multi-Level Computing) into the system through the human-machine interface. The specific input operating conditions and system parameters are shown in Table 1.

[0083] Table 1 shows the input operating conditions and system parameters.

[0084]

[0085] After receiving the user input, the parameter generation LLM uses its pre-trained knowledge of power electronics and the basic operating principles of MMC to perform reasoning, and initially defines the capacitor C, a sub-module of parameters to be optimized. sm and bridge arm inductor L m The reasonable physical range. Subsequently, the parameter generation LLM output contains 50 different C... sm and L m The initial parameter set is combined and formatted as JSON data for transmission to the steady-state analysis tool.

[0086] After receiving 50 sets of initial parameters, the steady-state analysis tool, based on the physical constraints of this embodiment, specifies them into four core physical constraint indicators: capacitor voltage ripple constraint C1, capacitor voltage peak constraint C2, modulation ratio constraint C3, and circulating current resonance constraint C4. The physical constraint inequalities corresponding to these four indicators are defined as follows:

[0087] (4)

[0088] (5)

[0089] (6)

[0090] (7)

[0091] In the formula, and These represent the peak and minimum values ​​of the capacitor voltage of the upper bridge arm submodule of phase A within one cycle. Rated voltage; and These represent the maximum and minimum values ​​of the modulation signal in the upper arm of phase A, respectively; and These represent the peak value of the interphase second harmonic circulating current and its limiting value when the circulating current suppression fails.

[0092] Equation (4) requires that the capacitor voltage be maintained at the rated capacitor voltage to prevent excessive capacitor ripple from affecting the capacitor life. Within 10%. Equation (5) To ensure that the submodule capacitor operates in a safe operating area and that the insulation is not broken down, it needs to be kept within 1.1 times the rated voltage. Equation (6) To avoid system instability and voltage distortion caused by overmodulation, the modulation signal needs to be in the linear modulation range of [0,1] at any time. Equation (7) To prevent the second harmonic circulating current component between phases from being too large and causing damage to the switching devices and system instability when the circulating current suppression fails, it needs to be kept within the constraint range. The system will substitute the generated parameters into the above four inequalities. Only when all four inequalities are true at the same time will the feasibility flag of the set of parameters be set. Set to 1 otherwise set to 0.

[0093] Subsequently, the data grouping tool uses feasibility flags. The Pareto dominance logic is used to filter and classify parameters, and the specific process is shown in the attached figure. Figure 3 As shown. First, the system reads the feasibility flag of each set of parameters. Perform initial screening, if A value of 0 indicates that the parameter violates physical constraints, and it is directly classified into the infeasible set. If If the value is 1, then the Pareto dominance logic decision-making stage begins. This applies to the capacitor C of each submodule, where the objective is to minimize the value. sm With bridge arm inductance L m The feasible solution set contains 26 sets of data. For any _th_ set... Group and No. The criteria for determining the dominance relationship in a set of data are shown in the following formula:

[0094] (8)

[0095] If the first The parameters of the group satisfy the above conditions, that is, the values ​​of capacitance and inductance are both better than or equal to those of the first group. If it is a group, then determine the first one. Group Domination Group.

[0096] Ultimately, the data grouping tool visually categorized the 50 parameter points into three classes based on feasibility flags and Pareto dominance logic. Crosses represented 24 infeasible solutions, which were deemed invalid due to exceeding constraints. Dots represented 19 dominated solutions, which, while satisfying physical constraints, had technical and economic indices inferior to the frontier solutions. Squares represented the dominant solutions, forming the initial 7 Pareto fronts, representing the globally optimal solutions in the current round. Their specific distribution is shown in the attached figure. Figure 4 As shown.

[0097] The grouped datasets are then transmitted to a frontier stability assessment tool to calculate the frontier improvement margin for the current round. Since this is the first round of generation, the solution set distribution has not yet converged, and the improvement is higher than the preset threshold ɛ=0.05. Therefore, the system will terminate the flag F. ea The value is assigned to 0, and the complete dataset containing the current round index, parameter set values, steady-state indices, and flag status is merged and sent to the parameter optimization LLM.

[0098] Parameter optimization LLM reads the termination flag F ea If the value is 0, the iterative optimization process is initiated. The parameter optimization LLM first increments the current round index by 1 and implements a differentiated evolution strategy based on the grouping results. For infeasible solutions, negatively correlated parameters are adjusted first for targeted correction, enabling them to quickly return to the feasible region boundary at minimal cost. For dominated solutions, C is significantly adjusted simultaneously. sm and L m This helps the population escape local optima and enhances its global exploration capabilities. For the dominant solution, the model employs an adaptive step-size search strategy, significantly reducing parameters in the high-margin region and fine-tuning them in the low-margin region, in order to approximate C while satisfying all constraints. sm and L m The theoretical minimum value.

[0099] The newly generated 50 sets of parameters are merged with the historical parameter set and then subjected to steady-state analysis, data grouping, and frontier stability assessment again. This process is repeated iteratively until the frontier stability assessment tool detects that the Pareto front improvement in two consecutive iterations is less than a preset threshold of 0.05, or the number of iterations n reaches the preset maximum limit N. max =20. At this point, the system determines that the optimization has converged, stops iterating, and outputs the final Pareto front set. For example... Figure 5 As shown, the final Pareto front is highly stable and no longer changes with iterations. The typical representative parameter set selected on the curve specifically quantifies the constraints between parameters; for example, the scheme biased towards low inductance design corresponds to C. sm =21200uF and L m =27mH, corresponding to 21200uF and 27mH respectively. The corresponding values ​​for the scheme biased towards low capacitance design are 10400uF and 55mH respectively. The equilibrium solution in the inflection point region is 14400uF and 40mH. These key data points provide engineers with clear quantitative decision-making basis.

[0100] To verify that the device main circuit parameters of the final Pareto front set meet the physical constraints, the following verification is further carried out in conjunction with the embodiments, in which the main circuit parameters of the MMC are shown in Table 2.

[0101] Table 2 MMC Main Circuit Parameters

[0102]

[0103] Figure 6 This demonstrates the MMC's output active power P rated Under the operating conditions of 1200 MW and reactive power Q=300 Mvar, the modulation signal S of the upper arm of phase A is... ap (t) Waveform under steady-state operation. As shown in the figure, the MMC system is in a stable sinusoidal modulation state from t=1.90s to 2.00s. Through... Figure 6 As can be seen, the modulation signal S of the upper bridge arm of phase A ap The maximum and minimum values ​​of (t) are 0.94 and 0.039, respectively. At this point, the modulation waveform is strictly controlled between the upper limit 1 and the lower limit 0 of the modulation signal, without touching the modulation signal boundary. Based on the data analysis in the figure, the modulation signal margin value Mar at the lower boundary of the system at this time is... l The upper boundary margin value Mar is 0.039. h The value is 0.06. This indicates that under the current main circuit parameters, the MMC operates in the linear modulation region, without exceeding the physical limits of the modulation signal, effectively avoiding the risk of waveform distortion caused by overmodulation; and the upper boundary margin of 0.06 indicates that although the DC voltage utilization rate is already at a high level, it is still within a safe range, enabling the MMC to output a high-quality voltage waveform.

[0104] Figure 7 This demonstrates the MMC's output rated active power P rated Under operating conditions of 1200 MW and reactive power Q=300 Mvar, the submodule capacitor voltage U cap The steady-state waveform of (t). (Through) Figure 7 As can be seen, under the current main circuit parameter configuration, the submodule capacitor voltage U cap The maximum peak value of (t) reaches 2488V, while the minimum valley value after discharge is 2077V. According to the design guidelines of the MMC system main circuit, the peak constraint value of the submodule capacitor is usually set to 1.1 times the rated voltage of the submodule capacitor, and the capacitor voltage ripple constraint value is usually set to 0.1 times the rated voltage of the submodule capacitor. Under this operating condition, the steady-state calculation yields a peak constraint value of 2523V and a capacitor voltage ripple constraint value of 229V. Based on the data analysis in the figure, the peak margin under the current operating condition is 35V, and the peak margin percentage is 1.3%. At the same time, the peak-to-peak value of the voltage ripple under this operating condition is 411V, that is, the ripple amplitude is 205.5V. At this time, the ripple margin is 23.5V, and the remaining percentage of the ripple margin is 10.3%. The above results show that the operating peak value and ripple amplitude of the submodule capacitor voltage are strictly within the set safety constraints, which fully verifies the rationality of the main circuit parameter selection under the current operating condition, ensuring the stable energy exchange inside the MMC and the safe operation of the submodule capacitor.

[0105] Figure 8 This demonstrates the MMC's output active power P rated Under the operating conditions of 1200 MW and reactive power Q=300 Mvar, the interphase second harmonic circulating current I when the circulating current suppressor fails. cir,2ω The steady-state waveform of (t). (Through) Figure 8 As can be seen, under the current main circuit parameters, the amplitude of the second harmonic circulating current stabilizes at 769 A, indicating that a significant second harmonic circulating current component exists within the system when the circulating current suppressor fails. According to the main circuit design guidelines for MMC systems, the maximum allowable value of the interphase second harmonic circulating current is typically no greater than 0.2 times the phase current amplitude. Combining this with the steady-state calculations for the phase current amplitude under this operating condition, the maximum allowable value of the interphase second harmonic circulating current can be derived to be 776 A (obtained from actual engineering design guidelines and steady-state calculations). The interphase second harmonic circulating current margin is only 7 A, with a remaining margin percentage of 0.9%. This result reveals that under the current operating condition, the interphase second harmonic circulating current constraint is the main bottleneck limiting further optimization of the main circuit parameters. In other words, if an attempt is made to further reduce the submodule capacitance or bridge arm inductance, the system will first touch the interphase second harmonic circulating current boundary, leading to exceeding the limit. This indicates that the currently selected parameters, while satisfying physical constraints, have approximated the safe boundary of the circulating current peak as closely as possible. This verifies the accuracy of the selected submodule capacitance and bridge arm inductance values ​​under the fixed operating conditions and system parameters, and further proves the accuracy and effectiveness of the method proposed in this invention.

[0106] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A global optimization method for device main circuit parameters based on a large model iterator, characterized in that, Includes the following steps: S1, the user inputs operating condition information, and the parameter generation LLM generates an initial parameter set in JSON format based on the operating condition information. The initial parameter set includes m sets of main circuit parameters to be verified. S2, the steady-state analysis tool constrains and determines the parameters of the main circuit to be verified, obtaining a feasibility flag indicating whether it is feasible. ; S3, a data grouping tool based on feasibility flags. Feasibility groups are formed, including infeasible and feasible solutions, and multiple feasible solutions form a feasible solution pool; S4, determine the dominance relationship of the data in the feasible solution pool, further divide the feasible solutions into dominated solutions and dominant solutions, and multiple dominant solutions form the dominant solution parameter set, which constitutes the current Pareto front set; S5. Input the dominance group parameter set into the frontier stability judgment tool, calculate the improvement magnitude, and assign a value to the termination flag based on the improvement magnitude; S6, the parameter optimization LLM makes decisions based on the termination flag and the maximum number of iterations. If the termination flag is 0, a differentiated optimization strategy is implemented based on the feasibility grouping results to generate the parameter set of the (n+1)th round and merge it into the historical set. Then, it returns to step S2 for closed-loop iteration. If the system termination flag is 1 or the maximum number of iterations has been reached, the parameters are determined to converge, the iteration is terminated immediately, and the final Pareto front set is output, which is the final optimized main circuit parameter set. The implementation process of step S5 is as follows: First, extract the solution set of the nth generation. That is, the set of dominant solution parameters selected after the Pareto dominance comparison in step S4 of the current nth iteration; then, the previous generation solution set is read from the historical iteration data. That is, the set of dominant solution parameters saved in the (n-1)th iteration, and the current nth generation solution set is calculated. Relative to the solution set of generation n-1 The relative improvement As shown in formula (3): （3） Indicates a preset threshold; If formula (3) is satisfied, it means that the Pareto front has stabilized and the convergence condition has been met. At this time, the termination flag F will be set. ea The value is assigned to 1; if formula (3) is not satisfied, it means that convergence has not yet been achieved, and the termination flag F will be set at this time. ea If the value is assigned to 0, the system does not terminate and continues to enter the next generation loop for iterative optimization. The differentiation optimization strategy in step S6 is as follows: For infeasible solutions, a correction strategy is adopted to make targeted corrections to the negative correlation parameters so that they return to the feasible region. For the dominated solution, the minimum step size is reduced by a factor of 10 in each iteration to achieve a significant adjustment. For the dominant solution, an adaptive step size adjustment strategy is adopted. First, the index margin is used to make a judgment. When it is in the high margin region, it indicates that the current parameter design is too conservative, and the minimum step unit is reduced by 10 times in each iteration. When it is in the low margin region, it indicates that the current parameter is on the edge of the feasible region, and the minimum step unit is reduced by only 1 time in each iteration.

2. The global optimization method for device main circuit parameters based on a large model iterator according to claim 1, characterized in that, In step S2, the steady-state analysis tool has a built-in set of preset physical constraints. The set of physical constraints contains constraints in n key dimensions, and the constraint judgment logic is as follows: （1） in, Indicates the feasibility flag; This represents the physical constraint index of the i-th dimension. This is a binary indicator function; its value is 1 when the parameters satisfy the corresponding physical constraints, and 0 otherwise; it only evaluates when all constraints are satisfied simultaneously. A value of 1 indicates the parameter is feasible; if any constraint is not met, then... The value is 0.

3. The global optimization method for device main circuit parameters based on a large model iterator according to claim 2, characterized in that, In step S3, the feasibility flag bit A value of 0 indicates an infeasible solution, and the feasibility flag is set accordingly. A value of 1 indicates a feasible solution.

4. The global optimization method for device main circuit parameters based on a large model iterator according to claim 3, characterized in that, In step S4, suppose the feasible solution pool contains n sets of data, and each set of data contains m parameters to be optimized, denoted as... For any number of Group and No. The dominance relationship in the dataset is determined by Pareto dominance comparison, and the criterion is shown in equation (2): （2） in, Indicates the first The first set of data The values ​​of the parameters, Indicates the first The first set of data The values ​​of the parameters; If the first The set of data satisfies formula (2) and has at least one parameter. Make That is to say, the first The values ​​of the group of data in all m parameter dimensions are better than or equal to the values ​​of the first group. If the data is in the first set, then determine the first set. Group data domination Group of data, number The set of data is the dominant solution, the first set of data is the second set of data. The set of data represents the dominated solution.

5. The global optimization method for device main circuit parameters based on a large model iterator according to claim 4, characterized in that, The minimum step unit is the minimum value at which the parameter changes each time.

6. The global optimization method for device main circuit parameters based on a large model iterator according to claim 5, characterized in that, A margin greater than 20% indicates a high margin region, while a margin less than or equal to 20% indicates a low margin region.

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