Modeling method of ferroelectric field effect transistor

Abstract

The invention relates to a modeling method of a ferroelectric field effect transistor, and relates to the technical field of memories. Comprising the following steps: constructing a classical ferroelectric Preisach model to calculate an effective polarization value of a ferroelectric film; introducing a polarization relaxation time parameter tau, and establishing a differential relationship between the external voltage and the effective voltage of the ferroelectric capacitor, so as to establish a ferroelectric polarization dynamic model; and on the basis of the model, constructing electrical modeling of the ferroelectric field effect transistor. According to the method, the polarization relaxation time parameter tau is introduced into the Preisach model, the dynamic change of ferroelectric polarization is more accurately reflected, and the change rule of the storage window of the ferroelectric field effect transistor device after the grid pulse signal is written can be better predicted, so that the working voltage can be guided to be optimized, and the writing reliability of a memory is improved.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more specifically to a modeling method for ferroelectric field-effect transistors. Background Technology

[0002] Non-volatile memory (NVM) is an electronic memory that retains data even when power is off, and its applications are becoming increasingly widespread. The demands on storage performance are also constantly increasing. Ferroelectric field-effect transistors (FeFETs)

[0003] FeFET (FeFET Electron-Fluorescent Electron) memory is a novel type of non-volatile memory. Its basic principle is to control the polarization orientation of dipoles within the ferroelectric layer using gate voltage. These dipole polarizations persist even after the gate voltage is removed. The residual polarization on the ferroelectric layer can promote or suppress the generation of charge carriers in the FeFET channel, thereby controlling the channel current switching. Due to its relatively simple structure, fast read / write speed, and good ferroelectricity even with a ferroelectric layer thickness of only a few nanometers, along with compatibility with complementary metal-oxide-semiconductor (CMOS) manufacturing processes, FeFET represents a current research direction in non-volatile memory.

[0004] With the continuous advancement of microelectronics technology, memory devices are becoming increasingly miniaturized and integrated, achieving higher storage capacity within the same area. However, as the channel length shrinks to a certain scale during miniaturization, it may lead to short-channel and narrow-channel effects, reducing the gate's ability to control the channel current and thus affecting the electrical reliability of FeFETs.

[0005] To address the electrical reliability issues arising from transistor miniaturization, the industry needs reliable models to calculate the changes in ferroelectric layer polarization and device threshold voltage after applying arbitrary voltages and pulse signals of arbitrary pulse widths to the gate. Currently, the mainstream ferroelectric models are the Preisach model and the Landau–Khalatnikov model. Although significant work has been done in related modeling, existing models either lack the necessary physical background, are too simplistic and limited, or are too complex and computationally cumbersome, making parameter extraction difficult and unsuitable for intensive models used in SPICE circuits. Furthermore, most ferroelectric modeling research focuses on MFM (metal-ferroelectric layer-metal) structures, lacking intensive modeling that considers FeFETs as a whole. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a modeling method for ferroelectric field-effect transistors. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] Step 1: Establish the classical ferroelectric Preisach model and determine the historical static model of ferroelectricity.

[0008] The effective polarization value P of the ferroelectric layer after applying an arbitrary electric field under quasi-static conditions aux for:

[0009]

[0010] Where F aux P is the effective voltage of the ferroelectric capacitor acting on the polarization. s It is the magnitude of the saturation polarization of the ferroelectric layer, P r It is the magnitude of the remanent polarization of the ferroelectric layer, F c It is the coercive field size of the ferroelectric layer; c and P off These are parameters related to the Preisach function. w can be given by the following formula:

[0011]

[0012] For F c P s P r The experimental parameters can be extracted by obtaining the static saturation QV curve through quasi-static triangular wave scanning, and the QV curve can be obtained by performing the PV curve through the following physical calculation:

[0013]

[0014] The dielectric constant ε of ferroelectric materials can be obtained by measuring small signals at low frequencies. r The maximum inflection point of saturation on the PV curve was used to confirm P. s Confirm F at the intersection of the x-axis and y-axis c P r .

[0015] Step 2: Introduce the polarization relaxation time parameter τ to determine the ferropolarization dynamic model, where F aux The relationship is as follows:

[0016]

[0017] Where F(t) is the applied voltage on the ferroelectric layer, F aux (t) is the effective voltage of the ferroelectric capacitor used for calculating ferroelectric polarization, and τ is the relaxation time from the applied voltage to the effective voltage. The formula for calculating τ is as follows:

[0018]

[0019] Where τ ∞ V0 and m are fixed parameters related to ferroelectric materials, independent of external conditions, and only related to the polarization properties of the domains within the ferroelectric layer, and F aux =V aux / T fe Tfe The thickness of the ferroelectric layer is given. These fixed parameters can be obtained through ferroelectric domain flipping experiments. By analyzing multiple sets of ferroelectric domain flipping test data with different voltage amplitudes, the fixed parameters of the ferroelectric material can be obtained through mathematical fitting. τ can then determine P. aux The dynamic relaxation time is obtained, thus revealing the dynamic changes in ferropolarization.

[0020] To address the aforementioned technical problems and explain the beneficial effects of the model, one embodiment of the present invention provides a modeling method for ferroelectric field-effect transistor memory devices, comprising:

[0021] S1: Type I doping forms a Si substrate, which is uniformly doped in intrinsic silicon with a doping concentration of x.

[0022] S2: Insulating dielectric layer, located on the Si substrate, with a thickness of b and a width of w;

[0023] S3: HZO ferroelectric layer, located on the insulating layer, with a thickness of c;

[0024] S4: Gate electrode, composed of one of Ta, Al, TiN, W, TaN or other conductive materials, located on the HZO ferroelectric layer;

[0025] S5: Type II doped LDD region, located at both ends of the Si substrate, with its upper surface flush with the upper surface of the Si substrate. It is a surface-based Gaussian doped region with a surface doping concentration of y.

[0026] S6: Si3N4 or other dielectric materials form sidewalls, located on the Si substrate, and connected to the gate electrode formed by the insulating dielectric layer, ferroelectric layer, and gate electrode layer;

[0027] S7: The third type of doped drain and source regions are located at the left and right ends of the Si substrate. Their upper surfaces are flush with the upper surface of the Si substrate. They are surface-based Gaussian doped with a surface doping concentration of z.

[0028] S8: Substrate electrode, located on the lower surface of the Si substrate;

[0029] S9: Source electrode and drain electrode, located on the drain region and source region respectively;

[0030] The selected three types of doping concentrations must satisfy the condition z>y>x, and the first type of doping must be P-type doping, while the second and third types of doping must be N-type doping.

[0031] The second type of doped surface range is the upper surface region of the Si substrate excluding the gate;

[0032] The third type of doped surface range is the upper surface region of the Si substrate excluding the gate and sidewalls;

[0033] Optionally, the insulating dielectric layer is composed of one or more of SiO2, Si3N4, Al2O3, ZrO2, and HfO2, and its thickness b is between 0.8nm and 2.5nm.

[0034] Optionally, the HZO ferroelectric layer is either Zr-doped HfO2 or Zr-doped HfO2 with a second element doped on top. The second element can be one of the following: Si, Al, Zr, La, Ce, Sr, Lu, Gd, Sc, or other doping elements. Its thickness c is between 6 nm and 30 nm.

[0035] The ferroelectric field-effect transistor modeling method of the present invention has the following beneficial effects:

[0036] The classical Preisach ferroelectric model is a static model that can only accurately capture the variation of ferroelectric polarization under quasi-static conditions. Its core limitation is that the effective voltage of the ferroelectric capacitor is always equal to the applied voltage, neglecting the actual dynamic response characteristics of the ferroelectric capacitor. To address this deficiency, this invention innovatively introduces the polarization relaxation time parameter τ and the effective voltage V of the ferroelectric capacitor, based on the classical Preisach static model. aux The concept of ferroelectric polarization is used to construct a model of its dynamic evolution by establishing a differential equation between the applied voltage and the effective voltage. This model is simple and clear, requiring no complex extraction process of ferroelectric physical parameters, and can be directly adapted to mainstream EDA ferroelectric simulation modules. Attached Figure Description

[0037] Figure 1 This is a structural diagram of a ferroelectric transistor based on a lightly doped drain design, as described in this invention.

[0038] Figure 2 To generate polarization-voltage relationships for the ferroelectric layer under different voltage amplitudes and pulse widths

[0039] Figure 3 Polarization-time relationship for ferroelectric domain flipping in ferroelectric layers

[0040] Figure 4 The graph shows the transfer characteristic curves of the ferroelectric transistor under different gate voltage amplitudes and pulse widths. Figure label:

[0041] 1: Gate electrode; 2: Ferroelectric layer; 3: Insulating dielectric layer; 4: Drain electrode; 5: Drain region; 6: Substrate; 7: Substrate electrode; 8: Source electrode; 9: Source region; 10: Lightly doped LDD region; 11: Sidewall. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Descriptions of specialized knowledge are omitted in the embodiments to avoid obscuring the concepts of the present invention. Example 1

[0043] Based on the modeling steps of this invention, this embodiment constructs a TiN / HZO / TiN MFM ferroelectric device model, the steps of which are as follows:

[0044] Step 1: Establish the classical ferroelectric Preisach model and determine the historical static model of ferroelectricity.

[0045] Step 2: Introduce the polarization relaxation time parameter τ to determine the ferropolarization dynamic model.

[0046] The top electrode is connected to a voltage source, and the bottom electrode is grounded (0V). Key parameters of the model are as follows: ferroelectric layer thickness T. fe =10nm, saturated polarization P r =27.0μC / cm 2 Residual polarization P s =24.5μC / cm 2 coercive field size E c =0.85MV / cm. This model introduces a polarization relaxation time τ, the value of which changes dynamically with the applied voltage. This embodiment demonstrates the advantages of this model through a series of simulation experiments.

[0047] See the experimental results. Figure 2 and Figure 3 We first investigated the effect of the top electrode voltage amplitude on the MFM device, using a quasi-static model. We applied triangular waves with different voltage amplitude ranges to the top electrode; taking a voltage amplitude of 2.5V as an example, the scanning voltage changed from 0V→2.5V→-2.5V→2.5V. The results are as follows: Figure 2 As shown on the left, when the amplitude is 0.5V, the inflection point of the polarization-voltage curve is not on the saturation curve, and a closed curve is not formed. When the voltage amplitude is 2.0V, its hysteresis curve basically coincides with the saturation hysteresis curve, and further increasing the voltage amplitude does not significantly change the curve shape.

[0048] Different scanning frequencies of the top electrode have varying effects on MFM performance. The model considers the coupling of polarization relaxation time τ, with a voltage scanning range of +4V to -4V. The results show that the lower the scanning frequency, the smaller the coercive voltage, which is closer to the coercive voltage under quasi-static conditions, and the narrower the overall hysteresis curve becomes. This result clearly reveals the variation law of the ferroelectric hysteresis curve under the frequency coupling effect. Furthermore, Figure 3 The test results of ferroelectric domain flipping time are presented. The initial condition is to apply a large negative voltage to make the ferroelectric layer reach negative saturation polarization. After the negative voltage is removed, positive voltages of different amplitudes are continuously applied. The results show that the larger the positive voltage amplitude, the faster the ferroelectric domain flipping speed and the greater the polarization corresponding to the flipping. Example 2

[0049] This embodiment models a ferroelectric transistor, wherein the ferroelectric layer employs the dynamic modeling method proposed in this invention. This includes:

[0050] S1: Type I doping forms substrate 6, which is intrinsic silicon with uniform doping concentration of x;

[0051] S2: Insulating dielectric layer 3, located on substrate 6, with a thickness of b and a width of w;

[0052] S3: HZO ferroelectric layer 2, located on insulating layer 3, with a thickness of c;

[0053] S4: Gate electrode 1, composed of one of Ta, Al, TiN, W, TaN or other conductive materials, located on the HZO ferroelectric layer 2;

[0054] S5: The LDD region 10 of the second type of gate stack is located at the left and right ends of the substrate 6. Its upper surface is flush with the upper surface of the substrate 6. It is a surface-based Gaussian doping with a surface doping concentration of y.

[0055] S6: Si3N4 or other dielectric material forms a sidewall 11, located on the substrate 6, and is connected to the gate electrode formed by the insulating dielectric layer 3, the ferroelectric layer 2, and the gate electrode 1;

[0056] S7: The third type of doped drain region 5 and source region 9 are located at the left and right ends of the Si substrate 6. Their upper surfaces are flush with the upper surface of the Si substrate. They are surface-based Gaussian doped with a surface doping concentration of z.

[0057] S8: Substrate electrode 7, located on the lower surface of Si substrate 6;

[0058] S9: Source electrode 8 and drain electrode 4 are located on drain region 5 and source region 9, respectively;

[0059] The selected three types of doping concentrations must satisfy the condition z>y>x, with the first type of doping being P-type and the second and third types being N-type doping. The second type of doping surface area is the upper surface region of substrate 6 excluding the gate. The third type of doping surface area is the upper surface region of substrate 6 excluding the gate and sidewall 11.

[0060] The second type of doped surface area refers to the upper surface region of the Si substrate 6 excluding the gate. In this specific embodiment, the surface doping concentration y = 1 × 10⁻⁶. 18 cm -3 The doping depth is 6nm.

[0061] The third type of doped surface area refers to the upper surface region of the Si substrate 6 excluding the gate and sidewall 11. In this specific embodiment, the surface doping concentration z = 1 × 10⁻⁶. 20 cm -3 The doping depth is 15nm.

[0062] The insulating layer 3 is composed of one or more of SiO2, Si3N4, Al2O3, ZrO2, and HfO2, with a thickness b between 0.8 nm and 2.5 nm. In this specific embodiment, SiO2 is selected, and the thickness b is 1 nm.

[0063] The HZO ferroelectric layer 2 is either Zr-doped HfO2 or Zr-doped HfO2 doped with a second element, which can be one of Si, Al, Zr, La, Ce, Sr, Lu, Gd, Sc, or other doping elements. Its thickness c is between 6 nm and 30 nm. In this specific embodiment, Zr-doped HfO2 is selected, with a thickness c of 10 nm.

[0064] In this embodiment, the modeling of the ferroelectric layer of the FeFET adopts the dynamic polarization modeling method proposed in this invention, and the relevant test results are shown in Figure 4. First, under a sufficiently large pulse width, voltage pulses of different amplitudes are applied to the FeFET gate. A negative (erase) pulse is applied first to regulate the polarization state of the ferroelectric layer. After removing the pulse, a fast scan voltage (range -1.0V~2.5V, scan rate 5V / μs) is used to test and obtain the Id-Vg curve of the FeFET. Then, a positive (programming) pulse of the same amplitude is applied to regulate the polarization state of the ferroelectric layer again. After removing the pulse, another Id-Vg curve is obtained using the same fast scan method. The results show that the turn-on current Ion of this FeFET is within 10... -4FeFETs with drain currents on the order of A / μm, i.e., those designed with LDD doping, exhibit relatively large drain currents after conduction. Further analysis shows that the larger the gate pulse voltage amplitude, the higher the dipole switching ratio within the ferroelectric layer, resulting in a more significant change in the FeFET's threshold voltage and a corresponding expansion of the storage window. Besides the gate pulse amplitude, the pulse width is also a key factor affecting the storage window. Therefore, while keeping the gate pulse voltage amplitude fixed at ±4V, pulses with different widths were applied, and the Id-Vg curve of the FeFET was tested again. The results show that insufficient pulse width leads to a shift in the FeFET's threshold voltage, thereby causing changes in the storage window; however, once the pulse width reaches a sufficient value, further increasing the pulse width does not cause significant changes in the FeFET's Id-Vg characteristic curve. Therefore, the ferroelectric modeling method involved in this invention can effectively predict curve drift, thereby accurately obtaining the threshold voltage of the FeFET under different gate pulse conditions, and has certain guiding value.

[0065] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of the present invention and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of the present invention should be included within the protection scope of the present invention.

Claims

1. A modeling method for ferroelectric field-effect transistors. Its characteristic is that... The ferroelectric field-effect transistor features include: S1: The first type of doping forms a substrate (6), which is a uniformly doped intrinsic silicon with a doping concentration of x; S2: Insulating dielectric layer (3), located on substrate (6), with a thickness of b and a width of w; S3: HZO ferroelectric layer (2), located on the insulating layer (3), with a thickness of c; S4: Gate electrode (1), composed of one of Ta, Al, TiN, W, TaN or other conductive materials, located on the HZO ferroelectric layer (2); S5: The second type of doped LDD region (10) is located at the left and right ends of the substrate (6). Its upper surface is flush with the upper surface of the substrate (6). It is a surface-based Gaussian doping with a surface doping concentration of y. S6: Si3N4 or other dielectric materials form a sidewall (11) on the substrate (6) and are connected to the gate formed by the insulating dielectric layer (3), the ferroelectric layer (2) and the gate electrode (1); S7: The third type of doped drain region (5) and source region (9) are located at the left and right ends of the Si substrate (6). Their upper surfaces are flush with the upper surface of the Si substrate. They are surface-based Gaussian doped with a surface doping concentration of z. S8: Substrate electrode (7), located on the lower surface of the Si substrate (6); S9: The source electrode (8) and the drain electrode (4) are located on the drain region (5) and the source region (9), respectively.

2. The ferroelectric field-effect transistor based on lightly doped drain (LDD) design according to claim 1, and its ferroelectric polarization modeling method, is characterized in that... The selected three types of doping concentrations must satisfy the condition z>y>x, and the first type of doping must be P-type doping, while the second and third types of doping must be N-type doping.

3. The ferroelectric field-effect transistor based on lightly doped drain (LDD) design and its ferroelectric polarization modeling method according to claim 1, characterized in that... The second type of doped surface range is the upper surface region of the substrate (6) excluding the gate.

4. The ferroelectric field-effect transistor based on lightly doped drain (LDD) design according to claim 1, and its ferroelectric polarization modeling method, is characterized in that... The third type of doped surface range is the upper surface region of the substrate (6) excluding the gate and sidewall (11).

5. The ferroelectric field-effect transistor based on lightly doped drain (LDD) design and its ferroelectric polarization modeling method according to claim 1, characterized in that... The insulating layer (3) is composed of one or more of SiO2, Si3N4, Al2O3, ZrO2, and HfO2, and its thickness b is between 0.8nm and 2.5nm.

6. The ferroelectric field-effect transistor based on lightly doped drain (LDD) design and its ferroelectric polarization modeling method according to claim 1, characterized in that... The HZO ferroelectric layer (2) is either Zr-doped HfO2 or Zr-doped HfO2 with a second element doped on top. The second element can be one of the following: Si, Al, Zr, La, Ce, Sr, Lu, Gd, Sc, or other doping elements. Its thickness c is between 6 nm and 30 nm.

7. A method for modeling ferropolarization, characterized by the following steps: Step 1: Establish the classical ferroelectric Preisach model and determine the historical static model of ferroelectricity; Step 2: Introduce the polarization relaxation time parameter τ to determine the ferropolarization dynamic model.

8. The ferropolarization modeling method according to claim 7, step 1 includes the following features: Establish the classical ferroelectric Preisach model and determine the historical static model of ferroelectricity. The effective polarization value P of the ferroelectric layer after applying an arbitrary electric field under quasi-static conditions aux for: Where F aux P is the effective voltage of the ferroelectric capacitor acting on the polarization. s It is the magnitude of the saturation polarization of the ferroelectric layer, P r It is the magnitude of the remanent polarization of the ferroelectric layer, F c It is the coercive field size of the ferroelectric layer; c and P off These are parameters related to the Preisach function. w can be given by the following formula: For F c P s P r The experimental parameters can be extracted by obtaining the static saturation QV curve through quasi-static triangular wave scanning, and the QV curve can be obtained by obtaining the PV curve through the following physical calculation: The dielectric constant ε of ferroelectric materials can be obtained by measuring small signals at low frequencies. r The maximum inflection point of saturation on the PV curve was used to confirm P. s Confirm F at the intersection of the x-axis and y-axis c P r .

9. The ferropolarization modeling method according to claim 7, step 2 includes the following features: By introducing the polarization relaxation time parameter τ, the dynamic model of ferropolarization is determined, as shown in the following formula: Where F(t) is the applied voltage on the ferroelectric layer, F aux (t) is the effective voltage of the ferroelectric capacitor used for calculating ferroelectric polarization, and τ is the relaxation time from the applied voltage to the effective voltage of the ferroelectric capacitor. The formula for calculating τ is as follows: Where τ ∞ V0 and m are fixed parameters related to ferroelectric materials, independent of external conditions, and only related to the polarization properties of the domains within the ferroelectric layer, and F aux =V aux / T fe T fe The thickness of the ferroelectric layer is given. These fixed parameters can be obtained through ferroelectric domain flipping experiments. By analyzing multiple sets of ferroelectric domain flipping test data with different voltage amplitudes, the fixed parameters of the ferroelectric material can be obtained through mathematical fitting. τ can then determine P. aux The dynamic relaxation time is obtained, thus revealing the dynamic changes in ferropolarization.

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