Differential protection function test method and system based on remote data synchronization

Abstract

The invention discloses a differential protection function test method and system based on remote data synchronization, and relates to the technical field of power system relay protection tests.The method comprises the steps that host and slave test devices are deployed remotely, and communication is established through standby optical fibers; the host test device responds to the configuration parameters to generate two-dimensional test data, synchronizes the two-dimensional test data to the slave test device and calculates channel delay; based on the FPGA logic architecture and channel delay, the two test devices synchronously output test data to the differential protection device; the system comprises a remote testing device, a differential protection device and a standby optical fiber link, the testing device is integrated with a plurality of functional units such as an FPGA, the method supports fault-tolerant recovery, multi-scene expansion and result analysis, the remote synchronous testing problem is solved, the testing accuracy and comprehensiveness are improved, and the testing efficiency is improved. The method is suitable for substation differential protection function verification.

Description

Technical Field

[0001] This application relates to the field of power system relay protection testing technology, and in particular to a differential protection function testing method and system based on remote data synchronization. Background Technology

[0002] Differential protection is the core protection method for key equipment in power systems (such as lines and transformers). Its working principle is based on comparing the vector sum of the currents at each end of the protected equipment: when there is a fault within the zone, the vector sum of the currents at each end is not zero, and the protection device starts to operate; when there is a fault outside the zone, the vector sum is theoretically zero, and the protection device does not operate. The operating characteristics of differential protection are determined by the two-dimensional curve of differential current (the vector sum of the currents on both sides of the line) and restraining current (the sum of the absolute values ​​of the currents on both sides of the line). The restraining current is used to prevent false operation caused by external faults.

[0003] In practical applications, a group of differential protection devices are usually distributed in different substations, with a large physical distance between them. Traditional testing methods can only perform single-sided, single-end calibration, which has many shortcomings. It can only simulate faults within the zone and cannot verify fault conditions outside the zone. Single-sided calibration results in the braking current always being half of the differential current, making it impossible to fully verify the braking characteristics. It is difficult to simulate protection actions under various load conditions. It is impossible to quickly obtain the protection action status on the other side and compare the action delays on both sides. These problems lead to incomplete calibration of differential protection functions and pose safety hazards.

[0004] In existing related technologies, some solutions adopt multi-group test unit joint debugging or wireless synchronization architecture, but they have problems such as low synchronization accuracy, weak anti-interference ability, and failure to achieve full-scenario verification. For example, some solutions rely on satellite time synchronization, which has a second-level delay error; some solutions use wireless communication to transmit data, which is susceptible to interference and has large delay fluctuations; some solutions do not build structured two-dimensional test data, which cannot fully cover the braking characteristic curve. Therefore, there is an urgent need for a differential protection function test solution based on remote data synchronization to solve the verification problem caused by geographical distribution limitations. Summary of the Invention

[0005] This application provides a method and system for testing differential protection functions based on remote data synchronization, in order to solve the problem of remote synchronization testing, improve the accuracy and comprehensiveness of testing, and is applicable to the verification of differential protection functions in substations.

[0006] In a first aspect, embodiments of this application provide a differential protection function testing method based on remote data synchronization, applied to a pre-deployed testing device. The testing device is configured as a master testing device and a slave testing device, located in different substations and connected via a backup optical fiber. The master testing device and the slave testing device are respectively wired to the differential protection device to be functionally tested. The method includes: The host testing device responds to the received configuration test parameters, generates two-dimensional test data with braking current and output current as dimensions based on the configuration test parameters, and stores the two-dimensional test data. The host testing device transmits the two-dimensional test data to the slave testing device for storage via the backup optical fiber, and receives the data reception time feedback from the slave testing device. The host testing device calculates the channel delay based on the data reception time and the transmission time of the two-dimensional test data, and synchronizes it with the slave testing device. The host test device and the slave test device, based on the set FPGA logic architecture and the channel delay, respectively control the output of the two-dimensional test data to the waveform generator. The waveform generator parses the two-dimensional test data, generates an analog current waveform, and outputs it to the differential protection device. The host test device and the slave test device respectively monitor the action response status of the differential protection device, record the test results, and then synchronize the test results to complete the functional verification of the differential protection device based on the results of the data synchronization.

[0007] Furthermore, the testing device is configured to be divided into a host testing device and a slave testing device, including: The testing device receives a master control setting instruction and designates any one of the testing devices as the host testing device. The host testing device sends a configuration command to another testing device through the backup optical fiber. The configuration command includes a role identifier and synchronization parameters. Another of the aforementioned test devices receives the configuration command and parses the command content, automatically switches to the slave test device mode, and completes the role configuration.

[0008] Furthermore, in response to the received configuration test parameters, the host testing device generates two-dimensional test data with braking current and output current as dimensions, including: The host testing device responds to the received configuration test parameters through a set interactive interface. The configuration test parameters include the current amplitude range, the change step size, and the test duration. Based on the configured test parameters, with braking current as the first dimension and output current as the second dimension, two-dimensional test data is constructed. The two-dimensional test data includes a frame header and test point data. The frame header includes data identifier, parameter number and test duration information. The test point data includes amplitude, frequency and phase parameters.

[0009] Further, the host testing device calculates the channel delay based on the data reception time and the transmission time of the two-dimensional test data, including: The host testing device sends the two-dimensional test data to the slave testing device and records the time when the two-dimensional test data is sent. After receiving the two-dimensional test data, the slave test device immediately returns the data reception time to the host test device; The host testing device records the data reception time and the transmission time of the two-dimensional test data, and calculates the channel delay based on the time difference.

[0010] Furthermore, the host testing device and the slave testing device, based on the set FPGA logic architecture and the channel delay, control the read and write operations of the two-dimensional test data before sending it to the waveform generator, including: The host testing device reads the two-dimensional test data from the shared storage unit through its memory read / write unit, parses the two-dimensional test data flag bits, array number and number of test points, and writes them into the waveform output buffer according to the rules. The data feature buffer of the host testing device synchronously records the test point status identifiers of the two-dimensional test data. The first test point corresponds to the start identifier, and subsequent test points correspond to the normal identifier.

[0011] Furthermore, the host testing device and the slave testing device, based on the configured FPGA logic architecture and the channel delay, respectively control the output of the two-dimensional test data to be sent to the waveform generator. The waveform generator, after parsing the two-dimensional test data, generates an analog current waveform and outputs it to the differential protection device, including: After the output control unit of the host test device detects that there is two-dimensional test data in the waveform output buffer, it sends a test point instruction to the slave test device to read the two-dimensional test data and starts timing. When the timing value is equal to the channel delay, the host test device reads the two-dimensional test data from the waveform output buffer and sends it to the waveform generator. After receiving the test point instruction for reading the two-dimensional test data through the fiber optic interface unit, the slave test device immediately reads the two-dimensional test data from its own waveform output buffer and sends it to the waveform generator. The waveform generator of the slave test device generates an analog current waveform based on the analyzed amplitude, frequency and phase parameters and outputs it to the analog input interface of the differential protection device.

[0012] Furthermore, the host testing device and the slave testing device respectively monitor the action response status of the differential protection device and record the test results, including: The trip monitoring unit of the master test device and the slave test device monitors the trip signal of the differential protection device of their respective substations in real time, and immediately feeds back the trip signal to the test monitoring control unit after detecting the trip signal; The test monitoring and control unit records the current test point group number, waveform parameters and trip time. If no trip signal is detected, it records the test point parameters and test duration. The test monitoring and control unit synchronizes the recorded information to the shared storage unit to form structured test result data.

[0013] Furthermore, after the host test device and the slave test device control the output of the two-dimensional test data to the waveform generator based on the set FPGA logic architecture and the channel delay, and the waveform generator parses the two-dimensional test data to generate an analog current waveform and outputs it to the differential protection device, the method further includes fault tolerance and recovery steps: The host test device and the slave test device's test monitoring and control unit monitor the communication status of the fiber optic interface unit and the operating status of each unit in real time. If a communication interruption or equipment failure is detected, an alarm signal will be issued immediately, and the backup synchronization mechanism will be activated at the same time. After troubleshooting, based on the two-dimensional test data and progress information stored in the shared storage unit, the two-dimensional test data is read again through the memory read / write unit to continue the unfinished test process.

[0014] Furthermore, after completing the functional verification of the differential protection device based on the data synchronization results, the method also includes a test result analysis step: The host test device and the slave test device synchronize test result data bidirectionally through the fiber optic interface unit and integrate them to form a complete two-dimensional test dataset. Two-dimensional action characteristic curves of differential current and braking current are generated based on the aforementioned two-dimensional test dataset; Simulate the protection actions under in-zone faults, out-of-zone faults, and load conditions, and analyze the differences in braking characteristic parameters and action delays. The output includes a test report containing two-dimensional motion characteristic curves, motion delay comparison analysis, and fault simulation verification results.

[0015] Furthermore, following the test result analysis step, the method also includes a multi-scenario extended testing step: Configure test parameter combinations for different fault types, load levels, and boundary conditions; According to the preset scenario sequence, the corresponding two-dimensional test data are generated sequentially, and the output and status monitoring of the two-dimensional test data are completed through the collaborative work of each FPGA unit. The results of tests in multiple scenarios were summarized to analyze the adaptability and reliability of the differential protection device.

[0016] In a second aspect, embodiments of this application provide a differential protection function testing system based on remote data synchronization, comprising: The testing devices are set up in different substations. The testing devices are configured as a master testing device and a slave testing device. Both the master testing device and the slave testing device have built-in FPGA logic modules, shared storage units and interactive interfaces. The FPGA logic modules include memory read and write units, waveform output buffers, data feature buffers, output control units, waveform generators, trip monitoring units, test monitoring control units and fiber optic interface units. Differential protection devices are installed in different substations and are wiredly connected to the master test device and the slave test device of their respective substations. They are used to receive two-dimensional test data output by the master test device and the slave test device and perform protection actions. A backup fiber optic communication link is used to establish a communication connection between the host test device and the slave test device, so as to realize the two-dimensional test data transmission, synchronous command interaction, data reception time feedback and test result feedback. The host testing device generates and stores two-dimensional test data with braking current and output current as dimensions based on the configured test parameters, and sends the two-dimensional test data to the slave testing device for storage through the backup optical fiber communication link. The host testing device records the transmission time of the two-dimensional test data, and the slave testing device receives the two-dimensional test data and then feeds back the reception time of the two-dimensional test data. The host testing device calculates the channel delay based on the transmission time and the reception time and synchronizes it with the slave testing device. The host test device and the slave test device, based on the set FPGA logic architecture and the channel delay, respectively control the output of the two-dimensional test data to the waveform generator. The waveform generator parses the two-dimensional test data, generates an analog current waveform, and outputs it to the differential protection device. The host test device and the slave test device respectively monitor the action response status of the differential protection device, record the test results, and then synchronize the test results to complete the functional verification of the differential protection device based on the results of the data synchronization.

[0017] In a third aspect, embodiments of this application provide an electronic device, including: a memory and one or more processors; The memory is used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement a differential protection function test method based on remote data synchronization as described in the first aspect.

[0018] In a fourth aspect, embodiments of this application provide a storage medium for storing computer-executable instructions, which, when executed by a computer processor, are used to perform a differential protection function test method based on remote data synchronization as described in the first aspect.

[0019] This application establishes a stable communication link by deploying host and slave test devices in different locations and using backup optical fibers. The host test device generates structured two-dimensional test data containing braking current and output current dimensions and synchronizes it to the slave test device. Channel delay is accurately calculated by combining transmission and reception times. Then, an FPGA logic architecture controls the two test devices to synchronously output test data, overcoming the geographical limitations of traditional single-sided, single-end load scaling. It can reproduce fault conditions outside the testing area by adjusting the current vector and simulating faults within the testing area, and can also accurately configure the ratio of braking current to differential current to reproduce fault conditions outside the testing area. This solves the problems of traditional methods being unable to verify faults outside the testing area and incomplete coverage of braking characteristics. Because the two-dimensional test data includes multiple parameter test points such as amplitude, frequency, and phase, different fault types, load levels, and boundary conditions can be flexibly configured to achieve comprehensive simulation of various complex load conditions. This approach addresses the shortcomings of traditional methods in reproducing diverse operating conditions. Because two testing devices monitor the differential protection response of their respective substations in real time, recording tripping times, waveform parameters, and other information with bidirectional synchronization, they can directly compare the delay differences between the two sides, generating a complete two-dimensional action characteristic curve. This solves the problems of traditional methods being unable to quickly obtain the action status of the other side and analyze delay differences. Simultaneously, a backup fiber optic communication link ensures data transmission anti-interference capabilities, avoiding delay fluctuations in wireless transmission. The FPGA architecture achieves microsecond-level synchronization accuracy, far exceeding the second-level error of satellite time synchronization. Fault tolerance and recovery mechanisms ensure test continuity through shared storage units. Multi-scenario extended testing comprehensively verifies the adaptability of the protection device, fundamentally improving the comprehensiveness, accuracy, and reliability of differential protection function verification and eliminating safety hazards left by traditional testing. Attached Figure Description

[0020] Figure 1 This is a flowchart of a differential protection function test method based on remote data synchronization provided in an embodiment of this application; Figure 2 This is a flowchart of the fault tolerance and recovery steps of a differential protection function test method based on remote data synchronization provided in an embodiment of this application; Figure 3 This is a flowchart of the test result analysis steps of a differential protection function test method based on remote data synchronization provided in an embodiment of this application; Figure 4 This is a flowchart of the multi-scenario extended test steps of a differential protection function test method based on remote data synchronization provided in an embodiment of this application; Figure 5 This is a structural diagram of a differential protection function test system based on remote data synchronization provided in an embodiment of this application; Figure 6 This is a structural diagram of the built-in FPGA logic module of the testing device provided in the embodiments of this application; Figure 7 This is a structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but additional steps not included in the drawings may also be present. The above processes can correspond to methods, functions, procedures, subroutines, subroutines, etc.

[0022] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. For ease of understanding, this embodiment uses a testing device as the main body for performing a differential protection function test method based on remote data synchronization. Differential protection is the core protection method for key equipment in power systems (such as lines and transformers). Its working principle is based on comparing the vector sum of the currents at each end of the protected equipment: when there is a fault within the zone, the vector sum of the currents at each end is not zero, and the protection device starts to operate; when there is a fault outside the zone, the vector sum is theoretically zero, and the protection device does not operate. The operating characteristics of differential protection are determined by the two-dimensional curve of differential current (the vector sum of the currents on both sides of the line) and restraining current (the sum of the absolute values ​​of the currents on both sides of the line). The restraining current is used to prevent false operation caused by external faults. In practical applications, a group of differential protection devices are usually distributed in different substations, with a long physical distance between them. Traditional testing methods can only perform single-sided, single-end calibration, which has many drawbacks: it can only simulate faults within the zone and cannot verify fault conditions outside the zone; single-sided calibration results in the braking current always being half of the differential current, making it impossible to fully verify the braking characteristics; it is difficult to simulate protection actions under various load conditions; it is impossible to quickly obtain the protection action status on the other side and compare the action delays on both sides. These problems lead to incomplete calibration of the differential protection function and pose safety hazards. In existing related technologies, some solutions adopt multi-group test unit joint debugging or wireless synchronization architecture, but they have problems such as low synchronization accuracy, weak anti-interference ability, and failure to achieve full-scenario verification. For example, some solutions rely on satellite time synchronization, which has a second-level delay error; some solutions use wireless communication to transmit data, which is susceptible to interference and has large delay fluctuations; some solutions do not construct structured two-dimensional test data, which cannot fully cover the braking characteristic curve. Therefore, there is an urgent need for a differential protection function test solution based on remote data synchronization to solve the verification problem caused by geographical distribution limitations. Based on this, this embodiment provides a differential protection function test method and system based on remote data synchronization to solve the above-mentioned technical problems. Figure 1 For a flowchart illustrating a differential protection function test method based on remote data synchronization provided in this application embodiment, please refer to [link / reference]. Figure 1This includes steps such as role configuration, data generation, synchronous transmission, latency calculation, and synchronous output result monitoring, specifically including: Step S101: In response to the received configuration test parameters, the host test device generates two-dimensional test data with braking current and output current as dimensions based on the configuration test parameters, and stores the two-dimensional test data.

[0023] The testing device receives master control setting instructions. Taking a tester as an example, this application's testing device can designate any one of the test devices as the master test device. The master control setting instructions can be manually entered by the operator through the interactive interface of the testing device, or they can be uniformly issued by the remote monitoring center. For example, after the test devices are deployed in substation A and substation B respectively, the operator can enter instructions through the interactive interface of the test device in substation A to designate that device as the master test device; or instructions can be sent to any one of the test devices through the remote control platform to complete the master designation, flexibly adapting to on-site testing needs.

[0024] The host test device sends configuration instructions to another test device via a backup optical fiber. The configuration instructions include a role identifier and synchronization parameters. The role identifier clearly informs the receiver that it will act as a slave test device and uses a unique encoding format. The synchronization parameters include the communication baud rate, data frame format, and synchronization clock reference (based on the host test device's local clock), ensuring that the subsequent communication parameters of the two test devices are consistent. The configuration instructions can use CRC-32 verification to avoid data errors during transmission and ensure the integrity and reliability of the instruction transmission. Another test device receives the configuration command and parses the command content. It automatically switches to slave test device mode and completes the role configuration. After parsing, the slave test device sends a configuration success confirmation signal to the master test device, which includes the slave test device number and synchronization parameter confirmation information. After receiving the signal, both devices enter the collaborative test preparation state and establish a master-slave communication relationship.

[0025] Step S102: The host testing device sends the two-dimensional test data to the slave testing device for storage through the backup optical fiber, and receives the data reception time fed back by the slave testing device.

[0026] The host testing device responds to received configuration test parameters through a set interactive interface. These parameters include the current amplitude range, step size, and test duration. The interface is a touchscreen display supporting multi-touch operation. Operators can directly input parameters or select them via drop-down menus. The current amplitude range is determined based on the rated current of the differential protection device, for example, 0-50A, adapting to differential protection devices of different capacities. The step size determines the test accuracy and can be set to multiple levels such as 0.1A, 0.5A, and 1A; the smaller the step size, the higher the test accuracy. The test duration, i.e., the holding time for each test point, is typically set to 200ms-1s to ensure the differential protection device has sufficient time to respond to the test signal, avoiding distorted test results due to insufficient response. Based on the configured test parameters, with braking current as the first dimension and output current as the second dimension, two-dimensional test data is constructed. The construction of the two-dimensional test data adopts a matrix approach. First, the range and step size of the braking current are divided into 20 levels, such as a braking current range of 0-40A and a step size of 2A. Then, for each braking current level, the corresponding output current value is generated according to the range and step size of the output current, forming a matrix-style two-dimensional test data that covers the operating characteristic curve range of the differential protection device. The two-dimensional test data includes a frame header and test point data, both organized in 128-bit units to ensure standardized data transmission and storage. The frame header contains a data identifier, parameter number, and test duration information. The data identifier is a unique code used to distinguish test data from different batches. The parameter number identifies the position of the test point in the two-dimensional data matrix. The test duration information is consistent with the test duration in the configuration parameters. The test point data includes amplitude, frequency, and phase parameters. The amplitude corresponds to the specific value of the output current. The frequency defaults to the standard frequency of the power system, but can be adjusted according to test requirements. The phase parameter is used to simulate different fault types, such as a 0° phase difference between the currents on both sides during an in-zone fault and a 180° phase difference during an out-of-zone fault.

[0027] After the two-dimensional test data is generated, the host test device stores it in the built-in shared storage unit. The data is stored in a structured format, classified and stored according to the directory structure of braking current range - output current range. The data of each test point is stored in a separate file. The file name contains information such as data identifier and parameter number, which facilitates quick retrieval and reading. Step S103: The host testing device calculates the channel delay based on the data reception time and the transmission time of the two-dimensional test data, and synchronizes with the slave testing device.

[0028] The host testing device transmits two-dimensional test data to the slave testing device for storage via a backup optical fiber. The backup optical fiber link uses single-mode fiber, which can ensure the fast and stable transmission of a large amount of two-dimensional test data. During data transmission, a segmented transmission mechanism is adopted, and the two-dimensional test data is transmitted in segments of 1024 bytes each. A 16-byte header information is added before each data block, including the data block number, data length, checksum, etc. The data is transmitted block by block and checked. If the slave testing device detects a data block check error, it immediately requests a retransmission from the host testing device to ensure the integrity of data transmission. After receiving the two-dimensional test data, the slave test device immediately returns the data reception time to the host test device. The slave test device has a built-in clock module, and the data reception time records the moment when the last data block passes verification. It then encapsulates this timestamp into a feedback data packet and sends it to the host test device to ensure the accuracy of the time recording. The host testing device records the data reception time and the transmission time of the two-dimensional test data. The channel delay is calculated based on the time difference. The transmission time is the moment the first data block begins transmission, also recorded by the clock module of the host testing device. The channel delay calculation formula is: ,in For the sending time, The data reception time is divided by 2 because data transmission is a round trip. This calculation method can obtain the channel delay in one direction, avoiding synchronization errors caused by round trip transmission delay. The host test device sends the calculated channel delay to the slave test device via a backup optical fiber. After receiving the signal, the slave test device adjusts its output timing to synchronize with the host test device, ensuring that the subsequent data output times of the two test devices are consistent.

[0029] Step S104: The host test device and the slave test device, based on the set FPGA logic architecture and the channel delay, control the output of the two-dimensional test data to the waveform generator. The waveform generator parses the two-dimensional test data, generates an analog current waveform, and outputs it to the differential protection device.

[0030] The host test device reads two-dimensional test data from the shared storage unit using its memory read / write unit, and parses the two-dimensional test data flag bits, array numbers, and number of test points. The data is then written to the waveform output buffer according to the rules. The memory read / write unit uses DMA technology. During the parsing process, the flag bits are used to verify the validity of the data and use a fixed identifier "0x55". If the flag bits do not match, the data is considered invalid. The array number corresponds to the braking current level, and the number of test points specifies the number of output current test points for each level. The waveform output buffer uses a FIFO structure with an input bit width of 128 bits and an output bit width of 8 bits to ensure the continuity of data output and avoid output interruptions caused by untimely data reading. The data feature buffer of the host test device synchronously records the test point status identifiers of the two-dimensional test data. The first test point is written with the start identifier (8'h01), and subsequent test points are written with the normal identifier (8'h00). The data feature buffer and the waveform output buffer are read and written synchronously. The input bit width is 8 bits and the output bit width is 1 bit. Each time a test point data is written to the waveform output buffer, the corresponding identifier is written to the data feature buffer, which makes it easy for the output control unit to identify the start and normal output status of the test point and provide accurate status feedback for synchronous control. After the output control unit of the host test device detects two-dimensional test data in the waveform output buffer, it sends a test point instruction to the slave test device to read the two-dimensional test data and starts timing. The test point instruction includes information such as the test point number to be output, data length, and synchronization identifier. Encrypted transmission is used to prevent the instruction from being tampered with. The timing uses the timer inside the FPGA to ensure timing accuracy and provide an accurate time reference for channel delay compensation. Once the timing value equals the channel delay, the host test device reads the two-dimensional test data from the waveform output buffer and sends it to the waveform generator. The waveform generator uses a D / A conversion chip, which can convert digital test data into analog current waveforms. The waveform distortion and output current range meet the analog input requirements of the differential protection device. After receiving the test point command to read the two-dimensional test data through the fiber optic interface unit, the slave test device immediately reads the two-dimensional test data from its own waveform output buffer and sends it to the waveform generator. The waveform output buffer data of the slave test device is completely consistent with that of the master test device, which are both two-dimensional test data that were previously received and stored synchronously. There is no need to wait. Through this master timing compensation and slave instant response method, the synchronous output of the two test devices is achieved with small synchronization error.

[0031] The waveform generator of the slave test device generates a simulated current waveform based on the analyzed amplitude, frequency, and phase parameters and outputs it to the analog input interface of the differential protection device. The simulated current waveforms output by the two test devices correspond to the current inputs at both ends of the differential protection device, simulating the current conditions on both sides of the line in the power system. For example, when simulating a fault within the simulated zone, the currents on both sides are in phase and their amplitudes are superimposed; when simulating a fault outside the simulated zone, the currents on both sides are in opposite phases and their amplitudes cancel each other out, covering the test requirements of different fault scenarios.

[0032] Step S105: The host test device and the slave test device respectively monitor the action response status of the differential protection device, record the test results, and then synchronize the test results to complete the functional verification of the differential protection device based on the results of the data synchronization.

[0033] The trip monitoring units of the master test device and the slave test device monitor the trip signals of the differential protection devices in their respective substations in real time. The trip monitoring unit adopts a high-speed optocoupler isolation circuit, which can quickly capture the trip output signal (dry contact signal or level signal) of the differential protection device, avoiding signal missed detection. The optocoupler isolation circuit has a high isolation voltage, which effectively suppresses electromagnetic interference and ensures normal operation in the complex electromagnetic environment of the substation. Upon detecting a trip signal, the system immediately sends a feedback signal to the test monitoring and control unit. The feedback signal includes key information such as the trip occurrence time and the corresponding test point number. The test monitoring and control unit receives the signal and processes it in real time to avoid time recording errors caused by signal transmission delays.

[0034] The test monitoring and control unit records the current test point group number, waveform parameters, and trip time. The test point group number corresponds to the braking current and output current range of the two-dimensional test data. The waveform parameters include the amplitude, frequency, and phase of the output current. This provides data for analyzing the protection action delay. If no trip signal is detected, the test point parameters and test duration are recorded to confirm that the protection device did not operate at that test point, thus forming a complete test record and avoiding omission of test results. The test monitoring and control unit synchronizes the recorded information to the shared storage unit to form structured test result data. The structured data is stored in JSON format and includes fields such as test time, test point parameters, protection action status (action or no action), action time (empty when no action is taken), and waveform parameters.

[0035] The host test device and the slave test device synchronize test result data bidirectionally through the backup fiber optic interface unit. The data synchronization adopts an incremental synchronization mechanism, which only transmits newly added test result data (i.e., test records added after the last synchronization), reducing the amount of data transmission and improving synchronization efficiency. During the synchronization process, a data verification and comparison mechanism is adopted. Both parties verify the synchronized data. If data inconsistency is found, it is automatically retransmitted to ensure that the received data is complete and accurate. After both parties complete data synchronization, they integrate to form a complete two-dimensional test dataset. The complete dataset covers the protection action status of all test points, including test results under different load conditions, including faults within the zone, faults outside the zone, and different load conditions, providing comprehensive data for the functional verification of the main differential protection device. Based on a complete two-dimensional test dataset, the function of the differential protection device is verified. The verification includes: whether the differential protection device operates accurately under fault conditions within the zone; whether the braking function is effective and whether the protection device malfunctions under fault conditions outside the zone; whether the operating characteristics of the protection device meet the design requirements under different load currents; and whether the operating delay of both protection devices is within the allowable range. For example, if the differential protection device can operate within the specified time at the test point corresponding to the fault within the zone, it indicates that its fault protection function within the zone is normal; if the protection device does not operate at the test point corresponding to the fault outside the zone, it indicates that the braking function is effective; if there are test points with abnormal operation, the corresponding test parameters and operation conditions are recorded to provide a basis for fault analysis.

[0036] Please see Figure 2 The differential protection function testing method based on remote data synchronization provided in this application embodiment further includes a fault-tolerant recovery step, including: Step S701: The test monitoring and control unit of the host test device and the slave test device monitors the communication status of the fiber optic interface unit and the operating status of each unit in real time.

[0037] The test monitoring and control unit of the host test device and the slave test device monitors the communication status of the fiber optic interface unit and the operating status of each unit in real time. The communication status monitoring includes data transmission rate, bit error rate, link connection status, etc.; the operating status monitoring of each unit includes CPU load, memory usage, power supply voltage, module temperature, etc., including key system operating parameters. Step S702: If a communication interruption or equipment failure is detected, an alarm signal is immediately issued, and the backup synchronization mechanism is activated at the same time.

[0038] If a communication interruption or equipment failure is detected, an alarm signal is immediately issued via an audible and visual alarm device, which continues to sound until the fault is resolved. Simultaneously, alarm information is uploaded to the remote monitoring center, including the fault type (e.g., communication interruption, high memory usage, and power failure), the time of occurrence, and the fault location (e.g., the host test device - fiber optic interface unit). This facilitates quick fault location by operators. A backup synchronization mechanism is also activated. If the fault is a communication interruption, a backup 4G / 5G communication link is activated to ensure the transmission of test data and control commands. If the fault is a functional unit failure (e.g., a waveform generator failure in the host test device), the system switches to a redundant unit to continue operation. The redundant unit has the same performance as the main unit, ensuring uninterrupted testing.

[0039] Step S703: After troubleshooting, based on the two-dimensional test data and progress information stored in the shared storage unit, the two-dimensional test data is read again through the memory read / write unit to continue the unfinished test process.

[0040] After troubleshooting, the two-dimensional test data and progress information stored in the shared storage unit are used to restore the reading of the two-dimensional test data through the memory read / write unit. The progress information records the test progress before the fault occurred, including the number of completed test points, the current test point location, and the synchronized test result data. The test device can continue the unfinished test process from the interrupted test point without having to start over, thereby improving test efficiency and reducing test time waste.

[0041] Please see Figure 3 The differential protection function test method based on remote data synchronization provided in this application embodiment also includes a result analysis step, including: Step S801: The host test device and the slave test device synchronize test result data bidirectionally through the fiber optic interface unit and integrate them to form a complete two-dimensional test dataset.

[0042] The host test device and the slave test device synchronize test results data bidirectionally through the fiber optic interface unit, and integrate them to form a complete two-dimensional test dataset. The complete dataset includes the action results of each test point, as well as information such as action delay, waveform parameters, and fault simulation type. Step S802: Generate two-dimensional action characteristic curves of differential current and braking current based on the two-dimensional test dataset.

[0043] Two-dimensional operating characteristic curves of differential current and braking current are generated based on a complete two-dimensional test dataset. The two-dimensional operating characteristic curves are plotted using a plotting algorithm, such as an interpolation fitting algorithm. The horizontal axis represents the braking current, and the vertical axis represents the differential current. The curves show the operating boundaries of the differential protection device under different combinations of braking current and differential current. The area above the curve is the operating zone, and the area below the curve is the non-operating zone. After the curves are generated, they can be compared with the design operating characteristic curves of the differential protection device to analyze the deviation between the actual operating characteristics and the design requirements. The deviation value should be controlled within the threshold. If it exceeds the deviation range, the cause needs to be further analyzed. Step S803: Simulate the protection operation under faults within the zone, faults outside the zone, and load conditions, and analyze the differences in braking characteristic parameters and operation delay.

[0044] The simulation examines the protection operation under simulated faults within and outside the protection zone, as well as under load conditions. It analyzes the differences in braking characteristic parameters and operating delays. The simulated faults within the protection zone include different fault types such as three-phase short circuits, two-phase short circuits, and single-phase ground faults, analyzing the operating speed and reliability of the protection devices. The simulated faults outside the protection zone demonstrate the protection braking effect under different braking currents. The simulated load conditions include light load, rated load, and heavy load, simulating the protection response characteristics under different load levels. For example, the operating delay should not increase significantly under heavy load conditions. The analysis compares the operating time difference between the two protection devices to ensure it is within the allowable range. If the difference is too large, the synchronization accuracy of the two test devices or the hardware performance of the differential protection device needs to be checked.

[0045] Step S804: Output a test report containing two-dimensional motion characteristic curves, motion delay comparison analysis, and fault simulation verification results.

[0046] The output includes a test report containing two-dimensional motion characteristic curves, motion delay comparison analysis, and fault simulation verification results. The test report adopts a standardized format and includes the following sections: test overview (test time, test object, test personnel, test environment, etc.), test parameters (configured test parameters, synchronization parameters, etc.), test results (two-dimensional motion characteristic curves, motion statistics under various working conditions, motion delay comparison table, etc.), data analysis (comparison analysis of actual and design characteristics, analysis of the causes of motion anomalies, etc.), and conclusions and recommendations (test conclusions, optimization suggestions, subsequent test plans, etc.). It supports exporting and printing, which is convenient for technical personnel to review, archive, and make subsequent improvements.

[0047] Please see Figure 4 The differential protection function test method based on remote data synchronization provided in this application embodiment also includes a multi-scenario extended test step, including: Step S901: Configure test parameter combinations for different fault types, load levels, and boundary conditions.

[0048] The test parameter combinations are configured with different fault types, load levels, and boundary conditions. Fault types include three-phase short circuit, two-phase short circuit, single-phase ground fault, and two-phase ground fault, covering common fault forms in power systems. Load levels include light load (20% of rated load), rated load (100% of rated load), and heavy load (120% of rated load), adapting to different operating conditions. Boundary conditions include different system frequencies (45Hz, 50Hz, 55Hz), voltage levels (0.8 times rated voltage, 1.0 times rated voltage, 1.2 times rated voltage), and line impedances (0.1Ω, 0.5Ω, 1.0Ω), comprehensively verifying the adaptability of differential protection devices. Step S902: Generate the corresponding two-dimensional test data in sequence according to the preset scenario order, and complete the output and status monitoring of the two-dimensional test data through the collaborative operation of each FPGA unit.

[0049] According to the preset scenario order, the corresponding two-dimensional test data are generated sequentially. The scenario order can be set according to the test requirements. For example, fault type test can be performed first, then load level test, and finally boundary condition test. Alternatively, the scenarios can be sorted by importance priority, with key scenarios tested first. When generating two-dimensional test data, the combination of braking current and output current, as well as the amplitude, frequency, phase and other parameters of the test points, are automatically adjusted based on the preset scenario parameters, without the need for manual intervention, thus improving the degree of test automation. The FPGA unit works together to complete the output of two-dimensional test data and status monitoring. The memory read / write unit, output control unit, waveform generator and other components of the FPGA logic module work together to output test data according to the preset timing sequence. The trip monitoring unit monitors the protection action response in real time. The test monitoring control unit records the test results and synchronizes them to the shared storage unit to ensure the integrity and accuracy of the test data. Step S903: Summarize the test results of multiple scenarios and analyze the adaptability and reliability of the differential protection device.

[0050] The test results from multiple scenarios were summarized to analyze the adaptability and reliability of the differential protection device. Key indicators such as protection action rate, false action rate, failure to act rate, and action delay were statistically analyzed for each scenario. If the differential protection device can operate accurately, without false action or failure to act, and with action delay within the design allowable range in all test scenarios, it indicates that it has strong adaptability and high reliability. If false action or failure to act occurs in some scenarios, the reasons are analyzed, such as unreasonable braking characteristic parameter settings, insufficient hardware performance, and software algorithm defects, and optimization suggestions are proposed, such as adjusting protection settings, upgrading hardware modules, and optimizing software algorithms, to provide data suggestions for the improvement of differential protection devices.

[0051] Figure 5 This is a structural diagram of a differential protection function test system based on remote data synchronization provided in an embodiment of this application. Please refer to it. Figure 5 It consists of three parts: a testing device, a differential protection device, and a backup fiber optic communication link. These parts are connected via wires to form a complete testing system, specifically including: The testing devices are set up in substations A and B respectively. The testing devices are test instruments, which are divided into master test devices and slave test devices. Both have built-in FPGA logic modules, shared storage units and interactive interfaces. The hardware configurations of the two test devices are completely identical and can flexibly switch between master and slave roles. The FPGA logic module is the processing unit of the test device, which includes a memory read / write unit, waveform output buffer, data feature buffer, output control unit, waveform generator, trip monitoring unit, test monitoring and control unit, and fiber optic interface unit. Each unit is connected through an internal high-speed bus to work together to complete the reading, processing, output and status monitoring of test data, and achieve synchronous control accuracy. The shared storage unit uses high-speed SSDs to store two-dimensional test data, test result data, configuration parameters, progress information, etc. Data storage adopts partition management, which is divided into system area, data area and backup area. Redundant storage technology is used to prevent data loss and ensure data security. The interactive interface is a touch screen display that supports multi-touch operation. The interface includes a parameter configuration interface, a test control interface, a data display interface, and a report generation interface. The parameter configuration interface provides parameter input controls, such as numerical input boxes, drop-down menus, and sliders, and supports parameter saving and import. The test control interface can start, pause, and stop the test process and display the test progress. The data display interface displays test data in real time, such as the current output current amplitude, frequency, phase, and protection action status, such as whether it is activated or not, and the action delay. The report generation interface supports previewing, exporting, and printing test reports, and is easy to operate.

[0052] Differential protection devices are installed at substations A and B. These devices are relay protection equipment installed at both ends of a transmission line (or transformer, busbar, generator, etc.). They communicate with the testing devices at their respective substations via analog channels. The differential protection devices receive two-dimensional test data output from the testing devices and execute protection actions. Based on the received current signal, they determine whether a fault has occurred and quickly issue a trip command in case of a fault, disconnecting the faulty line and protecting the power system equipment. The trip command is transmitted to the testing device for trip monitoring through the trip output. The analog input interface of the differential protection device is compatible with the waveform generator output interface of the testing device to ensure accurate reception of the analog current signal.

[0053] The backup fiber optic communication link is used to establish a communication connection between the host test device and the slave test device through the fiber optic port. It adopts single-mode fiber to meet the needs of rapid transmission of large amounts of test data and control commands. The backup fiber optic communication link realizes functions such as two-dimensional test data transmission, synchronous command interaction, data reception time feedback and test result return. It adopts time division multiplexing technology to divide the transmission bandwidth into multiple time slots, which are used to transmit different types of data respectively, thereby improving bandwidth utilization. The link adopts a redundant design, including a primary link and a backup link. The primary and backup links are physically independent of each other. When the primary link fails, it automatically switches to the backup link to ensure uninterrupted communication. At the same time, the link has error detection and correction functions, and adopts CRC-32 check algorithm and forward error correction technology to ensure the reliability of data transmission and ensure the integrity of data transmission even in complex electromagnetic environments.

[0054] Figure 6 This is a structural diagram of the built-in FPGA logic module of the test device provided in this application embodiment. Please refer to it. Figure 6 The internal structure of the FPGA logic module and the connection relationships between its various units, with each unit having a clear division of labor and working collaboratively, constitute a complete FPGA logic processing system, specifically including: The memory read / write unit is used to read two-dimensional test data from the shared storage unit, parse information such as data flag bits, array number and number of test points, and write it to the waveform output buffer; at the same time, it writes test result data, such as protection action status and action time, to the shared storage unit to realize bidirectional high-speed data transmission. The memory read / write unit is connected to the test monitoring and control unit, receives start, pause, stop and other control signals from the test monitoring and control unit, and performs corresponding read / write operations according to the control signals.

[0055] The waveform output buffer adopts a FIFO storage structure with an input bit width of 128 bits and an output bit width of 8 bits. It is used to buffer the two-dimensional test data read from the memory read / write unit to ensure the continuity of data output and avoid output interruption due to untimely data reading. The waveform output buffer is connected to the memory read / write unit, the output control unit, and the waveform generator. It receives data written by the memory read / write unit, responds to the read command of the output control unit, and outputs data to the waveform generator to ensure the output of the analog current waveform. The data feature buffer works synchronously with the waveform output buffer. The input bit width is 8 bits and the output bit width is 1 bit. It is used to record the test point status identifier of the two-dimensional test data. The first test point is written with the start identifier (8'h01), and subsequent test points are written with the normal identifier (8'h00). This provides the output control unit with the start and normal output status information of the test points, so that the output control unit can accurately identify the transmission progress of the test data. The data feature buffer is connected to the memory read / write unit and the output control unit. It receives the identifier write signal from the memory read / write unit. Its write rate is consistent with that of the waveform output buffer. It outputs the status identifier to the output control unit. The output control unit is used to coordinate the working timing of each unit and realize the synchronous output control of test data. Its functions include: real-time detection of the data status (empty, half full, full) of the waveform output buffer; sending test point instructions (including test point number, synchronization identifier, etc.) to the slave test device; starting the internal timer and comparing it with the channel delay; when the timing value equals the channel delay, controlling the waveform output buffer to output data to the waveform generator. The output control unit is connected to the waveform output buffer, data feature buffer, fiber optic interface unit, and waveform generator, receives status feedback signals from each unit, and outputs corresponding control instructions to ensure that each unit works together and achieves synchronous output. The waveform generator uses a D / A converter chip to convert digital test data into high-precision analog current waveforms. It receives digital test data sent by the output control unit, analyzes parameters such as amplitude, frequency, and phase, and generates corresponding analog current waveforms to meet the test requirements of differential protection devices. The output of the waveform generator is connected to the analog input interface of the differential protection device, and a shielded cable is used to reduce the impact of electromagnetic interference on the output waveform. The trip monitoring unit adopts a high-speed optocoupler isolation circuit to monitor the trip signal of the differential protection device in real time. Its input terminal is connected to the trip output interface of the differential protection device to receive the trip signal (dry contact signal or level signal). After optocoupler isolation and signal shaping, it outputs a standard digital signal (high level 5V, low level 0V) to feed back to the test monitoring and control unit. The trip monitoring unit has a high isolation voltage, which can suppress electromagnetic interference and ensure reliable operation in the complex electromagnetic environment of the substation, avoiding false signals and misjudgments caused by interference.

[0056] The test monitoring and control unit employs an embedded microprocessor to coordinate the work of various units, record test results, and monitor the system's operating status. Its functions include: sending start, pause, and stop control signals to memory read / write units, output control units, etc.; receiving trip feedback signals from the trip monitoring unit and recording test results, such as test point number and action time; monitoring the communication status of the fiber optic interface unit, such as data transmission rate and bit error rate, and the operating status of each unit, such as CPU load, memory usage, and module temperature; issuing alarm signals and activating the backup synchronization mechanism when a fault is detected; and controlling the resumption of the test process after fault resolution, reading progress information from the shared storage unit, and controlling each unit to resume operation from the interrupted position. The test monitoring and control unit is connected to each functional unit, achieving centralized signal processing and control through an internal bus.

[0057] The fiber optic interface unit uses an SFP optical module to enable communication between the host test device and the slave test device. It supports single-mode fiber transmission and its functions include: receiving test point commands from the output control unit, encapsulating them into standard network data packets, and sending them to the slave test device; receiving feedback signals from the slave test device, such as data reception time and configuration confirmation information, parsing them, and transmitting them to the output control unit or test monitoring control unit; receiving test result data from the slave test device and transmitting it to the test monitoring control unit; and sending test result data from the host test device to the slave test device. The fiber optic interface unit has error detection and correction functions and uses the CRC-32 check algorithm to ensure the reliability of data transmission. The interactive interface receives configuration test parameters input by the operator, such as current amplitude range, change step size, and test duration, and sends them to the test monitoring and control unit of the host test device. The test monitoring and control unit of the host test device controls the memory read and write unit to generate two-dimensional test data with braking current and output current as dimensions, and stores it in the shared storage unit. The shared storage unit sends the two-dimensional test data to the slave test device through a backup optical fiber communication link. After receiving the data, the slave test device stores it in its own shared storage unit and feeds back the data reception time to the host test device through the optical fiber interface unit.

[0058] The output control unit of the host test device records the transmission and reception times of the two-dimensional test data, calculates the channel delay, and synchronizes the channel delay parameters with the slave test device through a backup fiber optic communication link. The memory read / write unit of the host test device reads the two-dimensional test data from the shared storage unit, parses it, and writes it to the waveform output buffer. The data feature buffer synchronously records the test point status identifier (start identifier or normal identifier). After the output control unit detects that there is data in the waveform output buffer, it sends a test point command to the slave test device and starts timing. After the timing value equals the channel delay, it controls the waveform output buffer to output data to the waveform generator. After receiving the test point command through the fiber optic interface unit, the slave test device immediately reads the data from its own waveform output buffer and sends it to the waveform generator. The waveform generators of the two test devices generate simulated current waveforms and output them to the analog input interface of the differential protection device of their respective substations to simulate current signals under different fault or load conditions. The trip monitoring unit monitors the trip signal of the differential protection device in real time. Upon detecting a trip signal, it feeds back to the test monitoring and control unit. The test monitoring and control unit records the test results (test point parameters, action time, etc.) and synchronizes them to the shared storage unit. If no trip signal is detected, it records the test point parameters and the test duration. The test monitoring and control unit monitors the system operating status (communication status, operating parameters of each unit, etc.) in real time. When a fault is detected, it issues an alarm signal and activates the backup synchronization mechanism (backup communication link or redundant unit). After the fault is cleared, the test process is restored based on the data in the shared storage unit. After the test is completed, the host test device and the slave test device synchronize the test result data bidirectionally through the backup fiber optic communication link, integrate them to form a complete two-dimensional test dataset, and the test monitoring and control unit generates a two-dimensional action characteristic curve based on the complete dataset. It simulates the protection action under multiple working conditions and analyzes the difference between braking characteristic parameters and action delay, outputs a standardized test report, and completes the functional verification of the differential protection device. During scenario expansion testing, the test parameter combination (different fault types, load levels, boundary conditions) is reconfigured, the above process is repeated, the test results of multiple scenarios are summarized, and the adaptability and reliability of the differential protection device are analyzed. Please refer to the structural schematic diagram of the electronic device provided in this application embodiment. Figure 7 The electronic device includes a processor 401, a memory 402, an input device 403, and an output device 404, wherein the number of processors 401 can be one or more. Figure 7 Taking a processor 401 as an example; the processor 401, memory 402, input device 403, and output device 404 can be connected via a bus or other means. Figure 7Taking a bus connection as an example, memory 402, as a computer-readable storage medium, can be configured to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the differential protection function test method based on remote data synchronization in this embodiment. Processor 401 executes various functional applications and data processing of electronic devices by running the software programs, instructions, and modules stored in memory 402, thereby realizing the aforementioned differential protection function test method based on remote data synchronization. Input device 403 can be configured to receive input digital or character information, such as configuration test parameters, master control setting instructions, etc., and generate key signal inputs related to user settings and function control of electronic devices. Output device 404 may include display devices such as a display screen for displaying test progress, two-dimensional action characteristic curves, test reports, and other information.

[0059] This application embodiment also provides a storage medium for storing computer-executable instructions. When executed by a computer processor, the computer-executable instructions are configured to perform the differential protection function testing method based on remote data synchronization described in the above embodiments. Specifically, the method includes: an application to a pre-deployed testing device, wherein the testing device is configured as a host testing device and a slave testing device, the host testing device and the slave testing device are located in different substations and establish a communication connection via a backup optical fiber. The host testing device and the slave testing device are respectively wired to the differential protection device to be functionally tested. The method includes: the host testing device, in response to received configuration test parameters, generating two-dimensional test data with braking current and output current as dimensions based on the configuration test parameters, and storing the two-dimensional test data; the host testing device sending the two-dimensional test data to the slave testing device for storage via the backup optical fiber, and receiving data reception time feedback from the slave testing device; the host testing device calculating the channel delay based on the data reception time and the transmission time of sending the two-dimensional test data, and synchronizing with the slave testing device. The host test device and the slave test device, based on the configured FPGA logic architecture and the channel delay, control the output of the two-dimensional test data to the differential protection device. The host test device and the slave test device monitor the action response status of the differential protection device, record the test results, and synchronize the test results to complete the functional verification of the differential protection device based on the data synchronization results. In addition, the method also includes the operation logic corresponding to the steps of test device role configuration, two-dimensional test data generation, channel delay calculation, fault tolerance and recovery, test result analysis, and multi-scenario extended testing to ensure the comprehensiveness and reliability of the differential protection function test.

[0060] This application establishes a stable communication link by deploying host and slave test devices in different locations and using backup optical fibers. The host test device generates structured two-dimensional test data containing braking current and output current dimensions and synchronizes it to the slave test device. The channel delay is accurately calculated by combining the transmission and reception times. Then, the two test devices are controlled by FPGA logic architecture to output test data synchronously. This solves the geographical limitations of traditional single-sided and single-end scaling. It can reproduce fault conditions outside the area by adjusting the current vector and simulating faults within the area, and can accurately configure the ratio of braking current and differential current to reproduce fault conditions outside the area. This solves the problems of traditional methods being unable to verify faults outside the area and incomplete coverage of braking characteristics. Because the two-dimensional test data contains test points for multiple parameters such as amplitude, frequency, and phase, different fault types, load levels, and boundary conditions can be flexibly configured to achieve comprehensive simulation of various complex load conditions, making up for the shortcomings of traditional methods in reproducing diverse operating conditions. Because the two testing devices monitor the differential protection action response of their respective substations in real time, record tripping time, waveform parameters and other information and synchronize bidirectionally, they can directly compare the action delay differences on both sides and generate a complete two-dimensional action characteristic curve. This solves the problem that traditional methods cannot quickly obtain the action status of the other side and are difficult to analyze delay differences. The backup fiber optic communication link ensures the anti-interference capability of data transmission and avoids the delay fluctuation problem of wireless transmission. The FPGA architecture achieves microsecond-level synchronization accuracy, far exceeding the second-level error of satellite time synchronization. The fault tolerance and recovery mechanism ensures the continuity of testing through shared storage units. Multi-scenario extended testing comprehensively verifies the adaptability of the protection device, fundamentally improving the comprehensiveness, accuracy and reliability of differential protection function verification, eliminating the safety hazards left by traditional testing. It is suitable for verifying the differential protection function before the commissioning of new power lines and for verifying the differential protection function of old lines during regular annual inspections, and has broad application prospects.

[0061] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments provided herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the claims.

Claims

1. A differential protection function testing method based on remote data synchronization, applied to a pre-deployed testing device, wherein the testing device is configured as a master testing device and a slave testing device, the master testing device and the slave testing device are located in different substations and establish a communication connection through a backup optical fiber, and the master testing device and the slave testing device are respectively wiredly connected to the differential protection device to be functionally tested, characterized in that, The method includes: The host testing device responds to the received configuration test parameters, generates two-dimensional test data with braking current and output current as dimensions based on the configuration test parameters, and stores the two-dimensional test data. The host testing device transmits the two-dimensional test data to the slave testing device for storage via the backup optical fiber, and receives the data reception time feedback from the slave testing device. The host testing device calculates the channel delay based on the data reception time and the transmission time of the two-dimensional test data, and synchronizes it with the slave testing device. The host test device and the slave test device, based on the set FPGA logic architecture and the channel delay, respectively control the output of the two-dimensional test data to the waveform generator. The waveform generator parses the two-dimensional test data, generates an analog current waveform, and outputs it to the differential protection device. The host test device and the slave test device respectively monitor the action response status of the differential protection device, record the test results, and then synchronize the test results to complete the functional verification of the differential protection device based on the results of the data synchronization.

2. The differential protection function test method based on remote data synchronization as described in claim 1, characterized in that, The testing device is configured to be divided into a host testing device and a slave testing device, including: The testing device receives a master control setting instruction and designates any one of the testing devices as the host testing device. The host testing device sends a configuration command to another testing device through the backup optical fiber. The configuration command includes a role identifier and synchronization parameters. Another of the aforementioned test devices receives the configuration command and parses the command content, automatically switches to the slave test device mode, and completes the role configuration.

3. The differential protection function test method based on remote data synchronization as described in claim 1, characterized in that, The host testing device, in response to the received configuration test parameters, generates two-dimensional test data with braking current and output current as dimensions, including: The host testing device responds to the received configuration test parameters through a set interactive interface. The configuration test parameters include the current amplitude range, the change step size, and the test duration. Based on the configured test parameters, with braking current as the first dimension and output current as the second dimension, two-dimensional test data is constructed. The two-dimensional test data includes a frame header and test point data. The frame header includes data identifier, parameter number and test duration information. The test point data includes amplitude, frequency and phase parameters.

4. The differential protection function test method based on remote data synchronization as described in claim 1, characterized in that, The host testing device calculates the channel delay based on the data reception time and the transmission time of the two-dimensional test data, including: The host testing device sends the two-dimensional test data to the slave testing device and records the time when the two-dimensional test data is sent. After receiving the two-dimensional test data, the slave test device immediately returns the data reception time to the host test device; The host testing device records the data reception time and the transmission time of the two-dimensional test data, and calculates the channel delay based on the time difference.

5. The differential protection function test method based on remote data synchronization as described in claim 1, characterized in that, The host testing device and the slave testing device, based on the set FPGA logic architecture and the channel delay, control the read and write operations of the two-dimensional test data before sending it to the waveform generator, including: The host testing device reads the two-dimensional test data from the shared storage unit through its memory read / write unit, parses the two-dimensional test data flag bits, array number and number of test points, and writes them into the waveform output buffer according to the rules. The data feature buffer of the host testing device synchronously records the test point status identifiers of the two-dimensional test data. The first test point corresponds to the start identifier, and subsequent test points correspond to the normal identifier.

6. The differential protection function test method based on remote data synchronization as described in claim 5, characterized in that, The host testing device and the slave testing device, based on the set FPGA logic architecture and the channel delay, respectively control the output of the two-dimensional test data to be sent to the waveform generator. The waveform generator parses the two-dimensional test data, generates an analog current waveform, and outputs it to the differential protection device, including: After the output control unit of the host test device detects that there is two-dimensional test data in the waveform output buffer, it sends a test point instruction to the slave test device to read the two-dimensional test data and starts timing. When the timing value is equal to the channel delay, the host test device reads the two-dimensional test data from the waveform output buffer and sends it to the waveform generator. After receiving the test point instruction for reading the two-dimensional test data through the fiber optic interface unit, the slave test device immediately reads the two-dimensional test data from its own waveform output buffer and sends it to the waveform generator. The waveform generator of the slave test device generates an analog current waveform based on the analyzed amplitude, frequency and phase parameters and outputs it to the analog input interface of the differential protection device.

7. The differential protection function test method based on remote data synchronization as described in claim 1, characterized in that, The host testing device and the slave testing device respectively monitor the action response status of the differential protection device and record the test results, including: The trip monitoring unit of the master test device and the slave test device monitors the trip signal of the differential protection device of their respective substations in real time, and immediately feeds back the trip signal to the test monitoring control unit after detecting the trip signal; The test monitoring and control unit records the current test point group number, waveform parameters and trip time. If no trip signal is detected, it records the test point parameters and test duration. The test monitoring and control unit synchronizes the recorded information to the shared storage unit to form structured test result data.

8. The differential protection function test method based on remote data synchronization as described in claim 1, characterized in that, Based on the configured FPGA logic architecture and the channel delay, the host test device and the slave test device respectively control the output of the two-dimensional test data to the waveform generator. After the waveform generator parses the two-dimensional test data, generates an analog current waveform, and outputs it to the differential protection device, the method further includes fault tolerance and recovery steps: The host test device and the slave test device's test monitoring and control unit monitor the communication status of the fiber optic interface unit and the operating status of each unit in real time. If a communication interruption or equipment failure is detected, an alarm signal will be issued immediately, and the backup synchronization mechanism will be activated at the same time. After troubleshooting, based on the two-dimensional test data and progress information stored in the shared storage unit, the two-dimensional test data is read again through the memory read / write unit to continue the unfinished test process.

9. The differential protection function test method based on remote data synchronization as described in claim 1, characterized in that, After completing the functional verification of the differential protection device based on the data synchronization results, the method further includes a test result analysis step: The host test device and the slave test device synchronize test result data bidirectionally through the fiber optic interface unit and integrate them to form a complete two-dimensional test dataset. Two-dimensional action characteristic curves of differential current and braking current are generated based on the aforementioned two-dimensional test dataset; Simulate the protection actions under in-zone faults, out-of-zone faults, and load conditions, and analyze the differences in braking characteristic parameters and action delays. The output includes a test report containing two-dimensional motion characteristic curves, motion delay comparison analysis, and fault simulation verification results; Following the test result analysis step, the method further includes a multi-scenario extended test step: Configure test parameter combinations for different fault types, load levels, and boundary conditions; According to the preset scenario sequence, the corresponding two-dimensional test data are generated sequentially, and the output and status monitoring of the two-dimensional test data are completed through the collaborative work of each FPGA unit. The results of tests in multiple scenarios were summarized to analyze the adaptability and reliability of the differential protection device.

10. A differential protection function testing system based on remote data synchronization, used to implement the differential protection function testing method based on remote data synchronization as described in any one of claims 1-9, characterized in that, include: The testing devices are set up in different substations. The testing devices are configured as a master testing device and a slave testing device. Both the master testing device and the slave testing device have built-in FPGA logic modules, shared storage units and interactive interfaces. The FPGA logic modules include memory read and write units, waveform output buffers, data feature buffers, output control units, waveform generators, trip monitoring units, test monitoring control units and fiber optic interface units. Differential protection devices are installed in different substations and are wiredly connected to the master test device and the slave test device of their respective substations. They are used to receive two-dimensional test data output by the master test device and the slave test device and perform protection actions. A backup fiber optic communication link is used to establish a communication connection between the host test device and the slave test device, so as to realize the two-dimensional test data transmission, synchronous command interaction, data reception time feedback and test result feedback. The host testing device generates and stores two-dimensional test data with braking current and output current as dimensions based on the configured test parameters, and sends the two-dimensional test data to the slave testing device for storage through the backup optical fiber communication link. The host testing device records the transmission time of the two-dimensional test data, and the slave testing device receives the two-dimensional test data and then feeds back the reception time of the two-dimensional test data. The host testing device calculates the channel delay based on the transmission time and the reception time and synchronizes it with the slave testing device. The host test device and the slave test device, based on the set FPGA logic architecture and the channel delay, respectively control the output of the two-dimensional test data to the waveform generator. The waveform generator parses the two-dimensional test data, generates an analog current waveform, and outputs it to the differential protection device. The host test device and the slave test device respectively monitor the action response status of the differential protection device, record the test results, and then synchronize the test results to complete the functional verification of the differential protection device based on the results of the data synchronization.

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