Asymmetric time division frequency multiplication interlaced modulation method, device and related equipment

Abstract

This invention discloses an asymmetric time-division multiplexing interleaved modulation method, apparatus, and related equipment, applied to power hardware-in-the-loop systems. The method includes: acquiring the reference current output of the converter under test (DUT) and collecting the total inductance current of the n-phase interleaved converter; the total inductance current is the sum of the inductance currents of all phases; for each of the n phases, determining the duty cycle of the switch below that phase based on the reference current, wherein the duty cycles of different phases are allowed to be different; based on the duty cycle of the switch below each phase, controlling the on / off state of the upper and lower switches of the corresponding phase half-bridge circuit, wherein within one switching cycle, the lower switches of the n-phase half-bridge circuit are controlled to conduct sequentially in turn, so that the total inductance current of the n-phase interleaved converter tracks the reference current. This enhances the control bandwidth and dynamic response capability of the power analog converter in the power hardware-in-the-loop system, improving the simulation accuracy and application range of the entire test platform.

Description

Technical Field

[0001] This invention relates to the field of electronic power, and in particular to an asymmetric time-division multiplexing frequency interleaving modulation method, apparatus and related equipment. Background Technology

[0002] The reliability and performance of power electronic converters need to be verified through thorough testing. Traditional mechanical test benches have limitations such as high cost, large size, insufficient flexibility, and frequent maintenance, making it difficult to meet the testing requirements under complex and variable operating conditions. In contrast, power hardware-in-the-loop (PHIL) test platforms use power analog converters to track and reproduce the electrical behavior of the converter under test in real time, offering significant advantages such as good economy, high flexibility, and strong security, and have become an important development direction in the field of power electronic device testing.

[0003] In power hardware-in-the-loop systems, achieving high-precision simulation requires power analog converters to have control bandwidths significantly higher than those of the converter under test. To improve power ratings and equivalent switching frequencies, multiphase interleaved parallel converter topologies and their interleaved modulation techniques are commonly employed. In existing technologies, traditional interleaved modulation methods reduce current ripple by operating the switching signals of each phase with a fixed phase difference. However, this method maintains a consistent duty cycle for all phases, and its control period is the same as the switching period, thus not altering the system's control step size.

[0004] Therefore, the limitation of existing technologies lies in the fact that while traditional interleaved modulation techniques can improve the equivalent switching frequency and power capacity, they cannot increase the system's control frequency or shorten the control step size without increasing the actual switching frequency. This limits the improvement of the control bandwidth of the power analog converter, making it difficult to meet the high-precision simulation requirements of wide-bandwidth, fast-dynamic-response test objects, thus restricting the application potential and simulation accuracy of the PHIL test platform under high-end and complex operating conditions. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides an asymmetric time-division multiplexing interleaved modulation method, apparatus, and related equipment. By allowing the duty cycle of each phase to be set independently and controlling the switches to conduct sequentially within a switching cycle, the effective control frequency of the system can be increased to n times the original without increasing the actual switching frequency of the switching devices. This enhances the control bandwidth and dynamic response capability of the power analog converter in the power hardware-in-the-loop system, ultimately improving the simulation accuracy and application range of the entire test platform.

[0006] In a first aspect, embodiments of the present invention provide an asymmetric time-division multiplexing interleaved modulation method applied to a power hardware-in-the-loop system. The power hardware-in-the-loop system includes a converter under test (DUT) and an n-phase interleaved converter. The n-phase interleaved converter includes n parallel half-bridge circuits, each half-bridge circuit including an upper switch and a lower switch and corresponding to a phase inductor. The method includes: acquiring a reference current output by the DUT and collecting the total inductor current of the n-phase interleaved converter; the total inductor current is the sum of the inductor currents of all phases; for each of the n phases, based on the reference current, determining the duty cycle of the lower switch of that phase, wherein the duty cycles of different phases are allowed to be set differently; based on the duty cycle of the lower switch of each phase, controlling the on / off state of the upper and lower switches of the corresponding phase half-bridge circuit, wherein within one switching cycle, the lower switches of the n-phase half-bridge circuits are controlled to be turned on sequentially in turn, so that the total inductor current of the n-phase interleaved converter tracks the reference current.

[0007] In one possible embodiment, the modulation method used to control the lower switches of the n-phase half-bridge circuit to turn on in turn is asymmetric interleaved time-division multiplexing modulation.

[0008] In one possible embodiment, the n-phase interleaved converter is a power analog converter used to make the total inductor current track a reference current from the converter under test in order to simulate the electrical characteristics of the converter under test.

[0009] In one possible embodiment, within one switching cycle, controlling the lower switches of the n-phase half-bridge circuit to sequentially turn on in turn includes:

[0010] Within one switching cycle, it sequentially enters 2n operating modes; where n is an integer greater than 1.

[0011] In the 2m-1 mode, only the lower switch of the m-th phase half-bridge circuit is turned on, while the lower switches of the remaining n-1 phase half-bridge circuits are turned off and the upper switches are turned on, where m is an integer from 1 to n.

[0012] In the 2m-th mode, all the lower switches of the n-phase half-bridge circuits are off and the upper switches are on, where m is an integer from 1 to n-1.

[0013] In one possible embodiment, for each of the n phases, the duty cycle of the switch in that phase is determined based on a reference current, including:

[0014] An independent control loop is set up for each phase;

[0015] In the control loop of each phase, the reference current is divided by the number of phases n to obtain the reference component of the inductor current of that phase.

[0016] Based on the actual sampled value and reference component of the phase inductor current, the duty cycle of the switch under that phase is calculated by the current controller.

[0017] In one possible embodiment, for each of the n phases, determining the duty cycle of the switch in that phase based on the reference current includes:

[0018] Calculate the total current error between the total inductor current and the reference current;

[0019] For each phase, the duty cycle of the switch in that phase is calculated based on the total current error.

[0020] In one possible embodiment, during the rise of the reference current, in the 2m-1 mode, only the m-th phase inductor is charged, and the current change rate of the other phase inductors is zero; in the 2m mode, the current change rate of all phase inductors is zero.

[0021] Secondly, embodiments of the present invention provide an asymmetric time-division frequency-multiplying interleaved modulation device applied to a power hardware-in-the-loop system. The power hardware-in-the-loop system includes a converter under test and an n-phase interleaved converter. The n-phase interleaved converter includes n parallel half-bridge circuits, each half-bridge circuit including an upper switch and a lower switch and corresponding to one phase inductor. The device includes: an acquisition module, a determination module, and a control module, wherein:

[0022] The acquisition module is used to acquire the reference current output by the converter under test and to collect the total inductor current of the n-phase interleaved converter; the total inductor current is the sum of the inductor currents of all phases.

[0023] The determination module is used to determine the duty cycle of the switch in each of the n phases based on the reference current, wherein the duty cycles of different phases are allowed to be set differently;

[0024] The control module is used to control the on / off state of the upper and lower switches of the corresponding phase half-bridge circuit based on the duty cycle of the lower switch of each phase. Within one switching cycle, the lower switches of the n-phase half-bridge circuit are controlled to be turned on in turn so that the total inductance current of the n-phase interleaved converter tracks the reference current.

[0025] Thirdly, embodiments of the present invention provide a computer storage medium storing multiple instructions adapted for loading by a processor and executing the steps of the above-described method.

[0026] Fourthly, embodiments of the present invention provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being adapted to be loaded by the processor and to execute the steps of the above-described method.

[0027] The beneficial effects of the technical solutions provided by some embodiments of the present invention include at least the following: allowing the duty cycle of each phase half-bridge circuit to be set independently, and controlling the switches of each phase to conduct sequentially and in a time-sharing manner within one switching cycle. This innovative mechanism enables the controller to perform up to n independent calculations and interventions on the multi-phase system within one physical switching cycle, thereby increasing the effective control frequency of the system to n times the original without increasing the actual switching frequency of the switching devices. The resulting significant widening of the control bandwidth fundamentally solves the problem of limited dynamic tracking accuracy caused by insufficient control bandwidth in traditional PHIL systems, providing strong technical support for the testing of high-precision, high-dynamic-performance power electronic devices. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the overall structure of the PHIL system provided in an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the topology of an n-phase interleaved converter provided in an embodiment of the present invention.

[0031] Figure 3 A schematic flowchart of the asymmetric time-division multiplexing interleaved modulation method provided in an embodiment of the present invention;

[0032] Figure 4 This is a block diagram of the n-phase half-bridge interleaved control method for time-division multiplexing modulation provided in an embodiment of the present invention;

[0033] Figure 5 This is a structural block diagram of the asymmetric time-division multiplexing interleaved modulation device provided in an embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0035] To make the features and advantages of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0037] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances. Furthermore, in the description of this invention, unless otherwise stated, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0038] As mentioned earlier, traditional interleaved modulation techniques primarily optimize current ripple but fail to overcome the binding relationship between control frequency and switching frequency. Since the control frequency cannot be multiplied without increasing the switching frequency, the closed-loop control bandwidth of the power analog converter is fundamentally limited. When dealing with converters under test (DUTs) exhibiting wide bandwidth and fast dynamic characteristics, traditional PHIL systems struggle to achieve high-precision, hysteresis-free current tracking, leading to decreased simulation fidelity and thus restricting the performance and reliability of the entire test platform in high-end, demanding application scenarios.

[0039] In view of this, the present invention provides an asymmetric time-division multiplexing interleaved modulation method, apparatus, and related equipment. It allows the duty cycle of each phase half-bridge circuit to be set independently, and within one switching cycle, controls the switches of each phase to conduct sequentially and in a time-division manner. This innovative mechanism enables the controller to perform up to n independent calculations and interventions on the multi-phase system within one physical switching cycle, thereby increasing the effective control frequency of the system to n times its original value without increasing the actual switching frequency of the switching devices. The resulting significant widening of the control bandwidth fundamentally solves the problem of limited dynamic tracking accuracy caused by insufficient control bandwidth in traditional PHIL systems, providing strong technical support for the testing of high-precision, high-dynamic-performance power electronic devices.

[0040] Please see Figure 1 , Figure 1 This is a schematic diagram of the overall structure of the PHIL system provided in an embodiment of the present invention. This method is applied to a power hardware-in-the-loop system containing an n-phase interleaved converter. The n-phase interleaved converter includes n parallel half-bridge circuits, each half-bridge circuit corresponding to one phase inductor, such as... Figure 1As shown, the system consists of two parts: the converter under test (DUT) on the left and the power simulation converter on the right. It adopts a common DC bus structure, reducing the number of bidirectional DC / AC power converters on both sides and changing the energy circulation path from "AC-side power circulation" to "DC bus power circulation." This allows the DUT SiC module and the high-frequency switching simulation unit to share the same DC bus, thereby significantly reducing the cost and size of active devices, passive components, and grid-connected operation without affecting the high-precision simulation of the DUT and energy circulation.

[0041] Please see Figure 2 , Figure 2 This is a schematic diagram of the topology of an n-phase interleaved converter provided in an embodiment of the present invention, as shown below. Figure 2 As shown, this topology is introduced into the PHIL system. In one possible embodiment, the n-phase interleaved converter serves as a power analog converter, used to make the total inductor current track a reference current from the converter under test (DUT) to simulate the electrical characteristics of the DUT. In this structure, V in and V o These are the input and output voltages of the analog converter, respectively. The unit under test is connected to the bus capacitor C. m Stable DC bus voltage V m and to C m Input or absorb input current I in The tested part of the bridge arm switch S L,H and S L,L The output voltage V is generated under the set control. in In the analog unit, the output capacitor C o This method is used to filter out high-frequency ripple and achieve local energy buffering. Energy is input from the bus voltage to the measured unit, then flows from the measured unit into the analog unit and finally back to the bus voltage, achieving energy feedback. Compared to traditional interleaved control techniques, the method provided in this embodiment allows each phase half-bridge switch to have a different duty cycle, and the control of each phase half-bridge is independent. Specifically, the upper and lower switches in the half-bridge circuit complementarily turn on and off, and the phase difference of the drive signals between each phase half-bridge is π / n.

[0042] Please see Figure 3 , Figure 3 This is a flowchart illustrating the asymmetric time-division multiplexing interleaved modulation method provided in this embodiment of the invention. The execution entity in this embodiment can be an electronic device performing asymmetric time-division multiplexing interleaved modulation, a processor within the electronic device performing the asymmetric time-division multiplexing interleaved modulation method, or an asymmetric time-division multiplexing interleaved modulation service within the electronic device performing the asymmetric time-division multiplexing interleaved modulation method. For ease of description, the following uses a processor within an electronic device as an example to illustrate the specific execution process of the asymmetric time-division multiplexing interleaved modulation method.

[0043] like Figure 3 As shown, the asymmetric time-division multiplexing interleaved modulation method can include at least:

[0044] S301. Obtain the reference current output of the converter under test, and collect the total inductance current of the n-phase interleaved converter; the total inductance current is the sum of the inductance currents of all phases.

[0045] Specifically, in the operation of a power hardware-in-the-loop (PHIL) system, to achieve high-precision simulation of the electrical characteristics of the converter under test (DUT) by the power analog converter, the starting point and foundation of its control logic lies in accurately acquiring the tracking target and real-time feedback. Specifically, firstly, the host computer or the local digital controller of the DUT, such as a DSP or FPGA, generates a reference current i characterizing its desired output or load behavior based on its internal algorithm and state. ref This signal is typically transmitted in real time to the controller of the power analog converter via a preset digital communication interface, such as Ethernet, PCIe, or an analog signal link. On the analog converter side, the controller synchronously receives the reference current i through its corresponding input interface. ref This value is then stored in a memory register as the tracking target value for the current control cycle. Simultaneously, to form the feedback necessary for closed-loop control, the total output current of the power analog converter needs to be acquired; this total output current is the total inductor current i of the n-phase interleaved converter. L Physically, this is equal to the sum of the instantaneous values ​​of the inductor currents in the n parallel half-bridge branches within it. In practice, one of two mainstream methods can be used for data acquisition: the first method is to connect a high-bandwidth, high-precision current sensor (e.g., a Hall effect current sensor or a Rogowski coil) in series on the converter's total output bus to directly measure and output the total inductor current i. L The first method involves a voltage or current signal that is directly proportional to the current. The second method reuses existing current sensors on each phase branch. Specifically, current sensors are installed on each branch containing the inductor to synchronously sample and obtain the instantaneous current values ​​of each phase. These sampled values ​​are then summed in real-time using a software algorithm within the controller to calculate the total inductor current i. L Regardless of the method used, the total inductance current i obtained is... L Analog signals all need to go through signal conditioning circuits, such as filtering and amplification, before being converted into digital quantities by the controller's analog-to-digital converter (ADC) for use by subsequent control algorithms.

[0046] S302. For each of the n phases, determine the duty cycle of the switch in that phase based on the reference current, wherein the duty cycles of different phases are allowed to be set differently.

[0047] Specifically, based on the acquired reference current i refThis generates duty cycle commands for the switches under each phase. A basic implementation is to set up an independent control loop for each phase. In each control loop, the total reference current i is first... ref Dividing by the number of phases n yields the theoretical current reference component i for that phase. ref / n. Then, the reference component is compared with the actual sampled value of the inductor current of that phase to obtain the current tracking error of that phase. This error signal is sent to a current controller (e.g., a proportional-integral (PI) controller, a proportional-resonant (PR) controller, or a predictive controller), which calculates in real time according to its built-in control algorithm and outputs a duty cycle command between 0 and 1. This duty cycle command determines the proportion of the switching time of that phase in the next time period. Since the instantaneous value and ripple condition of the inductor current of each phase may be different, the duty cycle calculated by each independent controller can naturally be different, thus realizing independent and precise scheduling of energy for each phase, providing a prerequisite for subsequent time-sharing frequency multiplication control.

[0048] In one specific implementation, please refer to Figure 4 , Figure 4 This is a block diagram of an n-phase half-bridge interleaved control method for a time-division multiplexing modulation method provided in an embodiment of the present invention. For an n-phase half-bridge interleaved converter, this control method consists of n control loops. For example: L1 phase control loop, L2 phase control loop, and L... n Phase control loop. Taking the L1 phase control loop as an example, a parameter 1 / n is introduced into this control loop to generate the L1 phase inductor current reference value iL1,r, from which the expression can be obtained:

[0049]

[0050] In the formula, i ref As the reference value for the total current of the n-phase interleaved circuit, by introducing the parameter 1 / n, the phase difference of the inductor current between each phase of the n-phase interleaved converter is made smaller, thereby realizing the total inductor current i L Equivalent to i ref In one possible embodiment, once iL is obtained... 1,r Then the current error iL 1,err The current is sent to the L1 phase current control regulator to calculate the duty cycle D1 of that phase, where the current error iL 1,err The calculation expression For the L1 phase current control regulator, PI control and predictive control can typically be used. Furthermore, since the topology of each phase of the n-phase interleaved converter is symmetrical, the control loops of other phases are equal to those of the L1 phase; this will not be elaborated further in the embodiments of the present invention.

[0051] S303. Based on the duty cycle of the lower switch of each phase, control the on / off state of the upper and lower switches of the corresponding phase half-bridge circuit. In one switching cycle, control the lower switches of the n-phase half-bridge circuit to be turned on in turn so that the total inductance current of the n-phase interleaved converter tracks the reference current.

[0052] Specifically, the calculated n duty cycles are written into the comparator registers of the corresponding pulse width modulation (PWM) generators. In this embodiment, the modulation method used to control the lower switches of the n-phase half-bridge circuit to turn on sequentially is asymmetric interleaved time-division multiplexing modulation. Specifically, in a complete switching cycle T S Within this framework, the timeline is divided into n equal-length control sub-intervals, each with a length of T. S / n. The controller is configured to sequentially and alternately allow the lower switch of one phase to conduct within these n sub-intervals, while the lower switches of other phases are forcibly turned off (their upper switches are turned on accordingly). For example, in the first T... S In the / n interval, only the lower switch S of the first phase is allowed. 1,L It may be turned on based on its duty cycle D1; in the second T S In the / n interval, only the lower switch S of the second phase is allowed. 2,L It may be turned on based on D2; and so on, until the nth interval corresponds to the nth phase.

[0053] Within one switching cycle, the circuit sequentially enters 2n operating modes. These 2n modes repeat periodically. For example, in the 2m-1th mode (where m is an integer from 1 to n), only the lower switch of the m-th phase half-bridge circuit is turned on, while the lower switches of the remaining n-1 phase half-bridge circuits are turned off and the upper switches are turned on. For instance, when m=1, it is the first mode, and in the n-phase half-bridge interleaved circuit, only phase L1 is the lower switch S. L1,L On, switch S L1,H When the circuit is off, all other phases are switched on by the upper switch and switched off by the lower switch. The only inductance in each phase is inductance L. 1 It is being charged. Therefore, in the first mode, the state-space equations for each inductor current are:

[0054]

[0055] In the formula, V in Represents the port input voltage, V o This is the port output voltage. Where V... in With V o Approximately equal, we can conclude that the rate of change of current in all inductors except L1 in the n-phase half-bridge interleaved circuit is 0 in mode I. Therefore, the total inductor current i can be obtained. L The value at time t1 is:

[0056]

[0057] In the formula, i L Let Δi be the inductor current. L1 (t1-t0) represents the current i L1 The change between t0 and t1, D1 is the switch S of phase L1. L1,L Duty cycle, T S The switching cycle.

[0058] In the 2m-th mode, all lower switches of the n-phase half-bridge circuit are off and all upper switches are on, where m is an integer from 1 to n-1. For example, when m=1, it is the second mode, in which all phases of the n-phase half-bridge interleaved circuit have their lower switches off and their upper switches on. Therefore, the state-space equations for the inductor currents in both modes are:

[0059]

[0060] In this embodiment, since the rate of change of each phase during the second mode is 0, the total inductance i L It remains constant during the period t1-t2. Therefore, the total inductance current i can be obtained. L The value at time t1 is:

[0061]

[0062] In the formula, Δi L1 (t2-t1) represents the current i L1 The change between t2 and t1.

[0063] In the 2m-1 mode, when m equals 2, it is the third mode. At this time, the N-phase half-bridge interleaved circuit only has L n Phase is the lower switch S Ln,L On, switch S Ln,H With the circuit off, all other phases have their upper switches on and lower switches off. Only inductor Ln is charged. Therefore, in mode 2m-1, the state-space equations for the inductor currents are:

[0064]

[0065] In this embodiment, V in With V o Approximately equal, it can be concluded that the rate of change of current in all inductors except Ln in the n-phase half-bridge interleaved circuit is 0 in mode 2m-1. Therefore, the total inductor current i can be obtained. L In t 2n-1 The value at time:

[0066]

[0067] In the formula, Δ iLn (t) 2n-1 -t 2n-2 ) is the current i Ln In t 2n-1 and t 2n-2 The change between them, D n For L n Phase-down switch S Ln,L The duty cycle. In summary, the total inductor current i can be obtained. L The value at the end of one switching cycle is:

[0068]

[0069] At the reference current i ref During the rise, one switching cycle of the n-phase half-bridge interleaved circuit has ended. Since the operating principle of the n-phase half-bridge interleaved circuit is symmetrically reversed when the reference current decreases, this will not be elaborated further in this embodiment. This 2n-mode sequence is a concrete manifestation of "interleaved modulation" and "sequential switching of the lower transistors" in the power circuit behavior. Odd-numbered modes enable each phase's lower transistor to charge its respective inductor in a time-sharing and orderly manner; even-numbered modes provide a unified freewheeling phase for all phases. This highly structured and regular operating mode not only simplifies system analysis and control design but also makes the total output current ripple frequency reach 2n times the switching frequency, improving the system's equivalent control bandwidth and facilitating smooth and fast current tracking.

[0070] Within each specific sub-interval, for the "selected" phase, its PWM generator generates the drive pulse for the lower switch of that phase based on the phase's duty cycle command and carrier wave (such as a triangular wave), with the drive signal for the upper switch complementing it (and inserting a dead time). For other unselected phases, within that sub-interval, their lower switch drive signal is forced to be low (off) and their upper switch drive signal is forced to be high (on). These drive signals, after isolation and amplification, are applied to the gates of each power switch. This "sequential turn-on" scheduling method essentially changes the control decision for a multiphase system from once per switching cycle (i.e., control frequency equals switching frequency f) to... s The effective control frequency is distributed across n time points within each switching cycle (i.e., the equivalent control frequency is increased to n*f). s In each control sub-interval, the controller can independently calculate and update the duty cycle of the "currently turned" phase based on the latest system state and reference commands. This significantly reduces the system's response delay to changes in external reference current, and multiplies the control bandwidth. The currents of each phase change controlled within their respective allocated time windows, and their sum—that is, the total inductor current i—is determined. LTherefore, it is possible to track the reference current i with higher speed and accuracy. ref This improves the simulation fidelity of the PHIL system.

[0071] This invention provides an asymmetric time-division multiplexing interleaved modulation method, allowing the duty cycle of each phase half-bridge circuit to be set independently, and controlling the switches of each phase to conduct sequentially and in a time-division manner within one switching cycle. This innovative mechanism enables the controller to perform up to n independent calculations and interventions on the multi-phase system within one physical switching cycle, thereby increasing the effective control frequency of the system to n times the original without increasing the actual switching frequency of the switching devices. The resulting significant widening of the control bandwidth fundamentally solves the problem of limited dynamic tracking accuracy caused by insufficient control bandwidth in traditional PHIL systems, providing strong technical support for the testing of high-precision, high-dynamic-performance power electronic devices.

[0072] Please see Figure 5 , Figure 5 This is a structural block diagram of an asymmetric time-division multiplexing interleaved modulation device provided in an embodiment of the present invention. Figure 5 As shown: The asymmetric time-division multiplexing interleaved modulation device 500 includes: an acquisition module 510, a determination module 520, and a control module 530, wherein:

[0073] The acquisition module 510 is used to acquire the reference current output by the converter under test and to collect the total inductor current of the n-phase interleaved converter; the total inductor current is the sum of the inductor currents of all phases.

[0074] The determination module 520 is used to determine the duty cycle of the switch in each of the n phases based on the reference current, wherein the duty cycles of different phases are allowed to be set differently.

[0075] The control module 530 is used to control the on / off state of the upper and lower switches of the corresponding phase half-bridge circuit based on the duty cycle of the lower switch of each phase. In one switching cycle, the lower switches of the n-phase half-bridge circuit are controlled to be turned on in turn so that the total inductance current of the n-phase interleaved converter tracks the reference current.

[0076] In some possible embodiments, the modulation method used to control the lower switches of the n-phase half-bridge circuit to turn on in turn is asymmetric interleaved time-division multiplexing modulation.

[0077] In some possible embodiments, the n-phase interleaved converter is a power analog converter used to make the total inductor current track a reference current from the converter under test in order to simulate the electrical characteristics of the converter under test.

[0078] In some possible embodiments, the control module 530 includes:

[0079] The cyclic unit is used to sequentially enter 2n operating modes within one switching cycle; where n is an integer greater than 1.

[0080] The first conducting unit is used in the 2m-1 mode to ensure that only the lower switch of the m-th phase half-bridge circuit is turned on, while the lower switches of the remaining n-1 phase half-bridge circuits are turned off and the upper switches are turned on, where m is an integer from 1 to n.

[0081] The second conducting unit is used in the 2m mode to ensure that the lower switches of all n-phase half-bridge circuits are turned off and the upper switches are turned on, where m is an integer from 1 to n-1.

[0082] In some possible embodiments, the determining module 520 includes:

[0083] The setting unit is used to set up an independent control loop for each phase;

[0084] The unit is used to divide the reference current by the number of phases n in the control loop of each phase to obtain the reference component of the inductor current of that phase.

[0085] The first calculation unit is used to calculate the duty cycle of the switch under the phase based on the actual sampled value and reference component of the phase inductor current through the current controller.

[0086] In some possible embodiments, the determining module 520 includes:

[0087] The second calculation unit is used to calculate the total current error between the total inductor current and the reference current.

[0088] The third calculation unit is used to calculate the duty cycle of the switch in each phase based on the total current error.

[0089] In some possible embodiments, during the rise of the reference current, in the 2m-1 mode, only the m-th phase inductor is charged, and the current change rate of the other phase inductors is zero; in the 2m mode, the current change rate of all phase inductors is zero.

[0090] It should be noted that the asymmetric time-division frequency-multiplying interleaved modulation device provided in the above embodiments is only illustrated by the division of the above functional modules when executing the asymmetric time-division frequency-multiplying interleaved modulation method. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the asymmetric time-division frequency-multiplying interleaved modulation device and the asymmetric time-division frequency-multiplying interleaved modulation method embodiments provided in the above embodiments belong to the same concept, and the implementation process is detailed in the method embodiments, which will not be repeated here.

[0091] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0092] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Figure 6 As shown, the electronic device 600 may include: at least one processor 601, at least one network interface 604, user interface 603, memory 605, and at least one communication bus 602.

[0093] The communication bus 602 is used to enable communication between these components.

[0094] The user interface 603 may include a display screen, and the optional user interface 603 may include a standard wired interface or a wireless interface.

[0095] The network interface 604 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0096] The processor 601 may include one or more processing cores. The processor 601 connects to various parts within the electronic device 600 using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 605, and by calling data stored in the memory 605. Optionally, the processor 601 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 601 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also not be integrated into the processor 601 and may be implemented as a separate chip.

[0097] The memory 605 may include random access memory (RAM) or read-only memory. Optionally, the memory 605 may include a non-transitory computer-readable storage medium. The memory 605 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 605 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 605 may also be at least one storage device located remotely from the aforementioned processor 601. Figure 6 As shown, the memory 605, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and an asymmetric time-division multiplexing interleaved modulation application program.

[0098] exist Figure 6 In the illustrated electronic device 600, the user interface 603 is mainly used to provide an input interface for the user and acquire user input data; while the processor 601 can be used to call the asymmetric time-division multiplexing interleaved modulation application stored in the memory 605, and specifically perform the following operations: acquire the reference current output by the converter under test, and collect the total inductance current of the n-phase interleaved converter; the total inductance current is the sum of the inductance currents of all phases; for each of the n phases, based on the reference current, determine the duty cycle of the switch under that phase, wherein the duty cycles of different phases are allowed to be set differently; based on the duty cycle of the switch under each phase, control the on / off state of the upper and lower switches of the corresponding phase half-bridge circuit, wherein, within one switching cycle, the lower switches of the n-phase half-bridge circuit are controlled to be turned on sequentially in turn, so that the total inductance current of the n-phase interleaved converter tracks the reference current.

[0099] In some possible embodiments, the modulation method used to control the lower switches of the n-phase half-bridge circuit to turn on in turn is asymmetric interleaved time-division multiplexing modulation.

[0100] In some possible embodiments, the n-phase interleaved converter is a power analog converter used to make the total inductor current track a reference current from the converter under test in order to simulate the electrical characteristics of the converter under test.

[0101] In some possible embodiments, the processor 601 executes, within a switching cycle, controlling the lower switches of the n-phase half-bridge circuit to be turned on sequentially in turn, specifically for performing:

[0102] Within one switching cycle, it sequentially enters 2n operating modes; where n is an integer greater than 1.

[0103] In the 2m-1 mode, only the lower switch of the m-th phase half-bridge circuit is turned on, while the lower switches of the remaining n-1 phase half-bridge circuits are turned off and the upper switches are turned on, where m is an integer from 1 to n.

[0104] In the 2m-th mode, all the lower switches of the n-phase half-bridge circuits are off and the upper switches are on, where m is an integer from 1 to n-1.

[0105] In some possible embodiments, processor 601 performs, for each of the n phases, determining the duty cycle of the switch in that phase based on the reference current, specifically for performing:

[0106] An independent control loop is set up for each phase;

[0107] In the control loop of each phase, the reference current is divided by the number of phases n to obtain the reference component of the inductor current of that phase.

[0108] Based on the actual sampled value and reference component of the phase inductor current, the duty cycle of the switch under that phase is calculated by the current controller.

[0109] In some possible embodiments, processor 601 performs the following: for each of the n phases, based on the reference current, determining the duty cycle of the switch in that phase, specifically for performing:

[0110] Calculate the total current error between the total inductor current and the reference current;

[0111] For each phase, the duty cycle of the switch in that phase is calculated based on the total current error.

[0112] In some possible embodiments, during the rise of the reference current, in the 2m-1 mode, only the m-th phase inductor is charged, and the current change rate of the other phase inductors is zero; in the 2m mode, the current change rate of all phase inductors is zero.

[0113] This invention also provides a computer-readable storage medium storing instructions that, when executed on a computer or processor, cause the computer or processor to perform the above-described instructions. Figure 3 One or more steps in the illustrated embodiment. If the constituent modules of the above-described asymmetric time-division multiplexing interleaved modulation device are implemented as software functional units and sold or used as independent products, they can be stored in the computer-readable storage medium.

[0114] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital versatile discs (DVDs)), or semiconductor media (e.g., solid state disks (SSDs)).

[0115] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The aforementioned storage medium includes various media capable of storing program code, such as read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks. Unless otherwise specified, the technical features of this embodiment and its implementation schemes can be combined arbitrarily.

[0116] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An asymmetric time division duplex frequency interlaced modulation method, characterized in that, The method is applied to a power hardware-in-the-loop system, which includes a converter under test (DUT) and an n-phase interleaved converter. The n-phase interleaved converter includes n parallel half-bridge circuits, each half-bridge circuit including an upper switch and a lower switch and corresponding to one phase inductor. Obtain the reference current output by the converter under test, and collect the total inductance current of the n-phase interleaved converter; the total inductance current is the sum of the inductance currents of all phases. For each of the n phases, the duty cycle of the switch in that phase is determined based on the reference current, wherein the duty cycles of different phases are allowed to be set differently; Based on the duty cycle of each phase lower switch, the on / off state of the upper and lower switches of the corresponding phase half-bridge circuit is controlled. In one switching cycle, the lower switches of the n-phase half-bridge circuit are controlled to be turned on in turn so that the total inductance current of the n-phase interleaved converter tracks the reference current. The control of the lower switches of the n-phase half-bridge circuit to be turned on sequentially in turn during one switching cycle includes: Within one switching cycle, it sequentially enters 2n operating modes; where n is an integer greater than 1. In the (2m-1)th mode, only the lower switch of the m-th phase half-bridge circuit is turned on, while the lower switches of the remaining n-1 phase half-bridge circuits are turned off and the upper switches are turned on, where m is an integer from 1 to n. In the 2m mode, all the lower switches of the n-phase half-bridge circuits are turned off and the upper switches are turned on, where m is an integer from 1 to n-1; during the rise of the reference current, in the (2m-1) mode, only the m-th phase inductor is charged, and the current change rate of the other phase inductors is zero; in the 2m mode, the current change rate of all phase inductors is zero.

2. The asymmetric time-division multiplexing interleaved modulation method according to claim 1, characterized in that, The modulation method used to control the sequential conduction of the lower switches of the n-phase half-bridge circuit is asymmetric interleaved time-division frequency multiplication modulation.

3. The asymmetric time-division multiplexing interleaved modulation method according to claim 1 or 2, characterized in that, The n-phase interleaved converter is a power analog converter used to make the total inductor current track the reference current from the converter under test in order to simulate the electrical characteristics of the converter under test.

4. The asymmetric time-division multiplexing interleaved modulation method according to claim 1, characterized in that, The step of determining the duty cycle of the switch for each of the n phases based on the reference current includes: An independent control loop is set up for each phase; In the control loop of each phase, the reference current is divided by the number of phases n to obtain the reference component of the inductor current of that phase. Based on the actual sampled value of the phase inductor current and the reference component, the duty cycle of the switch under that phase is calculated by the current controller.

5. The asymmetric time-division multiplexing interleaved modulation method according to claim 1, characterized in that, The step of determining the duty cycle of the switch for each of the n phases based on the reference current includes: Calculate the total current error between the total inductor current and the reference current; For each phase, the duty cycle of the switch in that phase is calculated based on the total current error.

6. An asymmetric time-division multiplexing interleaved modulation device, characterized in that, The device is applied to a power hardware-in-the-loop system, which includes a converter under test (DUT) and an n-phase interleaved converter. The n-phase interleaved converter includes n parallel half-bridge circuits, each half-bridge circuit including an upper switch and a lower switch and corresponding to one phase inductor. The device includes: The acquisition module is used to acquire the reference current output by the converter under test and to collect the total inductance current of the n-phase interleaved converter; the total inductance current is the sum of the inductance currents of all phases. The determination module is used to determine the duty cycle of the switch in each of the n phases based on the reference current, wherein the duty cycles of different phases are allowed to be set differently; The control module is used to control the on / off state of the upper and lower switches of the corresponding phase half-bridge circuit based on the duty cycle of each phase lower switch. Within one switching cycle, the lower switches of the n-phase half-bridge circuit are controlled to conduct sequentially in turn, so that the total inductor current of the n-phase interleaved converter tracks the reference current. The step of controlling the lower switches of the n-phase half-bridge circuit to conduct sequentially in turn within one switching cycle includes: Within one switching cycle, it sequentially enters 2n operating modes; where n is an integer greater than 1. In the (2m-1)th mode, only the lower switch of the m-th phase half-bridge circuit is turned on, while the lower switches of the remaining n-1 phase half-bridge circuits are turned off and the upper switches are turned on, where m is an integer from 1 to n. In the 2m mode, all the lower switches of the n-phase half-bridge circuits are turned off and the upper switches are turned on, where m is an integer from 1 to n-1; during the rise of the reference current, in the (2m-1) mode, only the m-th phase inductor is charged, and the current change rate of the other phase inductors is zero; in the 2m mode, the current change rate of all phase inductors is zero.

7. A computer storage medium, characterized in that, The computer storage medium stores a plurality of instructions adapted for loading by a processor and executing the steps of the method as described in any one of claims 1 to 5.

8. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of the method as described in any one of claims 1 to 5.

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