Vcm-free type capacitor switch switching scheme for SAR ADC (Synthetic Aperture Radar Analog to Digital Converter)
By adopting a Vcm-free capacitor switch switching scheme, the problem of high power consumption during CDAC switch switching in SAR ADC is solved, realizing low power consumption and low hardware overhead capacitor switch switching, which is more adaptable and has lower external power supply requirements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING UNIV OF TECH
- Filing Date
- 2025-12-05
- Publication Date
- 2026-04-24
AI Technical Summary
Existing SAR ADCs have high power consumption during CDAC switching, require a large number of reference voltages, have high hardware overhead, and have high external power supply requirements.
A Vcm-free capacitor switch switching scheme is adopted to reduce the number of reference voltages. A non-overlapping clock source and a new switching circuit are used. The switching method is optimized through differential sampling on the lower plate and a bootstrap switch structure, thereby reducing switching power consumption and hardware overhead.
While reducing power consumption during switching, it also reduces the number of capacitors and hardware area, improves robustness, enhances adaptability, and reduces external power supply requirements.
Smart Images
Figure CN121923657A_ABST
Abstract
Description
Technical Field
[0001] This invention is a Vcm-free capacitor switch switching scheme for SAR ADC, belonging to the field of analog integrated circuit technology. Background Technology
[0002] Analog-to-digital converters (ADCs), acting as a bridge between analog and digital signals, convert continuous analog signals into discrete digital signals to enable further signal processing, transmission, and improved noise immunity, making them indispensable in modern electronic devices. With continuous technological advancements and increasing demands for low-power applications, various ADCs have been proposed. Successive approximation ADCs (SAR ADCs), due to their simple architecture requiring only a capacitive digital-to-analog converter (CDAC), comparator, and SAR logic circuitry, exhibit advantages in low-voltage power supply, low power consumption, and high-speed conversion. This has made SAR ADCs a research hotspot in both academia and industry, yielding innovative results in consumer electronics, wireless communications, and other fields.
[0003] The key to the low-power performance of SAR ADCs lies in the switching power consumption of the CDAC (Comparator Dedicated Capacitor). This is because the quantization process requires continuous switching of capacitors within the CDAC to achieve successive approximation, and the number of capacitors in the CDAC increases exponentially with the ADC resolution. Furthermore, with process advancements, the power consumption of comparators and logic control decreases exponentially, making this power reduction more process-friendly and adaptable. To address the issue of reducing CDAC switching power consumption, the following measures are proposed: Figure 1 The schematic diagram of the Vcm-free switching scheme shown indicates that this scheme eliminates the need for the Vcm reference voltage required for switching, requiring only two sets of reference voltages, Vref and Vss. Traditional Vcm-based switching schemes require strictly ensuring the relationship Vref = 2 * Vref. Therefore, the switching scheme proposed in this invention not only reduces the number of reference voltages but also lowers the requirements for external power supply. Furthermore, Vref and Vss can be reused with the internal power supply voltage of the circuit, saving the power supply PAD requirement.
[0004] This switching scheme reduces the impact of channel charge injection by using differential sampling on the lower plate. During quantization, by controlling the lower plate switch of each capacitor, Vref and Vss are selected to connect to the lower plate, achieving continuous quantization of the sampled voltage. Compared to the switching scheme using Vcm, this invention reduces the capacitor switching requirement by 1 / 3. Therefore, this invention has certain advantages in reducing switching power consumption and hardware overhead. Summary of the Invention
[0005] The purpose of this invention is to address the shortcomings of Vcm-type switch switching schemes, such as low energy efficiency and complex switch layout, by proposing a Vcm-free capacitor switch switching scheme for SAR ADCs. By reducing the number of reference voltages used and optimizing the switching method, the CDAC achieves better energy efficiency during quantization. Furthermore, it requires fewer CDAC capacitors for the same resolution, effectively reducing the energy consumption caused by switch switching during quantization and the area overhead of the entire CDAC. It also exhibits good robustness and can be widely applied in SAR ADCs.
[0006] The technical solution to achieve the objective of this invention is:
[0007] A Vcm-free capacitor switching scheme for SAR ADC includes a non-overlapping clock source for controlling the operation of various circuits; a switched capacitor circuit for sampling and quantization of the SAR ADC; and a novel switching circuit applied in a CDAC to achieve the design goal of ultra-low power consumption for the SAR ADC.
[0008] Figure 1 The overall architecture of the Vcm-Free switching scheme shown consists of a P-terminal capacitor array connected to the comparator Vxp side, an N-terminal capacitor array connected to the comparator Vxn side, reference voltages Vref and Vss, input signals Vin and Vip, and various switches Φ whose control capacitors are connected to the reference voltage. n1 ~Φ n24 and Φ p1 ~Φ p24 Composition. Among the switches controlling the capacitor connected to the reference voltage, switch Φ is used to connect the sampling signals Vip and Vin. n2， Φ n5， Φ n8， Φ n11， Φ n14， Φ n17， Φ n20， Φ n20， Φ n23， Φ p2， Φ p5， Φ p8， Φ p11， Φ p14， Φ p17， Φ p20， Φ p20， Φ p23 The bootstrap switch employs a gate voltage bootstrap architecture, ensuring that the Vgs voltage is one supply voltage higher than the input signals Vip and Vin during each sampling process. The remaining switches are CMOS switches composed of one PMOS or one NMOS, where Φ is used to connect Vref. n1 , Φ n4 , Φ n7 ,Φn10 , Φ n13 , Φ n16 , Φ n19 , Φ n22 , Φ p1 , Φ p4 , Φ p7 , Φ p10 , Φ p13 , Φ p16 , Φ p19 , Φ p22 It is a PMOS switch used to connect to Vss's Φ n3 , Φ n6 , Φ n9 , Φ n12 , Φ n15 , Φ n18 , Φ n21 , Φ n24 , Φ p3 ,Φ p6 , Φ p9 , Φ p12 , Φ p15 , Φ p18 , Φ p21 , Φ p24 This is an NMOS switch. It's used to connect to the upper plate of a capacitor. S / H1 and _Φ S / H2 It is a CMOS transmission gate switch composed of a PMOS and an NMOS.
[0009] Figure 1 The N-bit CDAC switched capacitor circuit includes a P-side capacitor array C with its upper plate connected to the positive terminal Vxp of the comparator. p0 ~C pN-3 The N-side capacitor array C connected to the negative terminal Vxn of the comparator and the upper plate n0 ~C nN-3 C p Represents the capacitance on the P side, C n This represents the N-side capacitor, where N represents N-bit resolution. Taking the P-side capacitor array as an example, C... pN-3 The capacitance at the location is 2 N-3 C, and split into two 2s N-4 C capacitor, second highest capacitor C pN-4 The value for the two splits is 2. N-5 The capacitance C is halved in subsequent iterations until the capacitance C is reached. p1 and C p0 The value for two splits is 1 / 2 * 2 0 C is the capacitance, where C is the unit capacitance.
[0010] For the highest-position capacitor on the P side of the Vcm-Free type switching scheme, the lower plate of the capacitor is connected via Φ n1， Φ n2， Φ n3 Connected to Vref, Vin, and Vss respectively, the upper plate is connected via Φ S / H2 Connect to Vss via _Φ S / H1 The capacitor on the low-order side is connected to the positive input terminal Vxp of the comparator. The capacitors on the P-side, except for the highest-order capacitor, are connected to the lower plate via Φ. n4， Φ n5， Φ n6 ;Φ n7， Φ n8， Φ n9 ;…;Φ n22， Φ n23， Φ n24 Connected to Vref, Vin, and Vss respectively, the upper plate is connected via Φ S / H1 Connected to Vref via _Φ S / H1 The highest-order capacitor is connected to the comparator's positive input terminal Vxp. For the highest-order capacitor on the N-side of the Vcm-Free type switching scheme, the lower plate of the capacitor is connected via Φ... p1， Φ p2， Φ p3 Connected to Vref, Vip, and Vss respectively, the upper electrode plate is connected via Φ S / H3 Connect to Vss via _Φ S / H2 Connect the low-order capacitor to the comparator's negative input terminal Vxn. The capacitors on the P side, except for the highest-order capacitor, are connected to the lower plate via Φ. p4， Φ p5， Φ p6 ;Φ p7， Φ n8， Φ p9 ;…;Φ p22， Φ p23， Φ p24 Connected to Vref, Vip, and Vss respectively, the upper electrode plate is connected via Φ S / H4 Connected to Vref via _Φ S / H2 Connect it to the highest bit capacitor and to the positive input terminal Vxp of the comparator. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of the Vcm-Free switch switching scheme proposed in this invention.
[0012] Figure 2 This is a schematic diagram of the switching process of the Vcm-Free switch switching scheme proposed in this invention. Detailed Implementation
[0013] The specific working process of this invention is as follows: Figure 2 The diagram is shown in 4-bit resolution. It includes capacitors C1-C12 and switches S1-S6. C1-C6 form the N-side capacitors, and C7-C12 form the P-side capacitors. The upper plates of the N-side capacitors are connected to the positive input of the comparator, and the upper plates of the P-side capacitors are connected to the negative input of the comparator. The upper plates of N-side capacitors C1-C3 are also connected to Vss, and the upper plates of C4-C6 are connected to Vref. The upper plates of P-side capacitors C7-C9 are also connected to Vss, and the upper plates of C10-C12 are connected to Vref. S1 and S5 are PMOS switches composed of a single PMOS transistor, S2 and S4 are NMOS switches composed of a single NMOS transistor, and S3 and S6 are transmission gate switches composed of both PMOS and NMOS transistors. The relationships between the capacitors are as follows: C1, C4, C7, and C10 are equal; C2, C5, C8, C11, C3, C6, C9, and C12 are equal; and C1 = 2 * C2. The switching feature of this invention includes:
[0014] During the sampling phase, the input differential signal is sampled onto the lower plates of all capacitors C1~C12 of the CDAC via a lower plate sampling method, resulting in Vin and Vip. During this sampling phase, the upper plate sampling switch Φ... S / H Open the circuit. Connect the upper plates of capacitors C1-C3 and C7-C9 to Vss, and connect the upper plates of capacitors C4-C6 and C10-C12 to Vref. After sampling, turn on the upper plate sampling switch Φ. S / H Disconnect, and simultaneously, connect the switch Φ to the upper plate of the capacitor. S / H When switch B is closed, the voltage across the upper plate of the capacitor first reaches 1 / 2 Vref. Then, the lower plates of capacitors C1-C3 and C7-C9 are connected to Vref, and the lower plates of capacitors C4-C6 and C10-C12 are connected to Vss. At this point, the sampling and holding phase ends. The voltage across the upper plate of the capacitor at the positive terminal of the input comparator becomes Vref-Vin, and the voltage across the upper plate of the capacitor at the negative terminal of the input comparator becomes Vref-Vip. Switch Φ... S / H B remains closed until the current quantization is completely finished.
[0015] In the second stage, quantization begins, the comparator starts working, completes the first comparison, and based on the comparator result, the Vcm-free switching scheme begins to control the capacitor switch to switch.
[0016] When Vip > Vin, the most significant bit B[3] is quantized to "1". At this time, the lower plates of capacitors C10, C11, and C12 connected to the negative terminal of the comparator are switched from Vss to Vref. The voltage at the negative terminal of the input comparator is Vref - Vip + 1 / 2 Vref, while the voltage at the positive terminal remains unchanged at Vref - Vin. Conversely, when the most significant bit B[3] is quantized to "0", the lower plates of capacitors C4, C5, and C6 connected to the N terminal of the comparator are switched from Vss to Vref. The voltage at the positive terminal of the input comparator is Vref - Vip + 1 / 2 Vref, while the voltage at the negative terminal remains unchanged at Vref - Vin. After the most significant bit is quantized, the most significant bit capacitors C1 and C7 do not switch independently, which is one of the main features of this invention.
[0017] In the third stage, the next quantization is performed. When the second highest bit B[2] is quantized to "0", the lower plate of capacitor C7 connected to the negative terminal of the comparator is switched from Vref to Vss. At this time, the voltage value of the input comparator negative terminal is Vref-Vip+1 / 2Vref-1 / 4Vref. Conversely, when the second highest bit B[2] is quantized to "1", the lower plate of capacitor C1 is switched from Vref to Vss. The reference voltage of the capacitors at other positions does not change. In this stage, the highest bit capacitors C1 and C7 are switched independently once. Thus, the second highest bit B[2] is quantized.
[0018] In the fourth stage, the combination of B[3]B[2] has four cases: 00, 01, 10, and 11. Taking stage A as an example, when B[3]B[2]=11, the lower plate of capacitor C1 switches from Vref to Vss. When B[1]=1, the lower plate of capacitor C2 switches from Vref to Vss. At this time, the voltage of the upper plate of the capacitor connected to the positive terminal of the comparator is 1 / 4Vref-Vin, and the voltage of the lower plate of the capacitor connected to the negative terminal of the comparator is Vref-Vip. Then, the comparison of the last bit B[0] is performed. If Vip>Vin+3 / 4Vref, then B[0] is 1; otherwise, B[0] is 0. Thus, the 4-bit determination ends. At this time, wait for the sampling clock source to generate the sampling clock signal and enter the sampling stage again.
Claims
1. A Vcm-free capacitor switch switching scheme for SAR ADC, characterized in that: The capacitor array connected to the P-terminal of comparator Vxp, the capacitor array connected to the N-terminal of comparator Vxn, the reference voltages Vref and Vss, the input signals Vin and Vip, and the switches Φ controlling the capacitors connected to the reference voltage are all included. n1 ~Φ n24 and Φ p1 ~Φ p24 Composition; Among the switches that control the capacitor connected to the reference voltage, the switch Φ used to connect the sampling signals Vip and Vin. n2， Φ n5， Φ n8， Φ n11， Φ n14， Φ n17， Φ n20， Φ n20， Φ n23， Φ p2， Φ p5， Φ p8， Φ p11， Φ p14， Φ p17， Φ p20， Φ p20， Φ p23 The bootstrap switch employs a gate voltage bootstrap architecture, ensuring that the Vgs voltage is one supply voltage higher than the input signals Vip and Vin voltages during each sampling process; the remaining switches are all CMOS switches composed of one PMOS or one NMOS, wherein the Φ used to connect Vref... n1 , Φ n4 , Φ n7 , Φ n10 , Φ n13 , Φ n16 , Φ n19 , Φ n22 , Φ p1 , Φ p4 ,Φ p7 , Φ p10 , Φ p13 , Φ p16 , Φ p19 , Φ p22 It is a PMOS switch used to connect to Vss's Φ n3 , Φ n6 , Φ n9 ,Φ n12 , Φ n15 , Φ n18 , Φ n21 , Φ n24 , Φ p3 , Φ p6 , Φ p9 , Φ p12 , Φ p15 , Φ p18 , Φ p21 , Φ p24 This is an NMOS switch; a switch used to connect to the upper plate of a capacitor. S / H1 and _Φ S / H2 It is a CMOS transmission gate switch composed of a PMOS and an NMOS.
2. The Vcm-free capacitor switch switching scheme for SAR ADC according to claim 1, characterized in that: The N-bit CDAC switched capacitor circuit includes a P-side capacitor array C with its upper plate connected to the positive terminal Vxp of the comparator. p0 ~C pN-3 The N-side capacitor array C connected to the negative terminal Vxn of the comparator and the upper plate n0 ~C nN-3 C p Represents the capacitance on the P side, C n This represents the N-side capacitor, where N represents N-bit resolution; taking the P-side capacitor array as an example, C pN-3 The capacitance at the location is 2 N-3 C, and split into two 2s N-4 C capacitor, second highest capacitor C pN-4 The value for the two splits is 2. N-5 The capacitance C is halved in subsequent iterations until the capacitance C is reached. p1 and C p0 The value for two splits is 1 / 2 * 2 0 C is the capacitance, where C is the unit capacitance.
3. The Vcm-free capacitor switch switching scheme for SAR ADC according to claim 1, characterized in that: For the highest-position capacitor on the P side of the Vcm-Free type switching scheme, the lower plate of the capacitor is connected via Φ n1， Φ n2， Φ n3 Connected to Vref, Vin, and Vss respectively, the upper electrode is connected via Φ S / H2 Connect to Vss via _Φ S / H1 The capacitor on the low-order side is connected to the positive input terminal Vxp of the comparator; the capacitors on the P side, except for the highest-order capacitor, are connected to the lower plate through Φ. n4， Φ n5， Φ n6 ;Φ n7， Φ n8， Φ n9 ;…;Φ n22， Φ n23， Φ n24 Connected to Vref, Vin, and Vss respectively, the upper plate is connected via Φ S / H1 Connected to Vref via _Φ S / H1 The highest-order capacitor is connected to the comparator's positive input terminal Vxp. For the highest-order capacitor on the N-side of the Vcm-Free type switching scheme, the lower plate of the capacitor is connected via Φ... p1， Φ p2， Φ p3 Connected to Vref, Vip, and Vss respectively, the upper electrode plate is connected via Φ S / H3 Connect to Vss via _Φ S / H2 The capacitor on the low-order side is connected to the negative input terminal Vxn of the comparator; the capacitors on the P side, except for the highest-order capacitor, are connected to the lower plate through Φ. p4， Φ p5， Φ p6 ;Φ p7， Φ n8， Φ p9 ;…;Φ p22， Φ p23， Φ p24 Connected to Vref, Vip, and Vss respectively, the upper electrode plate is connected via Φ S / H4 Connected to Vref via _Φ S / H2 Connect it to the highest bit capacitor and to the positive input terminal Vxp of the comparator.