Semiconductor device and method of manufacturing the same

Abstract

According to various embodiments, there is provided a semiconductor device and a method of manufacturing the same, the method of manufacturing a semiconductor device including: forming a gate full-loop field effect transistor including a plurality of stacked channel layers and source / drain regions; executing a deposition process at a first temperature to form a first epitaxial layer above the source / drain region, so that the tail ends of the plurality of stacked channel layers are in contact with the first epitaxial layer; and executing a second deposition process at a second temperature to form a second epitaxial layer in contact with the first epitaxial layer. In various embodiments, the second temperature is 20% to 30% lower than the first temperature. The resulting contact epitaxial layer is substantially free of dopant precipitates, and includes less than 50 misalignments, each misalignment having a length of 1 nm to 40 nm, and at an angle of between 20 degrees and 70 degrees with respect to the [110] crystal plane.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] As the semiconductor industry moves towards nanometer-scale technology nodes, the demand for higher device density, enhanced performance, and reduced costs presents significant manufacturing and design challenges. These challenges have led to the adoption of three-dimensional structures, such as multi-gate field-effect transistors (FETs), including finfield-effect transistors (FinFETs), gate-all-around field-effect transistors (GAA-FETs), and complementary FETs (CFETs). For example, in a FinFET, the gate electrode interfaces with three sides of a channel region separated by a gate dielectric layer. Because the gate surrounds three surfaces of the channel, this configuration effectively controls the current flowing through the channel. However, the fourth side, forming the bottom of the channel, is relatively far from the gate electrode, resulting in poorer gate control. In contrast, the gate electrode of a GAA-FET surrounds all sides of the channel region, allowing for more comprehensive channel depletion, and the short-channel effect is mitigated due to a steeper subcritical swing and a lower drain-induced barrier layer. As transistor sizes continue to shrink, GAA-FET technology needs further development to meet the growing demands of modern semiconductor devices. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a method of manufacturing a semiconductor device includes forming a gate full-ring field-effect transistor (GFPT), the GFPT including a plurality of stacked channel layers and source / drain regions; performing a deposition process at a first temperature to form a first epitaxial layer over the source / drain regions, such that a plurality of ends of the stacked channel layers contact the first epitaxial layer; and performing a second deposition process at a second temperature to form a second epitaxial layer in contact with the first epitaxial layer, wherein the second temperature is 20% to 30% lower than the first temperature.

[0004] According to one embodiment of the present disclosure, a method of manufacturing a semiconductor device includes forming a plurality of stacked semiconductor nanostructures serving as a plurality of channel layers; forming source / drain regions adjacent to a plurality of ends of the channel layers; forming a gate structure surrounding each channel layer; performing a first deposition process at a first temperature to form a first epitaxial layer over the source / drain regions and in contact with each of the stacked semiconductor nanostructures; performing a second deposition process at a second temperature to form a front contact epitaxial layer over the first epitaxial layer, such that the second temperature is 20% to 30% lower than the first temperature; and performing a third deposition process at a third temperature to form a back contact epitaxial layer over the first epitaxial layer, such that the third temperature is 20% to 30% lower than the first temperature, wherein the first epitaxial layer contains a first dopant concentration; the front contact epitaxial layer and the back contact epitaxial layer each contain a second dopant concentration, the second dopant concentration being greater than the first dopant concentration; and the front contact epitaxial layer is formed after the first epitaxial layer, and the back contact epitaxial layer is formed after the front contact epitaxial layer.

[0005] According to one embodiment of this disclosure, a semiconductor device includes a transistor structure, a first epitaxial layer, a second epitaxial layer, and conductive contacts. The transistor structure includes a channel layer and source / drain regions. The first epitaxial layer is formed above the source / drain regions, such that the first epitaxial layer is in contact with the channel layer. The second epitaxial layer is in contact with the first epitaxial layer. The conductive contacts are connected to the second epitaxial layer, such that the second epitaxial layer is located between the second epitaxial layer and the conductive contacts. The first epitaxial layer includes a crystal structure, and the concentration of a first dopant in the crystal structure is 5 × 10⁻⁶. 20 atoms / cm 3 With 5×10 21 atoms / cm 3 Between. The second epitaxial layer contains a crystal structure, and the concentration of the second dopant in the crystal structure is greater than the concentration of the first dopant and is within 1×10. 20 atoms / cm 3 With 7×10 21 atoms / cm 3 Between, the second epitaxial layer contains fewer than 50 dislocations. Attached Figure Description

[0006] The contents of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A is a vertical cross-sectional view of a semiconductor device used as a gate-all-around field-effect transistor (GAA FET) according to various embodiments;

[0008] Figure 1 B is based on various embodiments Figure 1 A vertical cross-sectional view of a portion of the front contact of semiconductor device A;

[0009] Figure 1 C represents various embodiments. Figure 1 A vertical cross-sectional view of a portion of the back contact of semiconductor device A;

[0010] Figure 2 This is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0011] Figure 3 This is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0012] Figure 4 This is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0013] Figure 5 This is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0014] Figure 6 This is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0015] Figure 7 This is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0016] Figure 8 This is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0017] Figure 9A This is a vertical cross-sectional view of a structure for forming a front contact in a semiconductor device according to various embodiments;

[0018] Figure 9B This is a vertical cross-sectional view of a structure for forming a front contact in a semiconductor device according to various embodiments;

[0019] Figure 9C This is a vertical cross-sectional view of a structure for forming a front contact in a semiconductor device according to various embodiments;

[0020] Figure 10A This is a vertical cross-sectional view of a structure for forming a back contact in a semiconductor device according to various embodiments;

[0021] Figure 10B This is a vertical cross-sectional view of a structure for forming a back contact in a semiconductor device according to various embodiments;

[0022] Figure 10C This is a vertical cross-sectional view of a structure for forming a back contact in a semiconductor device according to various embodiments;

[0023] Figure 10D This is a vertical cross-sectional view of a structure for forming a back contact in a semiconductor device according to various embodiments;

[0024] Figure 10E This is a vertical cross-sectional view of a structure having front contacts and back contacts in a semiconductor device according to various embodiments;

[0025] Figure 10F A vertical cross-sectional view of a structure with alternative configurations of back contacts according to various embodiments;

[0026] Figure 10G A vertical cross-sectional view of a structure with alternative configurations of back contacts according to various embodiments;

[0027] Figure 10H A vertical cross-sectional view of a structure with alternative configurations of back contacts according to various embodiments;

[0028] Figure 11A A vertical cross-sectional view of a semiconductor device with crystal dislocation according to various embodiments;

[0029] Figure 11B A vertical cross-sectional view of a semiconductor device with crystal dislocation according to various embodiments;

[0030] Figure 11C A vertical cross-sectional view of a semiconductor device with crystal dislocation according to various embodiments;

[0031] Figure 11D This is a vertical cross-sectional view of a semiconductor device having crystal dislocations and dopant deposits according to various embodiments;

[0032] Figure 12 A is a vertical cross-sectional view of a semiconductor device having doped deposits and / or amorphous regions according to various embodiments;

[0033] Figure 12 B is a vertical cross-sectional view of a contact epitaxial layer having an amorphous region according to various embodiments;

[0034] Figure 12 C is a vertical cross-sectional view of a contact epitaxial layer with a crystal structure according to various embodiments;

[0035] Figure 12 D is a vertical cross-sectional view of the contact epitaxial layer with dopant precipitates according to various embodiments;

[0036] Figure 12 E is a vertical cross-sectional view of a contact epitaxial layer with an amorphous structure according to various embodiments;

[0037] Figure 13 A flowchart illustrating the operation of a method for forming a semiconductor device according to various embodiments;

[0038] Figure 14 A flowchart illustrating the operation of a method for forming a semiconductor device according to various embodiments.

[0039] [Symbol Explanation]

[0040] 100a: Semiconductor device

[0041] 106: SiGe source / drain characteristics

[0042] 116a: Front contact

[0043] 116b: Back contact

[0044] 118: Contact epitaxial layer

[0045] 120: Silicide layer

[0046] 122: Thickness

[0047] 200, 300, 600, 700, 800, 900a~900c, 1000a~1000h, 1100a~1100d, 1200a~1200e: Structure

[0048] 201: Substrate

[0049] 202: Carrier layer

[0050] 203: Insulation layer

[0051] 204: Semiconductor layer

[0052] 205: Fin-shaped structure

[0053] 205C: Passage Area

[0054] 205D: Drain region

[0055] 205S: Source Region

[0056] 206: Sacrificial Layer

[0057] 207, 207': Backside source contact opening

[0058] 208: Channel Layer

[0059] 210: Sacrificial gate stack

[0060] 211: Sacrificial dielectric layer

[0061] 212: Sacrificial gate electrode layer

[0062] 213: Silicon oxide layer

[0063] 214: Silicon nitride layer

[0064] 215: Hard masking layer at the top of the gate

[0065] 216: Gate spacer layer

[0066] 216a: First gate spacer layer

[0067] 216b: Second gate spacer layer

[0068] 218D: Drain opening

[0069] 218S: Source Opening

[0070] 220: Characteristics of internal spacers

[0071] 230: Isolation Structure

[0072] 232: Source / Drain Characteristics

[0073] 232D: Drain Characteristics

[0074] 232S: Source Characteristics

[0075] 234: Contact Etching Termination Layer

[0076] 234a: Part 1 of CESL

[0077] 234b: Part Two of CESL

[0078] 236: Interlayer dielectric layer

[0079] 240: Gate structure

[0080] 242: Gate dielectric layer

[0081] 244: Gate electrode layer

[0082] 262: Dielectric barrier layer

[0083] 402: Misalignment

[0084] 404: Misalignment length

[0085] 406: Dopant precipitate

[0086] 502: Amorphous region

[0087] 504: Crystal Structure

[0088] 1300, 1400: Method

[0089] 1302, 1304, 1306, 1402, 1404, 1406, 1408, 1410, 1412: Operations

[0090] H: Height

[0091] W_1, W_2: Width

[0092] W_B: Bottom width

[0093] X, Y, Z: Direction Detailed Implementation

[0094] It should be understood that the following disclosure provides several different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements described below are intended to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the range or values ​​disclosed, but may be determined depending on process conditions and / or the desired nature of the apparatus. Furthermore, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. For simplicity and clarity, various features may be drawn at any scale.

[0095] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature and another element or feature illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly. Additionally, the term “made of” may mean “comprising” or “consisting of.” In this disclosure, the phrase “one of A, B, and C” means “A, B, and / or C” (A; B; C; A and B; A and C; B and C; or A, B, and C), and unless otherwise stated, does not mean that one element comes from A, one element from B, and one element from C.

[0096] The disclosed embodiments are advantageous because they provide semiconductor device structures with improved source / drain characteristics and improved contact epitaxial layers. In this regard, the source / drain characteristics are formed by performing an epitaxial deposition process at a first temperature, and the contact epitaxial layer is formed by performing a second epitaxial deposition process at a second temperature, which is 20% to 30% lower than the first temperature. By controlling the process conditions according to the various disclosed embodiments, high-quality device structures with minimal dislocations, amorphous materials, and dopant deposits can be obtained.

[0097] Figure 1 A is a vertical cross-sectional view of a semiconductor device 100a used as a gate-all-around field-effect transistor (GAA-FET) device according to various embodiments. The semiconductor device 100a includes a plurality of semiconductor nanostructure layers, each serving as a channel layer 208. The semiconductor device 100a further includes a gate electrode layer 244 surrounding each channel layer 208. The gate electrode layer 244 includes a conductive material spaced from the plurality of channel layers 208 by a gate dielectric layer 242.

[0098] Semiconductor device 100a further includes source feature 232S and drain feature 232D formed above the ends of each channel layer 208. According to some embodiments, source feature 232S and drain feature 232D have similar structures and are collectively referred to as source / drain feature 232. In other embodiments, source feature 232S and drain feature 232D have different structures and compositions. According to various embodiments, semiconductor device 100a is formed above semiconductor layer 204. In this regard, Figure 1 The plane of A intersects the semiconductor layer 204 along the longitudinal direction (i.e., along the

[110] crystal of source feature 232S).

[0099] Semiconductor device 100a further includes a front contact 116a and a back contact 116b. Both the front contact 116a and the back contact 116b include a conductive material coupled to the source feature 232S. In this regard, both the front contact 116a and the back contact 116b include a contact epitaxial layer 118 formed in contact with the source feature 232S. According to various embodiments, the doping concentration of the contact epitaxial layer 118 is greater than the doping concentration of the source feature 232S. Therefore, the conductivity of the contact epitaxial layer 118 is selected to more closely match the conductivity of the conductive material forming the front contact 116a and the back contact 116b, thereby reducing the resistance associated with the front contact 116a and the back contact 116b. The gate structure 240 and the front contact 116a are formed within an interlayer dielectric (ILD) layer 236, as described in more detail below. The semiconductor device 100a further includes a contact etch-stop layer 234 formed between the ILD layer 236 and the source / drain features (232S, 232D), as described in more detail below.

[0100] Figure 1 B is a vertical cross-sectional view of a portion of the front contact 116a according to various embodiments, while Figure 1 C is a vertical cross-sectional view of a portion of the back contact 116b. (See diagram below.) Figure 1 A to Figure 1 As shown in Figure C, a silicide layer 120 is formed between the front contact 116a and the contact epitaxial layer 118, and between the back contact 116b and the corresponding contact epitaxial layer 118. According to various embodiments, the source feature 232S and the contact epitaxial layer 118 are formed of a doped semiconductor material (e.g., silicon, SiGe, etc.), while the conductive material of the front contact 116a and the back contact 116b is a metal. Therefore, the silicide layer 120 is selected as a metal / semiconductor alloy, such as TiSi. According to various embodiments, the contact epitaxial layer 118 has a thickness 122 between about 0.5 nm and about 10 nm, and the silicide layer 120 has a similar thickness.

[0101] According to various embodiments, both the source feature 232S and the contact epitaxial layer 118 are n-type doped semiconductor layers. For example, according to some embodiments, the source feature 232S is an n-type doped silicon layer, while the contact epitaxial layer 118 is an n-type doped silicon layer formed above the source feature 232S. The doping concentration of the contact epitaxial layer 118 is higher than that of the source feature 232S. For example, in some embodiments, the source feature 232S is doped with phosphorus at a doping concentration of approximately 5 × 10⁻⁶. 20 atoms / cm 3 With approximately 5×10 21 atoms / cm 3 Between these, the contact epitaxial layer 118 is doped with phosphorus, with a doping concentration of approximately 1 × 10⁻⁶. 21 atoms / cm3 With approximately 7×10 21 atoms / cm 3 between.

[0102] In other embodiments, both the source feature 232S and the contact epitaxial layer 118 are p-type doped semiconductor layers. For example, according to some embodiments, the source feature 232S is a first p-type doped SiGe alloy layer, while the contact epitaxial layer 118 is a second p-type doped SiGe alloy layer formed above the source / drain epitaxial layer. In some embodiments, the source feature 232S has a Si composition. x Ge 1-x The SiGe alloy layer has a doping concentration of x between about 0.4 and about 0.6, while the contact epitaxial layer 118 is a SiGe alloy layer with a composition of SixGe1-x, where x is between about 0.05 and about 0.5. The doping concentration of the contact epitaxial layer 118 is higher than that of the source feature 232S. For example, in some embodiments, the source feature 232S is doped with boron at a doping concentration of about 7 × 10⁻⁶. 20 atoms / cm 3 With approximately 1×10 21 atoms / cm 3 Between these layers, the contact epitaxial layer 118 is doped with boron, with a doping concentration of approximately 1 × 10⁻⁶. 20 atoms / cm 3 With approximately 7×10 21 atoms / cm 3 between.

[0103] like Figure 1 As shown in Figure A, semiconductor device 100a includes an inner spacer feature 220 formed between a gate dielectric layer 242 and a source feature 232S, and between a gate dielectric layer 242 and a drain feature 232D. In some embodiments, the inner spacer feature 220 is made of a dielectric material, such as a silicon-containing dielectric material, including but not limited to silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and / or oxygen-doped silicon carbonitride. In some embodiments, the inner spacer feature 220 comprises a low dielectric constant (low k) material. For example, in some embodiments, the dielectric constant (k) value of the inner spacer feature 220 is lower than the dielectric constant (k) value of silicon oxide, such as below 4.2, equal to or below about 3.9, or in the range of about 3.5 to about 3.9.

[0104] In some embodiments, the inner spacer feature 220 is formed by a deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or high aspect ratio process (HARP) CVD, other suitable techniques, and / or combinations thereof. In some embodiments, an etch-back process is performed, including: anisotropic etching processes, such as dry plasma etching; isotropic etching processes, such as dry chemical etching, remote plasma etching, wet chemical etching, and / or combinations thereof, as seen in [reference needed]. Figure 4 and Figure 5 To describe in more detail.

[0105] In embodiments where the semiconductor device 100a is formed as an n-channel nanostructure device (such as an n-channel GAA FET), the source / drain features (232S, 232D) comprise semiconductor materials such as silicon phosphide (SiP), silicon arsenide (SiAs), silicon carbide phosphide (SiCP), silicon carbide (SiC), silicon, gallium arsenide (GaAs), or other suitable semiconductor materials or combinations thereof. In some embodiments, the source / drain features (232S, 232D) are doped with an n-type dopant during an epitaxial growth process. For example, in some embodiments, the n-type dopant is phosphorus or arsenic. In some embodiments, the source / drain features (232S, 232D) are phosphorus-doped epitaxially grown silicon to form silicon phosphide (SiP).

[0106] In embodiments where the semiconductor device 100a is formed as a p-channel nanostructure device (such as a p-channel GAA FET), the source / drain features (232S, 232D) are made of a semiconductor material, such as silicon germanium (SiGe), silicon (Si), gallium arsenide (GaAs), or other suitable semiconductor materials or combinations thereof. In some embodiments, the source / drain features (232S, 232D) are doped with a p-type dopant during an epitaxial growth process. For example, in some embodiments, the p-type dopant is boron or boron difluoride (BF2). In some embodiments, the source / drain features (232S, 232D) are boron-doped epitaxially grown SiGe to form SiGe source / drain features 106.

[0107] In some embodiments, the epitaxial growth process for forming the source feature 232S is cyclic deposition etch epitaxy (CDE). CDE involves periodic deposition operations in which the semiconductor structure is exposed to precursor pulses for deposition and doping, followed by exposure to an etchant gas for a first cycle. This is followed by a second cycle, during which the semiconductor device is exposed only to the etchant gas and not to the precursor. The process is then repeated, and in a third cycle, the semiconductor device is again exposed to precursor pulses for deposition and doping, followed by exposure to the etchant gas. This cycle is repeated until the desired thickness of the source / drain features (232S, 232D) is formed. See below. Figures 2 to 10E More details are described in the processing operations used to form the semiconductor device 100a.

[0108] Figure 2 This is a vertical cross-sectional view of a structure 200 for forming a semiconductor device 100a according to various embodiments. Structure 200 includes a substrate 201. In embodiments, substrate 201 is a bulk silicon substrate (i.e., including bulk single-crystal silicon). In various embodiments, substrate 201 includes other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof, or other suitable materials. In some alternative embodiments, substrate 201 is a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate is fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. In the illustrated embodiment, substrate 201 is an SOI substrate and includes a carrier layer 202, an insulating layer 203 on the carrier layer 202, and a semiconductor layer 204 on the insulating layer 203. In some embodiments, semiconductor layer 204 is silicon, silicon-germanium, germanium, or other suitable materials, and is undoped or unintentionally doped with a low dose of dopant. In the illustrated example, carrier layer 202 includes silicon, insulating layer 203 includes silicon oxide, and semiconductor layer 204 includes silicon (i.e., monocrystalline silicon).

[0109] Structure 200 includes a fin structure 205 disposed above substrate 201. The fin structure 205 extends longitudinally along the X direction and is divided into a channel region 205C, a source region 205S, and a drain region 205D that overlap with the sacrificial gate stack 210 (described below). In this example, Figure 2 The diagram shows two channel regions 205C, one source region 205S, and two drain regions 205D. However, in other embodiments, structure 200 includes additional source / drain regions (205S, 205D) and channel region 205C.

[0110] The fin structure 205 is formed by a combination of photolithography and etching steps using a portion of semiconductor layer 204 and a vertically stacked alternating semiconductor layers (206, 208). An illustrative photolithography process involves spin-coating a photoresist layer, soft-baking the photoresist layer, aligning a mask, exposure, post-exposure baking, developing the photoresist layer, rinsing, and drying (e.g., hard baking). In some cases, the patterning of the fin structure 205 uses a dual-patterning or multi-patterning process to create patterns with a spacing smaller than that achievable using a single direct photolithography process. Etching processes include dry etching, wet etching, and / or other suitable techniques.

[0111] In the illustrated embodiment, the vertical stacking of alternating semiconductor layers (206, 208) includes multiple channel layers 208 interleaved with multiple sacrificial layers 206. Each channel layer 208 is composed of silicon (Si), and each sacrificial layer 206 is composed of silicon germanium (SiGe). The channel layers 208 and sacrificial layers 206 are epitaxially deposited on the substrate 201 using molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), and / or other suitable epitaxial growth processes.

[0112] although Figure 2Not explicitly shown, however, isolation features surround the fin structure 205 to isolate the fin structure 205 from adjacent fin structures (i.e., separated from each other along the y-direction). In some embodiments, the isolation features are deposited in trenches defining the fin structure 205. These trenches extend through the channel layer 208 and the sacrificial layer 206 and terminate at the substrate 201. Isolation features, also known as shallow trench isolation (STI) features, are formed using a dielectric material disposed above the structure 200 using techniques such as chemical vapor deposition (CVD), subatmospheric CVD (SACVD), flowable CVD (FCVD), physical vapor deposition (PVD), spin coating, and / or other suitable processes. The deposited dielectric material is planarized and recessed until the fin structure 205 rises above the isolation features. Dielectric materials with isolation characteristics include silicon oxide, silicon oxynitride, fluorosilicate glass (FSG), low-k dielectric materials and combinations thereof, and / or other suitable materials.

[0113] As described above, structure 200 includes a sacrificial gate stack 210 disposed above the channel region 205C of fin structure 205. The channel region 205C and the sacrificial gate stack 210 define a source region 205S and a drain region 205D, wherein the plurality of source regions 205S and drain regions 205D are regions of the sacrificial gate stack 210 that do not vertically overlap. Each channel region 205C is located between the source region 205S and the drain region 205D along the X direction. Figure 2 This describes two sacrificial gate stacks 210, but other embodiments of structure 200 include additional sacrificial gate stacks 210.

[0114] In the described embodiment, a gate replacement process (or post-gate process) is employed, wherein the sacrificial gate stack 210 serves as the functional gate structure (e.g., Figure 1 Placeholder for gate structure 240 shown in Figure A. The sacrificial gate stack 210 includes a sacrificial dielectric layer 211, a sacrificial gate electrode layer 212 above the sacrificial dielectric layer 211, and a gate top hard mask layer 215 above the sacrificial gate electrode layer 212. The sacrificial dielectric layer 211 includes silicon oxide, the sacrificial gate electrode layer 212 is made of polysilicon, and the gate top hard mask layer 215 is multilayered, including a silicon oxide layer 213 and a silicon nitride layer 214 formed on the silicon oxide layer 213. The dummy gate stack 210 is formed using appropriate deposition, lithography, and etching processes.

[0115] like Figure 2As shown, structure 200 includes a gate spacer layer 216 disposed above structure 200. Gate spacer layer 216 includes a first gate spacer layer 216a and a second gate spacer layer 216b conformally deposited above structure 200, covering the top surface and sidewalls of the sacrificial gate stack 210 and the top surface of the fin structure 205. The term "conformal" describes a layer having a substantially uniform thickness over various regions. In some embodiments, the dielectric constant of the second gate spacer layer 216b exceeds that of the first gate spacer layer 216a, and the second gate spacer layer 216b exhibits greater etch resistance compared to the first gate spacer layer 216a. In some embodiments, the first gate spacer layer 216a comprises silicon oxide, silicon carbide, or a suitable low-k dielectric material. In some embodiments, the second gate spacer layer 216b comprises silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. The first gate spacer layer 216a and the second gate spacer layer 216b are deposited on top of the dummy gate stack 210 using processes such as CVD, SACVD, FCVD, atomic layer deposition (ALD), PVD or other suitable processes.

[0116] Figure 3 This is a vertical cross-sectional view of a structure 300 for forming a semiconductor device 100a according to various embodiments. According to various embodiments, structure 300 is formed by structure 200 by recessing the source region 205S and two drain regions 205D of fin structure 205 to create source openings 218S and two drain openings 218D. In some embodiments, the source region 205S and drain region 205D of the fin structure not covered by the dummy gate stack and gate spacer layer 216 are anisotropically etched using a dry etching process or a suitable etching technique. The dry etching process utilizes oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma or combinations thereof. Source opening 218S and drain opening 218D extend through the vertical stack of channel layer 208 and sacrificial layer 206. These openings extend into the semiconductor layer 204 of substrate 201. The sidewalls of channel layer 208 and sacrificial layer 206 are exposed within the source and drain openings, as shown below. Figure 3 As shown.

[0117] See Figure 4 and Figure 5After creating the source opening 218S and drain opening 218D, the inner spacer feature 220 is formed. Once the source opening 218S and drain opening 218D are formed, the sacrificial layer 206 is exposed within these openings. Figure 4 As shown, the sacrificial layer 206 is selectively and partially recessed to create an inner spacer trench, while the exposed channel layer 208 is not significantly etched. In embodiments where the channel layer 208 is made of silicon (Si) and the sacrificial layer 206 is made of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 involves a selective isotropic etching process, which may include a selective dry etching process or a selective wet etching process. The degree of recess is controlled by the duration of the etching process. After forming the inner spacer trench, an inner spacer material layer is deposited over the structure (including within the trench). The inner spacer material layer includes silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or other suitable dielectric materials. The deposited inner spacer material layer is then etched back to remove excess material from the sidewalls of the channel layer 208, thereby forming the inner spacer feature 220, as shown. Figure 5 As shown. In some embodiments, the etch-back process is a dry etching process, similar to the process used to form the source aperture 218S and the drain aperture 218D.

[0118] Figure 6 This is a vertical cross-sectional view of a structure 600 for forming a semiconductor device 100a according to various embodiments. Figure 6 As shown, a source feature 232S is formed in a source opening 218S, and a drain feature 232D is formed in a drain opening 218D. Before forming the source feature 232S and drain feature 232D, an isolation structure 230 is formed at the bottom of the source opening 218S and the bottom of the drain opening 218D. The isolation structure 230 is a dielectric layer and is referred to in some embodiments as a “flexible bottom isolation” structure. The isolation structure 230 reduces or substantially prevents current leakage between the source feature 232S, the drain feature 232D, and the semiconductor layer 204 or additional features formed on the back side of the structure 200. In some embodiments, the isolation structure 230 comprises silicon oxide, silicon nitride, SiCN, SiCON, SiOC, SiC, or other suitable materials, and is formed by oxidation (e.g., forming silicon oxide) or by a conformal deposition process followed by further processing, as shown below.

[0119] An isolation structure 230 is formed by performing one or more conformal film deposition processes (such as plasma-enhanced atomic layer deposition (PEALD) or PECVD) followed by a film treatment process (such as etching back). The resulting conformal film inherits the shape of the underlying structure on which it is formed. The film deposition process employs a cyclic PEALD method, using dichlorosilane (DCS) and ammonia / argon (NH3 / Ar) plasma as the reaction gases. The subsequent film treatment process uses argon / nitrogen (Ar / N2) plasma for etching.

[0120] In other embodiments, the isolation structure 230 is formed as an epitaxial semiconductor feature, which is epitaxially and selectively formed on the exposed top surface of the semiconductor layer 204 using epitaxial processes such as molecular beam epitaxy (MBE), apor-phase epitaxy (VPE), ultra-high-vacuum chemical vapor deposition (UHV-CVD), metal-organic chemical vapor deposition (MOCVD), or other suitable epitaxial growth processes. In the various embodiments, the bottom surface of the isolation structure 230 generally follows the shape of the bottom surface of the source and drain openings (218S, 218D). Because the surface of the inner spacer feature 220 is unfavorable for epitaxial deposition, the isolation structure 230 is formed from the exposed surface of the semiconductor layer 204 of the substrate 201 in a bottom-up manner. In cross-section, the isolation structure 230 presents a crescent shape in the illustrated embodiment. Depending on the conductivity type of the source feature 232S, the isolation structure 230 comprises different components. In some embodiments, for the n-type source feature 232S, the isolation structure 230 comprises undoped silicon (Si), while for the p-type source feature 232S, the isolation structure 230 comprises undoped silicon germanium (SiGe).

[0121] In some embodiments, an additional isolation structure, including a dielectric layer, is formed on the epitaxial semiconductor feature. This isolation structure may be referred to as a “flexible bottom isolation” structure. Using an epitaxial process, such as vapor-phase epitaxy (VPE), ultra-high-vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), or other suitable processes, source features 232S and drain features 232D are formed over the isolation structure 230. The epitaxial process uses gaseous and / or liquid precursors that interact with the components of the isolation structure 230. Source features 232S and drain features 232D are coupled to a channel layer 208 in the channel region 205C of the fin structure 205. Depending on the conductivity type of the formed transistor, source features 232S and drain features 232D are n-type and p-type source / drain features, respectively.

[0122] Exemplary n-type source / drain features include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, which can be in-situ doped during the epitaxial process by introducing an n-type dopant (such as phosphorus, arsenic, or antimony) or non-field doped using an ion implantation process. Exemplary p-type source / drain features include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, which can be in-situ doped during the epitaxial process by introducing a p-type dopant (such as boron or gallium) or non-field doped using an ion implantation process. In some embodiments, a lightly doped epitaxial semiconductor layer is formed between the source / drain features (232S, 232D) and the corresponding isolation structure 230, and the doping concentration of the lightly doped epitaxial semiconductor layer is lower than the doping concentration of the source / drain features (232S, 232D).

[0123] Figure 7 According to various embodiments, by Figure 6 The formed structure includes a contact etch stop layer (CESL) 234 and an interlayer dielectric (ILD) 236. CESL 234 comprises silicon nitride, silicon oxynitride, and / or similar materials, and is formed by atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition or oxidation processes. Figure 7As shown, CESL 234 is deposited on the top surfaces of source feature 232S and drain feature 232D and on the sidewalls of gate spacer layer 216. ILD layer 236 is deposited on top of CESL 234 by PECVD process or another suitable deposition technique. ILD layer 236 is made of materials such as tetraethoxysilane (TEOS) oxide, undoped silicon glass, or doped silicon oxide, such as borosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. In some embodiments, after the formation of ILD layer 236, structure 200 is annealed to improve the integrity of ILD layer 236.

[0124] Figure 8 According to various embodiments, by Figure 7 Structure 800 is formed from structure 700. According to various embodiments, structure 800 is formed by replacing the sacrificial gate stack 210 with gate structure 240. Structure 700 is planarized using a process such as chemical mechanical polishing (CMP) to remove excess material and expose the top surface of the sacrificial gate electrode layer 212 in the sacrificial gate stack 210. After exposing the sacrificial gate electrode layer 212, the next step is to remove the sacrificial gate stack 210 of structure 700. Removal of the sacrificial gate stack 210 includes one or more etching processes selectively targeting the material in the sacrificial gate stack 210. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove the sacrificial gate stack 210. After removing the sacrificial gate stack 210, the sacrificial layer 206 is selectively removed to release the channel layer 208 in the channel region 205C. The selective removal of the sacrificial layer 206 is achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., an ammonia hydroxide-hydrogen peroxide-water mixture).

[0125] Each gate structure 240 includes a gate dielectric layer 242 and a gate electrode layer 244 located above the gate dielectric layer 242. In some embodiments, the gate dielectric layer 242 includes an interface layer disposed on the channel layer 208 and a high-k dielectric layer located above the interface layer. A high-k dielectric layer refers to a dielectric material with a dielectric constant (approximately 3.9) greater than that of silicon dioxide. A low-k dielectric layer refers to a dielectric material with a dielectric constant not greater than that of silicon dioxide. In some embodiments, the interface layer includes silicon oxide. The high-k dielectric layer is then deposited above the interface layer using ALD, CVD, or other suitable methods. According to various embodiments, the high-k dielectric layer includes hafnium oxide. Alternatively, according to various embodiments, the high-k dielectric layer includes other high-k dielectrics such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, SrTiO3, BaTiO3, BaZrO3, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, (Ba, Sr)Ti3 (BST), silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials.

[0126] The gate electrode layer 244 is deposited over the gate dielectric layer 242 using ALD, PVD, CVD, electron beam evaporation, electroplating, or other suitable methods. The gate electrode layer 244 comprises a single-layer or multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a pad layer, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode layer 244 comprises titanium nitride, aluminum titanium nitride, titanium aluminum nitride, tantalum nitride, aluminum tantalum nitride, aluminum tantalum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, silicon tantalum nitride, copper, other refractory metals, or other suitable metallic materials or combinations thereof. Furthermore, in embodiments where structure 800 includes n-type and p-type transistors, different gate electrode layers are formed for the n-type and p-type transistors, each layer comprising a different work function metal layer (e.g., providing different n-type and p-type work function metal layers).

[0127] Figures 9A to 9C This is a vertical cross-sectional view of a structure (900a, 900b, 900c) for forming a front contact 116a in a semiconductor device 100a according to various embodiments. Figure 9AAs shown, a portion of the ILD layer 236 is etched to form an opening 207. An etching process can be performed to also remove a portion of the source feature 232S. Furthermore, the etching process removes a portion of the CESL 234, causing the CESL 234 to be divided into a first CESL portion 234a and a second CESL portion 234b. In the embodiment described, the first CESL portion 234a and the second CESL portion 234b are angled relative to the horizontal direction (i.e., the X direction). This configuration illustrates that, according to various embodiments, the CESL 234 does not need to have a horizontal direction when the top surface of the source feature 232S does not have a horizontal surface. For example, in some embodiments, the source feature 232S has a beveled end face, and in these embodiments, the CESL 234 corresponds to the beveled end face, thus having an angled configuration. Therefore, during etching, the angled configuration of the CESL 234 produces tilted first CESL portion 234a and second CESL portion 234b, as... Figure 9A As shown.

[0128] After the opening 207 is formed, in some embodiments, a contact epitaxial layer 118 is formed over the source feature 232S by performing a deposition process (e.g., MOCVD deposition process), such as... Figure 9B As shown. For example, in some embodiments, the step of forming source feature 232S further includes the step of depositing a first n-type doped silicon layer, and the step of forming contact epitaxial layer 118 further includes the step of depositing a second n-type doped silicon layer over the first epitaxial layer 232S. According to these embodiments, a deposition process is performed to provide in-situ doping of source feature 232S and contact epitaxial layer 118, such that source feature 232S has a first concentration of phosphorus, the first concentration being approximately 5 × 10⁻⁶. 20 atoms / cm 3 With approximately 5×10 21 atoms / cm 3 Between, and the contact epitaxial layer 118 has a second concentration of phosphorus, the second concentration being approximately 1 × 10⁻⁶. 21 atoms / cm 3 With approximately 7×10 21 atoms / cm 3 between.

[0129] Alternatively, in other embodiments, the step of forming the source feature 232S further includes the step of depositing a first p-type doped SiGe alloy layer, and the step of forming the contact epitaxial layer 118 further includes the step of depositing a second p-type doped SiGe alloy layer over the source feature 232S. For example, in some embodiments, the source feature 232S comprises Si x Ge 1-x Where x is between 0.4 and 0.6, and the contact epitaxial layer 118 includes Six Ge 1-x Where x is between 0.05 and 0.5. According to these embodiments, a deposition process is performed to provide in-situ doping of the source feature 232S and the contact epitaxial layer 118, such that the source feature 232S has a first concentration of boron, the first concentration being approximately 7 × 10⁻⁶. 20 atoms / cm 3 With approximately 1×10 21 atoms / cm 3 Between, and the contact epitaxial layer 118 has a second concentration of boron, the second concentration being approximately 1 × 10⁻⁶. 20 atoms / cm 3 With approximately 7×10 21 atoms / cm 3 between.

[0130] Subsequently, in some embodiments, a silicide layer 120 is formed over the contact epitaxial layer 118 (see, for example, see...). Figure 9C As shown below, a thin metal (not shown), such as titanium, tantalum, cobalt, tungsten, or nickel, is deposited on the source / drain epitaxial layer and surrounding area. The metal layer is then subjected to a rapid thermal annealing process, in which the metal layer reacts with the underlying silicon or SiGe layer to form a silicide layer 120. The choice of metal and annealing conditions are controlled to optimize the formation of the desired silicide phase, such as titanium silicide, cobalt silicide, or nickel silicide, exhibiting lower resistivity and stable electrical properties than the source / drain characteristics. After the formation of the silicide layer 120, in some embodiments, any unreacted metal and metal silicides are removed from unrelated areas, for example, by a selective etching process. This results in the highly conductive silicide layer 120 directly contacting the contact epitaxial layer 118. The presence of the silicide layer 120 provides a highly conductive contact with the subsequently formed front contact 116a. Alternatively, in some embodiments, the selective etching process is omitted, and a thin layer of metal is left on the exposed surface of the ILD layer 236 (not shown) before the formation of the pre-contact 116a.

[0131] The front contact 116a is then formed by depositing a conductive material over the silicide layer 120 within the opening 207. According to various embodiments, the conductive material is a combination of a metal substrate (such as a metal nitride or metal carbide) and a metal filler material. Each metal substrate includes one or more TiN, TaN, WN, TiC, TaC, or WC, and each metal filler material portion includes W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal substrates and metal filler materials are also intended and may be used within the scope of this disclosure.

[0132] Figures 10A to 10EThe above is a vertical cross-sectional view of a structure (1000a, 1000b, 1000c, 1000d, 1000e) for forming a back contact 116b in a semiconductor device 100a according to various embodiments. Figures 10A to 10E The processing operations shown are Figures 9A to 9C The processing operation for forming the front contact 116a is similar. For example... Figure 10A As shown, the semiconductor layer 204 is patterned and etched to form the opening 207. (See above for reference.) Figures 9A to 9C The process allows for etching to remove the back side portion of the source feature 232S.

[0133] like Figure 10A As shown, after the opening 207 is formed, a portion of the isolation structure 230 remains. As described above, the isolation structure 230 is used to reduce or prevent leakage current. Figure 10B As shown, after forming the back-side source contact opening 207, in some embodiments, a dielectric barrier layer 262 is deposited over the structure 1000a. For example... Figure 10C As shown, the dielectric barrier layer 262 is then etched back to cover only the sidewalls of the back-side source contact opening 207 and expose the source feature 232S. The back-side source contact opening 207 partially covered by the dielectric barrier layer 262 is referred to as the back-side source contact opening 207'. In some embodiments, the dielectric barrier layer 262 comprises silicon nitride or other suitable material. Then, a contact epitaxial layer 118 is deposited over the source feature 232S using a conformal deposition process (e.g., MOCVD), as described above and as follows. Figure 10D As shown. Then, a silicide layer 120 and a back contact 116b are formed above the contact epitaxial layer 118, as described above. Figures 9A to 9C As stated and as Figure 10E As shown. Figures 9A to 10E The contacts (116a, 116b) formed in the source feature 232S are shown. In a further embodiment (not shown), a similar process is performed to form contacts in the drain feature 232D.

[0134] Figures 10F to 10H A vertical cross-sectional view of a structure (1000f, 1000g, 1000h) having an alternative configuration for back contact 116b and related structures (118, 120). For example, as... Figure 10F As shown, the contact epitaxial layer 118 and silicide layer 120 have curved shapes, with a minimum width W_1 (between about 1 nm and about 10 nm) and a bottom width W_B (between about 5 nm and about 15 nm), respectively. The height H of the contact structure below the surface of the gate structure 240 is between about 50 nm and about 100 nm. In a further embodiment, the contact epitaxial layer 118 and silicide layer 120 are used in other shapes, such as... Figure 10GThe triangle shown, such as Figure 10H The rhombus shown (with corresponding height H and widths W_1 and W_2), etc.

[0135] Figures 11A to 11D This is a vertical cross-sectional view of a semiconductor device structure (1100a, 1100b, 1100c, 1100d) with various defects according to various embodiments. Figures 11A to 11C As shown, the source feature 232S and the contact epitaxial layer 118 include a crystalline material with dislocations 402. The dislocations 402 are caused by lattice constant mismatch between different materials, such as the lattice constant mismatch between the material of the source feature 232S and the material of the inner spacer feature 220, and / or between the source feature 232S and the dielectric barrier layer 262.

[0136] The formation of misalignments 402 in source feature 232S has both advantages and disadvantages, affecting the performance and reliability of semiconductor device 100a. One advantage of misalignments 402 (e.g., in strained layers such as silicon-germanium (SiGe) in source feature 232S) is that these misalignments 402 can alleviate strain in the material, which helps prevent excessive stress that could lead to defects or device malfunction. In some cases, controlled misalignment formation can be used to alleviate strain without affecting overall device performance, especially in heterostructures where strain engineering is crucial for enhancing carrier mobility in transistor channels.

[0137] However, in some embodiments, the disadvantages of misalignment 402 may be more pronounced. In source feature 232S, misalignment 402 may create leakage current paths, thereby reducing the electrical performance of the device by increasing off-state current and decreasing the effectiveness of semiconductor device 100a. These defects also interfere with charge carrier mobility, resulting in reduced drive current and slower switching speed. In contact epitaxial layer 118, misalignment 402 at the metal-semiconductor interface may increase contact resistance, thereby hindering current flow between the metal and semiconductor. This can degrade device performance, especially in advanced transistor designs that require low contact resistance to maintain high efficiency and low power consumption. Furthermore, misalignment 402 can act as recombination centers for charge carriers, thereby reducing the efficiency of devices such as photodetectors and LEDs.

[0138] Overall, while misalignment 402 offers some strain mitigation advantages, its presence presents challenges such as increased leakage, reduced carrier mobility, and increased contact resistance, which can negatively impact the performance and lifespan of semiconductor devices. Therefore, minimizing misalignment 402 through careful epitaxial growth processes and strain management is crucial for ensuring optimal device function.

[0139] According to certain embodiments, a high-quality device (i.e., with low-density dislocations 402) is produced using a deposition process, wherein the source feature 232S is formed at a first temperature using the precursor gas composition and pressure described above, and the contact epitaxial layer 118 is formed at a second temperature, which is about 20% to about 30% lower than the first temperature. For example, the use of high-order Si and Ge precursors (i.e., chain-like molecules having multiple Si or Ge atoms bonded to hydrogen atoms) and the above-described temperature range allows for achievable values ​​up to 1.3 × 10⁻⁶. 21 cm -3 The hole activity concentration, for example, in in-situ B-doped Si. 0.5 Ge 0.5 This provides Ti / SiGe:B contacts with low specific resistivity. For example, higher processing temperatures (e.g., 600°C to 700°C) result in relatively higher resistivity (e.g., 0.55 mohm·cm), while lower processing temperatures (e.g., 500°C, 475°C, and 450°C) result in correspondingly lower resistivity (e.g., 0.31 mohm·cm, 0.27 mohm·cm, and 0.21 mohm·cm). Such results can be obtained, for example, using precursor gases including Si₂H₆, Ge₂H₆, or Cl₂.

[0140] According to certain embodiments, the semiconductor device structures (1100a, 1100b, 1100c, 1100d) are formed with 50 or fewer misalignments 402, and the misalignment length 404 of each misalignment 402 (see...) Figure 11A The wavelength is between approximately 1 nm and approximately 40 nm. Furthermore, according to some embodiments, it may be advantageous if the misalignment angle θ is not aligned with the crystal orientation. For example, as... Figure 11B As shown, in some embodiments, the formed dislocations 402 are at an angle θ between approximately 20 degrees and approximately 70 degrees relative to the

[110] crystal plane. These dislocations 402 can be used to reduce strain without significantly increasing resistance or allowing leakage current. Figure 11C As shown, misalignment 402 can be formed at various interfaces between source / drain features (232S, 232D), inner spacer features 220, contact epitaxial layer 118, etc.

[0141] like Figure 11D As shown, another drawback includes dopant deposits 406. The presence of dopant deposits 406 can increase resistivity by making dopant clusters electrically inactive. These dopant deposits 406 also tend to act as nucleation centers for dislocations 402. Therefore, various embodiments include controlling process conditions to reduce or eliminate dopant deposits 406.

[0142] Figure 12A is a vertical cross-sectional view of a semiconductor device structure 1200a having a doped deposit 406 and / or an amorphous region 502 according to various embodiments, and Figure 12 B to Figure 12 E is an amorphous structure 502 according to various embodiments (e.g., Figure 12 B and Figure 12 E), Crystal structure 504 (e.g., Figure 12 B. Figure 12 C and Figure 12 D) and dopant precipitate 406 (e.g., Figure 12 A vertical cross-sectional view of the contact epitaxial layer 118 (D). Similar to the case of dislocation 402, the amorphous structure 502 (e.g., Figure 12 B and Figure 12 The presence of E) offers certain advantages in reducing crystal strain. However, a disadvantage of the amorphous 502 structure is the increased resistivity due to the reduction in active dopant and its lower density. Figure 12 As shown in D, the dopant precipitate 406 serves as the nucleation site for the growth of the amorphous structure 502 and the center for the generation of dislocations 402 (see, for example, [reference]). Figure 11D Various methods are provided to improve device quality, including increasing the concentration of active dopant and reducing the density of dislocations 402, dopant deposits 406, and amorphous structures 502, thereby producing a high-quality contact epitaxial layer 118 with a dominant crystal structure 504, as described below. Figure 13 and Figure 14 As stated above.

[0143] Figure 13 This is a flowchart illustrating the operation of a method 1300 for forming a semiconductor device 100a according to various embodiments. In operation 1302, method 1300 includes the step of forming a gate full-ring field-effect transistor including a plurality of stacked channel layers 208 and source / drain regions (205S, 205D). In operation 1304, method 1300 includes the step of performing a deposition process at a first temperature to form a first epitaxial layer (232S, 232D) over the source / drain regions (205S, 205D), such that the ends of the plurality of stacked channel layers 208 contact the first epitaxial layer (232S, 232D). In operation 1306, method 1300 includes the step of performing a second deposition process at a second temperature to form a second epitaxial layer 118 in contact with the first epitaxial layer (232S, 232D). According to various embodiments, method 1300 is performed such that the second temperature is 20% to 30% lower than the first temperature.

[0144] According to various embodiments, the first epitaxial layer (232S, 232D) includes a first dopant concentration, the second epitaxial layer 118 includes a second dopant concentration greater than the first dopant concentration, and the second epitaxial layer 118 is formed after the first epitaxial layer (232S, 232D). According to various embodiments, when forming the first epitaxial layer (232S, 232D) according to operation 1304, method 130 further includes the step of depositing a first n-type doped silicon layer, and when forming the second epitaxial layer 118 according to operation 1306, method 1300 further includes the step of depositing a second n-type doped silicon layer over the first epitaxial layer (232S, 232D). According to various embodiments, the first epitaxial layer (232S, 232D) includes Si x Ge 1-x Where x is between about 0.4 and about 0.6. According to various embodiments, the first epitaxial layer (232S, 232D) further comprises a first concentration of phosphorus, the first concentration being about 5 × 10⁻⁶. 20 atoms / cm 3 With approximately 5×10 21 atoms / cm 3 Between, and the second epitaxial layer 118 further includes phosphorus of a second concentration, the second concentration being about 1 × 10 21 atoms / cm 3 With approximately 7×10 21 atoms / cm 3 between.

[0145] According to various embodiments, when depositing the first epitaxial layer (232S, 232D) according to operation 1304, method 1300 further includes the step of performing a first metal-organic chemical-vapor deposition (MOCVD) process using a first mixture of SiH4, H2SiCl2, HCl, or GeH4 precursor gases. When depositing the second epitaxial layer 118 according to operation 1306, method 1300 further includes the step of performing a second MOCVD deposition process using a second mixture of SiH4, Si2H6, Si3H8, H2SiCl2, HCl, or Cl2 precursor gases. According to various embodiments, the step of depositing the first epitaxial layer (232S, 232D) further includes the step of performing the first MOCVD deposition process such that a first temperature is between about 500°C and about 850°C, and the step of depositing the second epitaxial layer 118 further includes the step of performing the second MOCVD deposition process such that a second temperature is between about 350°C and about 680°C.

[0146] According to various embodiments, when forming the first epitaxial layer (232S, 232D) according to operation 1304, method 1300 further includes the step of depositing a first p-type doped SiGe alloy layer. When forming the second epitaxial layer 118 according to operation 1306, method 1300 further includes the step of depositing a second p-type doped SiGe alloy layer over the first epitaxial layer (232S, 232D). According to various embodiments, the first epitaxial layer (232S, 232D) comprises Si x Ge 1-x Where x is between approximately 0.4 and approximately 0.6, and the second epitaxial layer 118 comprises Si x Ge 1-x Where x is between about 0.05 and about 0.5. According to various embodiments, the first epitaxial layer (232S, 232D) comprises a first concentration of boron, the first concentration being about 7 × 10⁻⁶. 20 atoms / cm 3 With approximately 1×10 21 atoms / cm 3 Between, and the second epitaxial layer 118 includes boron of a second concentration, the second concentration being approximately 1 × 10⁻⁶. 20 atoms / cm 3 With approximately 7×10 21 atoms / cm 3 between.

[0147] According to various embodiments, when depositing the first epitaxial layer (232S, 232D) according to operation 1304, method 1300 further includes the step of performing a first MOCVD deposition process using a first mixture of SiH4, H2SiCl2, HCl, or GeH4 precursor gases. When depositing the second epitaxial layer 118 according to operation 1306, method 1300 further includes the step of performing a second MOCVD deposition process using a second mixture of SiH4, Si2H6, Si3H8, H2SiCl2, HCl, Cl2, GeH4, or Ge2H6 precursor gases. According to various embodiments, when depositing the first epitaxial layer (232S, 232D) according to operation 1304, method 1300 further includes the step of performing a first MOCVD deposition process such that a first temperature is between about 500°C and about 850°C. When depositing the second epitaxial layer 118 according to operation 1304, method 1300 further includes the step of performing a second MOCVD deposition process such that the second temperature is between about 320°C and about 680°C.

[0148] Figure 14This is a flowchart illustrating the operation of a method 1400 for forming a semiconductor device 100a according to various embodiments. In operation 1402, method 1400 includes the step of forming a plurality of stacked semiconductor nanostructures serving as channel layers 208. In operation 1404, method 1400 includes the step of forming source / drain regions (205S, 205D) adjacent to the ends of channel layers 208. In operation 1406, method 1400 includes the step of forming a gate structure 240 surrounding each channel layer 208. In operation 1408, method 1400 includes the step of performing a first deposition process at a first temperature to form a first epitaxial layer (232S, 232D) over the source / drain regions (205S, 205D) and in contact with each of the plurality of stacked semiconductor nanostructures 208. In operation 1410, method 1400 includes the step of performing a second deposition process at a second temperature to form a front-side contact epitaxial layer 118 over the first epitaxial layer (232S, 232D), such that the second temperature is about 20% to about 30% lower than the first temperature. In operation 1412, method 1400 includes the step of performing a third deposition process at a third temperature to form a back-side contact epitaxial layer 118 over the first epitaxial layer (232S, 232D), such that the third temperature is about 20% to about 30% lower than the first temperature.

[0149] According to various embodiments, the first epitaxial layer (232S, 232D) includes a first dopant concentration, the front contact epitaxial layer 118 and the back contact epitaxial layer 118 each include a second dopant concentration greater than the first dopant concentration, and the front contact epitaxial layer 118 is formed after the first epitaxial layer (232S, 232D), and the back contact epitaxial layer 118 is formed after the front contact epitaxial layer 118. According to various embodiments, the first epitaxial layer (232S, 232D) includes a first n-type doped silicon layer, the first n-type doped silicon layer including a first concentration of phosphorus, the first concentration being approximately 5 × 10⁻⁶. 20 atoms / cm 3 With approximately 5×10 21 atoms / cm 3 Between, and the front contact epitaxial layer 118 and the back contact epitaxial layer 118 each include a second n-type doped silicon layer, the second n-type doped silicon layer including phosphorus of a second concentration of about 1 × 10⁻⁶. 21 atoms / cm 3 With approximately 7×10 21 atoms / cm 3 between.

[0150] According to various embodiments, the first epitaxial layer (232S, 232D) comprises Si x Ge 1-xWhere x is between about 0.4 and about 0.6, and a first concentration of boron, the first concentration being about 7 × 10⁻⁶. 20 atoms / cm 3 With approximately 1×10 21 atoms / cm 3 Between, and the front contact epitaxial layer 118 and the back contact epitaxial layer 118 each include Si x Ge 1-x Where x is between about 0.05 and about 0.5, and a second concentration of boron, the second concentration being about 1 × 10⁻⁶. 20 atoms / cm 3 With approximately 7×10 21 atoms / cm 3 According to various embodiments, when depositing the first epitaxial layer (232S, 232D) according to operation 1408, method 1400 further includes the step of performing a first deposition process such that a first temperature is between about 500°C and about 850°C. According to various embodiments, when depositing the front-side contact epitaxial layer 118 according to operation 1410, and when depositing the back-side contact epitaxial layer 118 according to operation 1412, method 1400 further includes the steps of performing a second deposition process and a third deposition process such that a second temperature and a third temperature are between about 350°C and about 680°C, respectively.

[0151] According to various embodiments, method 1400 further includes the following steps: forming a front contact 116a; forming a back contact 116b; and forming a silicide layer 120 between the front contact epitaxial layer 118 and the front contact 116a or between the back contact epitaxial layer 118 and the back contact 116b, such that the silicide layer 120 has a thickness of less than about 10 nm.

[0152] Referring to all the accompanying drawings and various embodiments according to the present disclosure, a semiconductor device 100a is provided. The semiconductor device 100a includes: a transistor structure including a channel layer 208 and source / drain regions (205S, 205D); a first epitaxial layer (232S, 232D) formed over the source / drain regions (205S, 205D) such that the first epitaxial layer (232S, 232D) contacts the channel layer 208; a second epitaxial layer 118 in contact with the first epitaxial layer (232S, 232D); and conductive contacts (116a, 116b) connected to the second epitaxial layer 118 such that the second epitaxial layer 118 is located between the first epitaxial layer (232S, 232D) and the conductive contacts (116a, 116b).

[0153] According to various embodiments, the first epitaxial layer (232S, 232D) comprises a crystal structure having a first dopant concentration of approximately 5 × 10⁻⁶. 20 atoms / cm3 With approximately 5×10 21 atoms / cm 3 Between, and the second epitaxial layer 118 includes a crystal structure having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration and within about 1 × 10⁻⁶. 20 atoms / cm 3 With approximately 7×10 21 atoms / cm 3 Between these, the second epitaxial layer 118 includes fewer than 50 dislocations. According to various embodiments, the second epitaxial layer 118 is substantially free of dopant precipitates 406. In this regard, "substantially free" means that any precipitates present are smaller than the size resolution of a transmission electron microscopy (TEM) (i.e., about 1 nm to about 2 nm). According to various embodiments, the semiconductor device 100a further includes dislocations, the plurality of dislocations extending within the first epitaxial layer (232S, 232D) and the second epitaxial layer 118 with lengths between about 1 nm and about 40 nm, and the angles formed by the dislocations relative to the

[110] crystal plane are between about 20 degrees and about 70 degrees.

[0154] The disclosed embodiments are advantageous because they provide improved source / drain characteristics (232S, 232D) and improved contact epitaxial layer 118 for semiconductor device structure 100a. In this regard, the source / drain characteristics (232S, 232D) are formed by performing an epitaxial deposition process at a first temperature, and the contact epitaxial layer 118 is formed by performing a second epitaxial deposition process at a second temperature, which is about 20% to about 30% lower than the first temperature. By controlling the process conditions according to the various disclosed embodiments (1300, 1400), high-quality device structures (100a, 1100a, 1100b, 1100c, 1100d) with a small amount of dislocations 402, amorphous material 502, and dopant precipitates 406 can be obtained.

[0155] According to various embodiments, a method of forming a semiconductor device includes the steps of: forming a gate full-ring field-effect transistor including a plurality of stacked channel layers and source / drain regions; performing a deposition process at a first temperature to form a first epitaxial layer over the source / drain regions such that the ends of the plurality of stacked channel layers contact the first epitaxial layer; and performing a second deposition process at a second temperature to form a second epitaxial layer in contact with the first epitaxial layer, such that the second temperature is 20% to 30% lower than the first temperature. According to various embodiments, the method further includes the steps of: forming a contact etch-stop layer over the first epitaxial layer; forming a contact opening in the first epitaxial layer; and forming the second epitaxial layer after forming the contact opening. According to various embodiments, the method further includes the steps of: forming a contact etch-stop layer over the first epitaxial layer; forming a contact opening in the first epitaxial layer; and forming the second epitaxial layer after forming the contact opening. According to various embodiments, the first epitaxial layer includes a first dopant concentration, the second epitaxial layer includes a second dopant concentration greater than the first dopant concentration, and the second epitaxial layer is formed after the first epitaxial layer.

[0156] According to various embodiments, the step of forming the first epitaxial layer further includes the step of depositing a first n-type doped silicon layer, while the step of forming the second epitaxial layer further includes the step of depositing a second n-type doped silicon layer over the first epitaxial layer. According to various embodiments, the method includes the steps of forming an isolation structure over the source / drain region; and forming the first epitaxial layer over the isolation structure. According to various embodiments, the first epitaxial layer further includes phosphorus of a first concentration of 5 × 10⁻⁶. 20 atoms / cm 3 With 5×10 21 atoms / cm 3 Between, and the second epitaxial layer further comprises phosphorus of a second concentration, the second concentration being 1×10 21 atoms / cm 3 With 7×10 21 atoms / cm 3 In various embodiments, the step of depositing the first epitaxial layer further includes the following steps: performing a first metal-organic chemical-vapor deposition (MOCVD) process using a first mixture of two or more of the precursor gases SiH4, H2SiCl2, HCl, and GeH4, while the step of depositing the second epitaxial layer further includes the following steps: performing a second MOCVD deposition process using a second mixture of two or more of the precursor gases SiH4, Si2H6, Si3H8, H2SiCl2, HCl, and Cl2.

[0157] According to various embodiments, the step of depositing the first epitaxial layer further includes the following steps: performing a first MOCVD deposition process at a first temperature between 500°C and 850°C, while the step of depositing the second epitaxial layer further includes the following steps: performing a second MOCVD deposition process at a second temperature between 350°C and 680°C. According to various embodiments, the step of forming the first epitaxial layer further includes the following steps: depositing a first p-type doped SiGe alloy layer, while the step of forming the second epitaxial layer further includes the following steps: depositing a second p-type doped SiGe alloy layer over the first epitaxial layer.

[0158] According to various embodiments, the first epitaxial layer includes Si x Ge 1-x Where x is between 0.4 and 0.6, and the second epitaxial layer includes Si. x Ge 1-x Where x is between 0.05 and 0.5. According to various embodiments, the first epitaxial layer comprises a first concentration of boron, wherein the first concentration is 7 × 10⁻⁶. 20 atoms / cm 3 With 1×10 21 atoms / cm 3 Between, and the second epitaxial layer includes boron of a second concentration, the second concentration being 1×10 20 atoms / cm 3 With 7×10 21 atoms / cm 3 According to various embodiments, the step of depositing the first epitaxial layer further includes the following steps: performing a first MOCVD deposition process using a first mixture of two or more of the precursor gases SiH4, H2SiCl2, HCl, and GeH4, while the step of depositing the second epitaxial layer further includes the following steps: performing a second MOCVD deposition process using a second mixture of two or more of the precursor gases SiH4, Si2H6, Si3H8, H2SiCl2, HCl, Cl2, GeH4, and Ge2H6. According to various embodiments, the step of depositing the first epitaxial layer further includes the following steps: performing the first MOCVD deposition process such that a first temperature is between 500°C and 850°C, and the step of depositing the second epitaxial layer further includes the following steps: performing the second MOCVD deposition process such that a second temperature is between 320°C and 680°C.

[0159] According to various embodiments, a method of forming a semiconductor device includes the following steps: forming a plurality of stacked semiconductor nanostructures serving as channel layers; forming source / drain regions adjacent to the ends of the channel layers; forming a gate structure surrounding each channel region; performing a first deposition process at a first temperature to form a first epitaxial layer over the source / drain regions and in contact with each of the plurality of stacked semiconductor nanostructures; performing a second deposition process at a second temperature to form a front-side contact epitaxial layer over the first epitaxial layer, such that the second temperature is 20% to 30% lower than the first temperature; and performing a third deposition process at a third temperature to form a back-side contact epitaxial layer over the first epitaxial layer, such that the third temperature is 20% to 30% lower than the first temperature.

[0160] According to various embodiments, the first epitaxial layer includes a first dopant concentration, the front contact epitaxial layer and the back contact epitaxial layer each include a second dopant concentration greater than the first dopant concentration, and the front contact epitaxial layer is formed after the first epitaxial layer, and the back contact epitaxial layer is formed after the front contact epitaxial layer. According to various embodiments, the first epitaxial layer includes a first n-type doped silicon layer having a first concentration of phosphorus, wherein the first concentration is 5 × 10⁻⁶. 20 atoms / cm 3 With 5×10 21 atoms / cm 3 Between, and the front contact epitaxial layer and the back contact epitaxial layer each include a second n-type doped silicon layer with a second phosphorus concentration of 1×10⁻⁶. 21 atoms / cm 3 With 7×10 21 atoms / cm 3 between.

[0161] According to various embodiments, the first epitaxial layer includes Si x Ge 1-x Where x is between 0.4 and 0.6, and the first concentration of boron is 7 × 10⁻⁶. 20 atoms / cm 3 With 1×10 21 atoms / cm 3 Between, and the front contact epitaxial layer and the back contact epitaxial layer each include Si x Ge 1-x Where x is between 0.05 and 0.5, and the second concentration of boron is 1 × 10⁻⁶. 20 atoms / cm 3 With 7×10 21 atoms / cm 3According to various embodiments, the step of depositing the first epitaxial layer further includes the following steps: performing a first deposition process such that the first temperature is between 500°C and 850°C, while the steps of depositing the front contact epitaxial layer and the back contact epitaxial layer further include the following steps: performing a second deposition process and a third deposition process such that the second temperature and the third temperature are between 350°C and 680°C, respectively. According to various embodiments, the method further includes the following steps: forming a front contact; forming a back contact; and forming a silicide layer between the front contact epitaxial layer and the front contact or between the back contact epitaxial layer and the back contact, such that the silicide layer has a thickness of less than 10 nm.

[0162] According to various embodiments, a semiconductor device includes: a transistor structure including a channel layer and source / drain regions; a first epitaxial layer formed above the source / drain regions such that the first epitaxial layer contacts the channel layer; a second epitaxial layer in contact with the first epitaxial layer; and a conductive contact connected to the second epitaxial layer such that the second epitaxial layer is located between the first epitaxial layer and the conductive contact. According to various embodiments, the first epitaxial layer includes a first dopant concentration of 5 × 10⁻⁶. 20 atoms / cm 3 With 5×10 21 atoms / cm 3 The crystal structure between, and the second epitaxial layer includes a second dopant concentration greater than the first dopant concentration and within 1×10 20 atoms / cm 3 With 7×10 21 atoms / cm 3 The crystal structure between the two layers allows the second epitaxial layer to include fewer than 50 dislocations. According to various embodiments, the second epitaxial layer is substantially free of dopant deposits. According to various embodiments, the semiconductor device further includes dislocations that extend within the first and second epitaxial layers and have a length between 1 nm and 40 nm, and the dislocations are at an angle between 20 degrees and 70 degrees relative to the

[110] crystal plane.

[0163] The foregoing outlines the features of several embodiments or examples, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments or examples described herein. Those skilled in the art should also recognize that the various equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to the various equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A gate full-ring field-effect transistor is formed, the gate full-ring field-effect transistor comprising multiple stacked channel layers and a source / drain region; A deposition process is performed at a first temperature to form a first epitaxial layer over the source / drain region, such that multiple ends of the plurality of stacked channel layers contact the first epitaxial layer; as well as A second deposition process is performed at a second temperature to form a second epitaxial layer in contact with the first epitaxial layer. The second temperature is 20% to 30% lower than the first temperature.

2. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, Further steps include: A contact etch termination layer is formed above the first epitaxial layer; A contact opening is formed in the first epitaxial layer; and The second epitaxial layer is formed after the contact opening is formed. in: The first epitaxial layer contains a first dopant concentration; The second epitaxial layer contains a second dopant concentration greater than that of the first dopant concentration; and The second epitaxial layer is formed after the first epitaxial layer.

3. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that: The step of depositing the first epitaxial layer further includes the following steps: performing a first metal-organic chemical vapor deposition process using a first mixture of two or more of the precursor gases SiH4, H2SiCl2, HCl, and GeH4; and The step of depositing the second epitaxial layer further includes the following steps: performing a second metal-organic chemical vapor deposition process using a second mixture of two or more of the precursor gases SiH4, Si2H6, Si3H8, H2SiCl2, HCl or Cl2.

4. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that: The step of forming the first epitaxial layer further includes the following steps: depositing a first p-type doped SiGe alloy layer; and The step of forming the second epitaxial layer further includes the following steps: depositing a second p-type doped SiGe alloy layer on top of the first epitaxial layer.

5. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: Multiple stacked semiconductor nanostructures are formed to serve as multiple channel layers; A source / drain region is formed adjacent to the multiple ends of the multiple channel layers; A gate structure is formed around each channel layer; A first deposition process is performed at a first temperature to form a first epitaxial layer over the source / drain regions and in contact with each of the plurality of stacked semiconductor nanostructures; A second deposition process is performed at a second temperature to form a front-side contact epitaxial layer over the first epitaxial layer, such that the second temperature is 20% to 30% lower than the first temperature; and A third deposition process is performed at a third temperature to form a back-side contact epitaxial layer over the first epitaxial layer, such that the third temperature is 20% to 30% lower than the first temperature. in: The first epitaxial layer contains a first dopant concentration; The front contact epitaxial layer and the back contact epitaxial layer each contain a second dopant concentration, the second dopant concentration being greater than the first dopant concentration; and The front contact epitaxial layer is formed after the first epitaxial layer, and the back contact epitaxial layer is formed after the front contact epitaxial layer.

6. The method for manufacturing a semiconductor device as claimed in claim 5, characterized in that: The first epitaxial layer includes a first n-type doped silicon layer, the first n-type doped silicon layer including phosphorus of a first concentration of 5 × 10⁻⁶. 20 atoms / cm 3 With 5×10 21 atoms / cm 3 Between; and The front contact epitaxial layer and the back contact epitaxial layer each include a second n-type doped silicon layer, the second n-type doped silicon layer containing phosphorus of a second concentration of 1×10⁻⁶. 21 atoms / cm 3 With 7×10 21 atoms / cm 3 between.

7. The method for manufacturing a semiconductor device as claimed in claim 5, characterized in that: The first epitaxial layer comprises: Si x Ge 1-x Where x is between 0.4 and 0.6; and a first concentration of boron, wherein the first concentration is 7 × 10⁻⁶. 20 atoms / cm 3 With 1×10 21 atoms / cm 3 Between; and The front contact epitaxial layer and the back contact epitaxial layer each comprise: Si x Ge 1-x , where x is between 0.05 and 0.5; and a second concentration of boron, the second concentration being 1 × 10 20 atoms / cm 3 With 7×10 21 atoms / cm 3 between.

8. The method for manufacturing a semiconductor device as claimed in claim 5, characterized in that, Further steps include: Form a front contact point, Forming a back contact point; and A silicide layer is formed between the front contact epitaxial layer and the front contact, or between the back contact epitaxial layer and the back contact. The silicide layer has a thickness of less than 10 nm.

9. A semiconductor device, characterized in that, Include: A transistor structure comprising a channel layer and a source / drain region; A first epitaxial layer is formed above the source / drain region, such that the first epitaxial layer is in contact with the channel layer; A second epitaxial layer is in contact with the first epitaxial layer; as well as A conductive contact is connected to the second epitaxial layer, such that the second epitaxial layer is located between the first epitaxial layer and the conductive contact. in: The first epitaxial layer comprises a crystal structure, wherein the concentration of a first dopant in the crystal structure is 5 × 10⁻⁶. 20 atoms / cm 3 With 5×10 21 atoms / cm 3 Between; and The second epitaxial layer comprises a crystal structure in which the concentration of a second dopant is greater than the concentration of the first dopant and is within 1 × 10⁻⁶. 20 atoms / cm 3 With 7×10 21 atoms / cm 3 between, The second epitaxial layer contains fewer than 50 dislocations.

10. The semiconductor device as claimed in claim 9, characterized in that, Further includes: Multiple misalignments extend within the first and second epitaxial layers, with a length between 1 nm and 40 nm for each misalignment. The plurality of dislocations are at an angle between 20 and 70 degrees relative to a [110] crystal plane.

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