Groove type power device structure of integrated gate resistor and manufacturing method thereof

Abstract

The invention discloses a trench type power device structure of an integrated gate resistor and a manufacturing method thereof. The trench type power device structure comprises a substrate; the substrate comprises a first part substrate and a second part substrate; a plurality of grooves are formed in the first part of the substrate; a polysilicon gate is formed in each trench; an integrated gate resistance region is designed in each groove, and the polysilicon gate in the groove corresponding to the integrated gate resistance region is partially filled; a gate oxide layer is formed between the polysilicon gate and the first part of the substrate; the dielectric layer is formed in the groove corresponding to the integrated gate resistance region and on the surfaces of the first part substrate and the second part substrate; gate oxide layers are formed among the dielectric layer, the first part of substrate and the second part of substrate; the plurality of first and second contact holes are located in an area where the first part of substrate is located; and the metal electrodes are formed in the first contact hole and the second contact hole and on the dielectric layer. Integration on the surface of the chip in a polycrystalline silicon resistor mode is not needed, groove internal polycrystalline silicon resistor integration compatible with the groove technology is adopted, and the step problem caused by surface polycrystalline silicon resistors is avoided.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a trench-type power device structure with integrated gate resistor and its fabrication method. Background Technology

[0002] Currently, the power density of power MOS (Metal-Oxide-Semiconductor) and IGBT (Insulated Gate Bipolar Transistor) devices is continuously improving, and their application frequencies are also gradually increasing. Consequently, the requirements for these devices at the application end are becoming increasingly stringent. Common VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor) and IGBT products require the integration of gate resistors on the chip to adapt to relevant applications.

[0003] With increasingly higher power densities, power chip fabrication, such as VDMOS / IGBT, is increasingly employing DUV (Deep Ultraviolet) lithography. DUV lithography places stringent requirements on wafer flatness. Traditional trench-type power device structures with integrated gate resistors, such as... Figure 1 and Figure 2 As shown, integrating polysilicon resistors on the chip surface leads to poor compatibility with photolithography during wafer fabrication. Typically, CMP (Chemical Mechanical Polishing) planarization is required after dielectric layer deposition to avoid the steps caused by the polysilicon resistors, thereby meeting the requirements of subsequent DUV photolithography of the contact hole layer. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a trench-type power device structure with integrated gate resistors and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, embodiments of the present invention provide a trench-type power device structure with an integrated gate resistor, the trench-type power device structure comprising: Substrate; the substrate includes a first part of the substrate and a second part of the substrate; Several trenches are formed within the first portion of the substrate; A polysilicon gate is formed in each trench; wherein, an integrated gate resistor region is designed in each trench, and the integrated gate resistor region is partially filled with the polysilicon gate in the trench; a gate oxide layer is formed between the polysilicon gate and the first part of the substrate; A dielectric layer is formed in the trench corresponding to the integrated gate resistor region, and on the surfaces of the first and second partial substrates; wherein a gate oxide layer is formed between the dielectric layer and the first and second partial substrates respectively. A plurality of first contact holes and a plurality of second contact holes are located in the region where the first portion of the substrate is located; wherein, each first contact hole penetrates the dielectric layer and the gate oxide layer to the surface of the first portion of the substrate; each second contact hole penetrates the dielectric layer to the surface of the polysilicon gate; Metal electrodes are formed within the first and second contact holes and on the dielectric layer; wherein, viewed from the top: the metal electrodes in the region where the first portion of the substrate is located include a first metal electrode and a second metal electrode, the first metal electrode and the second metal electrode are not in contact, and the integrated gate resistor region is located in the region between the first metal electrode and the second metal electrode, a first contact hole is distributed under the first metal electrode, and a second contact hole is distributed under the second metal electrode; the metal electrodes in the region where the second portion of the substrate is located are not in contact with the first metal electrode but are in contact with the second metal electrode.

[0005] In one embodiment of the present invention, the linewidth of each trench is 0.2μm to 1μm and the depth is 3μm to 8μm.

[0006] In one embodiment of the present invention, the thickness of the polysilicon gate at the trench corresponding to the integrated gate resistor region is 10% to 90% of the trench depth.

[0007] In one embodiment of the present invention, the length of the integrated gate resistor region is 10μm to 200μm.

[0008] In one embodiment of the present invention, the desired gate resistance is obtained by adjusting the length of the integrated gate resistor region and the thickness of the polysilicon gate in the corresponding trench of the integrated gate resistor region.

[0009] Secondly, embodiments of the present invention provide a method for fabricating a trench-type power device structure with integrated gate resistors, the method comprising: S10. Obtain a substrate; the substrate includes a first part of the substrate and a second part of the substrate; S20. Several trenches are etched on the first part of the substrate and sacrificial oxidation is performed. S30. A gate oxide layer is grown in each trench after the sacrificial oxidation treatment, and on the first and second part of the substrate. S40. Polysilicon is deposited on the gate oxide layer and in each trench to form a polysilicon gate; S50: Etch away the polysilicon gate on the gate oxide layer, retaining the polysilicon gate in each trench; S60. Select the integrated gate resistor region and continue etching away part of the polysilicon gate at the corresponding trench of the integrated gate resistor region. S70. Perform P-type ion implantation on the device surface corresponding to the first part of the substrate, and continue to perform N-type ion implantation on the device surface after completing P-type ion implantation. S80. Deposit a dielectric layer in the trench corresponding to the gate oxide layer and the integrated gate resistor region; S90. The dielectric layer in the region where the first part of the substrate is located is etched to form a plurality of first contact holes and a plurality of second contact holes; wherein, each first contact hole penetrates the dielectric layer and the gate oxide layer to the surface of the first part of the substrate; each second contact hole penetrates the dielectric layer to the surface of the polysilicon gate; S100. Deposit metal electrodes in each first contact hole and second contact hole and on the dielectric layer; wherein, viewed from the top direction: the metal electrodes in the region where the first part of the substrate is located include a first metal electrode and a second metal electrode, the first metal electrode and the second metal electrode are not in contact, and the integrated gate resistor region is located in the region between the first metal electrode and the second metal electrode, a first contact hole is distributed under the first metal electrode, and a second contact hole is distributed under the second metal electrode; the metal electrodes in the region where the second part of the substrate is located are not in contact with the first metal electrode but are in contact with the second metal electrode.

[0010] In one embodiment of the present invention, a plurality of trenches are etched on a first portion of the substrate, including: Several trenches with a linewidth of 0.2 μm to 1 μm and a depth of 3 μm to 8 μm are etched on the first part of the substrate.

[0011] In one embodiment of the present invention, the length of the selected integrated gate resistor region is 10μm to 200μm.

[0012] In one embodiment of the present invention, further etching away a portion of the polysilicon gate at the trench corresponding to the integrated gate resistor region includes: Continue etching away 10% to 90% of the polysilicon gate at the corresponding trench in the integrated gate resistor region.

[0013] In one embodiment of the present invention, the desired gate resistance is obtained by adjusting the length of the integrated gate resistor region and the thickness of the polysilicon gate in the corresponding trench of the integrated gate resistor region.

[0014] The beneficial effects of this invention are: This invention proposes an innovative trench power device structure with integrated gate resistors, improving upon existing trench power device structures. It eliminates the need for surface-mount polysilicon resistors; instead, it integrates polysilicon resistors within the trench, compatible with trench technology. This avoids the step problem associated with surface-mount polysilicon resistors and integrates the gate resistor without any planarization steps. Furthermore, it offers better compatibility with DUV small-linewidth photolithography. Conventional gate resistor integration methods require adjustments to the polysilicon substrate size and photolithography for different applications. This invention allows for flexible gate resistor adjustment simply by adjusting the etching process during standard manufacturing. Different etching depths allow for flexible gate resistor adjustment without requiring modifications to conventional solutions or adjustments to polysilicon doping and thickness. This is simpler and more flexible, achieving flexible gate resistor adjustment by adding a single photolithography and etching step to the polysilicon resistance in the integrated gate resistor region. This invention can adapt to the gate resistor requirements of common trench gate power devices in various application areas, such as Trench MOS and Trench IGBTs.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is a cross-sectional schematic diagram of a traditional trench-type power device structure with integrated gate resistors; Figure 2 yes Figure 1 The diagram shows a top view of the trench power device structure with integrated gate resistors. Figure 3 This is a top view schematic diagram of a trench power device structure with integrated gate resistor provided in an embodiment of the present invention; Figure 4 yes Figure 3 The diagram shows a cross-sectional view of the trench power device structure with integrated gate resistor along section A1-A2. Figure 5 yes Figure 3 The diagram shows a cross-sectional view of the trench power device structure with integrated gate resistor along section B1-B2. Figure 6 yes Figure 3 The diagram shows a cross-sectional view of the trench power device structure with integrated gate resistor along section C1-C2. Figure 7 This is a schematic flowchart illustrating a method for fabricating a trench-type power device structure with integrated gate resistors according to an embodiment of the present invention. Figures 8(a) to 8(k) This is a schematic diagram of the fabrication process of the trench-type power device structure with integrated gate resistor provided in the embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Through research, the inventors discovered that the region located between the polysilicon gate tip and the effective channel region of the active region within the trench, which in conventional designs only serves as a connection and generally does not house N+ injection for the active region, will not significantly affect the effective channel area of ​​the active region even if an integrated gate resistor region is formed here. Based on this discovery, the inventors proposed a trench-type power device structure with integrated gate resistors and its fabrication method. Specifically: Firstly, please see Figure 3 , Figure 4 , Figure 5 , Figure 6 This invention provides a trench-type power device structure with integrated gate resistor, the trench-type power device structure comprising: Substrate; the substrate includes a first part of the substrate and a second part of the substrate; Several trenches are formed within the first portion of the substrate; A polysilicon gate is formed in each trench; wherein, an integrated gate resistor region is designed in each trench, and the integrated gate resistor region is partially filled with the polysilicon gate in the trench; a gate oxide layer is formed between the polysilicon gate and the first part of the substrate; A dielectric layer is formed in the trench corresponding to the integrated gate resistor region, and on the surfaces of the first and second partial substrates; wherein a gate oxide layer is formed between the dielectric layer and the first and second partial substrates respectively. A plurality of first contact holes and a plurality of second contact holes are located in the region where the first portion of the substrate is located; wherein, each first contact hole penetrates the dielectric layer and the gate oxide layer to the surface of the first portion of the substrate; each second contact hole penetrates the dielectric layer to the surface of the polysilicon gate; Metal electrodes are formed within the first and second contact holes and on the dielectric layer; wherein, viewed from the top: the metal electrodes in the region where the first portion of the substrate is located include a first metal electrode and a second metal electrode, the first metal electrode and the second metal electrode are not in contact, and the integrated gate resistor region is located in the region between the first metal electrode and the second metal electrode, a first contact hole is distributed under the first metal electrode, and a second contact hole is distributed under the second metal electrode; the metal electrodes in the region where the second portion of the substrate is located are not in contact with the first metal electrode but are in contact with the second metal electrode.

[0019] The substrate in this embodiment of the invention can be a silicon substrate; the substrate is described here as a first part substrate and a second part substrate in order to better illustrate the structural improvement.

[0020] The linewidth of each trench in the region where the substrate is located in the first part of the embodiment of the present invention d 0.2μm~1μm, depth h The size ranges from 3μm to 8μm.

[0021] In this embodiment of the invention, the sheet resistance of the polysilicon gate is 5Ω / □~20Ω / □.

[0022] Examples of embodiments of the present invention Figure 3 The length of the integrated gate resistor region shown l The diameter of the integrated gate resistor region is 10μm to 200μm, and the thickness of the polysilicon gate in the trench corresponding to the integrated gate resistor region is 10% to 90% of the trench depth. The required gate resistance can be obtained by adjusting the length of the integrated gate resistor region and the thickness of the polysilicon gate in the trench corresponding to the integrated gate resistor region.

[0023] Figure 3 This is a top view of the structure proposed in this invention, and... Figure 2 Compared to the top view of the traditional structure shown, the surface of the second part of the substrate on the right does not need to integrate polysilicon resistors, thus effectively avoiding the step problem caused by polysilicon resistors. The area on the left, which is only used for connection in the conventional solution, is used as the integrated gate resistor area. Theoretically, by adjusting the length of the integrated gate resistor area and the thickness of the polysilicon gate in the corresponding trench, a large range of gate resistances can be achieved. However, due to the difficulty of etching inside the trench corresponding to the integrated gate resistor area, it is recommended that the etching amount be in the range of 10% to 90% of the trench depth. If a larger resistor needs to be integrated, the length of the integrated gate resistor area can be increased to increase the gate resistance.

[0024] To more clearly illustrate the structure proposed in this invention, from... Figure 3 The three sections, A1-A2, B1-B2, and C1-C2, are used to illustrate this. Figure 4 The diagram shows a cross-sectional view along section A1-A2. It can be seen that the device surface in the area where the second part of the substrate is located only has metal electrodes. The area where the first part of the substrate is located includes an integrated gate resistor region. The integrated gate resistor region corresponds to a trench in which polysilicon is partially filled. Specifically, the bottom of the trench is a polysilicon gate and the top is a dielectric layer. Figure 5 The diagram shows a cross-sectional view along section B1-B2. It can be seen that the trenches in the first part of the substrate area, except for the trenches corresponding to the integrated gate resistor area, are fully filled with polysilicon gates, and the first contact holes are distributed under the first metal electrode. Figure 6 The diagram shows a cross-sectional view along section C1-C2. It can be seen that the second metal electrode is located near C1 in the first part of the substrate area. The second contact hole is distributed under the second metal electrode. The integrated gate resistor region is located in the area between the first metal electrode and the second metal electrode. The first metal electrode is located near C2. The polysilicon gate in each trench is U-shaped, and the recessed part forms a dielectric layer.

[0025] In summary, the trench power device structure with integrated gate resistor proposed in this invention innovatively improves upon existing trench power device structures. It eliminates the need for surface-mount polysilicon resistors, employing internal trench polysilicon resistor integration compatible with trench technology. This avoids the step problem caused by surface polysilicon resistors, integrates the gate resistor without requiring any planarization steps, and offers better compatibility with DUV small-linewidth photolithography. Furthermore, conventional gate resistor integration methods require adjustments to the polysilicon substrate size and photolithography for different application requirements. This invention only requires adjusting the etching process during conventional manufacturing to flexibly adjust the gate resistor. Different etching depths allow for flexible adjustment of the gate resistor without requiring modifications to conventional solutions or adjustments to polysilicon doping and thickness. This is simpler and more flexible, achieving flexible gate resistor adjustment by adding one photolithography and etching step to flexibly adjust the polysilicon resistance in the integrated gate resistor region. This invention can adapt to the gate resistor requirements of common trench gate power devices in various application fields, such as Trench MOS and Trench IGBT.

[0026] Secondly, please see Figure 7 This invention provides a method for fabricating a trench-type power device structure with integrated gate resistors, the method comprising: S10. Obtain a substrate; the substrate includes a first part of the substrate and a second part of the substrate.

[0027] In this embodiment of the invention, the substrate can be a silicon substrate, and the obtained silicon substrate is pretreated, such as by cleaning.

[0028] S20, several trenches are etched on the first part of the substrate and then subjected to sacrificial oxidation treatment.

[0029] In this embodiment of the invention, a hard mask, typically silicon dioxide, or a combination of silicon dioxide and silicon nitride, is first deposited on the first and second part of the substrate. The thickness can range from 1000 Å to 10000 Å. Optional processing methods include LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma-Enhanced Chemical Vapor Deposition), or high-temperature oxidation. Next, photolithography and etching processes are used to form several trenches in the area of ​​the first part of the substrate. The cross-sectional structure after trench formation is shown in Figure 8(a), where the linewidth of each trench is... d 0.2μm~1μm, depth hThe thickness is 3μm to 8μm. Then, the hard mask is removed. Further, high-temperature oxidation is performed, with an oxide thickness of 300Å to 2000Å and a temperature range of 950℃ to 1200℃, to achieve sacrificial oxidation. Finally, a wet etching process is used to peel off the sacrificial oxide layer, primarily using hydrofluoric acid (concentration range 5:1 to 200:1) or BOE chemicals (a mixture of ammonium fluoride and hydrofluoric acid, generally with a concentration range of 20:1 to 5:1).

[0030] S30. A gate oxide layer is grown in each trench after the sacrificial oxidation treatment, and on the first and second part of the substrate.

[0031] This invention employs a high-temperature oxidation process to grow a gate oxide layer with a thickness of 300 Å to 2000 Å in each trench after sacrificial oxidation treatment, as well as on the first and second part of the substrate. The cross-sectional structure after the gate oxide layer growth is shown in Figure 8(b). The temperature range in the high-temperature oxidation process is 950℃ to 1200℃.

[0032] S40. Polysilicon is deposited on the gate oxide layer and in each trench to form a polysilicon gate.

[0033] In this embodiment of the invention, polysilicon gates with sheet resistances of 5Ω / □ to 20Ω / □ are deposited on the gate oxide layer and in each trench using the LPCVD process. At this time, the thickness of the polysilicon gate on the gate oxide layer is 4000A to 12000A, and each trench is filled. The cross-sectional structure after polysilicon deposition is shown in Figure 8(c).

[0034] S50: Etch away the polysilicon gate on the gate oxide layer, leaving the polysilicon gate in each trench.

[0035] In this embodiment of the invention, an ICP (Inductively Coupled Plasma Etching Process) etching process is used to etch away the polysilicon gate on the gate oxide layer, while retaining the polysilicon gate in each trench. The cross-sectional structure after the polysilicon gate etching is completed is shown in Figure 8(d).

[0036] S60. Select the integrated gate resistor region on the first part of the substrate and continue to etch away part of the polysilicon gate at the corresponding trench of the integrated gate resistor region.

[0037] In this embodiment of the invention, photolithography is performed on the first portion of the substrate to integrate the gate resistor region, exposing only the area to be etched. Preferably, the etched area ranges from 10 μm to 200 μm. Figure 2 The length of the integrated gate resistor region shown lThe etching depth ranges from 10μm to 200μm, with the specific value chosen based on actual needs. Polysilicon etching is performed, with the etching depth selectable from 10% to 90% of the trench depth. This means etching away 10% to 90% of the top polysilicon to form an integrated gate resistor region within the first part of the substrate. The remaining polysilicon at the bottom is used as the gate resistor. The etching depth is selected based on actual needs, and the required gate resistance is obtained by adjusting the length of the integrated gate resistor region and the thickness of the corresponding polysilicon gate in the trench. Different etching depths achieve different gate resistances without requiring changes to the photomask; this can be achieved simply by adjusting the etching process. The completed cross-sectional structure is shown in Figures 8(e) and 8(f), where Figure 8(e) shows the cross-sectional structure along... Figure 2 The cross-sectional structure of section A1-A2 is shown in Figure 8(f). Figure 2 The cross-sectional structure of section B1-B2 shown indicates that the trench corresponding to the integrated gate resistor region is partially filled with polysilicon, while the other trenches are fully filled with polysilicon, maintaining the same full-fill state as in Figure 8(d) corresponding to S50. This polysilicon etching step requires targeted optimization of the etching process. Adjustments need to be made to the gas atmosphere, etching power, and pressure to avoid residues at corners and sidewalls after etching. Simultaneously, it is necessary to ensure a flat polysilicon surface after etching to guarantee the stability of the gate resistor and the reliability of subsequent dielectric layer deposition.

[0038] S70. Perform P-type ion implantation on the device surface corresponding to the first part of the substrate, and continue to perform N-type ion implantation on the device surface after completing P-type ion implantation.

[0039] This invention employs an ion implantation process. The first part of the substrate, corresponding to the device surface, undergoes P-well implantation, i.e., P-type ion implantation, typically boron implantation, with a dose range of 1E12~1E14 and an energy range of 50keV~200keV. Then, P-well push-in is performed, typically at a temperature range of 950℃~1180℃ for 20min~500min. The implantation and push-in conditions are selected according to product requirements. Further, the device surface after P-type ion implantation is subjected to N-type ion implantation, typically phosphorus or arsenic, or multiple implantations of both impurities, with a dose range of 1E14~5E16 and an energy range of 50keV~200keV. Implantation annealing can be performed using furnace annealing or rapid heat treatment. Typically, furnace annealing temperature ranges from 850℃~1000℃ for 20min~100min; rapid heat treatment annealing temperature ranges from 850℃~1000℃ for 10s~200s.

[0040] S80. Deposit a dielectric layer in the trench corresponding to the gate oxide layer and the integrated gate resistor region.

[0041] In this embodiment of the invention, a dielectric layer is deposited on the gate oxide layer within the trench corresponding to the integrated gate resistor region. The dielectric layer has a thickness of 5000 Å to 20000 Å on the gate oxide layer. The dielectric layer material can be selected from USG (undoped silicon dioxide film), BPSG (silicon dioxide film simultaneously doped with boron and phosphorus), TEOS (silicon dioxide film deposited by chemical vapor deposition using TEOS as a silicon source precursor and reactant gas), silicon nitride, etc., with USG+BPSG being the most common choice. The deposition method typically employs PECVD, SACVD (Sub-Atmospheric Pressure Chemical Vapor Deposition), or HDP CVD (High-Density Plasma Chemical Vapor Deposition). The structure after the dielectric layer deposition is completed is shown in Figures 8(g) and 8(h), where Figure 8(g) shows the structure along the... Figure 2 The cross-sectional structure of section A1-A2 is shown in Figure 8(h). Figure 2 The cross-sectional structure of section B1-B2 shows that, in addition to polysilicon, the trench corresponding to the integrated gate resistor region is also filled with a dielectric layer. The integrated gate resistor region fabricated according to this invention exhibits better device surface flatness, which is beneficial for subsequent DUV small linewidth lithography. Since the trenches of the integrated gate resistor region need to be filled, SACVD or HDP CVD is preferred to ensure that the filling morphology is free of holes and gaps.

[0042] S90. The dielectric layer in the region where the first part of the substrate is located is etched to form a plurality of first contact holes and a plurality of second contact holes; wherein, each first contact hole penetrates the dielectric layer and the gate oxide layer to the surface of the first part of the substrate; each second contact hole penetrates the dielectric layer to the surface of the polysilicon gate.

[0043] In this embodiment of the invention, the dielectric layer in the region where the first part of the substrate is located is etched to form a plurality of first contact holes and a plurality of second contact holes. The linewidths of the first contact holes and the second contact holes are both 0.1 μm to 1 μm. The first contact holes penetrate the dielectric layer and the gate oxide layer, extending to the surface of the first part of the substrate as shown in Figure 8(i); the second contact holes penetrate the dielectric layer, extending to the surface of the polysilicon gate as shown in Figure 8(i). Figure 2 The contact hole is shown in the trench area. Dry etching is selected as the etching method.

[0044] S100. Deposit metal electrodes in each first contact hole and second contact hole and on the dielectric layer; wherein, viewed from the top direction: the metal electrodes in the region where the first part of the substrate is located include a first metal electrode and a second metal electrode, the first metal electrode and the second metal electrode are not in contact, and the integrated gate resistor region is located in the region between the first metal electrode and the second metal electrode, a first contact hole is distributed under the first metal electrode, and a second contact hole is distributed under the second metal electrode; the metal electrodes in the region where the second part of the substrate is located are not in contact with the first metal electrode but are in contact with the second metal electrode.

[0045] In this embodiment of the invention, metal electrodes are deposited in each first and second contact hole and on the dielectric layer. The metal electrode structure can be TI-TIN-W-AL (titanium-titanium nitride-tungsten-aluminum). W is optional, and AL can be ALCU (aluminum-copper alloy), ALSICU (aluminum-silicon-copper alloy), or other materials. Typically, the thickness of TI and TIN is 100 Å to 1000 Å, the thickness of W is 1000 Å to 8000 Å, and the thickness of AL, ALSICU, ALCU, etc., electrode metals is 2 μm to 7 μm. A common process flow is to deposit TI-TIN, followed by rapid thermal processing (RTP), typically at a temperature range of 850℃ to 1000℃ for 10 to 200 seconds. W is then deposited, usually using CVD (Chemical Vapor Deposition). After this, W is etched back, followed by AL, ALSICU, or ALCU deposition. The metal deposition is then complete. Furthermore, photolithography is performed on the metal electrodes, with a linewidth > 1.0 μm. Etching of the metal electrodes can be performed using dry etching, wet etching, or a combination of both. The cross-sectional structures after etching are shown in Figures 8(j) and 8(k), where Figure 8(j) shows the cross-sectional structure along... Figure 2 The cross-sectional structure of section A1-A2 is shown in Figure 8(k). Figure 2 The cross-sectional structure of section B1-B2 is shown; the top view is as follows. Figure 2 As shown, viewed from above: the metal electrodes in the region where the first part of the substrate is located include a first metal electrode and a second metal electrode. The first metal electrode and the second metal electrode are not in contact, and the integrated gate resistor region is located in the region between the first metal electrode and the second metal electrode. A first contact hole is distributed under the first metal electrode, and a second contact hole is distributed under the second metal electrode. The metal electrodes in the region where the second part of the substrate is located are not in contact with the first metal electrode but are in contact with the second metal electrode.

[0046] As for the method embodiment of the second aspect, since it is basically similar to the device embodiment of the first aspect, the description is relatively simple, and relevant details can be found in the description of the device embodiment of the first aspect.

[0047] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0048] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0049] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A trench-type power device structure with integrated gate resistor, characterized in that, The trench-type power device structure includes: Substrate; the substrate includes a first part of the substrate and a second part of the substrate; Several trenches are formed within the first portion of the substrate; A polysilicon gate is formed in each trench; wherein, an integrated gate resistor region is designed in each trench, and the integrated gate resistor region is partially filled with the polysilicon gate in the trench; a gate oxide layer is formed between the polysilicon gate and the first part of the substrate; A dielectric layer is formed in the trench corresponding to the integrated gate resistor region, and on the surfaces of the first and second partial substrates; wherein a gate oxide layer is formed between the dielectric layer and the first and second partial substrates respectively. A plurality of first contact holes and a plurality of second contact holes are located in the region where the first portion of the substrate is located; wherein, each first contact hole penetrates the dielectric layer and the gate oxide layer to the surface of the first portion of the substrate; each second contact hole penetrates the dielectric layer to the surface of the polysilicon gate; Metal electrodes are formed within the first and second contact holes and on the dielectric layer; wherein, viewed from the top: the metal electrodes in the region where the first portion of the substrate is located include a first metal electrode and a second metal electrode, the first metal electrode and the second metal electrode are not in contact, and the integrated gate resistor region is located in the region between the first metal electrode and the second metal electrode, a first contact hole is distributed under the first metal electrode, and a second contact hole is distributed under the second metal electrode; the metal electrodes in the region where the second portion of the substrate is located are not in contact with the first metal electrode but are in contact with the second metal electrode.

2. The trench-type power device structure with integrated gate resistor according to claim 1, characterized in that, Each trench has a linewidth of 0.2μm to 1μm and a depth of 3μm to 8μm.

3. The trench-type power device structure with integrated gate resistor according to claim 1, characterized in that, The thickness of the polysilicon gate at the trench corresponding to the integrated gate resistor region is 10% to 90% of the trench depth.

4. The trench-type power device structure with integrated gate resistor according to claim 1, characterized in that, The length of the integrated gate resistor region is 10μm~200μm.

5. The trench-type power device structure with integrated gate resistor according to claim 1, characterized in that, The required gate resistance is obtained by adjusting the length of the integrated gate resistor region and the thickness of the polysilicon gate in the corresponding trench.

6. A method for fabricating a trench-type power device structure with integrated gate resistor, characterized in that, The manufacturing method includes: S10. Obtain a substrate; the substrate includes a first part of the substrate and a second part of the substrate; S20. Several trenches are etched on the first part of the substrate and sacrificial oxidation is performed. S30. A gate oxide layer is grown in each trench after the sacrificial oxidation treatment, and on the first and second part of the substrate. S40. Polysilicon is deposited on the gate oxide layer and in each trench to form a polysilicon gate; S50: Etch away the polysilicon gate on the gate oxide layer, retaining the polysilicon gate in each trench; S60. Select the integrated gate resistor region on the first part of the substrate and continue to etch away part of the polysilicon gate at the corresponding trench of the integrated gate resistor region. S70. Perform P-type ion implantation on the device surface corresponding to the first part of the substrate, and continue to perform N-type ion implantation on the device surface after completing P-type ion implantation. S80. Deposit a dielectric layer in the trench corresponding to the gate oxide layer and the integrated gate resistor region; S90. The dielectric layer in the region where the first part of the substrate is located is etched to form a plurality of first contact holes and a plurality of second contact holes; wherein, each first contact hole penetrates the dielectric layer and the gate oxide layer to the surface of the first part of the substrate; each second contact hole penetrates the dielectric layer to the surface of the polysilicon gate; S100. Deposit metal electrodes in each first contact hole and second contact hole and on the dielectric layer; wherein, viewed from the top direction: the metal electrodes in the region where the first part of the substrate is located include a first metal electrode and a second metal electrode, the first metal electrode and the second metal electrode are not in contact, and the integrated gate resistor region is located in the region between the first metal electrode and the second metal electrode, a first contact hole is distributed under the first metal electrode, and a second contact hole is distributed under the second metal electrode; the metal electrodes in the region where the second part of the substrate is located are not in contact with the first metal electrode but are in contact with the second metal electrode.

7. The method for fabricating a trench-type power device structure with integrated gate resistor according to claim 6, characterized in that, Several trenches are etched on the first portion of the substrate, including: Several trenches with a linewidth of 0.2 μm to 1 μm and a depth of 3 μm to 8 μm are etched on the first part of the substrate.

8. The method for fabricating a trench-type power device structure with integrated gate resistor according to claim 6, characterized in that, The length of the selected integrated gate resistor region is 10μm to 200μm.

9. The method for fabricating a trench-type power device structure with integrated gate resistor according to claim 6, characterized in that, Continue etching away a portion of the polysilicon gate at the trench corresponding to the integrated gate resistor region, including: Continue etching away 10% to 90% of the polysilicon gate at the corresponding trench in the integrated gate resistor region.

10. The method for fabricating a trench-type power device structure with integrated gate resistor according to claim 6, characterized in that, The required gate resistance is obtained by adjusting the length of the integrated gate resistor region and the thickness of the polysilicon gate in the corresponding trench.

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