Device structure and manufacturing method thereof
By introducing a junction electrode into the device structure to improve the gate's control over the channel, the problem of reduced gate control capability of traditional MOSFETs under short-channel effect is solved, achieving stronger gate control capability and lower leakage current, making it suitable for smart wearables, storage and digital circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG GREATER BAY AREA INST OF INTEGRATED CIRCUIT & SYST
- Filing Date
- 2024-10-24
- Publication Date
- 2026-04-24
AI Technical Summary
At nodes below 28nm, traditional planar silicon metal-oxide-semiconductor field-effect transistors suffer from reduced gate control over channel current due to the short-channel effect, requiring stronger gate control capabilities to optimize device performance.
A device structure is adopted, including a substrate, a buried oxide layer, a channel layer, a junction electrode, and a gate. The junction electrode has the same doping type as the channel layer but a higher concentration. By forming junction electrodes on both sides of the channel layer, the gate's control over the channel is improved, and leakage current is reduced.
It effectively suppresses the short-channel effect, improves the gate's control over the channel, reduces leakage current, enhances the device's radiation resistance and applicability to high-frequency and high-power applications, and meets the requirements for device miniaturization.
Smart Images
Figure CN121924801A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and in particular to a device structure and its manufacturing method. Background Technology
[0002] Below 28nm, the traditional planar metal-oxide-semiconductor (MOSFET) structure suffers from unacceptable gate current control due to the short-channel effect, necessitating processes with stronger gate control capabilities to optimize device performance. Advanced node semiconductor devices with enhanced gate control capabilities primarily include FinFETs and fully depleted silicon-on-insulator (FDSOI) transistors.
[0003] The short-channel effect refers to the scattering of electrons within the channel when the channel length is shortened to a value equal to or less than the mean free path of electrons. In this case, the approximation of a gradually varying channel in long-channel devices no longer holds. This two-dimensional potential distribution causes the threshold voltage to decrease as the channel length decreases. The presence of a two-dimensional potential distribution and a high electric field in the channel, distinct from the characteristics of long-channel MOS field-effect transistors, is collectively referred to as the short-channel effect. One such effect is the drain-induced barrier lowering effect (DIBL): as the channel length L decreases and the drain-source voltage Vds increases, the number of electrons injected into the channel from the source region increases, leading to an increase in drain-source current. The short-channel effect is caused by the junction electric field penetrating into the channel region, lowering the potential barrier and thus reducing the threshold voltage.
[0004] Suppressing the short-channel effect is a necessary approach to achieve large-scale device production. Summary of the Invention
[0005] In view of this, the purpose of this application is to provide a device structure and a method for manufacturing the same, which can effectively suppress short-channel effects for various device types.
[0006] This application provides a device structure, including:
[0007] Substrate, and buried oxide layer on the substrate;
[0008] The channel layer on the buried oxide layer has source and drain electrodes located on both sides of the channel layer in a first direction, and junction electrodes located on both sides of the channel layer in a second direction. The first direction is perpendicular to the second direction and lies in a plane parallel to the surface of the substrate. The doping type of the junction electrodes is the same as that of the channel layer, and the doping concentration of the junction electrodes is greater than that of the channel layer. The doping concentration of the junction electrodes and the size of the channel layer in the second direction are determined according to the device type of the device structure. The device type of the device structure is a first type, a second type, or a third type, and the required output current increases sequentially for the first type, the second type, and the third type.
[0009] The gate dielectric layer and gate on the channel layer.
[0010] Optionally, the doping concentration of the junction electrode is in the range of 10. 21 / cm 3 -10 22 / cm 3 The dimension of the channel layer in the second direction ranges from 30 to 200 nm.
[0011] Optionally, the doping concentration of the junction electrode is in the range of 10. 21 / cm 3 -10 22 / cm 3 ;
[0012] If the device type is the first type, the dimension of the channel layer in the second direction is 30-80nm; if the device type is the second type, the dimension of the channel layer in the second direction is 80-150nm; if the device type is the third type, the dimension of the channel layer in the second direction is 150-200nm.
[0013] Optionally, the doping concentration of the junction electrode is in the range of 10. 20 / cm 3 -10 21 / cm 3 The dimension of the channel layer in the second direction ranges from 30 to 150 nm.
[0014] Optionally, the doping concentration of the junction electrode is in the range of 10. 20 / cm 3 -10 21 / cm 3 ;
[0015] If the device type is the first type, the dimension of the channel layer in the second direction is 30-50 nm; if the device type is the second type, the dimension of the channel layer in the second direction is 50-100 nm; if the device type is the third type, the dimension of the channel layer in the second direction is 100-150 nm.
[0016] Optionally, the dimension of the channel layer in the first direction ranges from 10 to 100 nm.
[0017] Optionally, the materials of the channel layer, the source / drain, and the junction electrode all include silicon.
[0018] Optionally, the thickness of the buried oxide layer is 15-25 nm, and the thickness of the channel layer is 5-7 nm.
[0019] This application provides a method for manufacturing a device structure, including:
[0020] A substrate is provided, wherein the substrate has a buried oxide layer;
[0021] A channel layer is formed on the buried oxide layer, along with source / drain electrodes located on both sides of the channel layer in a first direction, and junction electrodes located on both sides of the channel layer in a second direction. The first direction is perpendicular to the first direction and lies in a plane parallel to the surface of the substrate. The doping type of the junction electrodes is the same as that of the channel layer, and the doping concentration of the junction electrodes is greater than that of the channel layer. The dimension of the channel layer in the second direction is determined according to the device type of the device structure and the doping concentration of the junction electrodes. The device type of the device structure is a first type, a second type, or a third type, with the required output current increasing sequentially for the first type, the second type, and the third type.
[0022] A gate dielectric layer and a gate electrode are formed on the channel layer.
[0023] Optionally, the substrate further comprises a semiconductor layer on a buried oxide layer, wherein a channel layer is formed on the buried oxide layer, and source / drain electrodes are located on both sides of the channel layer in a first direction, and junction electrodes are located on both sides of the channel layer in a second direction, including:
[0024] The semiconductor layer is patterned to obtain a functional layer, the functional layer including a channel layer, source and drain regions located on both sides of the channel layer in a first direction, and electrode regions located on both sides of the channel layer in a second direction.
[0025] The source / drain region is first doped to obtain the source / drain, and the electrode region is second doped to obtain the junction electrode.
[0026] Optionally, the doping concentration of the junction electrode is in the range of 10. 21 / cm 3 -10 22 / cm 3 The dimension of the channel layer in the second direction ranges from 30 to 200 nm.
[0027] Optionally, the doping concentration of the junction electrode is in the range of 10. 21 / cm 3 -10 22 / cm 3 ;
[0028] If the device type is the first type, the dimension of the channel layer in the second direction is 30-80nm; if the device type is the second type, the dimension of the channel layer in the second direction is 80-150nm; if the device type is the third type, the dimension of the channel layer in the second direction is 150-200nm.
[0029] Optionally, the doping concentration of the junction electrode is in the range of 10. 20 / cm 3 -10 21 / cm 3 The dimension of the channel layer in the second direction ranges from 30 to 150 nm.
[0030] Optionally, the doping concentration of the junction electrode is in the range of 10. 20 / cm 3 -10 21 / cm 3 ;
[0031] If the device type is the first type, the dimension of the channel layer in the second direction is 30-50 nm; if the device type is the second type, the dimension of the channel layer in the second direction is 50-100 nm; if the device type is the third type, the dimension of the channel layer in the second direction is 100-150 nm.
[0032] Optionally, the dimension of the channel layer in the first direction ranges from 10 to 100 nm.
[0033] Optionally, the materials of the channel layer, the source / drain, and the junction electrode all include silicon.
[0034] Optionally, the thickness of the buried oxide layer is 15-25 nm, and the thickness of the channel layer is 5-7 nm.
[0035] This application provides a device structure and its manufacturing method. The device structure may include a substrate, a buried oxide layer on the substrate, a channel layer on the buried oxide layer, a gate dielectric layer on the channel, and a gate electrode. It also includes source and drain electrodes located on both sides of the channel layer in a first direction, and junction electrodes located on both sides of the channel layer in a second direction. The first and second directions are perpendicular and lie in a plane parallel to the surface of the substrate. The doping type of the junction electrodes is the same as that of the channel layer, and the doping concentration of the junction electrodes is greater than that of the channel layer. The doping concentration of the junction electrodes and the dimension of the channel layer in the second direction are determined according to the device type of the device structure. The device type of the device structure is a first type, a second type, or a third type. The required output current increases sequentially for the first, second, and third types. Since different device types have different current requirements, different channel widths can be set. Different junction electrode doping concentrations have different suppression effects on short-channel effects, and the same junction electrode doping concentration also has different suppression effects on short-channel effects at different channel widths. Thus, by determining the appropriate doping concentration and appropriate channel width according to the device type of the device structure, appropriate current output and suppression of short-channel effects can be guaranteed. While meeting the current output requirements, the gate's control capability over the channel is improved, leakage current is reduced, and the ever-increasing demand for device miniaturization is met. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 A schematic diagram of a device structure provided in an embodiment of this application is shown;
[0038] Figure 2 This is a flowchart illustrating a method for manufacturing a device structure according to an embodiment of this application. Detailed Implementation
[0039] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0040] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0041] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0042] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.
[0043] See Figure 1 This figure is a schematic diagram of a device structure provided in an embodiment of this application. The device structure includes a substrate, a buried oxide (BOX) layer on the substrate, a channel layer on the buried oxide layer, a gate dielectric layer on the channel layer, and a gate (G). The device structure also includes source and drain electrodes located on both sides of the channel layer in a first direction, where source (S) and drain (D) refer to the source and drain electrodes, respectively.
[0044] In this embodiment, the substrate provides support for the films on it and can be a semiconductor substrate, such as a silicon substrate or a germanium substrate. The buried oxide layer isolates the substrate and the films thereon, thereby reducing leakage current from the substrate side of the device. Its material can be an oxide material, such as silicon oxide. The channel layer is made of a semiconductor material, such as silicon or germanium. When the channel layer is made of silicon, the substrate, buried oxide layer, and channel layer constitute a silicon-on-insulator (SOI) structure. The channel layer can also be called the top silicon layer. In advanced node devices, the thickness of the buried oxide layer ranges from 15-25 nm, and the thickness of the channel layer ranges from 5-7 nm.
[0045] The device structure also includes junction gates located on both sides of the channel layer in a second direction, the first direction being perpendicular to the first direction and located in a plane parallel to the surface of the substrate; the doping type of the junction gates is the same as that of the channel layer, and the doping concentration of the junction gates is greater than that of the channel layer. The device structure may also include a back gate (BG) connected to the substrate, and shallow trench isolation may be provided between the back gate and the junction gates. The back gate can be obtained by doping the substrate.
[0046] In other words, the device structure can be a G4-FET (Four Gate Field Effect Transistor). A G4-FET is a new type of transistor based on FDSOI. On the basis of FDSOI, two highly doped regions with opposite doping polarities to the source and drain are formed on the two sides of the channel as junction electrodes. Due to its high doping concentration and the effect of forming a PN junction-like structure with the channel, the junction electrodes can be connected to external electrodes. By applying a PN junction reverse bias voltage to the junction electrodes, the part of the channel near the PN junction is depleted, so that the current can only flow in the middle of the channel, reducing the scattering generated at the channel interface, thereby reducing the channel noise. Furthermore, since the current flows in the middle of the channel, its radiation resistance is also improved.
[0047] The working principle of G4-FET is as follows: under the control of the front gate, back gate, and junction electrode voltages, electrons or holes at the four interfaces of the channel are depleted, while electrons or holes accumulate in the middle region of the channel, forming a volume mode. This allows the current to flow only in the middle of the channel, thereby reducing the generated noise and improving the device's radiation resistance.
[0048] Due to the relative independence of the two junction electrodes, the front gate, and the rear gate, in devices with this relatively independent design, the two junction electrodes can influence the electric field distribution of the channel laterally, independently of the front and rear gates. This effectively reduces leakage current and improves the device's switching ratio and operating speed. In summary, precise gate control of the channel not only improves the overall performance of the device but also enhances its applicability in high-frequency, high-power applications.
[0049] Due to the reverse bias provided by the junction electrode, the G4-FET minimizes carrier contact with the interface during channel transport, thus reducing the impact of interface scattering. Therefore, G4-FET devices are more resistant to noise. By adjusting the electric field distribution between the junction electrode and the channel, more precise current transport path regulation can be achieved, further reducing the impact of noise on the device. In contrast, FDSOI devices exhibit significantly weaker noise performance due to carrier scattering at the upper and lower interfaces. Furthermore, the biasing effects of the junction electrode, front gate, and rear gate ensure current transport in the center of the channel, thereby improving the device's radiation resistance.
[0050] The direct cause of the DIBL effect is an excessively short channel. The drain voltage lowers the barrier of the entire channel, leading to a significant increase in leakage current and instability in the threshold voltage. In long-channel devices, the drain voltage only lowers the barrier of the section closest to the drain in the channel, so it does not cause a significant increase in leakage current.
[0051] The junction electrode has the same doping polarity as the channel, but a higher concentration, forming a P+P or N+N junction. Due to carrier diffusion, electrons or holes in the junction electrode can diffuse into the channel, increasing the carrier concentration in the channel, raising the channel barrier, reducing leakage current, and stabilizing the threshold voltage, thereby reducing the short-channel effect. Carrier diffusion refers to the movement of carriers (electrons or holes) from high concentration areas to low concentration areas under non-uniform concentration conditions. This movement is a natural result of the random thermal motion of carriers and is usually called diffusion. Especially in PN junctions, carriers move down the concentration gradient from high concentration areas to low concentration areas, forming a diffusion current. After reaching a stable state again, a depletion region is formed, in which the number of majority carriers decreases while the number of minority carriers increases. In P... + P junction or N + In an N-junction, the carrier concentration in the original low carrier concentration region can be increased.
[0052] In this embodiment, the materials of the channel layer, source / drain, and junction electrode can all include silicon; that is, the source / drain can be obtained by doping silicon, and the junction electrode can also be obtained by doping silicon. The dimension of the channel layer in the first direction is the channel length, which can range from 10 to 100 nm. The materials of the junction electrode and source / drain can be monocrystalline silicon or polycrystalline silicon. Doping materials include N-type doping materials such as phosphorus (P), arsenic (As), and antimony (Sb); and P-type doping materials such as gallium (Ga), aluminum (Al), boron (B), and indium (In).
[0053] The short-channel effect optimization capability of this G4-FET device varies depending on the junction electrode doping concentration and channel width. Higher doping concentration and narrower channel width result in stronger optimization capability for short-channel effects under the same conditions, leading to lower leakage current and a higher on / off ratio. Increasing the junction electrode doping concentration increases the polarity of the region, increases the width of the depletion layer within the channel, and improves current control capability. A wider channel lowers the potential barrier, resulting in higher leakage current; however, the increased channel width also increases the on-state current, making it suitable for devices requiring higher power.
[0054] However, an excessively narrow channel can lead to a significant drop in current during bulk transport mode due to the narrow cross-section of the transport channel. Narrow-channel devices exhibit a higher potential barrier and a reduced short-channel effect, making them suitable for devices requiring high channel control. Depending on the design requirements, devices with different junction electrode doping concentrations and channel widths can be selected.
[0055] In this embodiment, the doping concentration of the junction electrode and the dimension of the channel layer in the second direction are determined according to the device type of the device structure. The device type is a first type, a second type, or a third type, with the required output current increasing sequentially for the first, second, and third types. The first type device can be used in the field of smart wearables, requiring a smaller output current. The second type device can be used in the field of storage, such as in static random-access memory (SRAM), requiring a moderate output current. The third type device can be used in the field of digital circuits, such as in switching devices, requiring a larger output current. Specifically, the doping concentration of the junction electrode can be determined according to the device type of the device structure, and then the dimension of the channel layer in the second direction can be determined according to the doping concentration of the junction electrode and the device type of the device structure.
[0056] Because different device types have different current requirements, different channel widths can be set. Different junction electrode doping concentrations have varying effects on suppressing short-channel effects, and even with the same junction electrode doping concentration, the suppression effect varies with different channel widths. Therefore, determining the appropriate doping concentration and channel width based on the device type ensures suitable current output and suppression of short-channel effects. Specifically, for device structures with high output current requirements (e.g., those belonging to type 3), a larger channel width can be set to guarantee a larger output current, while a larger junction electrode doping concentration improves the suppression of short-channel effects. For device structures with low output current requirements (e.g., those belonging to type 1), a smaller channel width can be set to ensure better suppression of short-channel effects, reduce leakage current and noise. This satisfies current output requirements while improving gate control over the channel, reducing leakage current, and meeting the growing demand for device miniaturization.
[0057] Based on the device type and doping concentration, the channel length is determined, resulting in an optimized device structure. This optimized structure improves the channel barrier, reduces leakage current, and stabilizes the threshold voltage, thereby mitigating short-channel effects. This achieves stronger optimization of short-channel effect suppression at the same node, resulting in a higher resistance to short-channel effects. This enhances the G4-FET's ability to suppress short-channel effects without increasing manufacturing difficulty or cost, potentially enabling large-scale, high-quality production.
[0058] When the junction electrode doping concentration is 10 20 -10 22 / cm 3 The channel doping concentration is at 10 14 -10 15 / cm 3 Without considering other factors, the influence of the junction electrode on the channel should be within a few micrometers. However, due to the effects of the ultra-thin top silicon layer and the gate potential, the influence of the junction electrode on the channel carrier concentration is greatly reduced. When the channel width is above 200 nm, the optimization effect of G4-FET on short-channel effects is almost negligible. When the channel width is below 200 nm but above 30 nm, the junction electrode can significantly increase the channel potential, reduce the DIBL effect, and improve the resistance to short-channel effects.
[0059] Specifically, the doping concentration range of the junction electrode is 10. 21 / cm 3 -10 22 / cm 3The channel layer has a size ranging from 30 to 200 nm in the second direction. Specifically, the junction electrode has a doping concentration ranging from 10... 21 / cm 3 -10 22 / cm 3 In the case of a device of type 1, the dimension of the channel layer in the second direction is 30-80 nm; in the case of a device of type 2, the dimension of the channel layer in the second direction is 80-150 nm; and in the case of a device of type 3, the dimension of the channel layer in the second direction is 150-200 nm.
[0060] Specifically, the doping concentration range of the junction electrode is 10. 20 / cm 3 -10 21 / cm 3 The channel layer has a dimension ranging from 30 to 150 nm in the second direction. Specifically, the junction electrode has a doping concentration ranging from 10... 20 / cm 3 -10 21 / cm 3 In the case of a device of type 1, the dimension of the channel layer in the second direction is 30-50 nm; in the case of a device of type 2, the dimension of the channel layer in the second direction is 50-100 nm; and in the case of a device of type 3, the dimension of the channel layer in the second direction is 100-150 nm.
[0061] Refer to Table 1 for an example of the correspondence between junction electrode doping concentration, channel width, and device type.
[0062] Table 1. Examples of the correspondence between junction electrode doping concentration, channel width, and device type.
[0063]
[0064] This application provides a device structure including a substrate, a buried oxide layer on the substrate, a channel layer on the buried oxide layer, a gate dielectric layer on the channel, and a gate electrode. It also includes source and drain electrodes located on both sides of the channel layer in a first direction, and junction electrodes located on both sides of the channel layer in a second direction. The first and second directions are perpendicular and lie in a plane parallel to the surface of the substrate. The doping type of the junction electrodes is the same as that of the channel layer, and the doping concentration of the junction electrodes is greater than that of the channel layer. The doping concentration of the junction electrodes and the dimension of the channel layer in the second direction are determined according to the device type of the device structure. The device type of the device structure is a first type, a second type, or a third type. The required output current increases sequentially for the second and third types. Since different device types have different current requirements, different channel widths can be set. Different junction electrode doping concentrations have different suppression effects on short-channel effects. The same junction electrode doping concentration also has different suppression effects on short-channel effects at different channel widths. Thus, by determining the appropriate doping concentration and appropriate channel width according to the device type of the device structure, appropriate current output and suppression of short-channel effects can be guaranteed. While meeting the current output requirements, the gate's control capability over the channel is improved, leakage current is reduced, and the ever-increasing demand for device miniaturization is met.
[0065] Based on the device structure provided in the above embodiments, this application also provides a method for manufacturing the device structure, referencing... Figure 2 The diagram shown is a flowchart of a method for manufacturing a device structure according to an embodiment of this application. The method may include:
[0066] S101, providing a substrate having a buried oxide layer.
[0067] In this embodiment, the substrate can provide support for the film layer thereon, and it can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, etc. The buried oxide layer is used to isolate the substrate and the film layer thereon, thereby reducing the leakage current of the device from the substrate side, and its material can be an oxide material, such as silicon oxide.
[0068] S102, a channel layer is formed on the buried oxide layer, and source / drain electrodes are located on both sides of the channel layer in a first direction, and junction electrodes are located on both sides of the channel layer in a second direction.
[0069] The channel layer is made of semiconductor materials, such as silicon or germanium. When the channel layer is made of silicon, the substrate, buried oxide layer, and channel layer constitute a silicon-on-insulator (SOI) structure. The channel layer can also be called the top silicon layer. In advanced node devices, the thickness of the buried oxide layer ranges from 15 to 25 nm, and the thickness of the channel layer ranges from 5 to 7 nm.
[0070] The first direction is perpendicular to the first direction and lies in a plane parallel to the surface of the substrate; the doping type of the junction electrode is the same as the doping type of the channel layer, and the doping concentration of the junction electrode is greater than the doping concentration of the channel layer; the size of the channel layer in the second direction is determined according to the device type of the device structure and the doping concentration of the junction electrode; the device type of the device structure is a first type, a second type, or a third type, and the required output current corresponding to the first type, the second type, and the third type increases sequentially.
[0071] In this embodiment, the materials of the channel layer, source / drain, and junction electrode can all include silicon; that is, the source / drain can be obtained by doping silicon, and the junction electrode can also be obtained by doping silicon. The dimension of the channel layer in the first direction is the channel length, which can range from 10 to 100 nm. The materials of the junction electrode and source / drain can be monocrystalline silicon or polycrystalline silicon. Doping materials include N-type doping materials such as phosphorus (P), arsenic (As), and antimony (Sb); and P-type doping materials such as gallium (Ga), aluminum (Al), boron (B), and indium (In).
[0072] The substrate further comprises a semiconductor layer on a buried oxide layer, a channel layer formed on the buried oxide layer, source / drain regions located on both sides of the channel layer in a first direction, and junction electrodes located on both sides of the channel layer in a second direction. Specifically, the semiconductor layer is patterned to obtain a functional layer, the functional layer including the channel layer, source / drain regions located on both sides of the channel layer in the first direction, and electrode regions located on both sides of the channel layer in the second direction; the source / drain regions are first doped to obtain source / drain, and the electrode regions are second doped to obtain junction electrodes. During the first and second doping processes, the channel layer can be masked by a hard mask. The first and second doping can be achieved by ion implantation and activation. The hard mask can be patterned by depositing a hard mask layer and using photoresist as a mask to etch the hard mask layer to cover the channel layer. The material of the hard mask layer can include silicon oxide and silicon nitride. The etching of the hard mask layer can be achieved by plasma sputtering, which is performed using a plasma gas containing an inert gas.
[0073] S103, forming the gate dielectric layer and gate on the channel layer.
[0074] The resulting device structure can be referred to the aforementioned device structure embodiments, and will not be repeated here.
[0075] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.
Claims
1. A device structure, characterized in that, include: Substrate, and buried oxide layer on the substrate; The channel layer on the buried oxide layer has source and drain electrodes located on both sides of the channel layer in a first direction, and junction electrodes located on both sides of the channel layer in a second direction. The first direction is perpendicular to the second direction and lies in a plane parallel to the surface of the substrate. The doping type of the junction electrodes is the same as that of the channel layer, and the doping concentration of the junction electrodes is greater than that of the channel layer. The doping concentration of the junction electrodes and the size of the channel layer in the second direction are determined according to the device type of the device structure. The device type of the device structure is a first type, a second type, or a third type, and the required output current increases sequentially for the first type, the second type, and the third type. The gate dielectric layer and gate on the channel layer.
2. The device structure according to claim 1, characterized in that, The doping concentration range of the junction electrode is 10. 21 / cm 3 -10 22 / cm 3 The dimension of the channel layer in the second direction ranges from 30 to 200 nm.
3. The device structure according to claim 2, characterized in that, The doping concentration range of the junction electrode is 10. 21 / cm 3 -10 22 / cm 3 ; If the device type is the first type, the dimension of the channel layer in the second direction is 30-80nm; if the device type is the second type, the dimension of the channel layer in the second direction is 80-150nm; if the device type is the third type, the dimension of the channel layer in the second direction is 150-200nm.
4. The device structure according to claim 1, characterized in that, The doping concentration range of the junction electrode is 10. 20 / cm 3 -10 21 / cm 3 The dimension of the channel layer in the second direction ranges from 30 to 150 nm.
5. The device structure according to claim 4, characterized in that, The doping concentration range of the junction electrode is 10. 20 / cm 3 -10 21 / cm 3 ; If the device type is the first type, the dimension of the channel layer in the second direction is 30-50 nm; if the device type is the second type, the dimension of the channel layer in the second direction is 50-100 nm; if the device type is the third type, the dimension of the channel layer in the second direction is 100-150 nm.
6. The device structure according to any one of claims 1-4, characterized in that, The dimension of the channel layer in the first direction ranges from 10 to 100 nm.
7. The device structure according to any one of claims 1-4, characterized in that, The materials of the channel layer, the source / drain, and the junction electrode all include silicon.
8. The device structure according to any one of claims 1-4, characterized in that, The thickness of the buried oxide layer is 15-25 nm, and the thickness of the channel layer is 5-7 nm.
9. A method for manufacturing a device structure, characterized in that, include: A substrate is provided, wherein the substrate has a buried oxide layer; A channel layer is formed on the buried oxide layer, along with source / drain electrodes located on both sides of the channel layer in a first direction, and junction electrodes located on both sides of the channel layer in a second direction. The first direction is perpendicular to the first direction and lies in a plane parallel to the surface of the substrate. The doping type of the junction electrodes is the same as that of the channel layer, and the doping concentration of the junction electrodes is greater than that of the channel layer. The dimension of the channel layer in the second direction is determined according to the device type of the device structure and the doping concentration of the junction electrodes. The device type of the device structure is a first type, a second type, or a third type, with the required output current increasing sequentially for the first type, the second type, and the third type. A gate dielectric layer and a gate electrode are formed on the channel layer.
10. The method according to claim 9, characterized in that, The substrate further comprises a semiconductor layer on a buried oxide layer, a channel layer formed on the buried oxide layer, source / drain electrodes located on both sides of the channel layer in a first direction, and junction electrodes located on both sides of the channel layer in a second direction, including: The semiconductor layer is patterned to obtain a functional layer, the functional layer including a channel layer, source and drain regions located on both sides of the channel layer in a first direction, and electrode regions located on both sides of the channel layer in a second direction. The source / drain region is first doped to obtain the source / drain, and the electrode region is second doped to obtain the junction electrode.