High-voltage GPP chip with composite trench and preparation method thereof

Abstract

This invention relates to the field of chip technology, specifically to a high-voltage GPP chip with composite trenches and its fabrication method, comprising: N layers arranged sequentially from bottom to top. + Substrate, N-layer, P-layer + Layer, the N + The substrate layer and the N layer form an N-N + Substrate, the P + Layer P and N layers constitute P + -N junction; trenches in the chip edge region, with the inner walls of the trenches covered by a composite passivation layer, the composite passivation layer comprising an inner boron-doped silicon glass layer and an outer phosphorus-doped silicon glass layer; an isolation ring on the inner side of the trench; covering P + Layer surface and N + The metal layer on the lower surface of the substrate serves as the electrode lead-out layer of the chip. The optimized fabrication process of this invention is highly compatible with each structure, achieving a comprehensive improvement in the overall performance of the chip. The matching of each fabrication step with the structural design allows the functions of each component of the chip to be fully utilized, synergistically achieving a comprehensive effect of high breakdown voltage, low leakage current, low forward voltage drop, and excellent high-temperature stability.

Description

Technical Field

[0001] This invention relates to the field of chip technology, specifically to a high-voltage GPP chip with composite trenches and its fabrication method. Background Technology

[0002] In the rapid development of power electronics, new energy and other fields, high-voltage GPP chips, as core power devices, directly affect the reliability, efficiency and service life of the entire system. As application scenarios increasingly demand higher voltage withstand levels, insulation stability and high-temperature operating capabilities from chips, traditional high-voltage GPP chips are gradually revealing many problems that urgently need to be solved.

[0003] Traditional high-voltage GPP chips often employ a planar structure design, with the inner walls of the trenches typically insulated using a single layer of passivation material. Under high-voltage electric fields, this passivation layer is prone to charge accumulation, leading to uneven electric field distribution. This not only limits the improvement of the chip's reverse breakdown voltage but also increases leakage current, affecting the chip's operational stability in high-voltage scenarios. Furthermore, some chips lack effective isolation structures, making the chip edges weak points where the electric field is concentrated, further reducing the breakdown voltage. Moreover, in long-term high-temperature operating environments, the insulation performance of the single-layer passivation layer is prone to degradation, causing chip performance drift and shortening the device's lifespan.

[0004] Furthermore, during chip fabrication, the rationality of the trench etching process, the compatibility of the passivation layer deposition and annealing processes, and the matching degree of various structural parameters all directly affect the overall performance of the chip. In traditional fabrication processes, poor control of the inner wall curvature after trench etching can easily lead to sharp corner effects and exacerbate electric field concentration; an unreasonable ratio of passivation layer deposition temperature and reaction source can result in insufficient passivation layer density, porosity defects, and reduced insulation performance; and the lack of coordinated optimization in the design of parameters such as the thickness and doping concentration of each structural layer makes it difficult to simultaneously achieve both forward conduction performance and reverse withstand voltage performance of the chip.

[0005] Therefore, developing a high-voltage GPP chip with a reasonable structural design and optimized fabrication process that can simultaneously improve breakdown voltage, reduce leakage current, and ensure high-temperature stability has become an urgent need for the current industry development. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and to propose a high-voltage GPP chip with composite trenches and its fabrication method.

[0007] The specific technical solution is as follows: A high-voltage GPP chip with composite trenches, comprising:

[0008] N set sequentially from bottom to top + Substrate, N-layer, P-layer + Layer, the N+ The substrate layer and the N layer constitute NN + Substrate, the P + Layer P and N layers constitute P + -N junction;

[0009] The trenches in the chip edge region have a depth of 5-6 μm, and the inner wall of the trenches is covered with a composite passivation layer, which includes an inner boron-doped silicon glass layer with a thickness of 0.5-0.8 μm and an outer phosphorus-doped silicon glass layer with a thickness of 1.0-1.2 μm.

[0010] The inner side of the trench Isolation ring, and with P + The spacing between the layers is 1.5-2.0 μm;

[0011] Covering P + Layer surface and N + The metal layer on the lower surface of the substrate layer serves as the electrode lead-out layer of the chip.

[0012] As a further technical solution, the N-layer has a thickness of 15-20 μm and a doping concentration of 1×10⁻⁶. 14 -5×10 14 cm -3 The N + The substrate layer has a thickness of 100-150 μm and a doping concentration of 1×10⁻⁶. 19 -5×10 19 cm -3 The P + The layer thickness is 2-3 μm and the doping concentration is 1×10⁻⁶. 18 -5×10 18 cm -3 .

[0013] A method for fabricating a high-voltage GPP chip with composite trenches includes the following steps:

[0014] Step 1: P + -NN + Structure formation:

[0015] In N + An N-layer is grown on the substrate surface, followed by P-layer fabrication using ion implantation and laser annealing. + Layer: Boron ion implantation, energy 80keV, dose 5×10⁻⁶ 15 cm -2 Then, it is annealed with a laser with a wavelength of 532nm and a power of 50W at a scanning speed of 10mm / s to form P + -NN + structure;

[0016] Step 2: Selective oxide film growth:

[0017] In P + An oxide film is grown on the surface of the layer in N + An oxide film is grown on the lower surface of the substrate.

[0018] Step 3: Single photolithography and oxide film etching:

[0019] In P + Photoresist is spin-coated onto the surface of the layer, and trench areas are defined using a mask. After development, the oxide film is etched to expose the silicon surface.

[0020] Step 4: Trench Etching

[0021] A composite etching process is used to form trenches with a depth of 5-6 μm, and the radius of curvature of the inner wall of the trench is adjusted to 0.8-1.2 μm;

[0022] Step 5: Deposition and annealing of composite passivation layer:

[0023] A boron-doped silicon glass layer with an inner thickness of 0.5-0.8 μm and a phosphorus-doped silicon glass layer with an outer thickness of 1.0-1.2 μm were sequentially deposited using LPCVD, followed by rapid thermal annealing.

[0024] Step 6: Preparation and metallization of the isolation ring:

[0025] A doping concentration of 1×10⁻⁶ was formed through ion implantation. 15 -5×10 15 cm -3 of Isolation ring, controlling its connection with P + The interlayer spacing is 1.5-2.0 μm; subsequently, in P... + Layer surface and N + A metal layer is prepared on the lower surface of the substrate.

[0026] As a further technical solution, the growth of the N layer in step 1 adopts the depressurized epitaxy method. During the growth, a trace amount of germane is introduced into the reaction chamber at a flow rate of 5-10 sccm, so that the N layer is doped with 0.5-1.0% Ge atomic percentage.

[0027] As a further technical solution, in step 2, P + The oxide film on the surface of the layer is an aluminum oxide film with a thickness of 0.3 μm grown by atomic layer deposition, N + The oxide film on the lower surface of the substrate is a silicon dioxide film with a thickness of 0.5 μm.

[0028] As a further technical solution, step 3 uses a negative photoresist with a viscosity of 5000 cP, developed using 248nm deep ultraviolet lithography with an exposure dose of 150 mJ / cm². 2The oxide film was corroded using a diluted mixture of hydrofluoric acid and citric acid.

[0029] Dilute hydrofluoric acid to a ratio of HF:H₂O = 1:10;

[0030] Dilute the mixture of hydrofluoric acid and citric acid by a volume ratio of 3:1.

[0031] As a further technical solution, the composite etching process in step 4 is as follows: first, ICP plasma etching is used to form a preliminary outline, the gas is C4F8 / O2, the volume ratio is 4:1, the power is 250W, and the time is 45s. Then, chemical etching is performed using a mixture of 85℃ hot phosphoric acid and nitric acid with a volume ratio of 2:1, and the flow rate of the etching solution is controlled at 20mL / min.

[0032] As a further technical solution, in step 5, the deposition pressure of LPCVD is 1 Torr, the reaction source of the boron-doped silicon glass layer is B2H6 / SiH4 / O2, and the deposition temperature is 450℃; the reaction source of the phosphorus-doped silicon glass layer is PH3 / SiH4 / O2, and the deposition temperature is 480℃; the rapid thermal annealing is segmented: after holding at 600℃ for 10s, the temperature is raised to 850℃ and held for 30s, with a heating rate of 100℃ / s;

[0033] The flow ratio of B2H6 / SiH4 / O2 is 1:10:5;

[0034] The flow ratio of PH3 / SiH4 / O2 is 1:10:5.

[0035] As a further technical solution, in step 6... The ion implantation parameters for the isolation ring are: boron ion energy 50 keV, dose 1.5 × 10⁻⁶. 15 cm -3 .

[0036] As a further technical solution, in step 6, the metal layer is an aluminum-copper alloy layer with a Cu content of 0.5wt%, prepared by sputtering process with a power of 300W and a time of 60s, and then subjected to rapid thermal sintering at 400℃ for 2min.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] First, the chip of this invention uses N + Substrate, N-layer, P-layer + P composed of layers + -NN + The composite structure, by controlling the thickness and doping concentration of each layer, forms a reasonable carrier transport channel. +The substrate layer, with its high doping concentration and suitable thickness, provides a good current conduction path and reduces forward conduction resistance. The N-layer, serving as a drift region, has an optimized design in terms of thickness and doping concentration, ensuring sufficient space to withstand reverse high voltage while reducing carrier migration resistance. The P-layer... + P formed by layers N and N + The -N junction effectively blocks carrier flow under reverse bias, and combined with the buffering effect of the N layer, significantly improves the chip's reverse voltage withstand capability. Simultaneously, the incorporation of appropriate amounts of Ge atoms during N layer growth allows for adjustment of the N layer's lattice structure, increasing carrier mobility and thus reducing forward voltage drop. This enables the chip to achieve high voltage withstand capability while maintaining excellent forward conductivity, solving the problem of traditional chips struggling to balance forward conduction and reverse voltage withstand performance.

[0039] Secondly, the trench structure and composite passivation layer in the chip edge region The isolation rings work synergistically to fundamentally optimize the electric field distribution, solving the problems of low breakdown voltage and high leakage current caused by electric field concentration. The trench depth and inner wall curvature are controlled to avoid sharp corner effects and disperse the electric field intensity in the edge regions. The composite passivation layer employs a double-layer structure: an inner boron-doped silicon glass layer and an outer phosphorus-doped silicon glass layer. The boron-doped silicon glass layer has excellent interfacial bonding, allowing it to adhere tightly to the trench inner wall and effectively block charge injection. The phosphorus-doped silicon glass layer possesses excellent insulation properties and density, further enhancing the passivation effect. This synergistic effect of the double-layer structure significantly improves insulation performance and stability compared to traditional single-layer passivation layers, and significantly reduces leakage current. Simultaneously, Isolation ring and P + By maintaining a specific spacing between layers and designing appropriate doping concentrations and locations, additional potential barriers can be formed to further shield the electric field concentration at the chip edges. Combined with trenches and composite passivation layers, this constructs a multi-layered electric field optimization and insulation protection system, significantly improving the chip's reverse breakdown voltage. Furthermore, the thermal stability of the composite passivation layer remains consistent with... The structural stability of the isolation ring works synergistically to suppress performance degradation and ensure the reliability of the chip during long-term operation.

[0040] Finally, the optimized fabrication process of this invention is highly compatible with each structure, further amplifying the overall synergistic effect and achieving a comprehensive improvement in the chip's overall performance. During trench etching, a composite process combining ICP plasma etching and chemical etching is employed, which controls both the trench depth and contour while ensuring smooth inner walls and forming an ideal arc curvature, providing a good foundation for subsequent passivation layer deposition. During LPCVD deposition of the composite passivation layer, the density and uniformity of the passivation layer are ensured by controlling the deposition pressure, temperature, and reaction source flow rate ratio. Segmented rapid thermal annealing eliminates internal stress in the passivation layer, enhances its adhesion to the trench inner wall, and reduces defect generation. The metal layer uses an aluminum-copper alloy material and optimized sputtering and sintering processes, ensuring the reliability and conductivity of the electrode leads and reducing contact resistance. The matching of each fabrication step with the structural design allows the functions of each chip component to be fully utilized, and the synergistic effect of high breakdown voltage, low leakage current, low forward voltage drop and excellent high temperature stability is achieved, which meets the demand for high-performance chips in the field of high voltage power electronics. Moreover, the fabrication process steps are reasonable, highly controllable, and easy to industrialize and mass-produce. Attached Figure Description

[0041] Figure 1 This is a structural diagram of a high-voltage GPP chip with composite trenches;

[0042] 1 metal layer, 2P + Layer, 3N + Substrate layer, 4 trenches, 5N layer, 6 Isolation ring. Detailed Implementation

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] This invention provides a high-voltage GPP chip with composite trenches and its fabrication method, wherein the chip comprises N layers arranged sequentially from bottom to top. + Substrate layer 3, N layer 5, P + Layer 2, N + Substrate layer 3 and N layer 5 constitute NN + Substrate, P + Layer 2 and layer N5 constitute P +-N junction; a trench 4 is formed at the edge region of the chip, with a depth of 5-6μm. The inner wall of the trench is covered with a composite passivation layer, which includes an inner 0.5-0.8μm thick boron-doped silicon glass layer and an outer 1.0-1.2μm thick phosphorus-doped silicon glass layer; a trench 4 is formed on the inner side. Isolation ring 6, and with P + The spacing of layer 2 is 1.5-2.0 μm; P + Layer 2 surface and N + The lower surface of substrate 3 is covered with metal layer 1, which serves as the electrode lead-out layer of the chip.

[0045] In this invention, the thickness of the N-layer 5 is preferably 15-20 μm, and the doping concentration is preferably 1×10⁵ μm. 14 -5×10 14 cm -3 N + The thickness of substrate layer 3 is preferably 100-150 μm, and the doping concentration is preferably 1×10⁻⁶. 19 -5×10 19 cm -3 ;P + The thickness of layer 2 is preferably 2-3 μm, and the doping concentration is preferably 1×10⁻⁶. 18 -5×10 18 cm -3 .

[0046] The present invention provides a method for fabricating a high-voltage GPP chip with composite trenches, comprising the following steps:

[0047] Step 1: P + -NN + Structure formed in N + An N layer 5 is grown on the surface of substrate 3, followed by P layer fabrication using ion implantation and laser annealing. + Layer 2: Boron ion implantation, energy 80keV, dose 5×10⁻⁶ 15 cm -2 Then, it is annealed with a laser with a wavelength of 532nm and a power of 50W at a scanning speed of 10mm / s to form P + -NN + Structure. The N-layer 5 is preferably grown using depressurized epitaxy, with a trace amount of germane introduced into the reaction chamber during growth at a flow rate of 5-10 sccm, so that the N-layer 5 is doped with 0.5-1.0% Ge atomically.

[0048] Step 2: Selective oxide film growth on P + An oxide film is grown on the surface of layer 2, in N + An oxide film is grown on the lower surface of substrate layer 3. + The oxide film on the surface of layer 2 is preferably an alumina film with a thickness of 0.3 μm grown by atomic layer deposition, N+ The oxide film on the lower surface of the substrate layer 3 is preferably a silicon dioxide film with a thickness of 0.5 μm.

[0049] Step 3: Single photolithography and oxide film etching in P + Photoresist is spin-coated onto the surface of layer 2, and the trench 4 region is defined using a mask. After development, the oxide film is etched to expose the silicon surface. A negative photoresist with a viscosity of 5000 cP is preferably used. Development is performed using 248 nm deep ultraviolet lithography with an exposure dose of 150 mJ / cm². 2 The oxide film is etched using a mixture of diluted hydrofluoric acid and citric acid, wherein the diluted hydrofluoric acid is HF:H2O=1:10 and the volume ratio of the diluted hydrofluoric acid to citric acid mixture is 3:1.

[0050] Step 4: Trench etching is performed using a composite etching process to form trenches 4 with a depth of 5-6 μm, and the radius of curvature of the inner wall of the trench is adjusted to 0.8-1.2 μm. The preferred composite etching process is as follows: first, ICP plasma etching is used to form a preliminary outline, with the gas being C4F8 / O2 at a volume ratio of 4:1, a power of 250W, and a time of 45s; then, chemical etching is performed using a mixture of 85℃ hot phosphoric acid and nitric acid at a volume ratio of 2:1, with the etching solution flow rate controlled at 20mL / min.

[0051] Step 5: Composite passivation layer deposition and annealing. An inner 0.5-0.8 μm thick boron-doped silicon glass layer and an outer 1.0-1.2 μm thick phosphorus-doped silicon glass layer are sequentially deposited using LPCVD, followed by rapid thermal annealing. The preferred LPCVD deposition pressure is 1 Torr. The reaction source for the boron-doped silicon glass layer is B₂H₆ / SiH₄ / O₂ with a flow ratio of 1:10:5, and the deposition temperature is 450℃. The reaction source for the phosphorus-doped silicon glass layer is PH₃ / SiH₄ / O₂ with a flow ratio of 1:10:5, and the deposition temperature is 480℃. The rapid thermal annealing is segmented: holding at 600℃ for 10 s, then heating to 850℃ and holding for 30 s, with a heating rate of 100℃ / s.

[0052] Step 6: The isolation ring was fabricated and metallized by ion implantation to form a doping concentration of 1×10⁻⁶. 15 -5×10 15 cm -3 of Isolation ring 6, controlling its connection with P + The spacing of layer 2 is 1.5-2.0 μm; subsequently, in P... + Layer 2 surface and N + A metal layer 1 is prepared on the lower surface of substrate layer 3. The preferred ion implantation parameters for the isolation ring 6 are: boron ion energy 50 keV, dose 1.5 × 10⁻⁶. 15 cm -3The metal layer 1 is preferably an aluminum-copper alloy layer with a Cu content of 0.5 wt%. It is prepared by sputtering at a power of 300 W for 60 s and then subjected to rapid thermal sintering at 400 °C for 2 min.

[0053] The high-voltage GPP chip with composite trenches provided by this invention, through specific structural design and fabrication process, enables the composite passivation layer to effectively improve the chip's insulation performance and stability. The synergistic effect of isolation ring 6 and trench 4 can optimize the electric field distribution and improve the chip's withstand voltage performance. The fabrication process of metal layer 1 ensures the reliability of electrode lead-out. The overall structure and process adaptability enable the chip to have excellent comprehensive performance in high voltage application scenarios. At the same time, the fabrication process steps are reasonable and easy to industrialize.

[0054] To further illustrate the present invention, the following detailed description is provided through the examples and comparative examples.

[0055] Example 1:

[0056] Step 1: P + -NN + The structure was formed with a thickness of 100 μm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 N + Substrate 3 is on which an N-layer 5 is grown using depressurized epitaxy. During growth, germane is introduced into the reaction chamber at a flow rate of 5 sccm to dope the N-layer 5 with 0.5% atomic percentage of Ge. The thickness of the N-layer 5 is controlled to be 15 μm, and the doping concentration is 1 × 10⁻⁶. 14 cm -3 Subsequently, P was prepared using ion implantation and laser annealing processes. + Layer 2: Boron ion implantation, energy 80keV, dose 5×10⁻⁶ 15 cm -2 Then, it is annealed with a laser with a wavelength of 532nm and a power of 50W at a scanning speed of 10mm / s to form P + -NN + Structure, where P + Layer 2 is 2 μm thick and has a doping concentration of 1 × 10⁻⁶. 18 cm -3 .

[0057] Step 2: Selective oxide film growth is performed using atomic layer deposition on P + A 0.3 μm thick alumina film is grown on the surface of layer 2 using a thermal oxidation process on N. + A silicon dioxide film with a thickness of 0.5 μm is grown on the lower surface of substrate layer 3.

[0058] Step 3: Single photolithography and oxide film etching in P +A negative photoresist with a viscosity of 5000 cP was spin-coated onto the surface of layer 2. The trench 4 region was defined using a mask, and 248 nm deep ultraviolet lithography was employed for development with an exposure dose of 150 mJ / cm². 2 After development, the oxide film is etched using a mixture of diluted hydrofluoric acid and citric acid, wherein the diluted hydrofluoric acid is HF:H2O=1:10 and the volume ratio of the diluted hydrofluoric acid to citric acid mixture is 3:1. After etching, the silicon surface is exposed.

[0059] Step 4: Trench etching. First, ICP plasma etching is used to form a preliminary outline. The gas is C4F8 / O2 with a volume ratio of 4:1, the power is 250W, and the time is 45s. Then, chemical etching is performed using a mixture of 85℃ hot phosphoric acid and nitric acid with a volume ratio of 2:1. The flow rate of the etching solution is controlled at 20mL / min. Finally, a trench 4 with a depth of 5μm is formed, and the radius of curvature of the inner wall of the trench is adjusted to 0.8μm.

[0060] Step 5: Composite passivation layer deposition and annealing. LPCVD process was used. Under deposition pressure of 1 Torr and temperature of 450℃, a 0.5 μm thick boron-doped silicon glass layer was deposited using B2H6 / SiH4 / O2 as the reaction source and a flow rate ratio of 1:10:5. Subsequently, under deposition pressure of 1 Torr and temperature of 480℃, a 1.0 μm thick phosphorus-doped silicon glass layer was deposited using PH3 / SiH4 / O2 as the reaction source and a flow rate ratio of 1:10:5. After deposition, rapid thermal annealing was performed. The segmented process involved holding at 600℃ for 10 s, then heating to 850℃ and holding for 30 s, with a heating rate of 100℃ / s.

[0061] Step 6: The isolation ring was prepared and metallized using an ion implantation process. Isolation ring 6, boron ion implanted, energy 50keV, dose 1.5×10⁻⁶. 15 cm -3 ,control Isolation ring 6 and P + The spacing of layer 2 is 1.5 μm. Isolation ring 6 doping concentration 1×10 15 cm -3 Subsequently, a sputtering process was used on P + Layer 2 surface and N + An aluminum-copper alloy metal layer 1 with a Cu content of 0.5 wt% was prepared on the lower surface of substrate layer 3. The sputtering power was 300 W and the time was 60 s. After preparation, the high-voltage GPP chip with composite trenches was obtained by rapid thermal sintering at 400 °C for 2 min.

[0062] Example 2:

[0063] Step 1: P + -NN +The structure was formed with a thickness of 125 μm and a doping concentration of 3 × 10⁻⁶. 19 cm -3 N + Substrate 3 is on which an N-layer 5 is grown using depressurized epitaxy. During growth, germane is introduced into the reaction chamber at a flow rate of 8 sccm to dope the N-layer 5 with 0.8% atomic percentage of Ge. The thickness of the N-layer 5 is controlled to be 18 μm, and the doping concentration is 3 × 10⁻⁶. 14 cm -3 Subsequently, P was prepared using ion implantation and laser annealing processes. + Layer 2: Boron ion implantation, energy 80keV, dose 5×10⁻⁶ 15 cm -2 Then, it is annealed with a laser with a wavelength of 532nm and a power of 50W at a scanning speed of 10mm / s to form P + -NN + Structure, where P + Layer 2 is 2.5 μm thick and has a doping concentration of 3 × 10⁻⁶. 18 cm -3 .

[0064] Step 2: Selective oxide film growth is performed using atomic layer deposition on P + A 0.3 μm thick alumina film is grown on the surface of layer 2 using a thermal oxidation process on N. + A silicon dioxide film with a thickness of 0.5 μm is grown on the lower surface of substrate layer 3.

[0065] Step 3: Single photolithography and oxide film etching in P + A negative photoresist with a viscosity of 5000 cP was spin-coated onto the surface of layer 2. The trench 4 region was defined using a mask, and 248 nm deep ultraviolet lithography was employed for development with an exposure dose of 150 mJ / cm². 2 After development, the oxide film is etched using a mixture of diluted hydrofluoric acid and citric acid, wherein the diluted hydrofluoric acid is HF:H2O=1:10 and the volume ratio of the diluted hydrofluoric acid to citric acid mixture is 3:1. After etching, the silicon surface is exposed.

[0066] Step 4: Trench etching. First, ICP plasma etching is used to form a preliminary outline. The gas is C4F8 / O2, volume ratio 4:1, power 250W, time 45s. Then, chemical etching is performed using a mixture of 85℃ hot phosphoric acid and nitric acid with a volume ratio of 2:1. The flow rate of the etching solution is controlled at 20mL / min. Finally, a trench 4 with a depth of 5.5μm is formed, and the radius of curvature of the inner wall of the trench is adjusted to 1.0μm.

[0067] Step 5: Composite passivation layer deposition and annealing. LPCVD process was used. Under deposition pressure of 1 Torr and temperature of 450℃, a 0.65 μm thick boron-doped silicon glass layer was deposited using B2H6 / SiH4 / O2 as the reaction source at a flow rate of 1:10:5. Subsequently, under deposition pressure of 1 Torr and temperature of 480℃, a 1.1 μm thick phosphorus-doped silicon glass layer was deposited using PH3 / SiH4 / O2 as the reaction source at a flow rate of 1:10:5. After deposition, rapid thermal annealing was performed. The segmented process involved holding at 600℃ for 10 s, then heating to 850℃ and holding for 30 s, with a heating rate of 100℃ / s.

[0068] Step 6: The isolation ring was prepared and metallized using an ion implantation process. Isolation ring 6, boron ion implanted, energy 50keV, dose 1.5×10⁻⁶. 15 cm -3 ,control Isolation ring 6 and P + The spacing of layer 2 is 1.8 μm. Isolation ring 6 doping concentration 3×10 15 cm -3 Subsequently, a sputtering process was used on P + Layer 2 surface and N + An aluminum-copper alloy metal layer 1 with a Cu content of 0.5 wt% was prepared on the lower surface of substrate layer 3. The sputtering power was 300 W and the time was 60 s. After preparation, the high-voltage GPP chip with composite trenches was obtained by rapid thermal sintering at 400 °C for 2 min.

[0069] Example 3:

[0070] Step 1: P + -NN + The structure was formed with a thickness of 150 μm and a doping concentration of 5 × 10⁻⁶. 19 cm -3 N + Substrate 3 is on which an N-layer 5 is grown using depressurized epitaxy. During growth, germane is introduced into the reaction chamber at a flow rate of 10 sccm to dope the N-layer 5 with 1.0% atomic percentage of Ge. The thickness of the N-layer 5 is controlled to be 20 μm, and the doping concentration is 5 × 10⁻⁶. 14 cm -3 Subsequently, P was prepared using ion implantation and laser annealing processes. + Layer 2: Boron ion implantation, energy 80keV, dose 5×10⁻⁶ 15 cm -2 Then, it is annealed with a laser with a wavelength of 532nm and a power of 50W at a scanning speed of 10mm / s to form P + -NN + Structure, where P+ Layer 2 is 3 μm thick with a doping concentration of 5 × 10⁻⁶. 18 cm -3 .

[0071] Step 2: Selective oxide film growth is performed using atomic layer deposition on P + A 0.3 μm thick alumina film is grown on the surface of layer 2 using a thermal oxidation process on N. + A silicon dioxide film with a thickness of 0.5 μm is grown on the lower surface of substrate layer 3.

[0072] Step 3: Single photolithography and oxide film etching in P + A negative photoresist with a viscosity of 5000 cP was spin-coated onto the surface of layer 2. The trench 4 region was defined using a mask, and 248 nm deep ultraviolet lithography was employed for development with an exposure dose of 150 mJ / cm². 2 After development, the oxide film is etched using a mixture of diluted hydrofluoric acid and citric acid, wherein the diluted hydrofluoric acid is HF:H2O=1:10 and the volume ratio of the diluted hydrofluoric acid to citric acid mixture is 3:1. After etching, the silicon surface is exposed.

[0073] Step 4: Trench etching. First, ICP plasma etching is used to form a preliminary outline. The gas is C4F8 / O2 with a volume ratio of 4:1, the power is 250W, and the time is 45s. Then, chemical etching is performed using a mixture of 85℃ hot phosphoric acid and nitric acid with a volume ratio of 2:1. The flow rate of the etching solution is controlled at 20mL / min. Finally, a trench 4 with a depth of 6μm is formed, and the radius of curvature of the inner wall of the trench is adjusted to 1.2μm.

[0074] Step 5: Composite passivation layer deposition and annealing. LPCVD process was used. Under deposition pressure of 1 Torr and temperature of 450℃, a 0.8 μm thick boron-doped silicon glass layer was deposited using B2H6 / SiH4 / O2 as the reaction source at a flow rate ratio of 1:10:5. Subsequently, under deposition pressure of 1 Torr and temperature of 480℃, a 1.2 μm thick phosphorus-doped silicon glass layer was deposited using PH3 / SiH4 / O2 as the reaction source at a flow rate ratio of 1:10:5. After deposition, rapid thermal annealing was performed. The segmented process involved holding at 600℃ for 10 s, then heating to 850℃ and holding for 30 s, with a heating rate of 100℃ / s.

[0075] Step 6: The isolation ring was prepared and metallized using an ion implantation process. Isolation ring 6, boron ion implanted, energy 50keV, dose 1.5×10⁻⁶. 15 cm -3 ,control Isolation ring 6 and P + The spacing of layer 2 is 2.0 μm. Isolation ring 6 doping concentration 5×10 15cm -3 Subsequently, a sputtering process was used on P + Layer 2 surface and N + An aluminum-copper alloy metal layer 1 with a Cu content of 0.5 wt% was prepared on the lower surface of substrate layer 3. The sputtering power was 300 W and the time was 60 s. After preparation, the high-voltage GPP chip with composite trenches was obtained by rapid thermal sintering at 400 °C for 2 min.

[0076] Comparative Example 1:

[0077] The preparation method of Example 2 was adopted, except that: no composite passivation layer was set on the inner wall of trench 4, and only a single layer of boron-doped silicon glass with a thickness of 0.65 μm was deposited. The other preparation parameters were completely consistent with those of Example 2, and a high-voltage GPP chip was obtained.

[0078] Test experiment:

[0079] Experimental equipment: Semiconductor parameter analyzer, used to test forward voltage drop, reverse breakdown voltage and leakage current;

[0080] High and low temperature test chamber, used for high temperature stability testing;

[0081] The probe station is used in conjunction with a semiconductor parameter analyzer to test the electrical performance of chips.

[0082] Experimental methods:

[0083] Forward voltage drop test: At room temperature of 25°C, place the chip on the probe stage and apply a forward current of 100mA through a semiconductor parameter analyzer. Record the voltage value across the chip at this time, which is the forward voltage drop V_F.

[0084] Reverse breakdown voltage test: At room temperature of 25℃, a reverse voltage is applied. When the reverse leakage current reaches 10μA, the corresponding voltage value is the reverse breakdown voltage V_BR.

[0085] Leakage current test: At room temperature of 25°C, apply a reverse voltage of 80% of the reverse breakdown voltage and record the leakage current I_R.

[0086] High-temperature stability test: The chip was placed in a high and low temperature test chamber, the temperature was set to 150℃, and it was kept at that temperature for 1000 hours. After being removed and cooled to room temperature, the forward voltage drop, reverse breakdown voltage, and leakage current were tested again. The rate of change of forward voltage drop ΔV_F / V_F (initial) and the rate of change of reverse breakdown voltage ΔV_BR / V_BR (initial) were calculated. The experimental results are as follows:

[0087] Table 1

[0088] sample Forward pressure drop V_F(V) Reverse breakdown voltage V_BR (kV) Leakage current I_R (μA) High-temperature stability (150℃ / 1000h) positive pressure drop change rate High-temperature stability (150℃ / 1000h) Reverse breakdown voltage change rate Example 1 0.72 12.5 0.8 1.2% -0.8% Example 2 0.70 13.2 0.6 1.0% -0.6% Example 3 0.68 13.8 0.5 0.9% -0.5% Comparative Example 1 0.71 10.3 3.2 3.5% -3.2%

[0089] As can be seen from Table 1, the forward voltage drop analysis shows that the forward voltage drops of Examples 1-3 and Comparative Example 1 are within the range of 0.68-0.72V, with little difference. This indicates that the composite passivation layer has little impact on the forward conduction performance of the chip. The technical solution of this invention optimizes other performances while ensuring forward conductivity.

[0090] Reverse breakdown voltage analysis: The reverse breakdown voltages of Examples 1-3 were all above 12.5kV, with Example 3 reaching 13.8kV, while Comparative Example 1 (without composite passivation layer) was only 10.3kV. This is because the boron-doped silicon glass layer and the phosphorus-doped silicon glass layer in the composite passivation layer work synergistically to effectively reduce charge accumulation on the inner wall of trench 4 and reduce the electric field concentration effect. Comparative Example 1, lacking the auxiliary passivation of the phosphorus-doped silicon glass layer, had insufficient insulation performance on the inner wall of trench 4, leading to electric field concentration and a decrease in breakdown voltage.

[0091] Leakage current analysis: The leakage currents of Examples 1-3 were all between 0.5-0.8 μA, which is relatively small, while the leakage current of Comparative Example 1 was 3.2 μA. This is because the composite passivation layer has excellent insulation properties and can effectively block the leakage of charge carriers. In Comparative Example 1, the insulation effect of the single-layer boron-doped silicon glass layer is limited, and it cannot effectively block the leakage current.

[0092] High-temperature stability analysis: After aging at 150℃ for 1000h, Examples 1-3 showed a forward voltage drop change rate of only 0.9%-1.2% and a reverse breakdown voltage change rate of only -0.5% to -0.8%, demonstrating excellent stability. In contrast, Comparative Example 1 showed a forward voltage drop change rate of 3.5% and a reverse breakdown voltage change rate of -3.2%. This is because the double-layer structure of the composite passivation layer has good thermal stability, maintaining stable insulation performance at high temperatures. Comparative Example 1, due to the insufficient thermal stability of its single-layer passivation layer, experienced a decrease in insulation performance at high temperatures.

[0093] In summary, the composite passivation layer in the technical solution of this invention is a key technology for improving the reverse breakdown voltage of high-voltage GPP chips, reducing leakage current, and ensuring high-temperature stability.

[0094] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not describe all details exhaustively, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification.

Claims

1. A high-voltage GPP chip with composite trenches, characterized in that, include: N set sequentially from bottom to top + Substrate (3), N layer (5), P + Layer (2), the N + The substrate layer (3) and the N layer (5) constitute the NN + Substrate, the P + Layer (2) and N layers (5) constitute P + -N junction; The trench (4) in the chip edge region has a depth of 5-6 μm and the inner wall of the trench is covered with a composite passivation layer, which includes an inner layer of boron-doped silicon glass with a thickness of 0.5-0.8 μm and an outer layer of phosphorus-doped silicon glass with a thickness of 1.0-1.2 μm. The inner side of the groove (4) Isolation ring (6), and with P + The spacing between layers (2) is 1.5-2.0 μm; Covering P + Layer (2) surface and N + The metal layer (1) on the lower surface of the substrate layer (3) serves as the electrode lead-out layer of the chip; the N layer (5) has a thickness of 15-20 μm and a doping concentration of 1×10⁻⁶. 14 -5×10 14 cm -3 The N + The substrate layer (3) has a thickness of 100-150 μm and a doping concentration of 1×10⁻⁶. 19 -5×10 19 cm -3 The P + Layer (2) has a thickness of 2-3 μm and a doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 .

2. The method for fabricating a high-voltage GPP chip with composite trenches according to claim 1, characterized in that, Includes the following steps: Step 1: P + -NN + Structure formation: In N + An N layer (5) is grown on the surface of the substrate (3), and then P is prepared by ion implantation and laser annealing. + Layer (2): Boron ions were implanted at an energy of 80 keV and a dose of 5 × 10⁻⁶. 15 cm -2 Then, it is annealed with a laser with a wavelength of 532nm and a power of 50W at a scanning speed of 10mm / s to form P + -NN + structure; Step 2: Selective oxide film growth: In P + An oxide film is grown on the surface of layer (2) in N + An oxide film is grown on the lower surface of the substrate layer (3); Step 3: Single photolithography and oxide film etching: In P + Photoresist is spin-coated onto the surface of layer (2), and the trench area is defined by a mask. After development, the oxide film is etched to expose the silicon surface. Step 4: Trench Etching A composite etching process was used to form trenches with a depth of 5-6 μm (4), and the radius of curvature of the inner wall of the trench was adjusted to 0.8-1.2 μm; Step 5: Deposition and annealing of composite passivation layer: A boron-doped silicon glass layer with an inner thickness of 0.5-0.8 μm and a phosphorus-doped silicon glass layer with an outer thickness of 1.0-1.2 μm were sequentially deposited using LPCVD, followed by rapid thermal annealing. Step 6: Preparation and metallization of the isolation ring: A doping concentration of 1×10⁻⁶ was formed through ion implantation. 15 -5×10 15 cm -3 of Isolation ring (6), controlling its connection with P + The spacing between layers (2) is 1.5-2.0 μm; subsequently, in P + Layer (2) surface and N + A metal layer (1) is prepared on the lower surface of the substrate layer (3).

3. The preparation method according to claim 2, characterized in that, In step 1, the growth of the N layer (5) is carried out by depressurized epitaxy. During the growth, a small amount of germane is introduced into the reaction chamber at a flow rate of 5-10 sccm, so that the N layer (5) is doped with 0.5-1.0% of Ge atomic percentage.

4. The preparation method according to claim 2, characterized in that, In step 2, P + The oxide film on the surface of layer (2) is an aluminum oxide film with a thickness of 0.3 μm grown by atomic layer deposition, N + The oxide film on the lower surface of the substrate (3) is a silicon dioxide film with a thickness of 0.5 μm.

5. The preparation method according to claim 2, characterized in that, In step 3, a negative photoresist with a viscosity of 5000 cP is used, and development is performed using 248 nm deep ultraviolet lithography with an exposure dose of 150 mJ / cm². 2 The oxide film was corroded using a diluted mixture of hydrofluoric acid and citric acid. Dilute hydrofluoric acid to a ratio of HF:H₂O = 1:10; Dilute the mixture of hydrofluoric acid and citric acid by a volume ratio of 3:

1.

6. The preparation method according to claim 2, characterized in that, The composite etching process in step 4 is as follows: First, ICP plasma etching is used to form a preliminary outline. The gas is C4F8 / O2 with a volume ratio of 4:1, the power is 250W, and the time is 45s. Then, chemical etching is performed using a mixture of 85℃ hot phosphoric acid and nitric acid with a volume ratio of 2:

1. The flow rate of the etching solution is controlled at 20mL / min.

7. The preparation method according to claim 2, characterized in that, In step 5, the LPCVD deposition pressure is 1 Torr, the reaction source for the boron-doped silicon glass layer is B2H6 / SiH4 / O2, and the deposition temperature is 450℃; the reaction source for the phosphorus-doped silicon glass layer is PH3 / SiH4 / O2, and the deposition temperature is 480℃; the rapid thermal annealing is segmented: after holding at 600℃ for 10s, the temperature is increased to 850℃ and held for 30s, with a heating rate of 100℃ / s; The flow ratio of B2H6 / SiH4 / O2 is 1:10:5; The flow ratio of PH3 / SiH4 / O2 is 1:10:

5.

8. The preparation method according to claim 2, characterized in that, In step 6 The ion implantation parameters for the isolation ring are: boron ion energy 50 keV, dose 1.5 × 10⁻⁶. 15 cm -3 .

9. The preparation method according to claim 2, characterized in that, In step 6, the metal layer (1) is an aluminum-copper alloy layer with a Cu content of 0.5wt%. It is prepared by sputtering process with a power of 300W and a time of 60s, and is subjected to rapid thermal sintering at 400℃ for 2min.

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