Miniature monomer packaging electronic protection structure and manufacturing method thereof

Abstract

The invention relates to a micro monomer packaging electronic protection structure and a manufacturing method thereof. The packaging structure comprises a packaging main body which is of an integrally-formed structure and is internally provided with a closed functional cavity; the first inner conductor structure and the second inner conductor structure are arranged in the closed functional cavity and are oppositely arranged; the first outer electrode and the second outer electrode are respectively arranged on the outer surface of the packaging main body and are respectively and electrically connected with the first inner conductor structure and the second inner conductor structure; the volume of the closed functional cavity accounts for 15%-60% of the total volume of the packaging main body, so that a main electric field coupling region between the first inner conductor structure and the second inner conductor structure is positioned in the closed functional cavity; the projection overlapping area S of the first inner conductor structure and the second inner conductor structure in the direction perpendicular to the packaging length direction is not larger than 0.03 mm. According to the invention, parasitic coupling can be effectively reduced and relatively low parasitic capacitance can be obtained under the condition of submillimeter size.

Description

Technical Field

[0001] This invention relates to the field of electronic packaging technology, and in particular to a miniature single-unit packaged electronic protection structure and its manufacturing method. Background Technology

[0002] As automotive electronic systems become increasingly integrated and miniaturized, the number of protective electronic devices used in domain controllers, camera modules, radar systems, sensor interfaces, and power management modules has increased significantly. Especially under conditions of high-speed interfaces and high-density wiring, higher requirements are placed on the size, parasitic parameters, and reliability of electronic protection packaging structures.

[0003] Existing electronic protection packaging structures mainly include the following types: (1) A structure with an internal cavity formed by a multilayer printed circuit board stack-up structure; (2) It adopts a filled packaging structure, that is, a structure in which the interior is completely filled with high dielectric packaging material; (3) A plate-level structure that forms a cavity by enclosing a frame or spacer layer.

[0004] The aforementioned structures can meet certain structural and electrical performance requirements within the millimeter-scale and above. However, when the package size shrinks to the sub-millimeter scale below 1.0 mm, the existing technology gradually reveals the following problems: (1) The multilayer printed circuit board stack-up structure is difficult to achieve high-precision alignment and stable packaging in sub-millimeter size, and the interlayer interface and alignment error have a significant impact on electrical performance. (2) The interior of the filled packaging structure is made of a high dielectric constant material. The electric field flux between the first conductor and the second conductor is partially distributed in the high dielectric packaging material. The parasitic coupling path is long, making it difficult to achieve extremely low parasitic capacitance. (3) Some plate-level cavity structures rely on the splicing of multiple components to form the cavity, and the cavity boundary is composed of different components. Under sub-millimeter size, the structural stability and manufacturing consistency are limited. (4) Existing technologies usually only focus on the presence of cavities or size reduction in the structure, without limiting the distribution of electric field coupling paths in space, or establishing the correspondence between cavity proportion and electrical performance.

[0005] Therefore, under sub-millimeter package size conditions, traditional structural approaches cannot simultaneously meet the following requirements: stability of the single-unit package structure, formation of internal enclosed functional space, significant reduction of parasitic capacitance, and reliability in automotive environments.

[0006] Therefore, how to form a stable and closed functional cavity inside a sub-millimeter-level monolithic package under non-multilayer printed circuit board stack-up structure conditions, and control the electric field coupling path through spatial structure design, so as to achieve low parasitic capacitance while maintaining structural reliability, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The purpose of this invention is to address the problem that existing electronic protection packaging structures cannot simultaneously achieve structural stability and low parasitic capacitance under sub-millimeter size conditions, and to provide a miniature single-unit packaged electronic protection structure and its manufacturing method.

[0008] To address the aforementioned technical problems, this invention provides a miniature single-unit packaged electronic protection structure, comprising: The package body is a one-piece molded structure of continuous medium, and is not formed by stacking two or more printed circuit boards; A closed functional cavity is disposed inside the packaging body. The closed functional cavity is formed entirely by the material of the packaging body and does not penetrate any outer wall of the packaging body. A semiconductor functional unit is disposed inside the cavity. The first inner conductor structure and the second inner conductor structure are disposed inside the closed functional cavity and are disposed opposite to each other, with a predetermined distance between them; The first external electrode and the second external electrode are respectively disposed on the outer surface of the encapsulation body, and are electrically connected to the first inner conductor structure and the second inner conductor structure to form a continuous conductive path; in, The main electric field coupling region formed between the first inner conductor structure and the second inner conductor structure is located entirely within the internal space of the enclosed functional cavity, and is spatially separated from the solid material region of the encapsulation body; The volume of the enclosed functional cavity accounts for 15% to 60% of the total volume of the encapsulation body; The overlapping area S of the projection of the first inner conductor structure and the second inner conductor structure in the direction perpendicular to the package length is not greater than 0.03 mm².

[0009] Under the above structural constraints, the equivalent capacitance of the package structure is preferably no greater than 0.1 pF under 1 MHz testing conditions.

[0010] In one embodiment of the present invention, the external dimensions of the encapsulation body satisfy the following: length not greater than 1.0 mm; width not greater than 0.6 mm; and thickness not greater than 0.4 mm.

[0011] In one embodiment of the present invention, the encapsulation body has a length of 0.4 mm to 0.8 mm, a width of 0.2 mm to 0.4 mm, and a thickness of 0.15 mm to 0.3 mm.

[0012] In one embodiment of the present invention, the dimension of the enclosed functional cavity in the length direction of the encapsulation body is not less than 30% of the length of the encapsulation body; and the dimension of the enclosed functional cavity in the width direction of the encapsulation body is not less than 20% of the width of the encapsulation body.

[0013] In one embodiment of the present invention, the minimum spacing between the first inner conductor structure and the second inner conductor structure is not less than 20% of the width of the package body; the relative positional deviation Δd between the first inner conductor structure and the second inner conductor structure is not greater than ±0.01mm.

[0014] In one embodiment of the present invention, the semiconductor functional unit is a transient voltage suppression unit, a diode unit, or a thyristor unit; the size of the semiconductor functional unit is no greater than 0.25mm × 0.15mm.

[0015] In one embodiment of the present invention, the medium state inside the sealed functional cavity is any one or a combination of the following: Air; Dielectric materials with a dielectric constant not greater than 2.5; Low-pressure sealed cavity; A sealed cavity filled with inert gas.

[0016] In one embodiment of the present invention, the dielectric constant of the medium inside the enclosed functional cavity is lower than the dielectric constant of the encapsulation body material; the encapsulation body is formed of silicon-based material, ceramic-based material or polymer encapsulation material.

[0017] In one embodiment of the present invention, the encapsulation body is provided with at least one micro process release hole, the diameter of the micro process release hole is not greater than 0.05 mm, and the micro process release hole is sealed by a sealing structure.

[0018] The present invention also provides a method for manufacturing the aforementioned miniature single-unit packaged electronic protection structure for automotive electronic systems, comprising: S1. Basic Construction: Forming the first inner conductor structure and its lead-out connection structure on a temporary base or supporting substrate; S2. Temporary support structure: A temporary support structure is formed on top of the first inner conductor structure through mold prefabrication, micromachining or sacrificial layer construction process, and the volume of the temporary support structure corresponds to the volume ratio of the subsequently formed closed functional cavity. S3. Conductor alignment: A second inner conductor structure is formed above the temporary support structure, and the overlapping area of ​​the projection of the first inner conductor structure and the second inner conductor structure in the direction perpendicular to the package length is controlled to be no more than 0.03 mm². S4. Integrated packaging: A single-unit packaging body with a continuous medium is formed by molding or integral molding process, so that the first inner conductor structure, the second inner conductor structure and the temporary support structure are covered inside the packaging body. S5. Cavity Formation: A micro-process release hole is formed on the packaging body, and the temporary support structure is removed to form a closed functional cavity in situ inside the packaging body; S6. Electrode integration: A first external electrode and a second external electrode are formed on the encapsulation body, and the first inner conductor structure and the second inner conductor structure are electrically connected to the first external electrode and the second external electrode, respectively. S7. Environmental sealing: The micro-process release hole is sealed to form a sealed low-dielectric microenvironment in the closed functional cavity.

[0019] The technical solution of the present invention has the following advantages over the prior art: This invention discloses a miniature single-unit packaged electronic protection structure and its manufacturing method. A completely enclosed functional cavity is formed within the package body, and a first inner conductor structure and a second inner conductor structure are arranged opposite each other within this cavity. By defining the volume ratio of the closed functional cavity and the geometric relationship between the first and second inner conductor structures, the main electric field coupling region between them is located within the low-dielectric-constant closed functional cavity and spatially separated from the package body material. This effectively reduces parasitic coupling and achieves a low-parasitic-capacitance electronic protection package structure under sub-millimeter package size conditions. Under non-multilayer printed circuit board stack-up structures, structural unity between the sub-millimeter-scale closed functional cavity structure and low parasitic capacitance is achieved, enabling the package structure to maintain mechanical reliability while obtaining stable low-parasitic-capacitance characteristics.

[0020] In addition, the present invention has at least the following beneficial effects: I. Achieving a single-unit packaging structure at sub-millimeter size.

[0021] This invention uses a single-unit molded package body instead of a multi-layer printed circuit board stacked structure, which can form a stable package structure within a size range with a length of no more than 1.0 mm, and is suitable for the miniaturization integration needs of high-density automotive electronic systems.

[0022] 2. Forming a stable, sealed functional cavity in micro-packaging.

[0023] The present invention forms a closed functional cavity completely enclosed by the packaging body inside the monolithic packaging body, without penetrating the sidewalls. It can achieve a stable internal functional space structure under sub-millimeter size conditions and improve the overall structural integrity of the packaging.

[0024] Third, it effectively reduces parasitic coupling and parasitic capacitance.

[0025] By limiting the volume ratio of the functional cavity and the projected overlap area of ​​the first and second inner conductor structures, the main electric field coupling region is located inside the low-dielectric enclosed functional cavity, thereby reducing parasitic coupling formed by the high-dielectric packaging material. An equivalent capacitance of no more than 0.1 pF can be achieved at 1 MHz.

[0026] IV. Provide a configurable packaging platform.

[0027] The enclosed functional cavity can accommodate miniature semiconductor protection functional units, be filled with low-dielectric materials, or remain empty, giving the packaging structure configurable platform attributes that can be adapted to different types of electronic protection functional units.

[0028] V. Applicable to in-vehicle electronic system environments.

[0029] The packaging structure of this invention maintains structural and electrical stability within a temperature range of -40℃ to 150℃, making it suitable for automotive electronic system applications such as vehicle camera modules, radar systems, sensor interfaces, and power management modules.

[0030] VI. It is conducive to miniaturized mass production and consistency control.

[0031] The single-unit molded package structure eliminates the need for multiple printed circuit boards to be stacked and aligned or for board-level frame sandwich structures, which is beneficial for achieving mass production and consistency control of sub-millimeter-level package structures and improving production stability.

[0032] VII. Establish the correspondence between structural parameters and electrical performance.

[0033] By coordinating the design of the proportions of the enclosed functional cavities and the geometric relationship of the internal conductor structure, the low parasitic capacitance characteristic becomes a technical result directly determined by the structure, rather than simply obtained through size reduction or material replacement, thereby enhancing the predictability and stability of the structural design. Attached Figure Description

[0034] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0035] Figure 1 This is a schematic diagram of the micro-mono-packaged electronic protection structure of the vehicle electronic system in an embodiment of the present invention. Figure 1 .

[0036] Figure 2 This is a schematic diagram of the micro-mono-packaged electronic protection structure of the vehicle electronic system in an embodiment of the present invention. Figure 2 .

[0037] Figure 3 This is a schematic diagram showing the misaligned distribution of the first inner conductor structure and the second inner conductor structure in an embodiment of the present invention.

[0038] Figure 4 This is a top view showing the overlapping relationship between the projections of the first inner conductor structure and the second inner conductor structure in an embodiment of the present invention.

[0039] Figure 5 This is a longitudinal cross-sectional view showing the overlapping relationship of the projections of the first inner conductor structure and the second inner conductor structure in an embodiment of the present invention.

[0040] Figure 6 This is a diagram showing the spacing between the first inner conductor structure and the second inner conductor structure in an embodiment of the present invention.

[0041] Figure 7 This is a schematic diagram illustrating the overall dimensions of the encapsulation body and the relative proportions between the encapsulated functional cavity and the encapsulation body in an embodiment of the present invention.

[0042] Figure 8 This is a schematic diagram showing the relationship between the volume ratio of the enclosed functional cavity and the equivalent capacitance of the present invention.

[0043] Figure 9 This is a schematic diagram of the electric field distribution in the enclosed functional cavity of the present invention.

[0044] Figure 10 This is a schematic diagram of the encapsulation structure when the functional cavity accounts for a high percentage (over 60%) of the total volume.

[0045] Figure 11 This is a schematic diagram of the formation of a first inner conductor structure on a temporary base or supporting substrate according to the present invention.

[0046] Figure 12 This is a schematic diagram of the temporary support structure constructed above the first inner conductor structure according to the present invention.

[0047] Figure 13 This is a schematic diagram of the second conductor and the molded package of the present invention.

[0048] Figure 14 This is a schematic diagram illustrating the removal of the temporary support structure according to the present invention.

[0049] Figure 15 This is a schematic diagram of a cavity structure formed by multilayer printed circuit board stacking and frame structure in the prior art.

[0050] Explanation of reference numerals in the instruction manual: 10. Packaging body; 101. Miniature process release hole; 102. Sealing structure; 103. Temporary base or load-bearing substrate; 104. Temporary support structure; 20. Enclosed functional cavities; 31. First external electrode; 32. Second external electrode; 41. First inner conductor structure; 42. Second inner conductor structure. Detailed Implementation

[0051] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0052] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0053] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0054] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0055] Example 1 Reference Figures 1 to 3 As shown, this embodiment provides a miniature single-unit packaged electronic protection structure, including: The encapsulation body 10 is a one-piece molded structure of continuous medium, and is not formed by stacking two or more printed circuit boards; A closed functional cavity 20 is disposed inside the packaging body 10. The closed functional cavity 20 is formed entirely by the material of the packaging body 10 and does not penetrate any outer wall of the packaging body 10. A semiconductor functional unit is disposed inside it. The first inner conductor structure 41 and the second inner conductor structure 42 are disposed inside the closed functional cavity 20 and are disposed opposite to each other, and there is a predetermined distance between them; The first external electrode 31 and the second external electrode 32 are respectively disposed on the outer surface of the encapsulation body 10, and are respectively electrically connected to the first inner conductor structure 41 and the second inner conductor structure 42 to form a continuous conductive path; in, The main electric field coupling region formed between the first inner conductor structure 41 and the second inner conductor structure 42 is located entirely within the internal space of the closed functional cavity 20, and is spatially separated from the solid material region of the encapsulation body 10; The volume of the enclosed functional cavity 20 accounts for 15% to 60% of the total volume of the encapsulation body 10; The overlapping area S of the projection of the first inner conductor structure 41 and the second inner conductor structure 42 in the direction perpendicular to the package length is not greater than 0.03 mm².

[0056] By synergistically limiting the volume ratio of the enclosed functional cavity 20 and the projected overlapping area S, the equivalent capacitance of the packaging structure under 1MHz test conditions is not greater than 0.1 pF.

[0057] Reference Figure 1 As shown, the first external electrode 31 and the second external electrode 32 are respectively disposed on the outer surface of the encapsulation body 10 and partially embedded in the outer surface of the encapsulation body 10; in other embodiments, refer to Figure 2 As shown, the first external electrode 31 and the second external electrode 32 are respectively disposed on the outer surface of the encapsulation body 10 and are in close contact with the outer surface of the encapsulation body 10.

[0058] It should be noted that the enclosed functional cavity 20 is completely enclosed by the packaging body 10 and located inside the packaging body 10, and the enclosed functional cavity 20 does not penetrate the sidewall of the packaging body 10. The main electric field coupling region formed between the first inner conductor structure 41 and the second inner conductor structure 42 is located inside the enclosed functional cavity 20, and the solid material of the packaging body 10 does not constitute part of the main electric field coupling region.

[0059] For example, the first external electrode 31 and the second external electrode 32 may be disposed on the outside of the closed functional cavity 20 and disposed opposite to each other along the length or width direction of the encapsulation body 10.

[0060] Reference Figure 15 As shown, existing technologies use two or more printed circuit boards stacked together, with an insulating frame between the boards to form an internal cavity structure, and physical interfaces and alignment structures between the layers. In contrast, this embodiment uses a single, integrally molded packaging body 10, within which a closed functional cavity 20 is formed. The packaging body 10 has a continuous substrate structure, with no multi-board stack interfaces inside, and the closed functional cavity 20 is completely enclosed by the packaging body 10.

[0061] Reference Figure 3 , Figure 5 As shown, the shaded area represents the overlapping area S of the projections of the first inner conductor structure 41 and the second inner conductor structure 42.

[0062] Reference Figure 3 , Figure 4 , Figure 6 As shown, the longitudinal spacing d between the first inner conductor structure 41 and the second inner conductor structure 42, and their relative positional relationship within the enclosed functional cavity 20.

[0063] Reference Figure 7 The diagram shows the overall dimensions of the encapsulation body 10 and the relative proportions between the encapsulated functional cavity 20 and the encapsulation body 10. The external dimensions of the encapsulation body 10 satisfy the following: length L not greater than 1.0 mm; width W not greater than 0.6 mm; thickness T not greater than 0.4 mm.

[0064] Preferably, the encapsulation body 10 has a length L of 0.4 mm to 0.8 mm, a width W of 0.2 mm to 0.4 mm, and a thickness T of 0.15 mm to 0.3 mm.

[0065] Within the aforementioned sub-millimeter size range, traditional multilayer printed circuit board stack-up structures struggle to form stable, enclosed cavities. This invention achieves internal space integration through a single-unit packaging structure.

[0066] Specifically, the dimension of the enclosed functional cavity 20 in the length direction of the encapsulation body 10 is not less than 30% of the length of the encapsulation body 10; the dimension of the enclosed functional cavity 20 in the width direction of the encapsulation body 10 is not less than 20% of the width of the encapsulation body 10.

[0067] Through the above proportional design, the enclosed functional cavity 20 forms a stable low-dielectric internal space while ensuring the structural strength of the encapsulation body 10, and the main electric field coupling region is stably distributed within the range of the enclosed functional cavity 20.

[0068] Furthermore, the volume of the functional cavity accounts for 15% to 60% of the total volume of the encapsulation body 10 because: When the volume ratio of the enclosed functional cavity 20 is less than 15%, the low dielectric space is insufficient to cover the main electric field coupling region, and the effect of reducing parasitic capacitance is limited. When the volume ratio of the enclosed functional cavity 20 is greater than 60%, the effective wall thickness of the encapsulation body 10 decreases, which may cause microscopic deformation and change in the spacing between the inner conductors, thereby affecting the stability of electrical performance.

[0069] Therefore, the volume ratio of the enclosed functional cavity 20 is limited to the range of 15% to 60% in order to balance structural stability and electrical performance stability under sub-millimeter package size conditions.

[0070] Specifically, the minimum spacing between the first inner conductor structure 41 and the second inner conductor structure 42 is not less than 20% of the width of the package body 10. Furthermore, by limiting the first inner conductor structure 41 and the second inner conductor structure 42 to be arranged opposite each other in the functional cavity, the projected overlap area S of the two in the direction perpendicular to the package length satisfies: S ≤ 0.03 mm². By controlling the projected overlap area and the relative spacing, the spatial range of the main electric field coupling region can be limited, thereby reducing parasitic coupling and reducing parasitic capacitance.

[0071] Preferably, the relative positional deviation Δd between the first inner conductor structure 41 and the second inner conductor structure 42 is no greater than ±0.01mm, so as to ensure the stability of the overlapping area and spacing.

[0072] Specifically, the enclosed functional cavity 20 can be used to accommodate micro-semiconductor functional units, fill with low-dielectric materials, and remain empty to form a low-dielectric space.

[0073] The size of the semiconductor functional unit is preferably no greater than 0.25 mm × 0.15 mm.

[0074] The semiconductor functional unit may be a transient voltage suppression unit, a diode unit, a thyristor unit, or other semiconductor protection functional units.

[0075] With the above structural configuration, the enclosed functional cavity 20 can serve as a configurable internal functional space for the package to adapt to different types of protection functional units or media states, thereby giving the package structure scalable package platform attributes.

[0076] Specifically, the medium state inside the enclosed functional cavity 20 is any one or a combination of the following: Air; Dielectric materials with a dielectric constant not greater than 2.5; Low-pressure sealed cavity; A sealed cavity filled with inert gas.

[0077] Preferably, the dielectric constant of the medium inside the enclosed functional cavity 20 is lower than that of the material of the encapsulation body 10, so that the main electric field coupling region is preferentially distributed inside the enclosed functional cavity 20, thereby further reducing the parasitic coupling strength.

[0078] The encapsulation body 10 is formed of silicon-based material, ceramic-based material, or polymer encapsulation material. Preferably, the dielectric constant of the encapsulation body 10 material is higher than the dielectric constant of the medium inside the closed functional cavity 20, so that the main electric field coupling region is preferentially distributed inside the closed functional cavity 20, thereby reducing parasitic coupling formed through the encapsulation body 10 material.

[0079] It should be noted that the encapsulation structure maintains structural integrity and stable electrical performance within a temperature range of -40℃ to 150℃, making it suitable for automotive electronic system environments. Under temperature cycling, thermal shock, or high temperature and humidity conditions, the relative positions of the enclosed functional cavity 20 structure and the first inner conductor structure 41 and the second inner conductor structure 42 remain stable, thereby maintaining the stability of parasitic capacitance parameters.

[0080] Specifically, the encapsulation body 10 is provided with at least one micro process release hole 101, the micro process release hole 101 having a diameter of no more than 0.05 mm, and the micro process release hole 101 being sealed by a sealing structure 102.

[0081] It should be noted that the volume ratio of the enclosed functional cavity 20, the projected overlap area of ​​the first inner conductor structure 41 and the second inner conductor structure 42, and the path of the monolithic integrated packaging structure all affect the electric field distribution and parasitic coupling path inside the packaging structure.

[0082] Since the main electric field coupling region formed between the first inner conductor structure 41 and the second inner conductor structure 42 is located inside the closed functional cavity 20 with a low dielectric constant, the electric field flux is mainly distributed in the region of the closed functional cavity 20, thereby reducing the electric field flux through the high dielectric material region of the encapsulation body 10 and weakening the electric displacement flux and parasitic coupling strength formed through the high dielectric material region.

[0083] With the synergistic effect of the above structural elements, the package structure can achieve a low equivalent capacitance level under 1 MHz test conditions, preferably no more than 0.1 pF.

[0084] Therefore, the low parasitic coupling characteristic is not directly generated by a single size reduction or material replacement, but through the synergistic effect of the volume ratio of the closed functional cavity 20, the geometric relationship between the first inner conductor structure 41 and the second inner conductor structure 42, and the monolithic integrated packaging structure path, the main electric field coupling region inside the package is spatially separated from the high dielectric packaging body 10 material, thereby improving the parasitic coupling characteristics and obtaining a lower parasitic capacitance level under sub-millimeter package size conditions.

[0085] Figure 8 This diagram illustrates the relationship between the volume ratio of the enclosed functional cavity 20 and its equivalent capacitance in this invention. By obtaining different equivalent capacitance test data under different functional cavity volume ratios, a curve showing the relationship between capacitance and cavity volume ratio is formed. Figure 8 The horizontal axis represents the proportion of the volume of the enclosed functional cavity 20 to the total volume of the package body 10, and the vertical axis represents the equivalent capacitance value measured under 1 MHz test conditions.

[0086] Figure 9 This is a schematic diagram of the electric field distribution in the enclosed functional cavity 20 of the present invention. Figure 9 The electric field flux is mainly distributed inside the enclosed functional cavity 20. Figure 9 It can demonstrate the spatial constraint relationship of the electric field distribution path between the first inner conductor structure 41 and the second inner conductor structure 42 by the closed functional cavity 20.

[0087] Depend on Figure 9 It is understood that the first inner conductor structure 41 and the second inner conductor structure 42 are disposed inside the enclosed functional cavity 20 and are arranged opposite to each other, forming a main electric field coupling region between them. The main electric field coupling region is located within the internal space of the enclosed functional cavity 20 and is spatially separated from the solid material region of the encapsulation body 10.

[0088] Figure 10 This is a schematic diagram of the structural state of the encapsulation body 10 when the functional cavity volume accounts for a high proportion (more than 60%). Figure 10 This shows the state in which the longitudinal spacing d between the first inner conductor structure 41 and the second inner conductor structure 42 changes. It is used to illustrate the structural relationship between the volume ratio of the enclosed functional cavity 20 and the wall thickness of the package body 10 and the relative positions of the inner conductors.

[0089] Depend on Figure 10 It can be seen that when the proportion of the enclosed functional cavity 20 inside the encapsulation body 10 increases, the thickness of the side wall and top wall of the encapsulation body 10 decreases accordingly.

[0090] Under the influence of material curing shrinkage or external mechanical stress, the encapsulation body 10 may deform, thereby affecting the relative positional relationship between the first inner conductor structure 41 and the second inner conductor structure 42.

[0091] Example 2 This embodiment provides a method for manufacturing a miniature single-unit packaged electronic protection structure, including: S1. Basic Construction: A first inner conductor structure 41 and its lead-out connection structure are formed on a temporary base or supporting substrate 103; (Refer to...) Figure 11 As shown; S2. Temporary Support Structure: A temporary support structure 104 of predetermined volume is formed above the first inner conductor structure 41 through mold prefabrication, micromachining, or sacrificial layer construction processes. The volume of the temporary support structure 104 corresponds to the volume ratio of the subsequently formed closed functional cavity 20; refer to Figure 12 As shown; S3. Conductor alignment: A second inner conductor structure 42 is formed above the temporary support structure 104, and the overlapping area of ​​the projection of the first inner conductor structure 41 and the second inner conductor structure 42 in the direction perpendicular to the package length is controlled to be no more than 0.03 mm². S4. Integrated Packaging: A continuous single-unit packaging body 10 is formed using molding or integral molding processes, so that the first inner conductor structure 41, the second inner conductor structure 42, and the temporary support structure 104 are encapsulated inside the packaging body 10; Refer to Figure 13 As shown; S5. Cavity Formation: By forming a micro-process release hole 101 on the encapsulation body 10, the temporary support structure 104 is removed to form a closed functional cavity 20; see reference Figure 14 As shown; S6. Electrode integration: A first external electrode 31 and a second external electrode 32 are formed on the encapsulation body 10, and the first inner conductor structure 41 and the second inner conductor structure 42 are electrically connected to the first external electrode 31 and the second external electrode 32, respectively. S7. Environmental sealing: The micro-process release hole 101 is sealed to form a sealed microenvironment in the closed functional cavity 20.

[0092] The above manufacturing method, through the steps of forming a single-unit package body 10, forming a closed functional cavity 20 inside the package body 10, forming a first inner conductor structure 41 and a second inner conductor structure 42, forming a first outer electrode 31 and a second outer electrode 32, and sealing the package body 10, can form the closed functional cavity 20 inside the single-unit package body 10 without the need for multilayer printed circuit board stack alignment or board-level frame sandwich structure.

[0093] The above manufacturing method enables the enclosed functional cavity 20 to be formed in situ inside the monolithic package body 10; it does not rely on multilayer printed circuit board stack alignment or board-level frame sandwich structure; the relative positions of the first inner conductor structure 41 and the second inner conductor structure 42 are kept stable by the support structure before the sacrificial layer is removed, thereby maintaining the stability of the projected overlap area and the relative spacing.

[0094] Using the above manufacturing method, a monolithically formed closed functional cavity 20 structure can be formed under sub-millimeter package size conditions, so that the main electric field coupling region between the first inner conductor structure 41 and the second inner conductor structure 42 is located inside the closed functional cavity 20, thereby reducing parasitic coupling and realizing a package structure with low parasitic capacitance.

[0095] By using the above manufacturing method, the enclosed functional cavity 20 covers the main electric field coupling region between the first inner conductor structure 41 and the second inner conductor structure 42 inside the encapsulation body 10, thereby preferentially distributing the main electric field coupling region inside the enclosed functional cavity 20 and reducing the parasitic coupling strength.

[0096] Example 3: Low-dielectric cavity structure example like Figures 1 to 3 As shown, this embodiment provides a miniature single-unit packaged electronic protection structure. The package body 10 is formed using a single-unit integral molding structure, and its external dimensions are: length 0.8 mm; width 0.4 mm; thickness 0.3 mm.

[0097] A closed functional cavity 20 is formed inside the packaging body 10. The closed functional cavity 20 is completely enclosed by the packaging body 10 and does not penetrate the side wall of the packaging body 10.

[0098] In this embodiment: The volume of the functional cavity accounts for approximately 30% of the total volume of the package body; The first inner conductor structure 41 and the second inner conductor structure 42 are disposed inside the functional cavity and are arranged opposite to each other. The projected overlap area S of the two along the length of the package is approximately 0.025 mm². The main electric field coupling region formed between the first inner conductor structure 41 and the second inner conductor structure 42 is located inside the enclosed functional cavity 20. The interior of the enclosed functional cavity 20 is maintained as an air structure to form a low-dielectric internal space.

[0099] The equivalent capacitance of this package structure was measured to be approximately 0.085 pF under 1 MHz testing conditions.

[0100] This embodiment demonstrates that when the volume ratio of the enclosed functional cavity 20 is within a preferred range, the encapsulation structure can achieve a low level of parasitic capacitance.

[0101] Example 4: Example of Built-in Microsemiconductor Unit Based on the structure of Embodiment 3, this embodiment provides a micro-semiconductor functional unit inside the enclosed functional cavity 20.

[0102] The size of the semiconductor unit is 0.2 mm × 0.1 mm.

[0103] The semiconductor functional unit is disposed between the first inner conductor structure 41 and the second inner conductor structure 42 in a flip-chip configuration, and is electrically connected to the first inner conductor structure 41 and the second inner conductor structure 42 respectively.

[0104] The semiconductor functional unit occupies part of the functional cavity space, and the main electric field coupling region formed between the first inner conductor structure 41 and the second inner conductor structure 42 is still located inside the closed functional cavity 20.

[0105] The equivalent capacitance of this package structure remained below 0.09 pF under 1 MHz testing conditions.

[0106] This embodiment demonstrates that the packaging structure can still maintain a low level of parasitic capacitance when a micro-semiconductor functional unit is disposed within a closed functional cavity 20.

[0107] Example 5: Low Dielectric Filler Material Example Based on the structure of Example 3, this embodiment fills the enclosed functional cavity 20 with a low dielectric material with a dielectric constant of no more than 2.5.

[0108] Specifically, the low-dielectric material is a low-dielectric polymer material with a dielectric constant of approximately 2.2.

[0109] After filling, the projected overlap area of ​​the first inner conductor structure 41 and the second inner conductor structure 42 remains unchanged; The main electric field coupling region formed between the first inner conductor structure 41 and the second inner conductor structure 42 is still located inside the closed functional cavity 20.

[0110] The equivalent capacitance of this package structure was measured to be approximately 0.095 pF under 1 MHz testing conditions.

[0111] This embodiment demonstrates that the packaging structure can still achieve a low level of parasitic capacitance even when the functional cavity is filled with a low-dielectric material.

[0112] Example 6: Automotive-grade reliability example This embodiment performs vehicle environment reliability testing on the structure of Embodiment 3, including: Temperature cycling test (-40℃ to 150℃); Thermal shock test; High temperature and high humidity aging test.

[0113] After the above tests, the following was observed: The structure of the enclosed functional cavity 20 remains intact; The relative positional deviation Δd between the first inner conductor structure 41 and the second inner conductor structure 42 did not change significantly. Under 1 MHz testing conditions, the equivalent capacitance change is less than 5%.

[0114] This embodiment demonstrates that the packaging structure can maintain structural stability and electrical performance stability under automotive environment conditions.

[0115] Example 7: Experimental Example of the Relationship between Cavity Volume Ratio and Capacitance To illustrate the relationship between the volume ratio of functional cavities and the electrical performance of the packaging structure, this embodiment prepared multiple sets of packaging structure samples for comparative testing.

[0116] The outer dimensions of the main packaging body 10 of each group of samples are uniform: 0.8 mm × 0.4 mm × 0.3 mm.

[0117] The overlapping area of ​​the first inner conductor structure 41 and the second inner conductor structure 42 in the direction perpendicular to the package length is controlled to be approximately 0.025 mm².

[0118] While maintaining the basic consistency of the outer dimensions and geometric relationship of the inner conductor structure of the encapsulation body 10, only the proportion of the volume of the encapsulated functional cavity 20 to the total volume of the encapsulation body 10 is adjusted, which are 0%, 5%, 10%, 15%, 30%, 60%, and 70%, respectively.

[0119] The equivalent capacitance of each sample was measured under 1 MHz test conditions, and the test results are shown in Table 1.

[0120] Table 1: Equivalent capacitance test results cavity proportion Equivalent capacitance 0% 0.18 pF 5% 0.17 pF 10% 0.15 pF 15% 0.10 pF 30% 0.085 pF 60% 0.09 pF 70% 0.14 pF

[0121] The test results above show that: When the functional cavity volume accounts for less than about 15%, the equivalent capacitance shows a slow decreasing trend as the cavity volume increases. When the volume ratio of the functional cavity is in the range of approximately 15% to 60%, the equivalent capacitance is significantly reduced and remains in a low range. When the volume of the functional cavity exceeds approximately 60%, the equivalent capacitance increases as the effective wall thickness of the package body 10 decreases.

[0122] This embodiment demonstrates a correspondence between the volume ratio of the functional cavity and the equivalent capacitance of the packaging structure, and a low level of parasitic capacitance can be obtained within the specified ratio range.

[0123] In summary, this invention, through the coordinated design of the internal structure, functional cavity ratio, and internal conductor geometry of the single-unit package body 10, enables the package structure to form a stable closed functional space under sub-millimeter size conditions, and reduces parasitic coupling and parasitic capacitance.

[0124] Unlike traditional filler-type packaging or multilayer printed circuit board stack-up structures, the present invention forms a closed functional cavity 20 completely enclosed by the packaging body 10 inside the monolithic molded packaging body 10, so that the main electric field coupling region formed between the first inner conductor structure 41 and the second inner conductor structure 42 is located inside the closed functional cavity 20.

[0125] Since the interior of the functional cavity is a low-dielectric space or a low-dielectric material region, the electric field flux is mainly distributed in the low-dielectric functional cavity region, thereby reducing the electric displacement flux through the encapsulation body 10 material and reducing the degree of parasitic coupling.

[0126] By limiting: The volume of the functional cavity accounts for 15% to 60% of the total volume of the encapsulation body 10; The projected overlap area of ​​the first inner conductor structure 41 and the second inner conductor structure 42 is no greater than 0.03 mm². The relative positions between the first inner conductor structure 41 and the second inner conductor structure 42 are stable; By geometrically constraining the main electric field coupling region and charge induction region, the equivalent capacitance of the package structure can be controlled to below 0.1 pF under 1 MHz test conditions.

[0127] When the functional cavity volume accounts for more than approximately 60%, the equivalent capacitance tends to increase as the effective wall thickness of the package body 10 decreases. By limiting the functional cavity volume to the range of 15% to 60%, a good balance can be achieved between package structure stability and electrical performance.

[0128] Therefore, this invention achieves a stable correspondence between low parasitic capacitance characteristics and packaging structure through structural proportion design and control of internal conductor geometry, rather than simply by reducing size or replacing materials.

[0129] Compared with existing technologies that use multilayer printed circuit board stacked structures or filled packaging structures to form cavities, the present invention differs in terms of structural hierarchy, spatial configuration, electric field path control method, and the relationship between structure and electrical performance.

[0130] (a) Different structural levels.

[0131] Existing cavity structures typically consist of two or more stacked printed circuit boards with an insulating frame or spacer layer between them. These structures rely on board-level stack alignment, and structural interfaces exist between the layers.

[0132] The present invention employs a single-unit, one-piece molded packaging body 10, within which a closed functional cavity 20 is formed. The closed functional cavity 20 is completely enclosed by the packaging body 10 and is located inside the packaging body 10.

[0133] Therefore, the packaging structure described in this invention is a single-unit packaging structure, and its internal functional cavity is formed by the single-unit packaging body 10, which is different from the structure that forms a cavity by using a board-level stacking method in terms of structural hierarchy.

[0134] (ii) The size implementation paths are different.

[0135] Existing multilayer printed circuit board stack-up structures are typically suitable for package structures in the millimeter range or larger. As package sizes are further reduced to below approximately 1.0 mm, the manufacturing difficulty of board-level stack-up alignment and frame molding increases accordingly.

[0136] Under the condition of a package size with a length not exceeding 1.0 mm, the present invention achieves internal space integration and structural stability of the package by forming a closed functional cavity 20 inside the single package body 10.

[0137] Therefore, the packaging structure described in this invention is a micro-packaging structure formed under different structural implementation paths, and it differs from the structure that forms a cavity through board-level stacking in terms of size implementation.

[0138] (iii) The cavity is constructed differently.

[0139] Existing cavity structures are typically formed by plate-level enclosure or frame enclosure, and the cavity boundary is formed by the combination of multiple components.

[0140] The closed functional cavity 20 of the present invention is formed by the material of the single-unit packaging body 10 and is located inside the packaging body 10. The closed functional cavity 20 does not penetrate the side wall of the packaging body 10.

[0141] Therefore, the enclosed functional cavity 20 of the present invention is integrally formed by a single encapsulated body 10, which differs in spatial configuration from the structure formed by enclosing a cavity through multiple components.

[0142] (iv) Different electric field path control methods.

[0143] In the prior art, cavity structures are mostly used to reduce the overall equivalent dielectric constant of the package or to realize the internal space setting. They usually do not clearly define the distribution relationship of the electric field coupling path between the inner conductors in the internal space of the package, and rarely control the parasitic coupling region through the coordinated design of conductor geometry and cavity ratio.

[0144] This invention defines the internal spatial structure and geometric relationship of the inner conductor of the encapsulation body 10, including: The volume of the functional cavity accounts for 15% to 60% of the total volume of the encapsulation body 10; The projected overlap area between the first inner conductor structure 41 and the second inner conductor structure 42 is no greater than 0.03 mm². The main electric field coupling region formed between the first inner conductor structure 41 and the second inner conductor structure 42 is located inside the closed functional cavity 20; By defining the structure as described above, the main electric field coupling region is located inside the low-dielectric functional cavity and is spatially separated from the packaging body 10 material, thereby reducing the degree of parasitic coupling and obtaining a lower equivalent capacitance level.

[0145] Therefore, this invention achieves low parasitic capacitance characteristics under sub-millimeter package size conditions by coordinating the design of the internal spatial structure and conductor geometry to spatially constrain the electric field coupling path.

[0146] (v) Structure-performance relationship.

[0147] Existing technologies typically do not establish a correspondence between cavity proportions, conductor geometry, and electrical properties.

[0148] This invention has been verified through experiments: When the functional cavity volume accounts for a relatively small proportion, the equivalent capacitance decreases as the cavity volume increases, but the change is relatively limited. When the volume ratio of the functional cavity is in the range of approximately 15% to 60%, the equivalent capacitance is significantly reduced and remains in a low range. As the volume ratio of the functional cavity further increases, the equivalent capacitance shows an upward trend.

[0149] The above results show that, within a certain range, there is a corresponding relationship between the volume ratio of the functional cavity and the electrical performance of the package structure. By synergistically limiting the volume ratio of the functional cavity and the geometric relationship of the inner conductor, a low level of parasitic capacitance can be obtained under sub-millimeter package size conditions.

[0150] Therefore, by structurally defining the internal space ratio and conductor geometry of the package, this invention enables the package structure to achieve low parasitic capacitance characteristics while maintaining miniaturization. (vi) Different functional platform attributes.

[0151] Existing cavity structures are typically designed for specific applications.

[0152] The enclosed functional cavity 20 of the present invention can be used for: Contains a miniature semiconductor protection unit; Filled with low dielectric material; Alternatively, it can remain empty to form a low-dielectric space.

[0153] Therefore, the packaging structure of the present invention has a certain degree of configuration flexibility in different application scenarios and can be applied to different types of protection function units.

[0154] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A miniature single-unit packaged electronic protection structure, characterized in that, include: The encapsulation body (10) is a continuous dielectric integral molding structure and is not formed by stacking two or more printed circuit boards; A closed functional cavity (20) is disposed inside the packaging body (10). The closed functional cavity (20) is formed entirely by the material of the packaging body (10) and does not penetrate any outer wall of the packaging body (10). A semiconductor functional unit is disposed inside it. The first inner conductor structure (41) and the second inner conductor structure (42) are disposed inside the closed functional cavity (20) and are disposed opposite to each other, and there is a predetermined distance between them; The first external electrode (31) and the second external electrode (32) are respectively disposed on the outer surface of the encapsulation body (10) and are electrically connected to the first inner conductor structure (41) and the second inner conductor structure (42) to form a continuous conductive path; in, The main electric field coupling region formed between the first inner conductor structure (41) and the second inner conductor structure (42) is located entirely within the internal space of the closed functional cavity (20), and is spatially separated from the solid material region of the encapsulation body (10); The volume of the enclosed functional cavity (20) accounts for 15% to 60% of the total volume of the encapsulation body (10); The projected overlap area S of the first inner conductor structure (41) and the second inner conductor structure (42) in the direction perpendicular to the package length is not greater than 0.03 mm².

2. The miniature single-unit packaged electronic protection structure according to claim 1, characterized in that, The external dimensions of the encapsulation body (10) meet the following requirements: length not greater than 1.0 mm; width not greater than 0.6 mm; The thickness is no more than 0.4mm.

3. The miniature single-unit packaged electronic protection structure according to claim 1, characterized in that, The encapsulation body (10) has a length of 0.4 mm to 0.8 mm, a width of 0.2 mm to 0.4 mm, and a thickness of 0.15 mm to 0.3 mm.

4. The miniature single-unit packaged electronic protection structure according to claim 1, characterized in that, The dimension of the enclosed functional cavity (20) in the length direction of the encapsulation body (10) is not less than 30% of the length of the encapsulation body (10); the dimension of the enclosed functional cavity (20) in the width direction of the encapsulation body (10) is not less than 20% of the width of the encapsulation body (10).

5. The miniature single-unit packaged electronic protection structure according to claim 1, characterized in that, The minimum spacing between the first inner conductor structure (41) and the second inner conductor structure (42) is not less than 20% of the width of the encapsulation body (10); the relative positional deviation Δd between the first inner conductor structure (41) and the second inner conductor structure (42) is not greater than ±0.01mm.

6. The miniature single-unit packaged electronic protection structure according to claim 1, characterized in that, The semiconductor functional unit is a transient voltage suppression unit, a diode unit, or a thyristor unit; the size of the semiconductor functional unit is no greater than 0.25mm × 0.15mm.

7. The miniature single-unit packaged electronic protection structure according to claim 1, characterized in that, The medium state inside the closed functional cavity (20) is any one or a combination of the following: Air; Dielectric materials with a dielectric constant not greater than 2.5; Low-pressure sealed cavity; A sealed cavity filled with inert gas.

8. The miniature single-unit packaged electronic protection structure according to claim 1, characterized in that, The dielectric constant of the medium inside the enclosed functional cavity (20) is lower than the dielectric constant of the encapsulation body (10) material; the encapsulation body (10) is formed of silicon-based material, ceramic-based material or polymer encapsulation material.

9. The miniature single-unit packaged electronic protection structure according to claim 1, characterized in that, The encapsulation body (10) is provided with at least one micro process release hole (101), the diameter of the micro process release hole (101) is no greater than 0.05 mm, and the micro process release hole (101) is sealed by a sealing structure (102).

10. A method for manufacturing a miniature single-unit packaged electronic protection structure for an automotive electronic system according to any one of claims 1-9, characterized in that, include: S1, Basic construction: A first inner conductor structure (41) and its lead-out connection structure are formed on a temporary base or supporting substrate (103); S2, Temporary support structure: A temporary support structure (104) is formed above the first inner conductor structure (41) by mold prefabrication, micromachining or sacrificial layer construction process, and the volume of the temporary support structure (104) corresponds to the volume ratio of the subsequently formed closed functional cavity (20); S3, Conductor alignment: A second inner conductor structure (42) is formed above the temporary support structure (104), and the overlapping area of ​​the projection of the first inner conductor structure (41) and the second inner conductor structure (42) in the direction perpendicular to the package length is controlled to be no more than 0.03 mm². S4. Integrated packaging: A single-unit packaging body (10) with continuous medium is formed by molding or integral molding process, so that the first inner conductor structure (41), the second inner conductor structure (42) and the temporary support structure (104) are covered inside the packaging body (10); S5. Cavity formation: A micro-process release hole (101) is formed on the encapsulation body (10), and the temporary support structure (104) is removed to form a closed functional cavity (20) in situ inside the encapsulation body (10). S6. Electrode integration: A first external electrode (31) and a second external electrode (32) are formed on the encapsulation body (10), and the first inner conductor structure (41) and the second inner conductor structure (42) are electrically connected to the first external electrode (31) and the second external electrode (32) respectively. S7. Environmental sealing: The micro-process release hole (101) is sealed to form a sealed low-dielectric microenvironment in the closed functional cavity (20).

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