Voltage measuring circuit

Abstract

A voltage measurement circuit (23) is provided with: a first switched capacitor filter (9) connected to a first cell (C2) constituting a battery pack (50); a second switched capacitor filter (10) connected to a second cell (C3) constituting the battery pack (50); and a first amplifier (19) shared by the first switched capacitor filter (9) and the second switched capacitor filter (10), the first switched capacitor filter (9) comprising a first switch group (3), a first capacitor (5) and a third switch group (4), and the second switched capacitor filter (10) comprising a second switch group (6), a second capacitor (8) and a fourth switch group (7), the first switching group (3) and the second switching group (6) are electrically insulated from the third switching group (4) and the fourth switching group (7) by the first capacitor (5) and the second capacitor (8), respectively.

Description

Technical Field

[0001] This disclosure relates to voltage measurement circuits, and more particularly to voltage measurement circuits for measuring the voltage of cells in a battery pack consisting of multiple cells connected in series. Background Technology

[0002] Lithium-ion batteries or lithium-ion capacitors, as high-energy-density secondary batteries, are used in a variety of applications. They are particularly useful in applications requiring large capacity, such as electric vehicles or ESS (Energy Storage Systems), where they are used as lithium-ion battery packs composed of multiple cells connected in series or parallel.

[0003] Lithium-ion battery packs pose a risk of degradation due to over-discharge and overheating or explosion due to overcharging. Therefore, a battery management system (BMS) is indispensable in lithium-ion battery packs to measure the output voltage of each cell and control charging and discharging to prevent over-discharge or overcharging. Furthermore, the BMS estimates the state of charge (SOC) of each cell by measuring its output voltage, thus requiring high-precision voltage measurement.

[0004] Therefore, the following technology has been proposed: to incorporate a voltage measurement circuit, such as an analog-to-digital converter, into the battery management system so as to be able to measure the output voltage of each cell in the battery pack (see, for example, Patent Document 1 and Patent Document 2).

[0005] In the technology of Patent Document 1, each cell in a series-connected battery pack is connected to an analog-to-digital converter via a multiplexer for selecting the positive and negative terminals, and measurements are performed sequentially by the analog-to-digital converter while switching the cells. This method will be referred to hereafter as the multiplexing method. However, in the multiplexing method of Patent Document 1, since voltage measurements are performed by an analog-to-digital converter while sequentially switching the series-connected cells, there is a problem that the period for measuring the voltage of all cells becomes longer.

[0006] Furthermore, in the technology of Patent Document 2, multiple analog-to-digital converters are used for measurement, and these multiple analog-to-digital converters are connected in pairs with each cell in the series-connected battery pack. Hereinafter, this method will be referred to as the parallel method. According to the parallel method of Patent Document 2, since the output voltage of each cell in the series-connected battery pack can be measured simultaneously, the voltage measurement cycle of the cells can be shortened.

[0007] Furthermore, electric vehicle motors attempt to achieve high-speed rotation by increasing the gear ratio, thereby miniaturizing the motor. The current flowing through the lithium-ion battery pack connected to the motor fluctuates rapidly due to the high-speed rotation of the motor. Since the output voltage of each cell is the sum of the voltage generated by the battery's internal impedance and the current flowing through the battery pack, plus the cell's open-circuit voltage (OCV), the rapidly changing current causes the output voltage of each cell to fluctuate rapidly.

[0008] From this perspective, the multiplexing method in Patent Document 1 suffers from increased voltage measurement errors due to the measurement time difference between each cell. Therefore, for lithium-ion battery packs connected to high-speed rotating motors, the parallel method in Patent Document 2, which can simultaneously measure the output voltage of each cell, is ideal.

[0009] (Existing technical documents) (Patent Documents) Patent Document 1: International Publication No. 2019 / 044856 Patent Document 2: International Publication No. 2016 / 051684 Summary of the Invention

[0010] The problem that the invention aims to solve However, in the parallel approach of Patent Document 2, since the same number of analog-to-digital converters as the number of cells being measured are required, there is a problem of increased current consumption and mounting area of ​​the semiconductor device equipped with these converters.

[0011] The issue of current consumption will be explained in more detail below. In a typical battery management system, a semiconductor device measures the voltage of each cell in a series-connected battery pack consisting of 12 to 24 cells. Since a lithium-ion cell outputs approximately 3.7V, the total voltage of 24 cells in series is approximately 90V. In other words, the semiconductor device managing the 24 series-connected battery packs supplies power to the battery packs it manages, and therefore its power supply voltage is 90V.

[0012] On the other hand, one of the ΔΣ analog-to-digital converters, which is often used in battery management systems, consumes about 0.5 to 1.0 mA of current, so the power consumption of the semiconductor device is about 1 W according to the following formula.

[0013] 0.5mA × 24 units × 90V = 1080mW For semiconductor devices, the heat loss caused by a power consumption of 1W is unacceptable if it is only dissipated from the printed circuit board on which the semiconductor device is mounted. Therefore, special heat dissipation measures such as heat sinks are required.

[0014] Therefore, the purpose of this disclosure is to provide a voltage measurement circuit that operates faster than conventional multiplexing methods and is superior to conventional parallel methods in terms of current consumption and mounting area.

[0015] Methods for solving problems To address the aforementioned issues, one embodiment of this disclosure discloses a voltage measurement circuit for measuring the voltage of cells in a battery pack composed of multiple cells connected in series. The voltage measurement circuit includes: a first switched-capacitor filter whose input terminal is connected to a first cell constituting the battery pack; a second switched-capacitor filter whose input terminal is connected to either the first cell or a second cell constituting the battery pack; and a first amplifier whose input terminal is connected to the output terminals of both the first and second switched-capacitor filters. The first switched-capacitor filter includes a first switch group and a first capacitor. The input terminal of the first switch group is connected to the first cell, and the first capacitor is connected to the output terminal of the first switch group. The second switched-capacitor filter includes a second switch group and a second capacitor. The input terminal of the second switch group is connected to either the first or second cell, and the second capacitor is connected to the output terminal of the second switch group. The first and second switch groups are electrically insulated from the first amplifier via the first and second capacitors, respectively.

[0016] Invention Effects This disclosure provides a voltage measurement circuit that operates faster than conventional multiplexing methods and is superior to conventional parallel methods in terms of current consumption and mounting area. Attached Figure Description

[0017] Figure 1 This is a circuit block diagram showing a schematic configuration of the main parts of the voltage measurement circuit involved in the embodiment.

[0018] Figure 2A It is shown Figure 1 The circuit diagram shown is a detailed representation of the amplifier-shared analog-to-digital converter.

[0019] Figure 2B yes Figure 2A The timing diagram of the clock signal is shown.

[0020] Figure 3This is a block diagram showing the overall configuration of the voltage measurement circuit according to the embodiment.

[0021] Figure 4 This is a circuit block diagram showing a schematic configuration of the main parts of the voltage measurement circuit involved in the first variation of the embodiment.

[0022] Figure 5 This is a circuit block diagram showing a schematic configuration of the main parts of the voltage measurement circuit involved in the second variation of the embodiment.

[0023] Figure 6 This is a circuit diagram of an amplifier-shared analog-to-digital converter constituting a voltage measurement circuit, according to the third variation of the implementation.

[0024] Figure 7A This is a circuit diagram of an amplifier-shared analog-to-digital converter constituting a voltage measurement circuit, according to the fourth variation of the implementation.

[0025] Figure 7B yes Figure 7A The timing diagram of the clock signal is shown.

[0026] Figure 8A This is a circuit diagram of an amplifier-shared analog-to-digital converter constituting a voltage measurement circuit, according to the fifth variation of the implementation.

[0027] Figure 8B yes Figure 8A An example of a timing diagram for a clock signal is shown.

[0028] Figure 8C yes Figure 8A Another example of a timing diagram for a clock signal is shown. Detailed Implementation

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the embodiments described below are all specific examples of this disclosure. The values, circuits, circuit components, connection configurations of circuit components, signals, signal timing, and waveforms shown in the following embodiments are all illustrative and are not intended to limit this disclosure. Furthermore, the figures are not necessarily strictly drawn. In the figures, circuit components that have substantially the same function and type are given the same symbols, and repeated descriptions are omitted or simplified. Additionally, "A connected to B" means that A and B are electrically connected, including not only the case of a direct connection between A and B, but also the case of an indirect connection between A and B through other circuit elements.

[0030] Figure 1This is a circuit block diagram showing a schematic configuration of the main parts of the voltage measurement circuit 23 according to the embodiment. In this figure, an amplifier-shared analog-to-digital converter 21a is shown, which measures the voltage of cell C2 and cell C3 constituting the battery pack 50; and an amplifier-shared analog-to-digital converter 21b is shown, which measures the voltage of cell C6 and cell C7 constituting the battery pack 50. It should be noted that the voltage measurement circuit 23 is a semiconductor device implemented as an integrated circuit, which may include not only the two amplifier-shared analog-to-digital converters 21a and 21b, but also a number of amplifier-shared analog-to-digital converters sufficient to measure the voltage of all the cells constituting the battery pack 50. Furthermore, Figure 1 The main parts of voltage measurement circuit 23 are shown. For an overview and more detailed description of the voltage measurement circuit 23, please refer to [link / reference]. Figure 3 This will be explained later.

[0031] The battery pack 50 is a battery pack composed of multiple battery cells C1 to C7 connected in series, for example, a battery pack with 24 cells connected in series. The battery cells C1 to C7 are, for example, lithium-ion battery cells or lithium-ion batteries.

[0032] The amplifier-shared analog-to-digital converter 21a is a second-order ΔΣ modulator that modulates the voltages of the two cells C2 and C3 into pulse densities. It also includes a first switched-capacitor filter 9, a second switched-capacitor filter 10, a third switched-capacitor filter 11, a fourth switched-capacitor filter 12, a fifth switched-capacitor filter 13, a sixth switched-capacitor filter 14, a seventh switched-capacitor filter 15, an eighth switched-capacitor filter 16, a first amplifier 19, a second amplifier 20, and a quantizer 17.

[0033] Among these components, the first switched-capacitor filter 9, the third switched-capacitor filter 11, the fifth switched-capacitor filter 13, and the seventh switched-capacitor filter 15 are dedicated circuit components for converting the voltage of cell C2 into a digital value; while the second switched-capacitor filter 10, the fourth switched-capacitor filter 12, the sixth switched-capacitor filter 14, and the eighth switched-capacitor filter 16 are dedicated circuit components for converting the voltage of cell C3 into a digital value; and the first amplifier 19, the second amplifier 20, and the quantizer 17 are circuit components that are shared in a time-division manner for converting the voltages of cells C2 and C3 into digital values.

[0034] The first switched-capacitor filter 9 is a circuit that samples the voltage of the first battery cell C2 (i.e., stores charge in the capacitor). It has a first input terminal 1 connected to both ends of the first battery cell C2 and includes: a first switch group 3, whose input terminal is connected to the first battery cell C2 for on / off switching; a third switch group 4, whose output terminal is connected to the input terminal of the first amplifier 19 for on / off switching; and a first capacitor 5 connected between the output terminal of the first switch group 3 and the input terminal of the third switch group 4. It should be noted that "input terminal" refers to the two terminals on the input side of each circuit: the terminal connected to the signal line transmitting the voltage of the high-potential terminal of the battery cell (i.e., the high-potential line terminal) and the terminal connected to the signal line transmitting the voltage of the low-potential terminal of the battery cell (i.e., the low-potential line terminal). Similarly, "output terminal" refers to the two terminals on the output side of each circuit: the terminal connected to the high-potential line of the battery cell and the terminal connected to the low-potential line of the battery cell.

[0035] The first switch group 3 includes: two switching elements SW1P, which respectively conduct (i.e., connect) the high-potential line and the low-potential line of the first battery cell C2 during a first period; and two switching elements SW1N, which respectively cross and conduct (i.e. connect) the high-potential line and the low-potential line of the first battery cell C2 during a second period. It should be noted that the first period and the second period will refer to... Figure 2B Let me explain in detail.

[0036] The third switch group 4 includes: a first digital-to-analog converter 40a, which performs digital-to-analog conversion using the output of the quantizer 17 as input and outputs the resulting analog voltage to the input terminal of the third switch group 4; two switching elements SW1N, which respectively turn on (i.e. connect) the high-potential line and low-potential line of the first cell C2 during the second period; and two switching elements SW1P, which connect the high-potential line and low-potential line of the first cell C2 to a reference voltage during the first period. It should be noted that, without feedback to the output of the quantizer 17, the third switch group 4 is not a necessary component of the first switched-capacitor filter 9.

[0037] Furthermore, in the symbol of the switching element (e.g., "SW1P"), the "1" or "2" following the symbol "SW" indicates measurement for the first cell C2 and the second cell C3, respectively, and the "P" or "N" following it indicates conduction (i.e., connection) during the first and second periods, respectively. The switching element is, for example, a MOSFET.

[0038] The second switched capacitor filter 10 is a circuit that samples the voltage of the second cell C3 (i.e., stores charge in the capacitor). It has a second input terminal 2 connected to both ends of the second cell C3 and includes: a second switch group 6 whose input terminal is connected to the second cell C3 for on / off switching; a fourth switch group 7 whose output terminal is connected to the input terminal of the first amplifier 19 for on / off switching; and a second capacitor 8 connected between the output terminal of the second switch group 6 and the input terminal of the fourth switch group 7.

[0039] The second switch group 6 includes: two switch elements SW2N, which respectively conduct (i.e. connect) the high-potential line and the low-potential line of the second cell C3 during the second period; and two switch elements SW2P, which respectively conduct (i.e. connect) the high-potential line and the low-potential line of the second cell C3 by crossing each other during the first period.

[0040] The fourth switch group 7 includes: a second digital-to-analog converter 40b, which performs digital-to-analog conversion using the output of quantizer 17 as input and outputs the resulting analog voltage to the input terminal of the fourth switch group 7; two switching elements SW2N, which respectively turn on (i.e. connect) the high-potential line and low-potential line of the second cell C3 during the second period; and two switching elements SW2P, which connect the high-potential line and low-potential line of the second cell C3 to the reference voltage during the first period. It should be noted that, without feedback to the output of quantizer 17, the fourth switch group 7 is not a necessary component of the second switched-capacitor filter 10.

[0041] The first amplifier 19 is a time-division multiplexed amplifier used to integrate the charge stored in the first switched capacitor filter 9 (strictly speaking, the first capacitor 5) and the charge stored in the second switched capacitor filter 10 (strictly speaking, the second capacitor 8).

[0042] The third switched capacitor filter 11 is connected between the input terminal and the output terminal of the first amplifier 19. It is a switched capacitor used to integrate the charge stored in the first switched capacitor filter 9 (strictly speaking, the first capacitor 5). It includes: a capacitor inserted into the high potential line of the first cell C2 and two switching elements SW1N that are turned on during the second period; and a capacitor inserted into the low potential line of the first cell C2 and two switching elements SW1N that are turned on during the second period.

[0043] The fourth switched capacitor filter 12 is connected between the input terminal and the output terminal of the first amplifier 19. It is a switched capacitor used to integrate the charge stored in the second switched capacitor filter 10 (strictly speaking, the second capacitor 8). It includes: a capacitor inserted into the high potential line of the second cell C3 and two switching elements SW2P that are turned on during the first period; and a capacitor inserted into the low potential line of the second cell C3 and two switching elements SW2P that are turned on during the first period.

[0044] The fifth switched capacitor filter 13 is a second-stage circuit that samples the voltage of the first cell C2 (i.e., stores charge in the capacitor), and includes: a capacitor inserted into the high-potential line of the first cell C2, two switching elements SW1P that connect the two ends of the capacitor to a reference voltage during a first period, and two switching elements SW1N that connect the capacitor to the high-potential line during a second period; and a capacitor inserted into the low-potential line of the first cell C2, two switching elements SW1P that connect the two ends of the capacitor to a reference voltage during a first period, and two switching elements SW1N that connect the capacitor to the low-potential line during a second period.

[0045] The sixth switched capacitor filter 14 is a second-stage circuit that samples the voltage of the second cell C3 (i.e., stores charge in the capacitor), and includes: a capacitor inserted into the high-potential line of the second cell C3, two switching elements SW2N connecting the two ends of the capacitor to a reference voltage during a second period, and two switching elements SW2P connecting the capacitor to the high-potential line during a first period; and a capacitor inserted into the low-potential line of the second cell C3, two switching elements SW2N connecting the two ends of the capacitor to a reference voltage during a second period, and two switching elements SW2P connecting the capacitor to the low-potential line during a first period.

[0046] The second amplifier 20 is a time-division multiplexed amplifier used to integrate the charge stored in the capacitor of the fifth switched capacitor filter 13 and the charge stored in the capacitor of the sixth switched capacitor filter 14.

[0047] The seventh switched capacitor filter 15 is connected between the input and output terminals of the second amplifier 20. It is a switched capacitor used to integrate the charge stored in the capacitor of the fifth switched capacitor filter 13. It includes: a capacitor inserted into the high potential line of the first cell C2 and two switching elements SW1N that are turned on during the second period; and a capacitor inserted into the low potential line of the first cell C2 and two switching elements SW1N that are turned on during the second period.

[0048] The eighth switched capacitor filter 16 is connected between the input terminal and the output terminal of the second amplifier 20. It is a switched capacitor used to integrate the charge stored in the capacitor of the sixth switched capacitor filter 14. It includes: a capacitor inserted into the high potential line of the second cell C3 and two switching elements SW2P that are turned on during the first period; and a capacitor inserted into the low potential line of the second cell C3 and two switching elements SW2P that are turned on during the first period.

[0049] The quantizer 17 is connected to the output terminals of the first amplifier 19 and the second amplifier 20. It is shared in a time-division multiplexing manner to quantize the voltages of the first battery cell C2 and the second battery cell C3. It compares the high-potential line voltages and low-potential line voltages of the output terminals of the first amplifier 19 and the second amplifier 20, and outputs a 1-bit analog-to-digital converter (ADC) of the comparison result from the output terminal 18. The quantizer includes: capacitors connected to the high-potential and low-potential lines of the output terminals of the first amplifier 19 and the second amplifier 20 respectively; switching elements SW1N and SW2P connected to the capacitors; and a reset switching element SWRST. It should be noted that in this example, the quantizer 17 is connected to the output terminals of both the first amplifier 19 and the second amplifier 20, but this connection configuration is not limited; it can be connected to the output terminal of at least the second amplifier 20.

[0050] In the amplifier-shared analog-to-digital converter 21a configured as described above, such as Figure 1 As shown, the first switch group 3 and the second switch group 6 are located in the high-voltage region 51, which is a circuit region that operates by receiving a first power supply voltage. Furthermore, the subsequent circuits after the third switch group 4 and the fourth switch group 7 are located in the low-voltage region 52, which is a circuit region that operates by receiving a second power supply voltage lower than the first power supply voltage. Here, the first power supply voltage, for example, for the first switch group 3, is the power supply voltage grounded at the low-potential terminal of the first battery cell C2, and for the second switch group 6, it is the power supply voltage grounded at the low-potential terminal of the second battery cell C3. Additionally, the second power supply voltage, for example, for the subsequent circuits after the third switch group 4 and the fourth switch group 7, is the power supply voltage grounded at the low-potential terminal of the battery pack 50.

[0051] This insulation configuration creates an amplifier-shared level shifter that uses a shared amplifier while shifting the output voltage of the first cell from the battery pack's voltage level to the integrated circuit's GND level and the output voltage of the second cell from the battery pack's voltage level to the integrated circuit's GND level.

[0052] It should be noted that, Figure 1 The amplifier-shared analog-to-digital converter 21b shown is a second-order ΔΣ modulator, which modulates the voltages of the two cells C6 and C7 into pulse densities and has the same configuration as the amplifier-shared analog-to-digital converter 21a.

[0053] Figure 2A It is shown Figure 1 The circuit diagram shown is a detailed configuration of the amplifier-shared analog-to-digital converter 21a. Figure 2B yes Figure 2A The timing diagram of the clock signals (Φ1, Φ1D, Φ2, Φ2D) is shown.

[0054] It should be noted that, in Figure 2A In the first input terminal 1, the input voltage Input A (5V) is input, which will... Figure 1 The low-potential terminal VI_NA of the first cell C2 is set to 95V, and the high-potential terminal VI_PA is set to 100V; and the input voltage Input B (5V) is input to the second input terminal 2, which will... Figure 1 The potential of the low-potential terminal VI_NB of the second cell C3 is set to 90V, and the potential of the high-potential terminal VI_PB is set to 95V.

[0055] In addition, Figure 2A In the middle, the reference voltage and its reference potential are... Figure 2A The symbols shown on the right (“VREF” and “VREF_N”, respectively) represent this.

[0056] In addition, Figure 2A In the diagram, clock signals (Φ1, Φ1D, Φ2, Φ2D) supplied to the switching elements are recorded at their adjacent locations. The timing of the clock signals (Φ1, Φ1D, Φ2, Φ2D) is as follows: Figure 2B As shown, the switching element is turned on during the Hi period. The period after combining the Hi period of clock signal Φ1 with the Hi period of clock signal Φ1D, which is its delayed signal, is called the "first period". The period after combining the Hi period of clock signal Φ2 with the Hi period of clock signal Φ2D, which is its delayed signal, is called the "second period".

[0057] exist Figure 2AIn the amplifier-shared analog-to-digital converter 21a, the integrator of the first stage used for voltage measurement of the first cell C2 (i.e., Input A) is labeled as the first integrator 30a, and the integrator of the second stage is labeled as the second integrator 31a. Similarly, the integrator of the first stage used for voltage measurement of the second cell C3 (i.e., Input B) is labeled as the first integrator 30b, and the integrator of the second stage is labeled as the second integrator 31b.

[0058] It should be noted that the first amplifier 19 in the first integrator 30a is also shared by the first integrator 30b. Similarly, the second amplifier 20 in the second integrator 31a is also shared by the second integrator 31b.

[0059] here, Figure 2A It was also shown Figure 1 The additional circuitry included in the amplifier-shared analog-to-digital converter 21a (not shown) is as follows. For example, the two DC shift circuits 32 constituting each of the first integrators 30a and 30b are circuits that subtract a fixed voltage (e.g., 2.5V) from the voltage of a cell that only takes positive voltage (0-5V here) to convert it into a differential signal (e.g., -2.5V to 2.5V). Furthermore, the two jitter circuits 33 constituting each of the second integrators 31a and 31b are circuits used to reduce the idle tone that is theoretically generated in the ΔΣ modulator according to this embodiment. Additionally, the two feedforward paths 34 constituting each of the quantizers 17a and 17b are constructed by... Figure 1 The circuit shown in the figure, consisting of switching elements SW1N and SW2P, is a CIFF (Cascaded Integrator Feed Forward) type feedforward path.

[0060] from Figure 2A and Figure 2B It can be seen that, Figure 2A The main operation of the amplifier-shared analog-to-digital converter 21a shown is as follows.

[0061] As a voltage measurement of the first cell C2 (i.e., Input A), in the first period (clock signal Φ1 or Φ1D is Hi), the voltage of the first cell C2 (i.e., Input A) is sampled by the first switched capacitor filter 9 (strictly speaking, the charge is stored in the first capacitor 5), and in the second period (clock signal Φ2 or Φ2D is Hi), the difference between the voltage sampled by the first switched capacitor filter 9 and the voltage obtained by digital-to-analog conversion based on the output of quantizer 17a is integrated by the first integrator 30a.

[0062] Furthermore, in the subsequent first period (clock signal Φ1 or Φ1D is Hi), the value integrated by the first integrator 30a is sampled by the fifth switched capacitor filter 13, and in the subsequent second period (clock signal Φ2 or Φ2D is Hi), the voltage sampled by the fifth switched capacitor filter 13 is integrated by the second integrator 31a and quantized by the quantizer 17a.

[0063] Furthermore, as a voltage measurement of the second cell C3 (i.e., Input B), during the second period (clock signal Φ2 or Φ2D is Hi), the voltage of the second cell C3 (i.e., Input B) is sampled by the second switched capacitor filter 10 (strictly speaking, the charge is stored in the second capacitor 8), and during the first period (clock signal Φ1 or Φ1D is Hi), the difference between the voltage sampled by the second switched capacitor filter 10 and the voltage obtained by digital-to-analog conversion based on the output of the quantizer 17b is integrated by the first integrator 30b.

[0064] Furthermore, in the subsequent second period (clock signal Φ2 or Φ2D is Hi), the value integrated by the first integrator 30b is sampled by the sixth switched capacitor filter 14, and in the subsequent first period (clock signal Φ1 or Φ1D is Hi), the voltage sampled by the sixth switched capacitor filter 14 is integrated by the second integrator 31b and quantized by the quantizer 17b.

[0065] It should be noted that, Figure 1 The amplifier-shared analog-to-digital converter 21b shown also performs the same function as... Figure 2A The amplifier-shared analog-to-digital converter 21a shown operates in the same manner.

[0066] Thus, in each of the amplifier-shared analog-to-digital converters 21a and 21b, the first amplifier 19, the second amplifier 20, and the quantizer 17 are shared in a time-sharing manner (i.e., used alternately) in order to convert the voltages of cells C2 and C3 into digital values.

[0067] Therefore, in the voltage measurement circuit 23 according to this embodiment, since the voltage measurement is multiplexed for every two cells, it can operate at a higher speed compared to the conventional multiplexing method that multiplexes the voltage measurement of all cells. Furthermore, in the voltage measurement circuit 23 according to this embodiment, the first switch group 3 and the second switch group 6 are electrically insulated from the circuits following the third switch group 4 and the fourth switch group 7 via the first capacitor 5 and the second capacitor 8, respectively. And since the first amplifier 19, the second amplifier 20, and the quantizer 17 are shared for every two cells' voltage measurement, it is superior in terms of current consumption and mounting area compared to the conventional parallel method.

[0068] Typically, the current consumption of a delta-Σ type analog-to-digital converter or a level shifter using a switched-capacitor filter integrator is the sum of the charging and discharging current of the switched capacitor and the current consumption of the amplifier, but the majority of the current consumption is due to the amplifier. Therefore, by sharing the amplifier as described in this embodiment, the current consumption can be halved by having two circuits share the amplifier.

[0069] In conventional parallel battery pack voltage measurement circuits, since the same number of analog-to-digital converters as the battery cells are used, the current consumption can be halved by using amplifier-shared analog-to-digital converters or amplifier-shared level shifters, as in this embodiment, thereby eliminating the need for special heat dissipation measures for the semiconductor device.

[0070] Furthermore, switched capacitors consist of three elements: a switch, a capacitor, and an amplifier. In amplifier-shared analog-to-digital converters or amplifier-shared level shifters, the circuit area can be reduced because a single shared amplifier can be used to implement amplifiers for two voltage measurement circuits.

[0071] Furthermore, the analog-to-digital converters used in the voltage measurement circuits of battery packs typically operate as oversampling analog-to-digital converters. For the amplifier-shared analog-to-digital converters 21a and 21b of this disclosure, the measurement timing of the first and second cells will have an offset of half a cycle (i.e., half a cycle of the period after the clock signals Φ1 and Φ2 are combined) relative to the input sampling clock. However, the input sampling clock is very high-speed relative to the output data rate. When using a ΔΣ-type analog-to-digital converter with 256x oversampling at an output rate of 10ksps (Sample per second), the input sampling frequency is 2.56MHz, and this half-cycle offset is negligible for the simultaneity of the measurements.

[0072] Thus, in the voltage measurement circuit of a parallel battery pack, the use of the amplifier-shared analog-to-digital converters 21a and 21b of this disclosure, which also function as amplifier-shared level shifters, is effective in terms of power consumption, circuit area, and functional safety.

[0073] Figure 3 This is a block diagram showing the overall configuration of the voltage measurement circuit 23 according to the embodiment. The block diagram of the voltage measurement circuit 23 shown here constitutes a ΔΣ-type analog-to-digital converter, which consists of six amplifier-shared analog-to-digital converters 21a-21f and six decimation filters 22a-22f. These are necessary for parallel measurement of the voltages of all cells C1-C12 constituting the battery pack 50.

[0074] The six amplifier-shared analog-to-digital converters 21a to 21f all have the same... Figure 1 and Figure 2A The amplifier-shared analog-to-digital converter 21a shown has the same configuration.

[0075] Six decimation filters 22a to 22f average the 1-bit high-speed bit stream output from the amplifier-shared analog-to-digital converters 21a to 21f, and output two 16-bit signals showing the voltages of the two cells respectively.

[0076] Figure 4 This is a circuit block diagram showing a schematic configuration of the main parts of the voltage measurement circuit 23a according to the first variation of the embodiment. An amplifier-shared analog-to-digital converter 21g is shown here, which measures the voltage of cell C2 and cell C3 constituting the battery pack 50; and an amplifier-shared analog-to-digital converter 21h, which measures the voltage of cell C6 and cell C7.

[0077] The amplifier-shared analog-to-digital converters 21g and 21h involved in this variation are different from... Figure 1 The amplifier-shared analog-to-digital converters 21a and 21b involved in the implementation methods are characterized in that they both constitute a first-order ΔΣ modulator, and Figure 1 The implementation method constitutes a second-order ΔΣ modulator. Furthermore, the amplifier-shared analog-to-digital converters 21g and 21h involved in this variation differ from the amplifier-shared analog-to-digital converters 21a and 21b involved in the implementation method in that: they all have 1.5-bit (i.e., output three values) quantizers 17c and 17d, while the implementation method has a 1-bit quantizer.

[0078] Since the voltage measurement circuit 23a involved in this variation also has the same features as the voltage measurement circuit 23 involved in the embodiment, it can operate at a higher speed than conventional multiplexing methods, is superior in terms of current consumption and installation area compared to conventional parallel methods, and can also be configured as a ΔΣ type analog-to-digital converter with these features.

[0079] Figure 5 This is a circuit block diagram showing a schematic configuration of the main parts of the voltage measurement circuit 23b according to the second modification of the embodiment. The difference between this modification and the voltage measurement circuit 23b according to the embodiment is that the first input terminal 1 and the second input terminal 2 of the amplifier-shared analog-to-digital converters 21a and 21b are both connected to the two ends of the same battery cell, and voltage measurement is performed through two redundant sets of switched-capacitor filter circuits. This improves the fault tolerance of the voltage measurement circuit 23b.

[0080] In other words, in the implementation, a single amplifier-shared analog-to-digital converter (ADC) is used for voltage measurement of the upper and lower cells in the battery pack. However, in this variation, a single ADC is used to measure the voltage of one cell via two input terminals. The voltage measurement circuit of the battery pack may employ redundancy due to the functional safety requirements of ISO 26262. For the ADC in this variation, since the amplifier is shared, it is not completely redundant. However, in terms of failure rate, the terminals of the semiconductor device, the switches connected to the terminals, and the capacitors connected via the switches have a higher failure rate. On the other hand, since the amplifier, as a common cause of failure, has a lower failure rate, a higher safety level (SIL) can be achieved even with this configuration.

[0081] Figure 6 This is a circuit diagram of the amplifier-shared analog-to-digital converter 21i constituting the voltage measurement circuit according to the third variation of the embodiment. The circuit configuration of such an amplifier-shared analog-to-digital converter 21i is shown here, in which a single amplifier is shared in a time-sharing manner between the first-order and second-order integrators.

[0082] The amplifier-shared analog-to-digital converter 21i involved in this modification constitutes a second-order ΔΣ modulator and includes: a first integrator 30c, whose input terminal is connected to a cell constituting a battery pack 50; a second integrator 31c, whose input terminal is connected to the output terminal of the first integrator 30c; a first amplifier 19 shared by the first integrator 30c and the second integrator 31c; a quantizer 17e, whose input terminal is connected to the output terminal of the second integrator 31c; and a first digital-to-analog converter 40a, which performs digital-to-analog conversion using the output of the quantizer 17e as input and outputs the resulting analog voltage to the input terminal of the first integrator 30c. The first integrator 30c and the second integrator 31c integrate the input signal by sharing the first amplifier 19 in a time-division manner.

[0083] It should be noted that the first integrator 30c includes the first switched capacitor filter 9; the first switched capacitor filter 9 includes a first switch group 3 whose input terminal is connected to the battery cell and is turned on / off, a third switch group 4 whose output terminal is connected to the input terminal of the amplifier and is turned on / off, and a first capacitor 5 connected between the output terminal of the first switch group 3 and the input terminal of the third switch group 4; the first switch group 3 is electrically insulated from the third switch group 4 through the first capacitor 5; and the first switch group 3 is disposed in a high-voltage region 51, which is a circuit region that operates by receiving a first power supply voltage, and the third switch group 4 and the first amplifier 19 are disposed in a low-voltage region 52, which is a circuit region that operates by receiving a second power supply voltage lower than the first power supply voltage, which is the same as the amplifier-shared analog-to-digital converter 21a involved in the embodiment.

[0084] Therefore, according to the amplifier-shared analog-to-digital converter 21i involved in this variation, the first switch group 3 is electrically isolated from the circuit after the third switch group 4 through the first capacitor 5 (i.e., constitutes a level shifter), and since the first amplifier 19 is shared by two integrators, it is superior in terms of current consumption and installation area compared with the conventional parallel method.

[0085] Figure 7A This is a circuit diagram of the amplifier-shared analog-to-digital converter 21j constituting the voltage measurement circuit, according to the fourth variation of the implementation. Figure 7B yes Figure 7A The timing diagram of the clock signal is shown.

[0086] The amplifier-shared analog-to-digital converter 21j involved in this variation is similar in several aspects to... Figure 2A The amplifier-shared analog-to-digital converter 21a involved in the illustrated embodiment is the same, but differs in that it operates by accepting a supply of clock signals with four phases (Φ1 and Φ1D, Φ2 and Φ2D, Φ3 and Φ3D, Φ4 and Φ4D) in a way that differs from the embodiment that operates by accepting a supply of clock signals with two phases (Φ1 and Φ1D, Φ2 and Φ2D).

[0087] The amplifier-shared analog-to-digital converter 21j includes a first integrator 30d, a second integrator 31d, and a quantizer 17f for voltage measurement of the first cell C2 (i.e., Input A), and includes a first integrator 30e, a second integrator 31e, and a quantizer 17g for voltage measurement of the second cell C3 (i.e., Input B).

[0088] The first integrator 30d consists of a first switched-capacitor filter 9a, a third switched-capacitor filter 11a, and a first amplifier 19. The first switched-capacitor filter 9a includes a first switch group 3, a third switch group 4a, and a first capacitor 5. The third switched-capacitor filter 11a is a switched-capacitor filter with a reset (short-circuit) function.

[0089] The second integrator 31d consists of a fifth switched-capacitor filter 13a, a seventh switched-capacitor filter 15a, and a second amplifier 20. The seventh switched-capacitor filter 15a is a switched-capacitor filter with a reset (short-circuit) function.

[0090] The first integrator 30e is composed of a second switched-capacitor filter 10a and a fourth switched-capacitor filter 12a. The second switched-capacitor filter 10a includes a second switch group 6, a fourth switch group 7a, and a second capacitor 8. The fourth switched-capacitor filter 12a is a switched-capacitor filter with a reset (short-circuit) function.

[0091] The second integrator 31e is composed of a sixth switched-capacitor filter 14a and an eighth switched-capacitor filter 16a. The eighth switched-capacitor filter 16a is a switched-capacitor filter with a reset (short-circuit) function.

[0092] As for the voltage measurement of the first cell C2 (i.e., Input A), in the first period (clock signal Φ1 or Φ1D is Hi), the voltage of the first cell C2 (i.e., Input A) is sampled by the first switched capacitor filter 9a (strictly speaking, the charge is stored in the first capacitor 5). At the same time, the input and output terminals of the first amplifier 19 are short-circuited and reset by the third switched capacitor filter 11a. In the second period (clock signal Φ2 or Φ2D is Hi), the difference between the voltage sampled by the first switched capacitor filter 9a and the voltage obtained by digital-to-analog conversion based on the output of the quantizer 17f is integrated by the first integrator 30d.

[0093] Furthermore, in the subsequent first period (clock signal Φ1 or Φ1D is Hi), the value integrated by the first integrator 30d is sampled by the fifth switched capacitor filter 13a. At the same time, the input and output terminals of the second amplifier 20 are short-circuited and reset by the seventh switched capacitor filter 15a. In the subsequent second period (clock signal Φ2 or Φ2D is Hi), the voltage sampled by the fifth switched capacitor filter 13a is integrated by the second integrator 31d and quantized by the quantizer 17f.

[0094] On the other hand, as a voltage measurement of the second cell C3 (i.e., Input B), in the third period (clock signal Φ3 or Φ3D is Hi), the voltage of the second cell C3 (i.e., Input B) is sampled by the second switched capacitor filter 10a (strictly speaking, the charge is stored in the second capacitor 8). At the same time, the input and output terminals of the first amplifier 19 are short-circuited and reset by the fourth switched capacitor filter 12a. In the fourth period (clock signal Φ4 or Φ4D is Hi), the difference between the voltage sampled by the second switched capacitor filter 10a and the voltage obtained by digital-to-analog conversion based on the output of the quantizer 17g is integrated by the first integrator 30e.

[0095] Furthermore, in the subsequent third period (clock signal Φ3 or Φ3D is Hi), the value integrated by the first integrator 30e is sampled by the sixth switched capacitor filter 14a. At the same time, the input and output terminals of the second amplifier 20 are short-circuited and reset by the eighth switched capacitor filter 16a. In the subsequent fourth period (clock signal Φ4 or Φ4D is Hi), the voltage sampled by the sixth switched capacitor filter 14a is integrated by the second integrator 31e and quantized by the quantizer 17g.

[0096] As described above, in the amplifier-shared analog-to-digital converter 21j according to this variant, the first amplifier 19 and the second amplifier 20 alternately integrate and reset, thereby suppressing the generation of offset.

[0097] Furthermore, in the amplifier-shared analog-to-digital converter 21j involved in this variant, similar to the amplifier-shared analog-to-digital converter 21a involved in the embodiment, the first amplifier 19, the second amplifier 20, and the quantizer 17 are shared in a time-sharing manner (i.e., used alternately) in order to convert the voltages of cells C2 and C3 into digital values.

[0098] Therefore, according to the voltage measurement circuit of the amplifier-shared analog-to-digital converter 21j included in this modification, since the voltage measurement is performed once for every two cells, it can operate at a higher speed compared to the conventional multiplexing method that multiplexes the voltage measurement of all cells. Furthermore, according to the voltage measurement circuit of the amplifier-shared analog-to-digital converter 21j included in this modification, the first switch group 3 and the second switch group 6 are electrically insulated from the circuits after the third switch group 4 and the fourth switch group 7 via the first capacitor 5 and the second capacitor 8, respectively. And since the voltage measurement of every two cells shares the first amplifier 19, the second amplifier 20, and the quantizer 17, it is superior in terms of current consumption and mounting area compared to the conventional parallel method.

[0099] Figure 8AThis is a circuit diagram of the amplifier-shared analog-to-digital converter 21k constituting the voltage measurement circuit, according to the fifth variation of the implementation. Figure 8B yes Figure 8A An example of a timing diagram for a clock signal is shown. Figure 8C yes Figure 8A Another example of a timing diagram for a clock signal is shown.

[0100] The amplifier-shared analog-to-digital converter 21k involved in this modification includes a first integrator 30f and a quantizer 17h for voltage measurement of the first cell C2 (i.e., Input A), and a first integrator 30g and a quantizer 17i for voltage measurement of the second cell C3 (i.e., Input B).

[0101] The amplifier-shared analog-to-digital converter 21k involved in this variation operates by accepting a supply of clock signals with four phases, which is similar to... Figure 7A The amplifier-shared analog-to-digital converter 21j involved in the fourth variation shown is similar, but the difference is that it constitutes a first-order ΔΣ modulator, while the amplifier-shared analog-to-digital converter 21j involved in the fourth variation constitutes a second-order ΔΣ modulator.

[0102] It should be noted that, Figure 8B The timing of the clock signal shown Figure 7B The timing involved in the fourth variation shown is the same.

[0103] However, Figure 8C The timing of the clock signals shown is unique to this variant. As shown in the figure, clock signals Φ1 and Φ1D also function as clock signals Φ3 and Φ3D, respectively (i.e., they are the same).

[0104] Therefore, according to Figure 8C The timing is different Figure 8B The timing is performed simultaneously as follows (1) and (2): (1) During the first period (clock signal Φ1 or Φ1D is Hi), the voltage of the first cell C2 (i.e., Input A) is sampled by the first switched capacitor filter 9a (strictly speaking, the charge is stored in the first capacitor 5), and at the same time, the input and output terminals of the first amplifier 19 are short-circuited and reset; and (2) During the third period (clock signal Φ3 or Φ3D is Hi), the voltage of the second cell C3 (i.e. Input B) is sampled by the second switched capacitor filter 10a (strictly speaking, the charge is stored in the second capacitor 8), and at the same time, the input and output terminals of the first amplifier 19 are short-circuited and reset.

[0105] As mentioned above, according to Figure 8CThe timing is essentially achieved by integrating and resetting the first amplifier 19 and the second amplifier 20 using three sets of phased clock signals, which differs from... Figure 8B The timing is achieved by integrating and resetting the first amplifier 19 and the second amplifier 20 using four sets of phase clock signals, thus improving the speed of analog-to-digital conversion.

[0106] In addition, in the amplifier-shared analog-to-digital converter 21k involved in this modification, the first amplifier 19 and the quantizer 17 are shared in a time-sharing manner (i.e., used alternately) in order to convert the voltages of cells C2 and C3 into digital values.

[0107] Therefore, according to the voltage measurement circuit of the amplifier-shared analog-to-digital converter 21k included in this modification, since the voltage measurement is performed once for every two cells, it can operate at a higher speed compared to the conventional multiplexing method that multiplexes the voltage measurement of all cells. Furthermore, according to the voltage measurement circuit of the amplifier-shared analog-to-digital converter 21k included in this modification, the first switch group 3 and the second switch group 6 are electrically isolated from the circuits after the third switch group 4 and the fourth switch group 7 via the first capacitor 5 and the second capacitor 8, respectively, and the first amplifier 19 and the quantizer 17 are shared for the voltage measurement of every two cells. Therefore, it is superior in terms of current consumption and mounting area compared to the conventional parallel method.

[0108] As described above, the voltage measurement circuit 23 of this embodiment is a voltage measurement circuit for measuring the voltage of cells in a battery pack 50 composed of multiple cells C1 to C3 connected in series. It includes: a first switched capacitor filter 9, whose input terminal is connected to the first cell C2 constituting the battery pack 50; a second switched capacitor filter 10, whose input terminal is connected to the first cell C2 or the second cell C3 constituting the battery pack 50; and a first amplifier 19, whose input terminal is connected to the output terminal of the first switched capacitor filter 9 and the output terminal of the second switched capacitor filter 10. The first switched capacitor filter 9 includes a first switch group 3 and a first capacitor 5 connected to the output terminal of the first switch group 3. The second switched capacitor filter 10 includes a second switch group 6 and a second capacitor 8 connected to the output terminal of the second switch group 6. The first switch group 3 and the second switch group 6 are electrically insulated from the first amplifier 19 through the first capacitor 5 and the second capacitor 8, respectively.

[0109] Therefore, since the voltage measurement is performed once for every two cells, it can operate at a higher speed compared to the conventional multiplexing method that multiplexes the voltage measurement of all cells. Furthermore, in the voltage measurement circuit 23 of this embodiment, the first switch group 3 and the second switch group 6 are electrically insulated from the circuit after the first amplifier 19 via the first capacitor 5 and the second capacitor 8, respectively, and the first amplifier 19 is shared for the voltage measurement of every two cells. Therefore, it is superior in terms of current consumption and installation area compared to the conventional parallel method.

[0110] In other words, according to the voltage measurement circuit 23 of this embodiment, in a semiconductor device employing a parallel configuration (which uses multiple analog-to-digital converters to connect and measure each cell of a series-connected battery pack in pairs), by configuring an amplifier-shared analog-to-digital converter, the current consumption and area of ​​the multiple analog-to-digital converters can be reduced, and a battery pack voltage measurement circuit can be provided that can measure the cell voltage of the battery pack at almost the same time.

[0111] Here, the first switched capacitor filter 9 may further include a third switch group 4, which is connected between the first capacitor 5 and the input terminal of the first amplifier 19; the second switched capacitor filter 10 may further include a fourth switch group 7, which is connected between the second capacitor 8 and the input terminal of the first amplifier 19.

[0112] Furthermore, the first switch group 3 and the second switch group 6 can be configured in the high-voltage region 51, which is a circuit region that operates by receiving a first power supply voltage; the third switch group 4, the fourth switch group 7, and the first amplifier 19 can be configured in the low-voltage region 52, which is a circuit region that operates by receiving a second power supply voltage lower than the first power supply voltage. This constitutes an amplifier-shared level shifter, thereby suppressing current consumption and heat loss.

[0113] Furthermore, the voltage measurement circuit 23 may further include a third switched-capacitor filter 11 and a fourth switched-capacitor filter 12, which are connected between the input and output terminals of the first amplifier 19. Thus, integration can be achieved through the first amplifier 19.

[0114] Furthermore, the voltage measurement circuit 23 may further include a quantizer 17, which is connected to a subsequent stage compared to the first amplifier 19. The voltage measurement circuit 23, etc., can constitute an analog-to-digital converter that converts the voltage of the first cell C2 into a digital value, or converts the voltages of the first cell C2 and the second cell C3 into digital values ​​in a time-division multiplexing manner. This achieves a high-speed operating analog-to-digital converter that is superior to conventional ones in terms of current consumption and installation area.

[0115] Furthermore, the third switch group 4 may include a first digital-to-analog converter 40a, which uses the output of the quantizer 17 as input to perform digital-to-analog conversion and outputs the resulting analog voltage to the input terminal of the third switch group 4. The fourth switch group 7 may include a second digital-to-analog converter 40b, which uses the output of the quantizer 17 as input to perform digital-to-analog conversion and outputs the resulting analog voltage to the input terminal of the fourth switch group 7. The voltage measurement circuit 23, etc., can constitute a ΔΣ-type analog-to-digital converter. Thus, a high-speed operating ΔΣ-type analog-to-digital converter is achieved that is superior to conventional ΔΣ-type analog-to-digital converters in terms of current consumption and installation area.

[0116] Furthermore, in the path between the first amplifier 19 and the quantizer 17, the following components may be further included: a fifth switched-capacitor filter 13 and a sixth switched-capacitor filter 14, the input terminals of which are connected to the output terminals of the first amplifier 19; a second amplifier 20, the input terminals of which are connected to the output terminals of the fifth switched-capacitor filter 13 and the sixth switched-capacitor filter 14; and a seventh switched-capacitor filter 15 and an eighth switched-capacitor filter 16, which are connected between the input and output terminals of the second amplifier 20. The voltage measurement circuit 23 can thus constitute a second-order or higher ΔΣ-type analog-to-digital converter. This achieves a high-speed operating ΔΣ-type analog-to-digital converter that is superior to conventional second-order or higher ΔΣ-type analog-to-digital converters in terms of current consumption and installation area.

[0117] Additionally, the input terminal of the second switched-capacitor filter 10 can also be connected to the second battery cell C3. Thus, by using two redundant sets of switched-capacitor filter circuits for voltage measurement, a voltage measurement circuit that meets a high level of safety is achieved.

[0118] Alternatively, a voltage measurement circuit can be provided for measuring the voltage of cells in a battery pack 50 composed of multiple cells C1 to C3 connected in series. This circuit includes: a first integrator 30c, whose input terminal is connected to the cells constituting the battery pack 50; a second integrator 31c, whose input terminal is connected to the output terminal of the first integrator 30c; a first amplifier 19 shared by the first integrator 30c and the second integrator 31c; a quantizer 17e, whose input terminal is connected to the output terminal of at least the second integrator 31c; and a first digital-to-analog converter 40a, which performs digital-to-analog conversion using the output of the quantizer 17e as input and outputs the resulting analog voltage to the input terminal of the first integrator 30c. The first integrator 30c and the second integrator 31c integrate the input signal by sharing the first amplifier 19 in a time-division manner. This voltage measurement circuit can be configured as a second-order or higher ΔΣ-type analog-to-digital converter.

[0119] Accordingly, since the first amplifier 19 is shared by two integrators, a voltage measurement circuit is realized that is superior in terms of current consumption and mounting area compared to the conventional parallel method.

[0120] Here, the first integrator 30c may include a first switched-capacitor filter 9, which may include a first switch group 3 and a first capacitor 5 connected to the output terminal of the first switch group 3. The first switch group 3 may be electrically isolated from the first amplifier 19 through the first capacitor 5. Thus, the first switch group 3 is electrically isolated from the circuit after the first amplifier 19 through the first capacitor 5, thereby realizing a voltage measurement circuit in which current consumption is suppressed.

[0121] It should be noted that the first switched capacitor filter 9 may further include a third switch group 4, which is connected between the first capacitor 5 and the input terminal of the first amplifier 19.

[0122] Furthermore, the first switch group 3 can be configured in the high-voltage region 51, which is a circuit region that operates by receiving a first power supply voltage. The third switch group 4 and the first amplifier can be configured in the low-voltage region 52, which is a circuit region that operates by receiving a second power supply voltage lower than the first power supply voltage. This constitutes an amplifier-shared level shifter, thereby suppressing current consumption and heat loss.

[0123] The voltage measurement circuit involved in this disclosure has been described above based on embodiments and modifications, but this disclosure is not limited to these embodiments and modifications. Various modifications to these embodiments and modifications that can be conceived by those skilled in the art without departing from the spirit of this disclosure, as well as other forms constructed by combining some of the constituent elements of the embodiments and modifications, are also included within the scope of this disclosure.

[0124] For example, in the above embodiments, the amplifier-shared analog-to-digital converter is applicable to ΔΣ-type analog-to-digital converters, but the applicability of the amplifier-shared analog-to-digital converter is not limited to this, and it can also be applied to cyclic or successive approximation analog-to-digital converters.

[0125] Industrial availability The voltage measurement circuit disclosed herein can be used as a voltage measurement circuit for measuring the voltage of cells in a battery pack consisting of multiple cells connected in series. In particular, it can be used as a voltage measurement circuit that is faster than conventional multiplexing methods in terms of operating speed and superior to conventional parallel methods in terms of current consumption and mounting area.

[0126] Explanation of reference numerals in the attached figures 1 First input terminal 2 Second Input Terminal 3 First Switch Group 4, 4a Third switch group 5 First capacitor 6 Second Switch Group 7, 7a Fourth Switch Group 8 Second capacitor 9.9a First switched capacitor filter 10, 10a Second switched capacitor filter 11, 11a Third switched capacitor filter 12, 12a Fourth switched capacitor filter 13, 13a Fifth switched capacitor filter 14, 14a Sixth Switched Capacitor Filter 15, 15a Seventh Switched Capacitor Filter 16, 16a Eighth switched capacitor filter 17, 17a~17i quantizers 18 Output terminals 19 First Amplifier 20 Second Amplifier 21a~21k Amplifier Shared Analog-to-Digital Converter 22a~22f Decimation Filters 23, 23a, 23b Voltage measurement circuits 30a~30g First Integrator 31a~31e Second Integrator 32 DC shift circuit 33. Jitter Circuit 34 Feedforward Path 40a First Digital-to-Analog Converter 40b Second Digital-to-Analog Converter 50 battery pack 51 High Voltage Area 52 Low Voltage Region C1~C12 battery cells.

Claims

1. A voltage measuring circuit for measuring the voltage of cells in a battery pack consisting of multiple cells connected in series. The voltage measurement circuit includes: The first switched capacitor filter has its input terminal connected to the first cell constituting the battery pack; A second switched-capacitor filter, the input terminal of which is connected to the first battery cell or a second battery cell constituting the battery pack; and The first amplifier has its input terminals connected to the output terminals of both the first and second switched-capacitor filters. The first switched-capacitor filter includes a first switch group and a first capacitor. The input terminal of the first switch group is connected to the first battery cell, and the first capacitor is connected to the output terminal of the first switch group. The second switched-capacitor filter includes a second switch group and a second capacitor. The input terminal of the second switch group is connected to either the first or the second battery cell, and the second capacitor is connected to the output terminal of the second switch group. The first switch group and the second switch group are electrically insulated from the first amplifier through the first capacitor and the second capacitor, respectively.

2. The voltage measurement circuit as described in claim 1, The first switched-capacitor filter further includes a third switch group, which is connected between the first capacitor and the input terminal of the first amplifier. The second switched capacitor filter further includes a fourth switch group, which is connected between the second capacitor and the input terminal of the first amplifier.

3. The voltage measurement circuit as described in claim 2, The first switch group and the second switch group are located in a high-voltage region. The third switch group, the fourth switch group, and the first amplifier are located in a low-voltage region, which is a circuit region that operates by accepting a lower power supply voltage compared to the high-voltage region.

4. The voltage measurement circuit as described in claim 2 or 3, The voltage measurement circuit also includes a third switched capacitor filter and a fourth switched capacitor filter, which are connected between the input terminal and the output terminal of the first amplifier.

5. The voltage measurement circuit as described in claim 4, The voltage measurement circuit also includes a quantizer, which is connected in a subsequent stage compared to the first amplifier. The voltage measurement circuit constitutes an analog-to-digital converter, which converts the voltage of the first battery cell into a digital value, or converts the voltage of the first battery cell and the voltage of the second battery cell into digital values ​​in a time-division manner.

6. The voltage measurement circuit as described in claim 5, The third switch group includes a first digital-to-analog converter, which uses the output of the quantizer as input to perform digital-to-analog conversion and outputs the resulting analog voltage to the input terminals of the third switch group. The fourth switch group includes a second digital-to-analog converter, which uses the output of the quantizer as input to perform digital-to-analog conversion and outputs the resulting analog voltage to the input terminals of the fourth switch group. The voltage measurement circuit constitutes a ΔΣ type analog-to-digital converter.

7. The voltage measurement circuit as described in claim 5, The path between the first amplifier and the quantizer also includes: A fifth switched-capacitor filter and a sixth switched-capacitor filter, wherein the input terminals of the fifth switched-capacitor filter and the sixth switched-capacitor filter are connected to the output terminals of the first amplifier; The second amplifier has its input terminals connected to the output terminals of the fifth switched-capacitor filter and the sixth switched-capacitor filter; and A seventh switched-capacitor filter and an eighth switched-capacitor filter are connected between the input and output terminals of the second amplifier. The voltage measurement circuit constitutes a second-order or higher ΔΣ-type analog-to-digital converter.

8. The voltage measuring circuit as described in any one of claims 1 to 7, The input terminal of the second switched capacitor filter is connected to the second battery cell.

9. A voltage measuring circuit for measuring the voltage of cells in a battery pack consisting of multiple cells connected in series. The voltage measurement circuit includes: The first integrator has its input terminals connected to the cells constituting the battery pack; The second integrator has its input terminal connected to the output terminal of the first integrator; A first amplifier shared by the first integrator and the second integrator; A quantizer, the input terminals of which are connected to the output terminals of at least one of the first integrator and the second integrator; as well as The first digital-to-analog converter uses the output of the quantizer as input to perform digital-to-analog conversion and outputs the resulting analog voltage to the input terminal of the first integrator. The first integrator and the second integrator share the first amplifier in a time-division manner to integrate the input signal. The first integrator includes a first switched-capacitor filter. The first switched-capacitor filter includes a first switch group and a first capacitor. The input terminal of the first switch group is connected to the battery cell, and the first capacitor is connected to the output terminal of the first switch group. The first switch group is electrically insulated from the first amplifier through the first capacitor.

10. The voltage measurement circuit as described in claim 1, The first switched capacitor filter further includes a third switch group, which is connected between the first capacitor and the input terminal of the first amplifier.

11. The voltage measurement circuit as described in claim 10, The first switch group is located in the high-voltage region. The third switch group and the first amplifier are located in a low-voltage region, which is a circuit region that operates by accepting a lower power supply voltage compared to the high-voltage region.

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