Low latency alignment module for data streams

Abstract

A multi-chiplet system includes: a first chiplet including a first transceiver and a first chiplet to chiplet (C2C) interface module; and a second chiplet including a programmable logic circuit and a second C2C interface module. The first transceiver is configured to generate a clock that is transmitted from the first C2C interface module to the second C2C interface module over the clock transmission line for data transmission between the first chiplet and the second chiplet.

Description

Technical Field

[0001] The examples disclosed herein generally relate to integrated circuit (IC) design, and more specifically to a multi-chiplet IC that enables low-latency aligned data streams via a chiplet-to-chiplet (C2C) interface. Background Technology

[0002] System-on-a-Chip (SoC) designs using modular chiplets are more popular than traditional monolithic chips because chiplets offer advantages such as flexible design and reduced costs. Allowing semiconductor chiplets to interconnect on a single package via C2C (or die-to-die (D2D)) interfaces enables an ecosystem that supports decomposed die architectures with different protocols and functionalities. The Universal Chiplet Interconnect High Speed ​​(UCIe) standard is a significant step towards heterogeneous integration of semiconductor chiplets.

[0003] While the connectivity standard provided by UCIe is useful, it also comes with overhead (e.g., increased latency) and is not well-suited to the specific requirements of certain components, such as high-speed transceivers. For example, in the construction of modularly designed programmable logic devices, the high-speed transceiver is implemented on a transceiver chiplet, while the transceiver protocol is implemented in programmable logic on a separate chiplet. This presents challenges for transceiver protocol implementation if the currently defined standard UCIe interface is used. For instance, transceiver protocol implementations often require the use of a clock signal (or clock) generated within the high-speed transceiver circuitry within the transceiver protocol circuitry. The current UCIe standard does not define a mechanism for transmitting such a clock. Another limiting aspect of the current UCIe standard is the lack of flexibility in module alignment. The standard describes Multi-Module Physical (PHY) Logic (MMPL), which is fixed in two or four module implementations. In programmable logic applications, where transceiver protocols can be defined with one, two, four, or more linked channels as part of a single channel, flexibility in module alignment is desirable. Furthermore, since the specific purpose may not be known when the device is constructed, the current UCIe standard does not provide flexibility in combining adjacent modules.

[0004] Therefore, a solution is needed to maintain transceiver clock characteristics, reduce latency, and improve the flexibility of multi-module alignment for data flow between chipsets. Summary of the Invention

[0005] A system, method, and apparatus for achieving low-latency alignment of data streams between chiplets via a C2C interface are described.

[0006] According to one aspect, a system includes: a first chiplet having a first transceiver and a first C2C interface module; and a second chiplet having a second C2C interface module. The first transceiver is configured to generate a clock, which is transmitted from the first C2C interface module to the second C2C interface module via a clock transmission line for data transmission between the first and second chiplets.

[0007] According to another aspect, a method performed by a system having a first chiplet and a second chiplet includes: generating a clock by a first transceiver on the first chiplet; transmitting the clock from a first C2C interface module on the first chiplet to a second C2C interface module on the second chiplet; and using the clock by the second chiplet to perform data transmission between the first chiplet and the second chiplet.

[0008] According to another aspect, a chiplet includes a transceiver and a C2C interface module, wherein the transceiver is configured to send a clock generated by the transceiver to another chiplet for data transmission via the C2C interface module. Attached Figure Description

[0009] To gain a more detailed understanding of the features described above, a more specific description of the brief summary can be obtained by referring to the exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical exemplary embodiments and should not be considered as limiting their scope.

[0010] Figure 1A A block diagram of a multi-chip IC, comprising two small chips coupled to each other via a UCIe interface module, is illustrated according to the example.

[0011] Figure 1B A block diagram of a multi-chip IC, comprising two small chips coupled to each other via a UCIe interface module, is illustrated according to the example.

[0012] Figure 2A A flowchart illustrating a method for data transfer between two chips in transmit (TX) mode is provided, based on an example.

[0013] Figure 2B A flowchart illustrating a method for data transfer between two chips in receive (RX) mode is provided, based on an example.

[0014] Figure 3A A block diagram illustrating, based on an example, shows the portions of a first chiplet and the portions of a second chiplet coupled to each other via a UCIe interface module in TX mode.

[0015] Figure 3BA block diagram illustrating, based on an example, shows portions of a first chiplet and portions of a second chiplet coupled to each other via a UCIe interface module in RX mode.

[0016] Figure 4A A block diagram illustrating four UCIe interface modules that provide data via four independent GT links or channels, based on an example, is shown.

[0017] Figure 4B A block diagram illustrating four UCIe interface modules combined to provide data via two independent GT direct links or channels is shown.

[0018] Figure 4C A block diagram illustrating four UCIe interface modules combined to provide data via a single independent GT direct link or channel, according to an example, is shown.

[0019] Figure 5A A block diagram illustrating four UCIe interface modules that provide data via four independent Ethernet links or channels, based on an example.

[0020] Figure 5B A block diagram illustrating four UCIe interface modules combined to provide data over two separate Ethernet links or channels, according to an example, is shown.

[0021] Figure 5C A block diagram illustrating four UCIe interface modules combined to provide data over a single, independent Ethernet link or channel, according to an example, is shown.

[0022] Figure 6 A block diagram illustrating a chiplet IC architecture based on an example is shown.

[0023] Figure 7 A block diagram of a multi-chip IC including alignment circuitry is shown according to the example.

[0024] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is conceivable that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0025] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of this description, nor as a limitation on the scope of the claims. Furthermore, the illustrated examples do not necessarily possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described.

[0026] Monolithically integrated programmable logic devices typically consist of programmable logic and a high-speed transceiver (HST) integrated on the same semiconductor die, where data and clock signals on the HST can be transmitted to the programmable logic at high speed and low latency. For example, data transmission between external pins of the HST and the programmable logic on the same semiconductor die may experience latency as low as 10 nanoseconds. However, when the transceiver and programmable logic are formed on different dies or chiplets, the transceiver communicates with the programmable logic through a C2C (e.g., UCIe) interface module implemented on the chiplet.

[0027] Under the current UCIe interface specification, instead of transmitting the transceiver clock signal (or clock) (e.g., transmit (TX) clock and receive (RX) clock) directly from the transceiver chiplet to the programmable logic chiplet, the transceiver clock must be converted to the clock of the UCIe interface module (e.g., the UCIe PHY clock) (and vice versa) before being transmitted to the programmable logic.

[0028] For certain transceiver protocols (e.g., synchronous Ethernet, video broadcasting, inline "bump in line" applications), maintaining the transceiver-generated clock and its characteristics is important to ensure that transceivers and protocols implemented in programmable logic operate synchronously. Embodiments of this disclosure describe systems, methods, and apparatus for implementing low-latency aligned data streams between chiplets via UCIe interface modules while also supporting certain proprietary protocols (e.g., high-speed transceiver protocols).

[0029] Regarding the current UCIe interface specification and / or other than the current UCIe interface specification, the multi-chip IC in this disclosure also provides a low-latency synchronous clock forwarding UCIe interface module. This interface module enables the transmission of a transceiver-generated clock from a transceiver chiplet to another chiplet (e.g., an anchor chiplet having a transceiver protocol implemented in programmable logic), maintaining the characteristics of the transceiver-generated clock (e.g., long-term jitter, etc.) throughout the system to improve synchronization between the two chipsets. The multi-chip IC also provides a data path through the UCIe interface module, wherein the data path bypasses at least a portion of the D2D adapter layer and protocol layer of the UCIe interface module to reduce latency in inter-chiplet data transmission. The multi-chip IC includes alignment circuitry on the transceiver chiplet located between the transceiver and the UCIe interface module to support flexible multi-module alignment. The multi-chip IC also includes alignment circuitry on the anchor chiplet located between the UCIe interface module and the protocol implemented in programmable logic to meet the channel alignment requirements of certain dedicated transceiver protocols.

[0030] Figure 1A A block diagram of a multi-chiplet IC 100A, comprising chiplet ICs 110 and 120 coupled to each other via a UCIe interface module, is shown according to an example. Figure 1A As illustrated, chiplet 110 includes programmable logic 112 and a UCIe interface module 114. By way of example only, programmable logic 112 may be provided at least in part by one or more FPGAs in a field-programmable gate array (FPGA). Programmable logic 112 may house one or more lookup tables (LUTs) and other logic in a configurable logic block (CLB). Programmable logic 112 can be programmed to perform a wide variety of functions corresponding to a specific end-user application. UCIe interface module 114 may include a UCIe protocol layer, a UCIe D2D adapter layer, and a UCIe PHY layer. Figure 1A Not explicitly shown. The UCIe interface module 114 is implemented on chiplet 110 to send data to another chiplet (such as chiplet 120) and receive data from another chiplet. In another example, chiplet 110 may include an application-specific integrated circuit (ASIC) coupled to the UCIe interface module 114 to send data to another chiplet (such as chiplet 120) and receive data from another chiplet.

[0031] In this example, chiplet 110 is an anchor chiplet. Chiplet 110 may include circuitry including one or more data processing blocks (such as a processing system or subsystem (PS), a memory system (e.g., including a memory controller), etc.) to process data provided by or supplied to chiplet 120.

[0032] like Figure 1A As illustrated, chiplet 120 includes gigabit transceivers (GTs) 122A, 122B, 122C, and 122D (collectively referred to as "GT 122") and a UCIe interface module 124. In another example, each GT in GT 122 may be coupled to a separate UCIe interface module 124. Chiplet 120 may also include other intellectual property (IP) blocks, such as a high-speed peripheral component interconnect (PCIe) / accelerator cache coherent interconnect (CCIX) media access control (MAC) core associated with the processor subsystem (PS) and direct memory access (DMA) engine and controller; for clarity, all of these are derived from... Figure 1A Omitted in .

[0033] In this example, chiplet 120 is a GT Media Access Control (MAC) PCIe chiplet (GMPC), a versatile high-speed I / O chiplet. Chiplet 120 may include highly flexible and programmable Adaptive and Embedded Computing Group (AECG) modules to handle a wide range of applications. Chiplet 120 can utilize protocols implemented in programmable logic 112 with different configurations to handle GT direct applications. Examples of protocols that chiplet 120 can handle include, but are not limited to, Ethernet, Synchronous Ethernet (SyncE), PCIe Test and Measurement (PCIe-T&M), Joint Electronic Equipment Engineering Committee (JEDEC) Data Converter Serial Interface (JESD), Optical Interconnect Forum-General Electric Interface (OIF-CEI), Interlaken (ILKN), General Public Radio Interface (CPRI), and Advanced Microcontroller Bus Architecture (AMBA) Advanced Extensible Interface 4 (AXI-4).

[0034] The GT 122 can be individually programmed to conform to different standards or protocols. Furthermore, the TX and RX paths of each GT 122 can be individually programmed, allowing the transceiver's TX path to support one standard or protocol, while the RX path of the same transceiver can support different standards or protocols. Additionally, two or more GT 122s can be bundled together to provide faster transmission speeds and / or greater bandwidth. Each GT in the GT 122 can perform serial-to-parallel conversion on received data and parallel-to-serial conversion on transmitted data.

[0035] In some implementations, each GT in GT 122 can achieve bandwidth from 1.25 gigabits per second (Gbps) to 112 Gbps per data channel, and aggregate bandwidth up to 1.6 terabits per second (Tbps) on a single data link. In some implementations, chiplet 120 may also include PCIe Gen6 AXI-S and DMA AXI-MM interfaces with a number of possible bifurcated configurations (e.g., x2, x4, x8, x16, or any combination thereof). Figure 1A (Not explicitly shown in the text). In some implementations, the chiplet 120 may support Ethernet MAC AXI-S with a variety of possible port configurations (e.g., 10G, 25G, 50G, 100G, 200G, 400G, 800G, 1.6T, etc.).

[0036] Chip 120 may be coupled to chip 110 via UCIe interface modules 114 and 124 and physical or hardwired connections. UCIe interface modules 114 and 124 may be programmable (e.g., via a programming software model employing a programming interface for end users). In some embodiments, the UCIe interface modules may include digital and analog components enabling communication between two or more chiplets.

[0037] According to embodiments of this disclosure, the clock characteristics from one or more GTs in GT 122 are transmitted to programmable logic 112 via UCIe interface modules 124 and 114 without substantially alteration. In other words, chiplets 110 and 120 are able to maintain the characteristics (e.g., frequency, long-term jitter, etc.) of the transceiver-generated clock signal throughout the system. Figure 1A The multichip IC 100A shown is essentially synchronized across the UCIe interface module between the clock domain on the GT side and the clock domain on the programmable logic side, thereby eliminating the need for a first-in-first-out (FIFO) buffer, which would otherwise add latency and create differences between clock domains.

[0038] It should be understood that although only one chiplet 120 is coupled to chiplet 110 in the multi-chiplet IC 100A (e.g., anchor chiplet), chiplet 110 may support multiple chipslets with a homogeneous arrangement of a single type of chiplet 120 or a heterogeneous arrangement of more than one type of chiplet 120.

[0039] Figure 1B A block diagram illustrating a multi-chiplet IC 100B comprising chiplet ICs 120 and 130 coupled to each other via a UCIe interface module is shown. In this example, chiplet 120 may correspond to... Figure 1AChip 120 is included in the chip. Chip 130 includes GT 132A, 132B, 132C, and 132D (collectively referred to as "GT 132") and UCIe interface module 134. In this example, chip 130 performs substantially similar functions to chip 120 and supports substantially similar protocols. In another example, chip 130 performs different functions than chip 120 and supports different protocols. GT 122 in chip 120 and GT 132 in chip 130 can communicate with each other via UCIe interface modules 124 and 134.

[0040] According to embodiments of this disclosure, the clock characteristics of one or more GTs from GT 122 are maintained without change (e.g., not converted to a UCIe PHY clock) when transmitted to GT 132 via UCIe interface modules 124 and 134, and vice versa. For example, GT 122 on chiplet 120 can each provide serial data streams and clock signals to one or more GTs from GT 132 on chiplet 130 via UCIe interface modules 124 and 134. One or more GTs from GT 132 on chiplet 130 can receive clock signals from GT 122 without losing clock characteristics. In other words, Figure 1B The multi-chip IC100B shown is synchronized between GT 122 and GT 132, thereby eliminating the need for a FIFO buffer, which would otherwise add latency and create differences between clock domains.

[0041] It should be noted that the scope of various aspects of this disclosure should not be limited. Figure 1A and Figure 1B The limitations of the characteristics of the multi-chip IC shown (e.g., chip type, transceiver protocol, bandwidth, clock frequency, etc.) are illustrated.

[0042] Figure 2A A flowchart 200A illustrates a method for data transfer between two chips in transmit (TX) mode, based on an example. (See also...) Figure 3A Describe the methods illustrated in flowchart 200A.

[0043] Figure 3A A block diagram of a system 300A according to an example is shown, illustrating portions of chiplet 310 and chiplet 320 coupled to each other via UCIe interface modules in TX mode. In TX mode, data is transmitted from chiplet 310 (e.g., an anchor chiplet with programmable logic) to chiplet 320 (e.g., a GMPC with one or more GTs). In one embodiment, Figure 3A The small chips 310 and 320 shown can be substantially corresponding to respectively Figure 1A The small chips 110 and 120 are included.

[0044] In this example, chiplet 310 includes programmable logic 302 and a UCIe interface module. The UCIe interface module includes a UCIe TX interface module 314 ( Figure 3A (as shown) and UCIe RX interface module 315 ( Figure 3B (As shown). Each of the UCIe TX interface module 314 and the UCIe RX interface module 315 includes a UCIe PHY layer, a UCIe D2D adapter layer, and a UCIe protocol layer. In another example, the UCIe interface module on chiplet 310 may include a single module operating in TX mode and / or RX mode.

[0045] In this example, chiplet 320 includes at least one GT 322 and a UCIe interface module. The UCIe interface module includes UCIe RX interface module 324 ( Figure 3A (as shown) and UCIe TX interface module 325 ( Figure 3B (As shown). Each of the UCIe RX interface module 324 and the UCIe TX interface module 325 includes a UCIe PHY layer, a UCIe D2D adapter layer, and a UCIe protocol layer. In another example, the UCIe interface module on chiplet 320 may include a single module operating in TX mode and / or RX mode.

[0046] like Figure 3A As illustrated, chiplet 310 may include a spacer 316 between programmable logic 302 and UCIe TX interface module 314. Chiplet 320 may include a spacer 326 between GT 322 and UCIe RX interface module 324. It should be understood that the spacer architecture (e.g., spacer 316 or 326) allows a higher bit-width channel operating at a lower frequency to be connected to a lower bit-width channel operating at a higher frequency.

[0047] In this example, the GT 322 includes a programmable physical media attach (PMA) module, a programmable physical decoder sublayer (PCS) module, and a clock management module. The PMA module includes a programmable TX PMA module 332 ( Figure 3A (as shown) and programmable RXPMA module 333 ( Figure 3B As shown). The programmable PCS module includes a programmable TX PCS module 342 ( Figure 3A (as shown) and programmable RXPCS module 343 ( Figure 3B As shown). The clock management module includes the TX clock management module 350 ( Figure 3A (as shown) and RX clock management module 351 ( Figure 3B(As shown). In another example, the programmable PMA module, the programmable PCS module, and the clock management module may each be included as a single module operating in TX mode and / or RX mode.

[0048] In TX mode, the programmable TX PCS module 342 can receive TX data from the UCIe RX interface module 324 via the spacer 326, and convert the data into transmit parallel data, for example, according to the TX PMA PCS interface settings. The programmable TX PMA module 332 can also convert transmit parallel data from the programmable TX PCS module 342 into transmit serial data, for example, according to programmed serialization settings.

[0049] In TX mode, the TX clock management module 350 is operatively coupled to the programmable TX PMA module 332 and the programmable TX PCS module 342. The TX clock management module 350 generates the TX clock (the clock generated by the transceiver) and sends the TX clock to the chiplet 310. The TX clock management module 350 also performs clock phase adjustment, for example, by using one or more built-in phase interpolators (PIs) in a phase-locked loop (PLL).

[0050] It should be noted that the UCIe interface modules in GT 322, programmable logic 302, and chiplets 310 and 320 may also include components for handling sideband (SB) logic and data; details are omitted for brevity.

[0051] Return to reference Figure 2A In box 202, the transceiver on the first chip generates a clock, which is the TX output clock (TXOUTCLK) when the transceiver is in TX mode.

[0052] refer to Figure 3A In TX mode, the TX clock management module 350 of GT 322 on chiplet 320 generates TXOUTCLK 352 and provides TXOUTCLK to the UCIe RX interface module 324 of chiplet 320.

[0053] like Figure 3AAs shown, the voltage-controlled oscillator (VCO) clock is provided to the TX PMAPI and programmable divider (ProgDiv) in the TX clock management module 350. The VCO clock may be based on one or more reference clocks received by the GT 322. The one or more reference clocks may include, but are not limited to, an external clock, the internal clock of the GT 322, and / or the system clock. The TX PMAPI receives the VCO clock and provides a clock (e.g., a phase-aligned clock) to the dual clock generator. The dual clock generator provides two clock signals to the programmable TX PMA module 332 and a transmit PCS clock (TX PCSCLK) to the programmable TX PCS module 342. The ProgDiv divides the VCO clock and provides the divided VCO clock to the TX delay aligner (DA) PI. The TX DAPI performs instantaneous phase alignment and compensates for phase changes in the TXOUTCLK 352 caused by, for example, voltage, temperature, and / or crystal variations.

[0054] In one example, the TXOUTCLK 352 has a frequency of 2.8 GHz. The frequency of the TXOUTCLK 352 can be related to the data line rate of the GT322. In other examples, the frequency of the TXOUTCLK 352 may be higher or lower than 2.8 GHz.

[0055] Return to reference Figure 2A In block 204, the transceiver provides TXOUTCLK from the first C2C interface module of the first chiplet to the second C2C interface module of the second chiplet via one or more clock transmission lines (e.g., auxiliary clock transmission lines).

[0056] refer to Figure 3A The GT 322 transmits the TXOUTCLK 352 from the UCIe RX interface module 324 of the chiplet 320 to the UCIe TX interface module 314 of the chiplet 310 via the auxiliary clock transmission line 390. For example... Figure 3A As illustrated, TXOUTCLK 352 is not altered by any of the PHY, D2D adapter, or protocol layer of the UCIe RX interface module 324 before it is sent to the UCIe TX interface module 314 of chiplet 310. Therefore, the characteristics of TXOUTCLK 352 are maintained in system 300A because TXOUTCLK 352 is sent directly from chiplet 320 to chiplet 310 via the UCIe interface module without being converted into a UCIe PHY clock.

[0057] Return to reference Figure 2AIn block 206, the second chiplet transmits TXOUTCLK from the second C2C interface module of the second chiplet back to the first C2C interface module of the first chiplet via one or more clock transmission lines (e.g., UCIe module transmit clock phase-1 / transmit clock phase-2 (TXCKP / TXCKN) clock transmission lines as defined in the current UCIe interface specification). TXOUTCLK is used as the TX clock (TXCLK) of the second chiplet.

[0058] refer to Figure 3A After reaching the UCIe TX interface module 314 on chiplet 310, TXOUTCLK 352 is folded back as the TX clock (TXCLK) 354 and transmitted to the UCIe RX interface module 324 on chiplet 320 via the UCIe module TXCKP / TXCKN clock transmission line 392. Figure 3A As shown, TXOUTCLK 352 is provided to the divider 362 in the UCIe TX interface module 314 of chiplet 310. Divider 362 provides TXOUTCLK 352 (e.g., 2.82GHz) as TXCLK 354 to the UCIe module's TXCKP / TXCKN clock transmit line 392. Therefore, the TXCLK 354 of chiplet 310 (e.g., anchor chiplet) is the same as the TXOUTCLK 352 of chiplet 320 (e.g., GMPC). It should be understood that although in Figure 3A The frequency divider 362 is shown as being included within the UCIe TX interface module 314, but in another example, the frequency divider 362 may be a separate component outside the UCIe TX interface module 314 on the chiplet 310.

[0059] Return to reference Figure 2A In block 208, the first chiplet generates a first logic clock (LCLK) locally from TXCLK, and provides the first LCLK and the phase-shifted TXCLK (or TXCLK) as the first PHY clock (PHYCLK) to the first UCIe PHY layer of the first C2C interface module.

[0060] refer to Figure 3AThe same TXCLK 354 as TXOUTCLK 352 (e.g., 2.82 GHz) is provided to the divider 356 in the UCIe RX interface module 324 on chiplet 320. Divider 356 locally generates a logic clock (LCLK) on chiplet 320 by dividing TXCLK 354 by N (e.g., N=4) and provides the LCLK (e.g., 705 MHz) to the UCIe PHY layer 382 of the UCIe RX interface module 324. Divider 356 also provides a 90-degree phase-shifted TXCLK as the UCIe PHY clock (PHYCLK) (e.g., 2.82 GHz) to the UCIe PHY layer 382 of the UCIe RX interface module 324. In another example, divider 356 may provide TXCLK as the UCIe PHY clock (PHYCLK) (e.g., 2.82 GHz) to the UCIe PHY layer 382 of the UCIe RX interface module 324. It should be understood that, although in Figure 3A The frequency divider 356 is shown as being included within the UCIe RX interface module 324, but in another example, the frequency divider 356 may be a separate component outside the UCIe RX interface module 324 on the chiplet 320.

[0061] Return to reference Figure 2A In block 210, the second chiplet generates the second LCLK locally from the TXCLK, and provides the second LCLK and TXCLK as the second PHYCLK to the second UCIe PHY layer of the second C2C interface module.

[0062] refer to Figure 3A In chiplet 310, divider 362 locally generates LCLK by dividing TXCLK 354, which is the same as TXOUTCLK 352 (e.g., 2.82 GHz), by N (e.g., N=4), and provides LCLK (e.g., 705 MHz) to the UCIe PHY layer 372 of the UCIe TX interface module 314 on chiplet 310. Divider 362 also provides TXCLK 354 as the PHY clock (PHYCLK) to the UCIe PHY layer 372 of the UCIe TX interface module 314 on chiplet 310. PHYCLK and / or LCLK can be used to send data in the UCIe main band (MB) from UCIe TX interface module 314 to UCIe RX interface module 324.

[0063] Return to reference Figure 2A In block 212, the second chiplet provides the frequency-divided second LCLK (or second LCLK) to the programmable logic on the second chiplet for transmitting data using a transceiver protocol implemented in the programmable logic.

[0064] refer to Figure 3A Divider 364 divides LCLK (e.g., 705MHz) by N (e.g., N=2) and provides the divided LCLK (e.g., LCLK÷2) to programmable logic 302. In another example, spacer 316 is optional, in which case LCLK can be provided to programmable logic 302 without division. In this example, deskewing between the UCIe clock domain in chiplet 310 and the programmable logic clock domain can be handled by the AEGG auxiliary clock IP.

[0065] Return to reference Figure 2A In block 214, the second chiplet, based on TXOUTCLK, transmits data from the programmable logic to the transceiver on the first chiplet via the second C2C interface module and the first C2C interface module.

[0066] refer to Figure 3A Programmable logic 302 receives a divided clock (e.g., LCLK ÷ 2) from frequency divider 364 and uses the divided clock to transmit data, which is based on LCLK from frequency divider 362. LCLK is provided by frequency divider 362 by dividing TXOUTCLK 352 by N (e.g., N = 4).

[0067] exist Figure 3A In the example shown, data is transmitted by programmable logic 302 at a divided clock (e.g., 352.6 MHz). In TX mode, data and clock from programmable logic 302 can bypass at least a portion of the UCIe D2D adapter layer 374 and the UCIe protocol layer 376 of the UCIe TX interface module 314. For example, certain functions of the UCIe D2D adapter layer 374 (such as data integrity checks (e.g., parity and cyclic redundancy check (CRC))) may not be bypassed. In another example, programmable logic 302 can completely bypass both the UCIe protocol layer 376 and the UCIe D2D adapter layer 374 of the UCIe TX interface module 314 to directly provide data and clock to the UCIe PHY layer 372. Bypassing the UCIe protocol layer 376 and the UCIe D2D adapter layer 374 of the UCIe TX interface module 314 reduces data transmission latency.

[0068] exist Figure 3AIn the example shown, the bit-width up / down sizer in shim 316 halves the data width and doubles the clock frequency before providing data and clock from programmable logic 302 to UCIe TX interface module 314. In another example, shim 316 is optional, in which case signals and clock from programmable logic 302 are provided directly to UCIe PHY layer 372 of UCIe TX interface module 314 without any data width or frequency modulation, thereby further reducing latency.

[0069] On chiplet 320, data and clock signals from the UCIe TX interface module 314 of chiplet 310 are received by the UCIe PHY of the UCIe RX interface module 324. Figure 3A In the example shown, the data received by the UCIe RX interface module 324 is serialized (e.g., 8 to 1 serialization). After deserialization, the parallel data buses can each operate at a lower frequency (e.g., 705 MHz).

[0070] like Figure 3A As illustrated, in TX mode, data and clock from the UCIe PHY layer 382 of the UCIe RX interface module 324 can bypass at least a portion of the UCIe protocol layer 386 of the UCIe RX interface module 324 of the chiplet 320 and the UCIe D2D adapter layer 384. For example, some functions of the UCIe D2D adapter layer 384, such as data integrity verification functions (e.g., parity check and CRC) may not be bypassed. In another example, the UCIe PHY layer 382 of the UCIe RX interface module 324 can completely bypass the UCIe D2D adapter layer 384 and the UCIe protocol layer 386 of the UCIe RX interface module 324 to directly provide data and clock to the pad 326. Bypassing the UCIe D2D adapter layer 384 and the UCIe protocol layer 386 of the UCIe RX interface module 324 also reduces data transmission latency.

[0071] exist Figure 3A In the example shown, the bit-width scaler in shim 326 halves the data width and doubles the clock frequency before providing data from UCIe RX interface module 324 to GT 322. In another example, shim 326 is optional, in which case the signals and clock from UCIe RX interface module 324 are provided directly to GT 322 without any data width or frequency modulation, thereby further reducing latency.

[0072] Return to reference Figure 2AIn block 216, the first chiplet performs clock phase adjustment by using one or more phase interpolators to ensure synchronized data transmission.

[0073] refer to Figure 3A The divider 356 on chiplet 320 provides another clock (e.g., LCLK×2) by dividing TXCLK 354 (e.g., 2.82 GHz) by N (e.g., N=2), and provides LCLK×2 (e.g., 1.41 GHz) to the bit-width scaler of pad 326 and the programmable TX PCS module 342 of GT 322.

[0074] The TX clock management module 350 is operatively coupled to the programmable TX PMA module 332 and the programmable TX PCS module 342, and receives feedback through the programmable TX PCS module 342, thereby forming a PLL (e.g., an LCPLL). Based on the feedback in the PLL, the TX clock management module 350 performs clock phase adjustment (e.g., via TX DA PI) to compensate for phase changes in the TXOUTCLK 352 caused, for example, by voltage, temperature, and / or crystal variations.

[0075] In system 300A, the clock generated by the transceiver (e.g., TXOUTCLK 352) is used as the UCIe PHY clock for data transmission. In other words, the clock generated by GT 322 on chiplet 320 does not need to be converted to a UCIe PHY clock before being provided to the programmable logic 302 residing on chiplet 310. TXOUTCLK 352 generated by GT 322 is provided to chiplet 310 from chiplet 320. The programmable logic 302 uses a divided TXOUTCLK 352 (e.g., LCLK ÷ 2) to send data from chiplet 310 to chiplet 320, maintaining the characteristics of TXOUTCLK 352 (e.g., long-term jitter, etc.) throughout system 300A to ensure synchronous data transmission between the two chipsets.

[0076] Figure 2B A flowchart 200B illustrates a method for data transfer between two chips in receive (RX) mode, based on an example. (See also...) Figure 3B Describe the methods illustrated in flowchart 200B.

[0077] Figure 3BThe block diagram of example system 300B illustrates portions of chiplet 310 and chiplet 320 coupled to each other via a UCIe interface module in RX mode. In RX mode, data received by chiplet 320 (e.g., a GMPC with one or more GTs) is sent to chiplet 310 (e.g., an anchor chiplet with programmable logic). In one embodiment, Figure 3B The small chips 310 and 320 shown can be substantially corresponding to respectively Figure 1A The small chips 110 and 120 are included.

[0078] like Figure 3B As illustrated, chiplet 310 includes programmable logic 302 and a UCIe RX interface module 315. Chiplet 310 may include a spacer 316 between the programmable logic 302 and the UCIe RX interface module 315. Chiplet 320 includes at least one GT 322 and a UCIe TX interface module 325. Chiplet 320 may include a spacer 326 between the GT 322 and the UCIe TX interface module 325.

[0079] In RX mode, the programmable RX PMA module 333 can receive serial data and, for example, convert the received serial data into received parallel data according to programmed deserialization settings. The programmable RX PCS module 343 can convert the parallel data received from the programmable RX PMA module 333 into received serial data according to the RXIMA_PCS interface settings.

[0080] In RX mode, the RX clock management module 351 is operatively coupled to the programmable RX PMA module 333 and the programmable RX PCS module 343. The RX clock management module 351 generates the RX clock (the clock generated by the transceiver) and sends the RX clock to the chiplet 310. The RX clock management module 351 performs clock phase adjustment, for example, by using one or more built-in PIs in the PLL.

[0081] Return to reference Figure 2B In block 222, the transceiver on the first chip generates a clock, which is the RX output clock (RXOUTCLK) when the transceiver is in RX mode.

[0082] refer to Figure 3B In RX mode, the RX clock management module 351 of GT 322 on chiplet 320 generates RXOUTCLK 353 and provides RXOUTCLK to the UCIe TX interface module 325 of chiplet 320.

[0083] like Figure 3BAs shown, the VCO clock is provided to the RX PMA PI and ProgDiv in the RX clock management module 351. The VCO clock may be based on one or more reference clocks received by the GT 322. The one or more reference clocks may include, but are not limited to, an external clock, the internal clock of the GT 322, and / or the system clock. The RX PMA PI receives the VCO clock and provides a clock (e.g., a phase-aligned clock) to the dual clock generator. The dual clock generator provides two clock signals to the programmable RX PMA module 333 and provides the RX PCS CLK to the programmable RX PCS module 343. The ProgDiv divides the VCO clock and provides the divided VCO clock to the RX DA PI. The RX DA PI performs instantaneous phase alignment and compensates for phase changes in RXOUTCLK 353 caused by, for example, voltage, temperature, and / or crystal variations.

[0084] In one example, the RXOUTCLK 353 has a frequency of 2.8 GHz. The frequency of the RXOUTCLK 353 can be related to the data line rate of the GT322. In other examples, the frequency of the RXOUTCLK 353 may be higher or lower than 2.8 GHz.

[0085] Return to reference Figure 2B In block 224, the transceiver provides RXOUTCLK from the first C2C interface module of the first chiplet to the second C2C interface module of the second chiplet via one or more clock transmission lines (e.g., UCIe module TXCKP / TXCKN clock transmission lines as defined in the current UCIe interface specification), wherein RXOUTCLK is used as the TX clock (TXCLK) by the first C2C interface.

[0086] refer to Figure 3B The GT 322 transmits the RXOUTCLK 353 from the UCIe TX interface module 325 of chiplet 320 to the UCIe RX interface module 315 of chiplet 310 via the UCIe module TXCKP / TXCKN clock transmission line 394. For example... Figure 3B As illustrated, RXOUTCLK 353 is not altered by any of the PHY, D2D adapter, or protocol layer of the UCIe TX interface module 325 before it is sent to the UCIe RX interface module 315 of chiplet 310. Therefore, the characteristics of RXOUTCLK 353 are maintained in system 300B because RXOUTCLK 353 is sent directly from chiplet 320 to chiplet 310 via the UCIe interface module without being converted to a UCIe PHY clock.

[0087] Return to reference Figure 2BIn block 226, the first chiplet generates a first logic clock (LCLK) locally from RXOUTCLK, and provides the first LCLK and RXOUTCLK as the first PHY clock (PHYCLK) to the first PHY layer of the first C2C interface module.

[0088] refer to Figure 3B RXOUTCLK 353 (e.g., 2.82 GHz) is provided to divider 357 in UCIe TX interface module 325. Divider 357 locally generates a first logic clock (e.g., LCLK) on chiplet 320 by dividing RXOUTCLK 353 by N (e.g., N=4), and provides LCLK (e.g., 705 MHz) to UCIe PHY layer 381 of UCIe TX interface module 325. Divider 357 also provides RXOUTCLK 353 as the first PHY clock (PHYCLK) (e.g., 2.82 GHz) to UCIe PHY layer 381 of UCIe TX interface module 325. It should be understood that although in Figure 3B The frequency divider 357 is shown as being included within the UCIeTX interface module 325, but in another example, the frequency divider 357 may be a separate component outside the UCIeTX interface module 325 on the chiplet 320.

[0089] Return to reference Figure 2B In block 228, the first chiplet performs clock phase adjustment by using one or more phase interpolators to ensure synchronized data transmission.

[0090] refer to Figure 3B The divider 357 on chiplet 320 provides LCLK (e.g., 705MHz) to the UCIe PHY layer 381 of UCIe TX interface module 325 and the bit-width scaler in pad 326. Divider 357 also divides RXOUTCLK 353 by N (e.g., N=2) and provides the divided RXOUTCLK 353 (e.g., LCLK×2) to the bit-width scaler in pad 326 and the programmable RX PCS module 343 of GT 322.

[0091] The RX clock management module 351 is operatively coupled to the programmable RX PMA module 333 and the programmable RX PCS module 343, and receives feedback through the programmable RX PCS module 343, thereby forming a PLL (e.g., an LCPLL). Based on the feedback in the PLL, the RX clock management module 351 performs clock phase adjustment (e.g., via RX DA PI) to compensate for phase changes in the RXOUTCLK 353 caused, for example, by voltage, temperature, and / or crystal variations.

[0092] Return to reference Figure 2B In box 230, the second chiplet generates the second LCLK locally from TXCLK, and provides the second LCLK and TXCLK as the second PHY clock (PHYCLK) to the second PHY layer of the second C2C interface module.

[0093] refer to Figure 3B In chiplet 310, the same TXCLK 355 as RXOUTCLK 353 (e.g., 2.82GHz) is provided to divider 363 in UCIe RX interface module 315 on chiplet 310. Divider 363 provides TXCLK 355 as a second PHY clock (e.g., PHYCLK) to UCIe PHY layer 371 of UCIe RX interface module 315. Divider 363 also divides TXCLK 355 by N (e.g., N=4) to generate a logic clock (e.g., LCLK), and provides LCLK (e.g., 705MHz) to UCIe PHY layer 371 of UCIe RX interface module 315. It should be understood that although in Figure 3B The frequency divider 363 is shown as being included within the UCIe RX interface module 315, but in another example, the frequency divider 363 may be a separate component outside the UCIe RX interface module 315 on the chiplet 310.

[0094] Return to reference Figure 2B In block 232, the second chiplet provides the frequency-divided second LCLK (or second LCLK) to the programmable logic on the second chiplet for receiving data using a transceiver protocol implemented in the programmable logic.

[0095] refer to Figure 3B Divider 365 divides LCLK (e.g., 705MHz) by N (e.g., N=2) and provides the divided LCLK (e.g., LCLK÷2) to programmable logic 302. In another example, spacer 316 is optional, in which case LCLK can be provided to programmable logic 302 without division. In this example, deskewing between the UCIe clock domain in chiplet 310 and the programmable logic clock domain can be handled by the AEGG auxiliary clock IP.

[0096] Return to reference Figure 2B In block 234, the first chiplet is based on RXOUTCLK and transmits data from the transceiver to the programmable logic on the second chiplet through the first C2C interface module and the second C2C interface module.

[0097] refer to Figure 3BGT 322 sends data and clock to pad 326. In RX mode, data and clock from pad 326 can bypass at least a portion of the D2D adapter layer 383 of the UCIe TX interface module 325 and the UCIe protocol layer 385. For example, some functions of the UCIe D2D adapter layer 383, such as data integrity checks (e.g., parity and CRC), may not be bypassed. In another example, GT 322 can completely bypass the UCIe protocol layer 385 and the UCIe D2D adapter layer 383 of the UCIe TX interface module 325 to directly provide data and clock to the UCIe PHY layer 381. Bypassing the UCIe protocol layer 385 and the UCIe D2D adapter layer 383 of the UCIe TX interface module 325 reduces data transmission latency.

[0098] exist Figure 3B In the example shown, the bit-width scaler in shim 326 doubles the data width and halves the clock frequency before providing data and clock from GT 322 to UCIe TX interface module 325. In another example, shim 326 is optional, in which case the signals and clock from GT 322 are provided directly to the UCIe PHY layer 381 of UCIe TX interface module 325 without any data width or frequency modulation, thereby further reducing latency.

[0099] Data and clock signals from the UCIe TX interface module 325 of chiplet 320 are received by the UCIe PHY layer 371 of the UCIe RX interface module 315 of chiplet 310. Figure 3B In the example shown, the data received by the UCIe RX interface module 315 is serialized (e.g., 8 to 1 serialization). After deserialization, the parallel data buses can each operate at a lower frequency (e.g., 705 MHz).

[0100] like Figure 3BAs illustrated, in RX mode, data and clock from the UCIe PHY layer 371 of the UCIe RX interface module 315 can bypass at least a portion of the UCIe protocol layer 375 and the UCIe D2D adapter layer 373 of the UCIe RX interface module 315 of the chiplet 310 before being provided to the pad 316. For example, certain functions of the UCIe D2D adapter layer 373, such as data integrity verification functions (e.g., parity check and CRC) may not be bypassed. In another example, the UCIe PHY layer 371 of the UCIe RX interface module 315 can completely bypass the UCIe D2D adapter layer 373 and the UCIe protocol layer 375 of the UCIe RX interface module 315 to provide data and clock directly to the pad 316. Bypassing the UCIe D2D adapter layer 373 and the UCIe protocol layer 375 of the UCIe RX interface module 315 also reduces data transmission latency.

[0101] exist Figure 3B In the example shown, the bit-width scaler in shim 316 halves the clock frequency and doubles the data width before providing data and clock from UCIe RX interface module 315 to programmable logic 302. In yet another example, shim 316 is optional, in which case data and clock from UCIe PHY layer 371 of UCIe RX interface module 315 are provided directly to programmable logic 302 without any data width or frequency modulation, thereby further reducing latency.

[0102] In system 300B, the clock generated by the transceiver (e.g., RXOUTCLK 353) is used as the UCIe PHY clock for data transmission. In other words, the clock generated by GT 322 on chiplet 320 does not need to be converted to a UCIe PHY clock before being provided to the programmable logic 302 residing on chiplet 310. In chiplet 310, the programmable logic 302 receives data from GT 322 using a divided RXOUTCLK 353 (e.g., LCLK÷2). Therefore, the characteristics of RXOUTCLK 353 (e.g., long-term jitter, etc.) are maintained throughout system 300B to ensure synchronous data transmission between the two chipsets.

[0103] Return to reference Figure 2B In block 236, before providing data from the transceivers to the first C2C interface module of the first chiplet, the first chiplet may optionally perform multi-module alignment among two or more transceivers. For example, when the first chiplet includes multiple transceivers, the first chiplet may include alignment circuitry to align the data before providing data from different transceivers to the UCIe interface module.

[0104] In block 238, the second chiplet may optionally perform multichannel alignment before providing data to the programmable logic. For example, when the first chiplet includes multiple transceivers, the second chiplet may include alignment circuitry to align the data received from the UCIe interface module on the second chiplet via different channels before providing the programmable logic.

[0105] Now for reference Figures 4A to 4C , Figure 4A A block diagram 400A illustrates four UCIe interface modules that provide data via four independent GT links or channels, according to an example. Figure 4B Block diagram 400B illustrates four UCIe interface modules combined to provide two independent GT direct links or channels, according to another example. Figure 4C Block diagram 400C illustrates four UCIe interface modules combined to provide a single independent GT direct link or channel, according to yet another example.

[0106] like Figures 4A to 4C As illustrated, UCIe interface modules 425A, 425B, 425C, and 425D (collectively referred to as "UCIe interface module 425") each include a UCIe PHY layer and a UCIe D2D adapter layer. Each UCIe interface module in UCIe interface module 425 may also include a UCIe protocol layer, which... Figures 4A to 4C The example shown is bypassed and therefore omitted for clarity.

[0107] exist Figures 4A to 4C In the example shown, each UCIe interface module in UCIe interface module 425 receives data from GT (not explicitly shown) via four data paths. Data from two or more modules may be aligned by alignment module 476 before being provided to UCIe interface module 425. Figures 4A to 4C In the example shown, the chiplet is in GT direct mode (e.g., where the Protocol Handling Unit (PHU) 478 is not needed and is therefore bypassed). Each UCIe PHY layer in the UCIe PHY layer operates in an 8:1 mode, where each data path is split into 8 data channels. Therefore, each UCIe PHY layer outputs data through 32 data channels.

[0108] Furthermore, each of the UCIe interface modules 425 can receive a different high-speed clock provided by a PLL in its respective GT. The high-speed clock from the GT is used as the UCIe PHY clock. Therefore, a UCIe PLL is not required. The logic clock (LCLK) is generated by dividing the high-speed clock using a divider (e.g., a ÷4 divider) in each of the UCIe interface modules 425.

[0109] like Figure 4A As illustrated, the UCIe interface module 425 can receive data with different data widths and clock frequencies from its corresponding GTs because the GTs may have different channel types or protocols. For example, UCIe interface modules 425A, 425B, 425C, and 425D receive signals at 10Gbps, 26Gbps, 56Gbps, and 112Gbps, respectively. Figure 4A In the example shown, TXCLK has a frequency range of approximately 2.00 GHz to approximately 2.82 GHz. Each data path clock (e.g., LCLK) has a frequency range of approximately 500 MHz to approximately 705 MHz (e.g., 4 data paths per GT).

[0110] like Figure 4A As illustrated, the first GT direct link (e.g., LINK 0) outputs data at 10Gbps through 32 data channels, the second GT direct link (e.g., LINK 1) outputs data at 26Gbps through 32 data channels, the third GT direct link (e.g., LINK 2) outputs data at 56Gbps through 32 data channels, and the fourth GT direct link (e.g., LINK 3) outputs data at 112Gbps through 32 data channels.

[0111] exist Figure 4A In the example shown, since each UCIe interface module in UCIe interface module 425 receives data with different data widths, protocols, and / or clock frequencies, alignment module 476 is not used, thus bypassing the alignment module.

[0112] like Figure 4B As illustrated, UCIe interface modules 425A and 425B receive data with the same data width from their respective GTs. For example, UCIe interface modules 425A and 425B each receive data at 26 Gbps from their respective GTs (not explicitly shown). Furthermore, UCIe interface modules 425A and 425B receive the same high-speed clock TXCLK generated by the LCPLL in each GT. For example, UCIe interface modules 425A and 425B operate at the same clock frequency because the GTs coupled to UCIe interface modules 425A and 425B have the same channel type and protocol. In this example, the LCPLL in UCIe interface modules 425A and 425B is also the same. Additionally, the link control of UCIe interface modules 425A and 425B is also combined; for example, one FDI is designated as the primary FDI, and the other FDI is designated as the secondary FDI. Link control can be provided in parallel to each FDI.

[0113] Similarly, UCIe interface modules 425C and 425D can receive signals of the same width at 56Gbps from their respective GTs (not explicitly shown). Furthermore, UCIe interface modules 425C and 425D receive the same high-speed clock TXCLK generated by the LCPLL in each GT. For example, UCIe interface modules 425C and 425D operate at the same clock frequency because the GTs coupled to UCIe interface modules 425C and 425D have the same channel type and protocol. In this example, the LCPLL in UCIe interface modules 425C and 425D is also the same. Additionally, the link control of UCIe interface modules 425C and 425D is also combined; for example, one FDI is designated as the primary FDI, and the other FDI is designated as the secondary FDI. Link control can be provided in parallel to each FDI.

[0114] exist Figure 4B In the example shown, a framing pattern is added to UCIe interface module 425. Alignment module 476 is used to perform alignment based on the framing pattern. For example, data from the first GT and the second GT are aligned by alignment module 476 before being provided to UCIe interface modules 425A and 425B. UCIe interface modules 425A and 425B are combined together to provide a GT direct link or channel. Furthermore, data from the third GT and the fourth GT are aligned by alignment module 476 before being provided to UCIe interface modules 425C and 425D. UCIe interface modules 425C and 425D are combined together to provide another GT direct link or channel. Thus, the first GT direct link (e.g., LINK 0) outputs data (e.g., phase-aligned data) at 52 Gbps through 64 data channels, and the second GT direct link (e.g., LINK 1) outputs data (e.g., phase-aligned data) at 112 Gbps through 64 data channels.

[0115] like Figure 4C As illustrated, all four UCIe interface modules 425 receive data with the same width from their respective GTs. For example, each UCIe interface module 425 receives data at 112 Gbps from its respective GT (not explicitly shown). Furthermore, the UCIe interface modules 425 receive the same high-speed clock TXCLK generated by the LCPLL in each GT. For example, the UCIe interface modules 425 operate at the same clock frequency because the GTs coupled to the UCIe interface modules 425 have the same channel type and protocol. In this example, the LCPK in all four UCIe interface modules 425 is the same.

[0116] exist Figure 4CIn the example shown, a framing pattern is added to UCIe interface module 425. Alignment module 476 is used to perform alignment based on the framing pattern. For example, data from four GTs is aligned by alignment module 476 before being provided to UCIe interface module 425. The four UCIe interface modules 425 are combined together to provide a single GT direct link or channel. Thus, the GT direct link (e.g., LINK 0) uses 128 data channels to output data (e.g., phase-aligned data) at 448 Gbps. Additionally, the link control of all four UCIe interface modules 425 is also combined; for example, one FDI is designated as the primary FDI, while the remaining FDIs are designated as secondary FDIs. Link control can be provided in parallel to each FDI.

[0117] exist Figures 4A to 4C In the example shown, a UCIe PLL is not required because the UCIe TXCLK in each UCIe interface module of the UCIe interface module 425 is the same as the high-speed clock TXCLK generated by the PLL (e.g., LCPLL) in each GT. Furthermore, in Figures 4A to 4C In the example shown, in GT direct mode, the high-speed clock TXCLK in each UCIe interface module 425 bypasses the UCIe protocol layer and the D2D adapter layer and is sent directly to the UCIe PHY layer. The logic clock (LCLK) in each UCIe interface module can also bypass at least a portion of the D2D adapter layer and the UCIe protocol layer. In another example, the logic clock in each UCIe interface module can be directly supplied to the UCIe PHY layer, completely bypassing the UCIe protocol layer and the D2D adapter layer.

[0118] exist Figures 4A to 4C In the example shown, the high-speed GT clock (e.g., TXCLK) in the UCIe interface module 425 is used throughout the system for various protocols implemented in programmable logic (e.g., the High-Speed ​​Serial Input / Output (HSSIO) protocol). This maintains the clock at parts per million (PPM). Furthermore, latency is further reduced by using the alignment module 476 to provide a synchronous interface connection.

[0119] Now for reference Figures 5A to 5C , Figure 5A A block diagram 500A illustrates four UCIe interface modules that provide data via four independent Ethernet links or channels, as illustrated in the example. Figure 5B A block diagram 500B illustrates four UCIe interface modules combined to provide data over two separate Ethernet links or channels, according to another example. Figure 5C A block diagram 500C illustrates four UCIe interface modules combined to provide data over a single, independent Ethernet link or channel, according to yet another example.

[0120] like Figures 5A to 5C As illustrated, UCIe interface modules 525A, 525B, 525C, and 525D (collectively referred to as "UCIe interface module 525") each include a UCIe PHY layer and a UCIe D2D adapter layer. Each UCIe interface module in UCIe interface module 525 may also include a UCIe protocol layer, which... Figures 5A to 5C The example shown is bypassed and therefore omitted for clarity.

[0121] exist Figures 5A to 5C In the example shown, each UCIe interface module 525 receives data from an Advanced Extensible Interface 4 (AXI4) stream (AXI-S). This data may include two or more Time Division Multiplexing (TMD) stream signals and can be provided to each UCIe interface module 525 via four data paths. Data from two or more modules may be aligned by an alignment module 576 before being provided to the PHU 578. The alignment module 576 may align two or more data paths using alignment logic (e.g., AECG alignment logic). The PHU 578 may perform one or more features, including but not limited to channel redirection (e.g., data word inter-channel redirection), framing (e.g., up to 4 DW framing), error protection (e.g., parity checking), flow control (e.g., a transition between handshake-based flow control at the upper layer and credit-based flow control at the data word level), and clocking (e.g., where the protocol layer assumes a different clock than the PL / hard logic, and where each PHY requires the same clock). Data is then provided from the PHU 578 to the UCIe interface module 525. Each UCIe PHY layer operates in an 8:1 mode, where each data path is divided into 8 data channels. Therefore, each UCIe PHY layer outputs data through 32 data channels.

[0122] In addition, such as Figures 5A to 5C As illustrated, each UCIe interface module in UCIe interface module 525 can receive a data path clock (e.g., DATAPATH_CLK0). In some examples, all data paths use a single clock sourced from ChipMAC or PCIe. In some examples, the AECG PLL is used to provide a logic clock (LCLK) to the UCIe PLL. The UCIe PLL generates the PHY clock.

[0123] like Figure 5AAs illustrated, the AXI-S TMD data provided to the UCIe interface module 525 has different data widths and different clock frequencies because the data may have different channel types or protocols. For example, UCIe interface modules 525A, 525B, 525C, and 525D receive data in 10 Gigabit Ethernet (GE), 25GE, 50GE, and 100GE, respectively.

[0124] exist Figure 5A In the example shown, alignment module 576 is not used because the AXI-S TDM data has different data widths and / or different protocols. Therefore, the AXI-S TDM data is provided to PHU 578. PHU 578 then provides this data to UCIe interface module 525. For example, the data bypasses the UCIe protocol layer ( Figure 5A (Not explicitly shown) is provided to the UCIe D2D adapter layer and UCIe PHY layer of the UCIe interface module 525.

[0125] like Figure 5A As illustrated, the first link (e.g., LINK 0) outputs data at 10GE through 32 data channels, the second link (e.g., LINK 1) outputs data at 25GE through 32 data channels, the third link (e.g., LINK 2) outputs data at 50GE through 32 data channels, and the fourth link (e.g., LINK 3) outputs data at 100GE through 32 data channels.

[0126] like Figure 5B As illustrated, UCIe interface modules 525A and 525B receive AXI-S TMD data with the same data width (e.g., 25GE). UCIe interface modules 525A and 525B receive the same data path clock (e.g., DATAPATH_CLK0). The link control of UCIe interface modules 525A and 525B is also combined; for example, one FDI is designated as the primary FDI and the other as the secondary FDI. Similarly, UCIe interface modules 525C and 525D receive AXI-S TMD data with the same data width (e.g., 100GE). UCIe interface modules 525C and 525D receive the same data path clock (e.g., DATAPATH_CLK0). The link control of UCIe interface modules 525C and 525D is also combined; for example, one FDI is designated as the primary FDI and the other as the secondary FDI.

[0127] exist Figure 5BIn the example shown, a framing pattern is added to UCIe interface module 525. Alignment module 576 is used to perform alignment based on the framing pattern. For example, AXI-S TDM data provided to UCIe interface modules 525A and 525B is aligned by alignment module 576 before being provided to PHU 578. Furthermore, AXI-S TDM data provided to UCIe interface modules 525C and 525D is aligned by alignment module 576 before being provided to PHU 578. Then, PHU 578 bypasses the UCIe protocol layer (… Figure 5B (Not explicitly shown in the text) provides data to the UCIe D2D adapter layer and UCIe PHY layer of the UCIe interface module 525.

[0128] like Figure 5B As illustrated, UCIe interface modules 525A and 525B are combined to provide an Ethernet link (e.g., LINK 0). Additionally, UCIe interface modules 525C and 525D are combined to provide another Ethernet link (e.g., LINK 1). Since each UCIe PHY layer outputs data in 32 data channels, the first Ethernet link (e.g., LINK 0) outputs data (e.g., phase-aligned data) at 50GE through 64 data channels, and the second Ethernet link (e.g., LINK 1) outputs data (e.g., phase-aligned data) at 200GE through 64 data channels.

[0129] like Figure 5C As illustrated, all four UCIe interface modules 525 receive AXI-S TMD data with the same data width (e.g., 100GE) and the same data path clock (e.g., DATAPATH_CLK0). Additionally, the link control of all four UCIe interface modules 525 is also combined; for example, one FDI is designated as the primary FDI, while the remaining FDIs are designated as secondary FDIs.

[0130] exist Figure 5C In the example shown, a framing pattern is added to UCIe interface module 525. Alignment module 576 is used to perform alignment based on the framing pattern. For example, AXI-S TDM data provided to all four UCIe interface modules 525 is aligned by alignment module 576 before being provided to PHU 578. PHU 578 then bypasses the UCIe protocol layer ( Figure 5C (Not explicitly shown in the text) provides data to the UCIe D2D adapter layer and UCIe PHY layer of the UCIe interface module 525.

[0131] like Figure 5CAs illustrated, UCIe interface modules 525A, 525B, 525C, and 525D are combined to provide a single Ethernet link (e.g., LINK 0). Since each UCIe PHY layer outputs data in 32 data channels, the Ethernet link (e.g., LINK 0) outputs data (e.g., phase-aligned data) at 400GE through 128 data channels. In one example, the combined data paths can be aligned to the same clock domain in the programmable logic at frequencies between 350MHz and 500MHz.

[0132] Figure 6 A block diagram of the chip 620 based on the example is shown. Figure 6 In the example shown, chiplet 620 is a GMPC capable of providing multiple connectivity solutions to another chiplet (e.g., an anchor chiplet or another GMPC) via a UCIe interface module. In one implementation, chiplet 620 may substantially correspond to Figure 1A The small chip 120 in it.

[0133] like Figure 6 As illustrated, chiplet 620 includes GT 622A, 622B, 622C, and 622D (collectively referred to as "GT 622") and UCIe interface modules 624A, 624B, 624C, and 624D (collectively referred to as "UCIe interface module 624"). Chiplet 620 also includes a multi-module alignment circuit 676 and a PHU 678 between GT 622 and UCIe interface module 624. GT 622A, 622B, 622C, and 622D are coupled to auxiliary clock modules 680A, 680B, 680C, and 680D (collectively referred to as "auxiliary clock module 680"), respectively.

[0134] The chiplet 620 may also include other hard intellectual property (IP) blocks 674A, 674B, 674C, and 674D (collectively, “Hard IP Block 674”). By way of example only, Hard IP Block 674 may include one or more of the PCIe / CCIXMAC cores associated with the PS and DMA engines and controllers. The chiplet 620 may also include other interfaces, such as PCIe Gen6 AXI-S and DMA AXI-MM interfaces with many possible forked configurations (e.g., x2, x4, x8, x16, or any combination thereof). Figure 6 (Not explicitly shown in the text). In some implementations, the chip 620 may include an Ethernet MAC AXI-S with a variety of possible port configurations (e.g., 10G, 25G, 50G, 100G, 200G, 400G, 800G, 1.6T, etc.).

[0135] In GT direct mode, the GT LCPLL within each GT 622 generates TXOUTCLK or RXOUTCLK. A logic clock (e.g., LCLK1) is generated by an auxiliary clock module 680 associated with each GT 622. For example, LCLK1 can be generated by dividing TXOUTCLK or RXOUTCLK by N (e.g., N=4). LCLK1 can be provided to the UCIe PHY layer of the multi-module alignment circuit 676 and the UCIe interface module 624. While the PHU 678 is bypassed in GT direct mode, in another implementation (e.g., when chiplet 620 is in PHU mode), LCLK1 can also be provided to the PHU 678.

[0136] In GT direct TX mode, the TXOUTCLK is directly provided to the anchor chiplet and used as the TXCLK on the anchor chiplet for sending data to chiplet 620. In GT direct TX mode, data is received by the UCIe PHY layer in each UCIe interface module of UCIe interface module 624 through multiple channels. For example, each UCIe PHY layer can receive data through 32 data channels. Within each UCIe interface module 624, a first-stage de-skew can be performed to align the data before it is passed to a higher level via different data channels. Framing patterns can be added so that the multi-module alignment circuit 676 can align the data between two or more UCIe interface modules in UCIe interface module 624 before the data is transmitted to GT 622 for transmission.

[0137] In GT direct RX mode, RXOUTCLK is provided to the UCIe PHY layer and used directly as the UCIe PHY clock (PHYCLK) in the UCIe interface module 624. Furthermore, data received from two or more GTs in GT 622 can be aligned by the multi-module alignment circuit 676 before being provided to the UCIe interface module 624.

[0138] like Figure 6 As shown, the UCIe D2D adapter layer of each UCIe interface module 624 can provide RXSSCLK to the auxiliary clock module 680. The auxiliary clock module 680 then provides LCLK2 based on RXSSCLK. Each GT 622 can perform clock phase adjustment based on feedback from LCLK2. In another embodiment, the UCIe physical layer of each UCIe interface module 624 can provide RXSSCLK to the auxiliary clock module 680.

[0139] In this embodiment, when PHU 678 is used (e.g., when chiplet 620 is in PHU mode), AECGPLL module 682 generates a PHU mode logic clock (LCLK) and provides the LCLK to PHY PLL module 684 coupled to UCIe interface module 624. PHY PLL module 684 generates a UCIe PHY clock from the LCLK and distributes the UCIe PHY clock to all four UCIe interface modules 624. For example, AECGPLL module 682 may be a Birch PLL and may have the same core as the UCIe PLL module.

[0140] In PHU RX mode, data can be received by GT 622. Multi-module alignment circuitry 676 performs alignment between two or more GTs in GT 622 before data is passed to PHU 678. PHU 678 may include a cross-time-frequency domain (CDC) FIFO buffer for each UCIe interface module in UCIe interface module 624. The CDC FIFO buffer allows data to be transferred from the GT clock domain to the UCIe clock domain. PHU 678 can use one, two, or four data path clocks at the PHU interface. PHU 678 can present 256 bits to the UCIe D2D adapter layer. In some implementations, the PHU interface may have a frequency of 1 GHz. PHU 678 can present 256 bits to each UCIe interface module in UCIe interface module 624.

[0141] In PHU TX mode, data can be received by the UCIe interface module 624 (e.g., from the anchor chiplet) for transmission by the GT 622. The PHU 678 is coupled to the UCIe interface module 624. A CDC FIFO buffer in the PHU 678 allows data to be transferred from the UCIe clock domain to the GT clock domain. Alignment can be achieved using a data pattern added to the flit format. For example, the data presented by the PHU 678 may include a 255-bit payload and one valid bit. In another example, the data alignment pattern presented by the PHU 678 may include a 252-bit payload, one valid bit, and three alignment bits. A multi-module alignment circuit 676 can perform alignment based on the alignment pattern before passing data to the GT 622.

[0142] Figure 7 This is a block diagram of a multi-chiplet IC 700, based on the example, which includes chiplet ICs 710 and 720. (See example...) Figure 7 As illustrated, the chiplet 710 includes programmable logic 712 and a UCIe interface module 714. The programmable logic 712 and the UCIe interface module 714 can respectively correspond to... Figure 1AThe programmable logic 712 and UCIe interface module 714 are omitted for brevity. Chip 710 also includes alignment circuitry 780 between the programmable logic 712 and the UCIe interface module 714. Chip 720 includes GT 722A to 722P (collectively referred to as "GT 722") and UCIe interface module 724. GT 722 and UCIe interface module 724 can respectively substantially correspond to... Figure 1A The details of GT 122 and UCIe interface module 124 are omitted for brevity. Chip 710 also includes alignment circuitry 776 between GT 722 and UCIe interface module 724.

[0143] In this example, chiplet 720 includes 16 GT 722s, each GT having at least one TX channel and at least one RX channel. Therefore, there are at least 32 data channels between chiplets 710 and 720. UCIe interface module 724 includes a UCIe TX interface module and a UCIe RX interface module, respectively coupled to the TX and RX channels of each GT 722. In some implementations, each GT channel can support independent protocols and clocks. For example, the GT 722 in chiplet 720 can generate 16 independent data paths and clocks, and send these data paths and clocks to chiplet 710 and vice versa.

[0144] When GT 722 is in RX mode, alignment circuit 776 performs channel alignment on the data received from GT 722 and then provides the aligned data to UCIe (TX) interface module 724. UCIe (TX) interface module 724 on chiplet 720 sends data to UCIe (RX) interface module 714 on chiplet 710 through 16 data channels.

[0145] In this example, one or more protocols 713 implemented in programmable logic 712 support multi-channel interfaces (e.g., Ethernet, PCIe, etc.) and require channel alignment before data from different channels of UCIe (RX) interface module 714 can be provided to programmable logic 712. For example, chiplets 710 and 720 may need to meet the channel alignment requirements of 800G MAC and PCIe Gen6 controllers. In another example, channel alignment is required in protocols implemented in programmable logic (e.g., HSSIO protocol) for test and measurement purposes or for protocol customization purposes.

[0146] In this example, data from different channels of the UCIe (RX) interface module 714 is provided to the alignment circuit 780, where channel alignment is achieved, for example, through low-skew REFCLK allocation and SERDES bit-slip capability. In this example, the alignment circuit 780 is located adjacent to the UCIe interface module 714. In another example, the alignment circuit 780 may be located within the UCIe interface module 714.

[0147] When GT 722 is in TX mode, alignment circuit 780 performs channel alignment on the data received from protocol 713, and then provides the aligned data to UCIe (TX) interface module 714. UCIe (TX) interface module 714 on chiplet 710 sends data to UCIe (RX) interface module 724 on chiplet 720 via 16 data channels. Data from different channels of UCIe (RX) interface module 724 is sent to alignment circuit 776, and then the aligned data is provided to GT 722.

[0148] Alignment circuits 776 and 780 allow data from the UCIe interface module 714 to meet the channel alignment requirements of certain dedicated transceiver protocols (e.g., Ethernet, PCIe, etc.).

[0149] According to the example implementation, the transceiver-generated clock (e.g., TX and RX clocks) is used as the UCIe PHY clock, instead of using the UCIe module's own clock for inter-chip data transfer. Using the transceiver-generated clock in this manner allows for synchronous data transfer between two chips (e.g., between transceiver circuitry on the first chip and a transceiver protocol implemented in programmable logic on the second chip). To transmit the TX and RX clocks between the two chips, one or more auxiliary clock transmit lines are added to connect the two chips. Furthermore, at least one TX clock pin and at least one RX clock pin are reserved or added to the standard UCIe pinout pattern for directly transmitting and receiving the TX and RX clocks.

[0150] According to another example implementation, a data path that bypasses the UCIe protocol layer and the UCIe D2D adapter layer is used to allow the transceiver data path to connect directly to the UCIe PHY layer. Compared to data transmission through a standard UCIe module, bypassing at least a portion of the UCIe D2D adapter layer and the UCIe protocol layer of the UCIe interface module reduces latency in data transmission. This standard UCIe module employs asynchronous FIFOs and adapter logic, both of which increase data transmission latency.

[0151] According to another example implementation, an alignment circuit layer is added between the UCIe interface module and the transceiver data path channel to allow flexible multi-module alignment. In one example, a data line is assigned as an alignment marker in each UCIe module (e.g., in the UCIe PHY layer), and logic is allocated on the receiver side that detects the marker and delays the faster module to align with the slower module. In another example, when no spare data line is available as an alignment marker within a module, an additional signal is added to the transceiver data path bus to act as an alignment marker to perform alignment at the data path level.

[0152] According to another example implementation, an alignment circuit layer is added between the UCIe interface module and the transceiver protocol implemented in programmable logic to meet the channel alignment requirements of certain protocols.

[0153] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible specific implementations of systems, methods, and computer program products according to various examples of the invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0154] The disclosed technology can also be described through one or more embodiments in the following non-limiting embodiments.

[0155] Example 1. A system comprising: a first chiplet including a first transceiver and a first chiplet-to-chiplet (C2C) interface module; and a second chiplet including a second C2C interface module, wherein the first transceiver is configured to generate a clock, and wherein the clock is transmitted from the first C2C interface module to the second C2C interface module via a clock transmission line for data transmission between the first chiplet and the second chiplet.

[0156] Example 2. The system according to Example 1, wherein: the second chiplet further includes programmable logic circuitry, and the clock is used by a transceiver protocol implemented in the programmable logic circuitry to perform the data transmission between the first chiplet and the second chiplet.

[0157] Example 3. The system according to Example 1, wherein: the clock is a TX clock generated by the first transceiver when the first transceiver is in transmit (TX) mode; and the TX clock is transmitted from the second C2C interface module of the second chiplet back to the first C2C interface module of the first chiplet via another clock transmission line.

[0158] Example 4. According to the system of Example 1, wherein the second chiplet further includes a programmable logic circuit configured to send data in a data path to the physical (PHY) layer of the second C2C interface module, the data path bypassing at least a portion of the die-to-die (D2D) adapter layer and the C2C protocol layer of the second C2C interface module.

[0159] Example 5. According to the system of Example 4, wherein the PHY layer of the first C2C interface module is configured to receive the data in the data path from the PHY layer of the second C2C interface module and send the data to the first transceiver, wherein the data path bypasses at least a portion of the D2D adapter layer and the C2C protocol layer of the first C2C interface module.

[0160] Example 6. The system according to Example 1, wherein: the clock is an RX clock generated by the first transceiver when the first transceiver is in receive (RX) mode; and the physical (PHY) layer of the first C2C interface module is configured to receive data from the first transceiver in a data path that bypasses at least a portion of the die-to-die (D2D) adapter layer and the C2C protocol layer of the first C2C interface module.

[0161] Example 7. The system according to Example 6, wherein: the second chiplet further includes a programmable logic circuit; and the PHY layer of the second C2C interface module is configured to receive the data in the data path from the PHY layer of the first C2C interface module, and send the data to the programmable logic circuit, the data path bypassing at least a portion of the D2D adapter layer and the C2C protocol layer of the second C2C interface module.

[0162] Example 8. The system according to Example 1, wherein: the first chiplet further includes a second transceiver and an alignment circuit; and the alignment circuit is configured to align the data before sending data from the first transceiver and the second transceiver to the first C2C interface module.

[0163] Example 9. The system according to Example 1, wherein: the first chiplet further includes a second transceiver; the second chiplet further includes programmable logic circuitry and alignment circuitry; and the alignment circuitry is configured to align the data before transmitting data from the first transceiver and the second transceiver to the programmable logic circuitry.

[0164] Example 10. A method performed by a system including a first chiplet and a second chiplet, the method comprising: generating a clock by a first transceiver on the first chiplet; transmitting the clock from a first chiplet-to-chiplet (C2C) interface module on the first chiplet to a second C2C interface module on the second chiplet; and using the clock by the second chiplet to perform data transmission between the first chiplet and the second chiplet.

[0165] Example 11. According to the method of Example 10, the method further includes: when the first transceiver is in transmit (TX) mode, sending the clock from the second C2C interface module of the second chip back to the first C2C interface module of the first chip; and wherein the clock is a TX clock generated by the first transceiver when the first transceiver is in the TX mode.

[0166] Example 12. According to the method of Example 11, the method further includes: sending data in the data path to the physical (PHY) layer of the second C2C interface module by the programmable logic circuit on the second chip, the data path bypassing at least a portion of the die-to-die (D2D) adapter layer and the C2C protocol layer of the second C2C interface module.

[0167] Example 13. According to the method of Example 12, the method further includes: receiving the data in the data path from the PHY layer of the second C2C interface module by the PHY layer of the first C2C interface module; and sending the data in the data path to the first transceiver by the PHY layer of the first C2C interface module, wherein the data path bypasses at least a portion of the D2D adapter layer and the C2C protocol layer of the first C2C interface module.

[0168] Example 14. According to the method of Example 10, the method further includes: when the first transceiver is in receive (RX) mode, the physical (PHY) layer of the first C2C interface module receives data in a data path from the first transceiver, the data path bypassing at least a portion of the die-to-die (D2D) adapter layer and the C2C protocol layer of the first C2C interface module, wherein the clock is an RX clock generated by the first transceiver when the first transceiver is in the RX mode.

[0169] Example 15. According to the method of Example 14, the method further includes: receiving the data in the data path from the PHY layer of the first C2C interface module by the PHY layer of the second C2C interface module; and sending the data in the data path to the programmable logic circuit on the second chiplet by the PHY layer of the second C2C interface module, the data path bypassing at least a portion of the D2D adapter layer and the C2C protocol layer of the second C2C interface module.

[0170] Example 16. According to the method of Example 10, the method further includes: aligning the data before sending data from the first transceiver and the second transceiver of the first chip to the first C2C interface module.

[0171] Example 17. The method according to Example 10, the method further comprising: aligning the data before transmitting data from the first transceiver and the second transceiver of the first chiplet to programmable logic circuitry on the second chiplet.

[0172] Example 18. A chiplet, the chiplet comprising: a transceiver; and a chiplet-to-chiplet (C2C) interface module, wherein the transceiver is configured to send a clock generated by the transceiver to another chiplet via the C2C interface module for data transmission.

[0173] Example 19. The chiplet according to Example 18, wherein: the C2C interface module includes a physical (PHY) layer, a die-to-die (D2D) adapter layer and a C2C protocol layer; and the transceiver is configured to send or receive data in a data path between the transceiver and the PHY layer of the C2C interface module, the data path bypassing at least a portion of the D2D adapter layer and the C2C protocol layer.

[0174] Example 20. The chiplet according to Example 18, the chiplet further includes: another transceiver; and alignment circuitry, wherein the alignment circuitry is configured to align the data before sending data from the transceiver and the other transceiver to the C2C interface module.

[0175] While the foregoing describes specific embodiments, other and additional examples may be devised without departing from the basic scope of the invention, the scope of which is defined by the appended claims.

Claims

1. A system comprising: The first chiplet includes a first transceiver and a first chiplet-to-chiplet (C2C) interface module; and The second small chip includes a second C2C interface module. The first transceiver is configured to generate a clock, and The clock is transmitted from the first C2C interface module to the second C2C interface module via a clock transmission line for data transmission between the first chiplet and the second chiplet.

2. The system according to claim 1, wherein: The second chip also includes programmable logic circuitry, and The clock is used by a transceiver protocol implemented in the programmable logic circuit to perform the data transmission between the first chiplet and the second chiplet.

3. The system according to claim 1, wherein: The clock is a TX clock generated by the first transceiver when the first transceiver is in transmit (TX) mode; and The TX clock is sent from the second C2C interface module of the second chip back to the first C2C interface module of the first chip via another clock transmission line.

4. The system of claim 1, wherein the second chiplet further comprises a programmable logic circuit configured to send data in a data path to the physical (PHY) layer of the second C2C interface module, the data path bypassing at least a portion of the die-to-die (D2D) adapter layer and the C2C protocol layer of the second C2C interface module.

5. The system of claim 4, wherein the PHY layer of the first C2C interface module is configured to receive the data in the data path from the PHY layer of the second C2C interface module and send the data to the first transceiver, the data path bypassing at least a portion of the D2D adapter layer and the C2C protocol layer of the first C2C interface module.

6. The system according to claim 1, wherein: The clock is the RX clock generated by the first transceiver when the first transceiver is in receive (RX) mode; and The physical (PHY) layer of the first C2C interface module is configured to receive data from the first transceiver in a data path that bypasses at least a portion of the die-to-die (D2D) adapter layer and the C2C protocol layer of the first C2C interface module.

7. The system according to claim 6, wherein: The second chip also includes programmable logic circuitry; and The PHY layer of the second C2C interface module is configured to receive the data in the data path from the PHY layer of the first C2C interface module and send the data to the programmable logic circuit, wherein the data path bypasses at least a portion of the D2D adapter layer and the C2C protocol layer of the second C2C interface module.

8. The system according to claim 1, wherein: The first chip also includes a second transceiver and an alignment circuit; and The alignment circuit is configured to align the data before sending data from the first transceiver and the second transceiver to the first C2C interface module.

9. The system according to claim 1, wherein: The first chip also includes a second transceiver; The second chip also includes programmable logic circuitry and alignment circuitry; and The alignment circuit is configured to align the data before sending data from the first transceiver and the second transceiver to the programmable logic circuit.

10. A small chip, the small chip comprising: transceiver; and Chip-to-chip (C2C) interface modules, wherein the transceiver is configured to send a clock generated by the transceiver to another chip via the C2C interface module for data transmission.

11. The chiplet according to claim 10, wherein: The C2C interface module includes a physical (PHY) layer, a die-to-die (D2D) adapter layer, and a C2C protocol layer; and The transceiver is configured to send or receive data in a data path between the transceiver and the PHY layer of the C2C interface module, the data path bypassing at least a portion of the D2D adapter layer and the C2C protocol layer.

12. The chiplet according to claim 10, further comprising: Another transceiver; and An alignment circuit, wherein the alignment circuit is configured to align the data before sending data from the transceiver and the other transceiver to the C2C interface module.

13. A method performed by a system including a first chiplet and a second chiplet, the method comprising: The clock is generated by the first transceiver on the first chip; The clock is sent from the first chiplet-to-chiplet (C2C) interface module on the first chiplet to the second C2C interface module on the second chiplet; as well as The second chip uses the clock to perform data transmission between the first chip and the second chip.

14. The method of claim 13, further comprising at least one or more of the following: (A) When the first transceiver is in transmit (TX) mode, the clock is sent from the second C2C interface module of the second chip back to the first C2C interface module of the first chip; and The clock mentioned above is the TX clock generated by the first transceiver when the first transceiver is in the TX mode; (B) When the first transceiver is in receive (RX) mode, the physical (PHY) layer of the first C2C interface module receives data in the data path from the first transceiver, the data path bypassing at least a portion of the die-to-die (D2D) adapter layer and the C2C protocol layer of the first C2C interface module, wherein the clock is an RX clock generated by the first transceiver when the first transceiver is in the RX mode; (C) The PHY layer of the second C2C interface module receives the data in the data path from the PHY layer of the first C2C interface module; as well as The PHY layer of the second C2C interface module sends the data in the data path to the programmable logic circuit on the second chiplet, and the data path bypasses at least a portion of the D2D adapter layer and the C2C protocol layer of the second C2C interface module. (D) Aligning the data before sending the data from the first transceiver and the second transceiver from the first chiplet to the first C2C interface module; and (E) Align the data before sending the data from the first transceiver and the second transceiver of the first chiplet to the programmable logic circuit on the second chiplet.

15. The method of claim 13, further comprising: When the first transceiver is in transmit (TX) mode, the clock is sent from the second C2C interface module of the second chip back to the first C2C interface module of the first chip, wherein the clock is the TX clock generated by the first transceiver when the first transceiver is in the TX mode; as well as The programmable logic circuit on the second chip sends data in the data path to the physical (PHY) layer of the second C2C interface module, the data path bypassing at least a portion of the die-to-die (D2D) adapter layer and the C2C protocol layer of the second C2C interface module.

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