Improved doping for super junction devices

Abstract

A method of forming a semiconductor includes forming a super junction structure including a plurality of super junction pillars alternating in a conductivity type along a lateral direction of a semiconductor substrate; and forming a plurality of transistor cells in the active region of the semiconductor substrate, each of the transistor cells configured to control a vertical current flowing through the super junction structure, where forming the transistor cells includes forming a source region and a body region below the source region; wherein forming the body region includes forming a body layer extending from a main surface of the semiconductor substrate, in which a dopant distribution of the second conductivity type dopant in the body layer increases as the dopant distribution moves from the main surface into the semiconductor substrate until the dopant distribution reaches a maximum at a first depth from the main surface, and in which the second conductivity type dopant in the body layer reaches a maximum at a second depth from the main surface. The first depth is lower than a bottom depth of the source region.

Description

Background Technology

[0001] Power semiconductor devices conduct high load currents and withstand high blocking voltages. A superjunction device is a power semiconductor device comprising a superjunction structure with oppositely doped pillars formed in a drift region electrically arranged in series with the controllable device channel. When a blocking voltage is applied to a device in a superjunction configuration, a lateral electric field rises and clears mobile charge carriers along the vertical pn junction between the oppositely doped pillars. Space charge begins to extend perpendicular to the direction of load current flow in the on-state. Mobile charge carriers are completely driven out of the superjunction structure at relatively low blocking voltages. As the blocking voltage increases further, the depleted superjunction structure acts as a quasi-intrinsic layer, and the vertical electric field rises. The breakdown voltage is decoupled from the dopant concentration in the superjunction structure, allowing for relatively high dopant concentrations. Therefore, superjunction devices typically combine very low on-state resistance with high blocking capability. The higher the dopant concentration matching between the oppositely doped pillars, the higher the efficiency of the superjunction structure in terms of blocking capability and semiconductor volume.

[0002] There is a need to improve superjunction devices and the technologies used to form superjunction devices. Summary of the Invention

[0003] According to an embodiment, a method of forming a semiconductor device includes: forming a semiconductor substrate having a superjunction structure, the superjunction structure including a plurality of superjunction pillars alternating in conductivity type along a lateral direction of the semiconductor substrate; and forming a plurality of transistor cells in an active region of the semiconductor substrate, each transistor cell being configured to control a vertical current flowing through the superjunction structure, wherein forming the transistor cells includes: forming a source region extending to a main surface of the semiconductor substrate and a body region at least partially below the source region, the source region being a first conductivity type region and the body region being a second conductivity type region; wherein forming the body region includes: forming a body layer extending from the main surface of the semiconductor substrate, wherein the dopant distribution of a second conductivity type dopant in the body layer increases as it moves from the main surface into the semiconductor substrate until the dopant distribution reaches a maximum value at a first depth from the main surface, and wherein the first depth is lower than the bottom depth of the source region.

[0004] According to another embodiment, a method of forming a semiconductor device includes: forming a semiconductor substrate having a superjunction structure, the superjunction structure including a plurality of superjunction pillars alternating in conductivity type along a lateral direction of the semiconductor substrate; forming a plurality of transistor cells in an active region of the semiconductor substrate, each transistor cell being configured to control a vertical current flowing through the superjunction structure, wherein forming the transistor cells includes forming a plurality of gate trenches in a main surface of the semiconductor substrate, forming a body region adjacent to the gate trenches, and forming a body enhancement region laterally spaced from the gate trenches, the body enhancement region having a higher concentration of a second conductivity type dopant than the body region, wherein forming the body region and forming the body enhancement region includes: forming a body layer extending from the main surface into the semiconductor substrate and having a reference second conductivity type dopant throughout the body layer; and forming a partially compensated region of the body layer, wherein the reference second conductivity type dopant is partially compensated by a first conductivity type dopant, wherein the body enhancement region is provided by an uncompensated portion of the body layer having the reference second conductivity type dopant, and wherein the body region is formed by the partially compensated region of the body layer.

[0005] According to an embodiment, a semiconductor device includes: a semiconductor substrate having a superjunction structure, the superjunction structure including a plurality of superjunction pillars alternating in conductivity type along a lateral direction of the semiconductor substrate; and a plurality of transistor cells in an active region of the semiconductor substrate, each transistor cell being configured to control a vertical current flowing through the superjunction structure, wherein each transistor cell includes a source region extending to a main surface of the semiconductor substrate and a body region at least partially below the source region, the source region being a first conductivity type region and the body region being a second conductivity type region; wherein, for each body region, the dopant distribution of a second conductivity type dopant increases as it moves from the main surface into the semiconductor substrate until the dopant distribution reaches a maximum value at a first depth from the main surface, and wherein the first depth is below the bottom depth of the source region.

[0006] According to another embodiment, a semiconductor device includes: a semiconductor substrate having a superjunction structure, the superjunction structure including a plurality of superjunction pillars alternating in conductivity type along a lateral direction of the semiconductor substrate; and a plurality of transistor cells in an active region of the semiconductor substrate, each transistor cell being configured to control a vertical current flowing through the superjunction structure; and a body layer extending from a main surface of the semiconductor substrate in the active region and having a reference second conductivity type doping, wherein the transistor cells include a plurality of gate trenches in the main surface of the semiconductor substrate, a body region adjacent to the gate trenches, and a body enhancement region laterally spaced from the gate trenches, the body enhancement region having a higher second conductivity type dopant concentration than the body region, wherein the body enhancement region is formed by a portion of the body layer having reference second conductivity type doping, and wherein the body region is formed by a partial compensation region of the body layer, wherein the reference second conductivity type doping is partially compensated by a first conductivity type dopant. Attached Figure Description

[0007] The elements in the accompanying drawings are not necessarily drawn to scale relative to each other. The same reference numerals denote corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail below.

[0008] Figure 1 A power semiconductor device with a superjunction configuration according to an embodiment is shown.

[0009] Figure 2 A detailed view of the upper part of a transistor cell from a power semiconductor device with a superjunction configuration according to an embodiment is shown.

[0010] Figure 3 A plan view layout of the gate trench and doped semiconductor region according to an embodiment is shown.

[0011] include Figure 4A , Figure 4B and Figure 4C Figure 4 illustrates selected method steps in a method for forming a semiconductor device according to an embodiment.

[0012] Figure 5 A detailed view of the upper part of a transistor cell from a power semiconductor device with a superjunction configuration according to another embodiment is shown.

[0013] Figure 6 A plan view layout of the gate trench and doped semiconductor region according to another embodiment is shown.

[0014] include Figure 7A , Figure 7B and Figure 7C Figure 7 illustrates selected method steps in a method for forming a semiconductor device according to another embodiment. Detailed Implementation

[0015] refer to Figure 1 The image depicts a power semiconductor device 100 configured with a superjunction according to an embodiment. The semiconductor device 100 is formed in a semiconductor body 102. The semiconductor body 102 may be formed of a single-crystal semiconductor material, such as silicon (Si), silicon carbide (SiC), germanium (Ge), silicon-germanium crystal (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), etc. The semiconductor body 102 includes a main surface 104 and a back surface 106 opposite to the main surface 104, each of which may be a substantially flat surface.

[0016] Semiconductor device 100 is configured as a superjunction device. Examples of superjunction device corresponding techniques for forming semiconductor superjunction device structures are disclosed in U.S. Patents 10,084,038B2, 10,468,479B2, 11,211,483B2, and 11,329,126B2, the contents of which are incorporated herein by reference in their entirety. Superjunction devices are also referred to as compensation devices. The compensation principle is based on the mutual compensation of charges in the n-doped and p-doped regions (also commonly referred to as n-doped and p-doped pillars or pillar regions) in the drift region of a vertical transistor device (e.g., a vertical MOSFET). For this purpose, semiconductor device 100 includes a superjunction structure having a plurality of superjunction pillars 110 disposed within the active region of a semiconductor body 102. The superjunction pillars 110 alternate in conductivity type along the lateral direction of the semiconductor body 102. In other words, the superjunction structure includes first conductivity type pillars 112 and second conductivity type pillars 114 arranged alternately with each other along the lateral direction of the semiconductor body 102, wherein the second conductivity type pillars 114 have a conductivity type opposite to that of the first conductivity type pillars 112. For example, the first conductivity type pillars 112 may be n-type pillars, and the second conductivity type pillars 114 may be p-type pillars. The superjunction pillars 110 may be regularly spaced apart from each other at a pre-selected spacing. Each superjunction pillar 110 may be elongated in the plan view and may have a strip form extending into the plane of the drawing.

[0017] Generally, the semiconductor device 100 can be configured as any type of vertical power semiconductor device 100, such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT, diode, etc. In the following description, the semiconductor device 100 is configured as a MOSFET. Therefore, when referring to the first and second load terminal regions of the device (i.e., the regions that conduct load current and maintain blocking voltage), this application uses the terms "source" and "body". In different device configurations, different terms may be used to describe the corresponding first and second load terminal regions of the device; that is, in the case of an IGBT, the emitter and collector may correspond to the first and second load terminal regions, and in the case of a diode, the anode and cathode may correspond to the first and second load terminal regions. Furthermore, those skilled in the art will recognize that different device configurations can be achieved by appropriately modifying the cell structure; for example, an IGBT can be achieved by providing a doped contact layer having a conductivity type opposite to the drift region at the back surface 106 of the device, and a diode can be achieved by omitting the gate structure and / or the source region. The concepts disclosed below and the benefits derived therefrom are equally applicable to any of these variations of the superjunction configuration device.

[0018] Semiconductor device 100 includes a plurality of transistor cells formed within an active region of a semiconductor substrate. The active region may be surrounded by edges or termination regions that do not contain active transistor cells. Figure 1 In the view, the edge or termination region is not visible. Edge termination may include one or more features designed to relax the electric field at the lateral chip edge and prevent breakdown.

[0019] Semiconductor device 100 includes a body layer 116 extending from a main surface 104 of a semiconductor substrate into a semiconductor body 102. The body layer 116 is a second conductivity type layer (e.g., a p-type layer) forming the body region of each transistor cell. Semiconductor device 100 includes a first conductivity type (e.g., n-type) source region 118 extending from the main surface 104 and disposed above the body region. Semiconductor device 100 includes a gate structure 120 for each transistor cell. Gate structure 120 includes a gate trench 121 extending into the main surface 104 of the semiconductor substrate. Each gate trench 121 includes a conductive gate electrode 122 and a gate dielectric 124 electrically insulating the gate electrode 122 from adjacent semiconductor material. In a known manner, the gate electrode 122 is configured to control a channel in the body region, and thereby control a vertical current flowing between the main surface 104 and the back surface 106 of the semiconductor substrate.

[0020] The source region 118 and body region of semiconductor device 100 can be electrically connected to a source potential electrode (not shown) formed on the main surface 104 of semiconductor substrate 102. This electrical connection can be achieved by body contacts (not shown) extending into the main surface 104 of semiconductor substrate 102. These body contacts are formed in body contact trenches that form an ohmic connection with body layer 116 and source region 118. Semiconductor device 100 includes a body enhancement region 126 formed below the body contact trench. Body enhancement region 126 is a second conductivity type region having a higher dopant concentration than the dopant concentration of the underlying body layer 116, thereby promoting low-ohmic contact with the body contacts. Gate electrodes 122 can each be electrically connected to a gate potential electrode (not shown) formed on the main surface 104 of semiconductor substrate 102. The drain region of the device can be provided by a first conductivity type layer at the back surface 106 of semiconductor substrate 102 and electrically connected to a drain potential electrode (not shown).

[0021] A superjunction structure including superjunction pillar 110 is disposed below the source region 118 and body region of the transistor cell. The superjunction structure is configured such that, in the off-state of the device, the charges of the superjunction pillar 110 can mutually deplete, and in the active or on-state, an uninterrupted low-ohmic conductive path is formed between the source potential electrode at the main surface 104 and the drain potential electrode at the back surface 106. Due to the compensation of p-type and n-type dopants in the superjunction pillar 110 of the superjunction structure, the doping of the current-carrying region is increased, which significantly reduces the on-state resistance Ron, despite a reduction in the current-carrying area.

[0022] The superjunction pillar 110 can be formed by sequentially epitaxially depositing multiple layers onto a substrate (e.g., a silicon single crystal) to construct a semiconductor body 102, and by forming a laterally alternating stack of discrete regions of the same conductivity type by forming discrete doped regions including donors or acceptors in each layer; that is, the stack of discrete regions containing donors is staggered with the stack of discrete regions containing acceptors. A pillar of a specific conductivity type is formed from the stack of discrete regions through a subsequent diffusion process. To ensure that the superjunction pillars 110 of opposite conductivity types deplete each other in the off-state, the doping concentrations of the superjunction pillars 110 of opposite conductivity types can be selected to be the same or at least within a nearly the same range. In an embodiment, the doping concentration of the superjunction pillars 110 within the active region of the device is set to be as close as practically achievable by the fabrication technology.

[0023] refer to Figure 2The figure shows a detailed view of a transistor cell from a semiconductor device 100 according to an embodiment. The figure illustrates a region containing a body layer 116 between two gate trenches 121. According to an embodiment, the body layer 116 is configured such that the dopant distribution of a second conductivity type dopant in the body layer 116 increases as it moves from the main surface 104 into the semiconductor substrate 102, until the dopant distribution reaches a maximum at a first depth D1 from the main surface 104. The vertical dopant distribution of the second conductivity refers to the absolute concentration of the second conductivity type dopant extending in a direction perpendicular to the main surface 104. In this embodiment, the second conductivity type dopant reaches a peak concentration at its maximum value and decreases in two vertical directions away from the maximum value at the first depth D1.

[0024] According to an embodiment, the first depth D1 is set below the bottom depth of the source region 118. The bottom depth of the source region 118 refers to the deepest location within the semiconductor substrate 102 that includes the first conductivity type dopant used to form the source region 118. This arrangement of the maximum value of the second conductivity type dopant in the body region originates from the body layer 116 implantation technique, which will be described in further detail below. This technique utilizes an initial high-energy implantation step performed before the formation of the gate trench 121 to perform body layer 116 implantation. This initial high-energy implantation is intended to provide the maximum concentration of the second conductivity type dopant at a location corresponding to the location where the channel of the device is formed. In comparison, prior art involves implanting dopant atoms for the body layer 116 after the formation of the gate trench 121 and at a lower implantation energy. In these techniques, annealing is used to diffuse the second conductivity type dopant from a shallower location to produce the desired body region dopant concentration adjacent to the gate trench 121. In this case, the maximum value of the second conductivity type dopant appears closer to the surface of the substrate and not below the bottom of the source region 118.

[0025] refer to Figure 3 The figure shows a plan view of a semiconductor device 100 according to an embodiment. As shown, the gate trench 121 includes elongated segments extending parallel to each other. These elongated segments can be formed into a strip pattern, wherein each elongated gate trench corresponds to a transistor cell in a transistor cell. Additionally, the semiconductor device 100 is configured with vertical segments of the gate trench 121 that extend perpendicularly to the elongated segments and form a connection between two adjacent elongated segments. These vertical segments can be provided to improve the uniformity of the gate signal distribution.

[0026] Figure 3A planar layout of the source region 118 and body enhancement region 126 near the vertical segment of the gate trench 121 is shown. It can be seen that the body enhancement region 126, having a higher concentration of second conductivity type dopant than the body region of the device, extends beyond the source region 118 and is closer to the vertical segment of the gate trench 121. By bringing the body enhancement region 126 close to the vertical segment, this increases the effective threshold voltage adjacent to the vertical segment and the corner between the vertical segment and the elongated segment. In an embodiment, the body enhancement region 126 may contact the vertical segment of the gate trench 121. In particular, the body enhancement region 126 may contact the corner between the vertical segment and the elongated segment.

[0027] refer to Figure 4A The method for forming semiconductor device 100 includes forming a semiconductor body 102 having a superjunction structure. As described above, the superjunction structure can be formed by multiple epitaxial / multiple implantation processes, wherein multiple epitaxial layers are grown, dopants are implanted into the surface of the epitaxial layers, and the process is repeated. Subsequently, a square-shaped intrinsically doped epitaxial layer can be formed on the superjunction pillar 110, thereby forming a semiconductor material extending to the main surface 104 of the semiconductor body 102.

[0028] After providing the semiconductor substrate 102 with a superjunction structure, a first implantation step for forming a body layer 116 is performed. The first implantation step includes unmasked implantation of dopant atoms into the main surface 104 of the semiconductor substrate 102, wherein the dopant atoms used form a second conductive dopant in the semiconductor substrate 102. For example, the first implantation step may include implanting boron or gallium, which acts as a p-type dopant in silicon and other type IV semiconductor materials. The implantation energy of the first implantation step is selected such that the implanted dopant atoms nominally reach a target depth corresponding to a first depth D1, where, as described above, the dopant maximum of the body layer 116 exists at the first depth D1. Therefore, after the first implantation step, the semiconductor substrate 102 includes a high concentration of the second conductive dopant arranged substantially along a thin layer or plane within the semiconductor substrate 102 at the first depth D1.

[0029] refer to Figure 4B After performing the first implantation step, a gate structure 120 of the transistor cell is formed. Forming the gate structure 120 includes forming a gate trench 121 extending from the main surface 104 of the semiconductor substrate 102. This can be accomplished, for example, by a mask etching technique. Subsequently, a deposition step is performed to form a gate dielectric 124 in the gate trench 121. For example, silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiO2) can be deposited along the sidewalls of the gate trench 121. X N YThe dielectric material is then deposited. Subsequently, a deposition step is performed to form the gate electrode 122 in the gate trench 121. For example, a polysilicon layer can be deposited using a low-pressure chemical vapor deposition (LPCVD) tetraethoxysilane (TEOS) process. Polishing steps such as chemical mechanical polishing (CMP) can be performed to remove the deposited dielectric material and polysilicon material from the main surface 104 of the semiconductor body 102.

[0030] refer to Figure 4C After forming the gate structure 120 of the transistor cell, a further dopant implantation step can be performed to form a doped region of the semiconductor device 100. Specifically, a second implantation step can be performed after forming the gate trench 121 to form the source region 118. For example, as referenced... Figure 2 The second implantation step may include selectively implanting dopant atoms into the region corresponding to the location of the source region 118. For example, the second implantation step may be performed using a mask implantation technique. The dopant atoms implanted via the second implantation may be a first conductivity type dopant in the semiconductor material of the semiconductor substrate 102, such as arsenic or phosphorus in the case of a silicon substrate. The target implantation depth of the second implantation step may be shallower than the implantation depth of the first implantation step. Therefore, after dopant activation, the maximum concentration of the first conductivity type dopant from the source region 118 appears above the maximum concentration of the second conductivity type dopant from the body layer 116. Additionally, a third implantation step may be performed after forming the gate trench 121 to form the body enhancement region 126. This third implantation step may include selectively implanting dopant atoms into the region corresponding to the location of the body enhancement region 126. The third implantation step may be performed after forming the body contact trench, causing the dopant atoms to accumulate directly below the bottom of the body contact. The dopant atoms implanted via the third implantation step may be a second conductivity type dopant in the semiconductor material of the semiconductor substrate 102, such as boron or gallium in the case of a silicon semiconductor substrate 102.

[0031] Following the second and third implantation steps, multiple thermal processing steps may be performed. These thermal processing steps may include one or more dedicated annealing steps to diffuse and activate dopant atoms. In particular, long-duration annealing steps may be performed at relatively low temperatures, and rapid thermal annealing processes with shorter durations may be performed at higher temperatures. These thermal processing steps may also include deposition steps for forming a dielectric layer (e.g., a passivation layer, an interlayer dielectric layer, etc.) on the main surface 104 of the semiconductor substrate 102.

[0032] The aforementioned technique advantageously minimizes the thermal budget applied to the semiconductor substrate 102 after the formation of the superjunction structure. In this way, the technique facilitates the achievement of higher cell pitches, i.e., a more closely spaced arrangement of the superjunction pillars 110. By performing a high-energy implantation step prior to the formation of the gate trench 121 to implant dopant atoms of the body layer 116 deeper into the semiconductor body 102, subsequent thermal processing steps used to simultaneously form additional features of the semiconductor device 100 (i.e., features other than the body layer 116) can be used to activate and outward diffuse the dopant atoms of the body layer 116, thereby achieving efficient utilization of the thermal budget. In particular, the dopant atoms implanted through the first implantation step can be activated and outward diffused at least partially through the deposition steps used to form the gate dielectric 124 and the gate electrode 122. Additional thermal processing steps performed after the formation of the gate structure 120 can also contribute to the diffusion and activation of dopant atoms in the body layer 116. These additional thermal processing steps may include annealing steps performed after the second and third implantation steps, whereby dopant atoms from each of these implantation steps are simultaneously diffused and activated. These additional heat treatment steps may also include subsequent heat treatment steps, such as a thermal deposition step for forming a dielectric layer (e.g., passivation layer, interlayer dielectric, etc.) on the main surface 104 of the semiconductor substrate 102.

[0033] The above-described technique can advantageously maintain the thermal budget applied to the semiconductor substrate 102 after the formation of the superjunction structure at no more than 1050°C, or no more than 1100°C, or an equivalent thermal budget. The following is an exemplary description of a heat treatment step that can be performed after the first implantation step while maintaining the thermal budget within this constraint. In an embodiment, the sacrificial oxide layer can be formed (and subsequently removed) by performing a thermal oxidation process at a temperature of no more than 1000°C and about 950°C for a duration of no more than 180 minutes. The gate dielectric 124 can be formed by a two-step process, wherein a relatively thin (e.g., 5-10 nm thick) silicon dioxide layer is deposited by the performed thermal oxidation process, and an additional thickness (e.g., a 75-125 nm thick silicon dioxide layer) is formed by a low-pressure chemical vapor deposition (LPCVD) tetraethoxysilane (TEOS) process. The gate dielectric 124 can be compressed by an annealing step performed at a temperature of about 1000°C. Subsequently, gate polysilicon can be formed by, for example, LPCVD or plasma-enhanced chemical vapor deposition (PECVD) performed at temperatures between approximately 550°C and 650°C. After the second and third implantation processes, a long-duration annealing step can be performed at a temperature of approximately 90°C, and a rapid thermal annealing step can be performed at a temperature of approximately 1050°C.

[0034] refer to Figure 5This diagram shows a detailed view of a transistor cell from a semiconductor device 100 according to another embodiment. Similar to the previously described embodiment, the body layer 116 is configured to have a dopant maximum at a first depth D1 from the main surface 104, which is below the bottom depth of the source region 118 and below the body contact of the device. However, the body layer 116 is formed differently and has different lateral doping characteristics than the previously described device. In particular, the body layer 116 has a relatively high reference second conductivity type doping throughout the body layer 116. For example, the reference second conductivity type doping could be 1 × 10⁻⁶. 18 dopant atoms / cm 3 The magnitude is on the order of... Additionally, a partial compensation region 128 is provided within the body region, wherein the reference second conductivity type doping is partially compensated by a first conductivity type dopant. That is, the partial compensation region 128 includes both the first conductivity type dopant and the second conductivity type dopant, wherein the concentration of the first conductivity type dopant is lower than the concentration of the second conductivity type dopant. The partial compensation region 128 may include, for example, a 1×10... 14 dopant atoms / cm 3 Up to 1×10 16 dopant atoms / cm 3 The net concentration of second conductivity type dopant is on the order of magnitude.

[0035] The bulk enhancement region 126 of the semiconductor device 100 is formed by a portion of the bulk layer 116 doped with a reference second conductivity type. That is, due to the reference second conductivity type doping of the bulk layer 116, the bulk contact trench can achieve direct contact with P+ or P++ material. The bulk region of the device adjacent to the gate trench 121 is formed by a partial compensation region 128 of the bulk layer 116, wherein the net second conductivity type dopant concentration is lower than the reference second conductivity type doping of the bulk layer 116. This generates the necessary threshold voltage for the semiconductor device 100 because the device channel can be formed in a region with a lower second conductivity type dopant concentration.

[0036] refer to Figure 6 A plan view of a semiconductor device 100 according to an embodiment is shown. This plan view corresponds to... Figure 3 The plan view shown illustrates that the vertical segment of the gate trench 121 extends between elongated segments of the gate trench 121 that extend parallel to each other. It can be seen that a portion of the compensation region 128 of the body layer 116 is formed along the sidewall of the gate trench 121, thereby forming the necessary operating voltage of the device. Simultaneously, the body layer 116, doped with a reference second conductivity type, directly adjoins the vertical segment. That is, the portions of the vertical segment and the elongated segments of the gate trench 121 that form corners with the vertical segment do not adjoin the compensation region, but rather adjoin a material with a relatively high concentration of reference second conductivity type doping. Therefore, the threshold voltage increases in these regions in a manner similar to that described above.

[0037] Referring to FIG7, a method for forming a reference according to an embodiment is illustrated. Figure 5 and Figure 6 The method steps for selecting the semiconductor device 100 are described.

[0038] refer to Figure 7A A semiconductor body 102 including a superjunction structure is provided. Subsequently, a first pre-gate implantation step for forming a body layer 116 is performed before forming a gate trench 121. The pre-gate implantation step includes implanting dopant atoms having a second conductivity type into the semiconductor body 102 to a target depth. The first pre-gate implantation step can be compared with a reference... Figure 4A The first implantation step is described as the same, except that the dopant dose is higher. In this case, the dopant dose is selected to create a reference second conductivity type doping in the body layer 116 as a highly doped region, such as a P+ or P++ region. For example, the initial body layer 116 implantation step may include a 1×10⁻⁶ dopant layer. 15 dopant atoms / cm 2 Up to 1×10 16 dopant atoms / cm 2 The injection dose is within the range between these values.

[0039] refer to Figure 7B A second pre-gate implantation step is performed after the first pre-gate implantation step and before the formation of multiple gate trenches 121. The second pre-gate implantation step is a mask implantation step that implants dopant atoms in the region where the gate trenches 121 will be formed. Specifically, the second pre-gate implantation step includes forming a patterned mask 130 with an opening centered relative to the location where the gate trenches 121 will be formed on the substrate. The width of the opening in the mask may be greater than the width of the gate trenches 121 to be formed, in order to create a partial compensation region 128 adjacent to the gate trenches 121. The implantation energy is selected such that the dopant atoms in the second pre-gate implantation step are implanted to the same target depth as in the first pre-gate implantation step. The dose in the second pre-gate implantation step is lower than the dose in the first pre-gate implantation step. For example, the second pre-gate implantation step may include an energy of 1 × 10⁻⁶. 12 dopant atoms / cm 2 Up to 1×10 13 dopant atoms / cm 2 The implantation dose is on the order of magnitude of [amount missing]. As a result, at the location where the gate region will be formed, the semiconductor substrate 102 includes a certain concentration of a first conductivity type dopant and a lower concentration of a second conductivity type dopant.

[0040] Figure 7CThe semiconductor device 100 is shown after the formation of the gate structure 120 and subsequently the formation of the source region 118, followed by dopant activation. The methods used to form these features can be compared with those in the reference section. Figure 4B and Figure 4C The method described is the same, except that the fourth implantation step for forming the highly doped body region can be omitted. Since this technique forms a body layer 116 with a reference second conductivity type doping corresponding to the dopant concentration required for the body reinforcement region 126 throughout the body layer 116, a specific step for forming the highly doped body region after the gate trench is formed is not required. This advantageously reduces fabrication time and cost, as the doping step for forming the body reinforcement region 126 can be expensive and time-consuming.

[0041] Although this disclosure is not limited thereto, the examples numbered below illustrate one or more aspects of this disclosure.

[0042] Example 1. A method of forming a semiconductor device, the method comprising: forming a semiconductor substrate having a superjunction structure, the superjunction structure including a plurality of superjunction pillars alternating in conductivity type along a lateral direction of the semiconductor substrate; and forming a plurality of transistor cells in an active region of the semiconductor substrate, each transistor cell being configured to control a vertical current flowing through the superjunction structure, wherein forming the transistor cells includes: forming a first load terminal region extending to a main surface of the semiconductor substrate and a body region at least partially below the first load terminal region, the first load terminal region being a first conductivity type region and the body region being a second conductivity type region; wherein forming the body region includes: forming a body layer extending from the main surface of the semiconductor substrate, wherein the dopant distribution of a second conductivity type dopant in the body layer increases as it moves from the main surface into the semiconductor substrate until the dopant distribution reaches a maximum value at a first depth from the main surface, and wherein the first depth is below the bottom depth of the first load terminal region.

[0043] Example 2. According to the method of Example 1, forming a body layer includes: performing a first implantation step and activating and outwardly diffusing dopant atoms implanted through the first implantation step, wherein activating the dopant atoms implanted through the first implantation step is accomplished by one or more thermal processing steps simultaneously used to form additional features of the semiconductor device.

[0044] Example 3. According to the method of Example 2, forming a plurality of transistor cells includes: forming a gate trench extending into the main surface of a semiconductor substrate, wherein a first implantation step is performed before forming the gate trench.

[0045] Example 4. According to the method of Example 3, one or more thermal processing steps for forming additional features of the semiconductor device are performed after the gate trench is formed.

[0046] Example 5. According to the method of Example 4, one or more thermal processing steps for forming additional features of the semiconductor device include any of the following: a thermal oxidation step for forming a gate dielectric in a gate trench; a recrystallization step after depositing material for forming a gate electrode in a gate trench; and an annealing step for forming a sacrificial oxide performed after forming the gate trench.

[0047] Example 6. According to the method of Example 3, forming the first load terminal region includes performing a second implantation step after forming a gate trench, and wherein the heat treatment step performed after forming the gate trench includes an annealing step, the annealing step causing the dopant atoms implanted through the first implantation step and the second implantation step to be simultaneously activated and diffused.

[0048] Example 7. The method according to Example 3 further includes: forming a bulk enhancement region within the bulk layer, the bulk enhancement region having a higher concentration of a second conductivity type dopant than the bulk region; and forming a bulk contact portion that ohmically contacts the bulk enhancement region, wherein a first depth is lower than the bottom side of the bulk contact portion.

[0049] Example 8. According to the method of Example 1, the gate trench is formed to include: elongated segments extending parallel to each other and a vertical segment extending perpendicular to the elongated segments and forming a connection between two adjacent elongated segments in the elongated segments, and wherein the body enhancement region 126 extends closer to the vertical segment than the first load terminal region.

[0050] Example 9. A semiconductor device comprising: a semiconductor substrate having a superjunction structure, the superjunction structure including a plurality of superjunction pillars alternating in conductivity type along a lateral direction of the semiconductor substrate; and a plurality of transistor cells in an active region of the semiconductor substrate, each transistor cell being configured to control a vertical current flowing through the superjunction structure, wherein each transistor cell includes a first load terminal region extending to a main surface of the semiconductor substrate and a body region at least partially below the first load terminal region, the first load terminal region being a first conductivity type region and the body region being a second conductivity type region; wherein, for each body region, the dopant distribution of a second conductivity type dopant increases as it moves from the main surface into the semiconductor substrate until the dopant distribution reaches a maximum at a first depth from the main surface, and wherein the first depth is below the bottom depth of the first load terminal region.

[0051] Example 10. A semiconductor device according to Example 9, wherein the semiconductor device includes a body layer extending to a main surface, wherein a body region is formed by the body layer, and wherein the semiconductor device further includes: a body enhancement region formed within the body layer and extending to the main surface, the body enhancement region having a higher concentration of a second conductivity type dopant than the body region; and a body contact portion in ohmic contact with the body enhancement region, wherein a first depth is below the bottom side of the body contact portion.

[0052] Example 11. According to the semiconductor device of Example 10, each transistor cell includes a gate trench, wherein the gate trench includes: elongated segments extending parallel to each other and a vertical segment extending perpendicular to the elongated segments and forming a connection between two adjacent elongated segments in the elongated segments, and wherein the body enhancement region extends closer to the vertical segment than the first load terminal region.

[0053] Example 12. A method of forming a semiconductor device, the method comprising: forming a semiconductor substrate having a superjunction structure, the superjunction structure including a plurality of superjunction pillars alternating in conductivity type along a lateral direction of the semiconductor substrate; and forming a plurality of transistor cells in an active region of the semiconductor substrate, each transistor cell being configured to control a vertical current flowing through the superjunction structure, wherein forming the transistor cells includes: forming a plurality of gate trenches in a main surface of the semiconductor substrate; forming a body region adjacent to the gate trenches; and forming a body enhancement region laterally spaced from the gate trenches, the body enhancement region having a higher concentration of a second conductivity type dopant than the body region, wherein forming the body region and forming the body enhancement region includes: forming a body layer extending from the main surface into the semiconductor substrate and having a reference second conductivity type dopant throughout the body layer; and forming a partially compensated region of the body layer, wherein the reference second conductivity type dopant is partially compensated by a first conductivity type dopant, wherein the body enhancement region is provided by an uncompensated portion of the body layer having the reference second conductivity type dopant, and wherein the body region is formed by the partially compensated region of the body layer.

[0054] Example 13. According to the method of Example 12, forming the body layer includes performing a first pre-gate formation implantation step before forming a plurality of gate trenches, wherein the dopant dose of the first pre-gate formation implantation step is selected to generate a reference second conductivity type doping in the body layer.

[0055] Example 14. According to the method of Example 13, the partial compensation region of the formed body layer includes: performing a second pre-gate formation implantation step after the first pre-gate formation implantation step and before forming a plurality of gate trenches, wherein the second pre-gate formation implantation step is a mask implantation step of implanting a first conductivity type dopant in the region where the gate trenches will be formed.

[0056] Example 15. According to the method of Example 14, wherein the first pre-gate formation implantation step and the second pre-gate formation implantation step each implant dopant atoms to a first target depth below the main surface of the semiconductor substrate.

[0057] Example 16. The method according to Example 15 further includes: after forming the gate trench, activating the dopant atoms implanted through the first pre-gate formation implantation step and the second pre-gate formation implantation step, wherein the activation of the dopant atoms implanted through the first pre-gate formation implantation step and the second pre-gate formation implantation step is accomplished by one or more thermal processing steps simultaneously used to form additional features of the semiconductor device.

[0058] Example 17. According to the method of Example 12, forming a transistor cell includes: forming a first load terminal region extending to a main surface of a semiconductor substrate, wherein the dopant distribution of a second conductivity type dopant in the bulk layer increases as it moves from the main surface into the semiconductor substrate until the dopant distribution reaches a maximum at a first depth from the main surface, and wherein the first depth is lower than the bottom depth of the first load terminal region.

[0059] Example 18. The method according to Example 17 further includes: forming a body contact portion that ohmically contacts the body reinforcement region, wherein a first depth is below the bottom side of the body contact portion.

[0060] Example 19. According to the method of Example 12, the gate trench is formed to include: elongated segments extending parallel to each other and vertical segments extending perpendicular to the elongated segments and forming a connection between two adjacent elongated segments in the elongated segments.

[0061] Example 20. According to the method of Example 19, the body layer with reference second conductivity type doping is directly adjacent to the vertical segment.

[0062] Example 21. A semiconductor device includes: a semiconductor substrate having a superjunction structure, the superjunction structure including a plurality of superjunction pillars alternating in conductivity type along a lateral direction of the semiconductor substrate; and a plurality of transistor cells in an active region of the semiconductor substrate, each transistor cell being configured to control a vertical current flowing through the superjunction structure; a body layer extending from a main surface of the semiconductor substrate in the active region and having a reference second conductivity type doping, wherein the transistor cells include a plurality of gate trenches in the main surface of the semiconductor substrate, a body region adjacent to the gate trenches, and a body enhancement region laterally spaced from the gate trenches, the body enhancement region having a higher second conductivity type dopant concentration than the body region, wherein the body enhancement region is formed by a portion of the body layer having reference second conductivity type doping, and wherein the body region is formed by a partially compensated region of the body layer, wherein the reference second conductivity type doping is partially compensated by a first conductivity type dopant.

[0063] Example 22. According to the semiconductor device of Example 21, the dopant distribution of the second conductivity type dopant in the body layer includes a maximum value at a first depth from the main surface, and the dopant distribution of the first conductivity type dopant in the partial compensation region of the body layer includes a maximum value at a first depth from the main surface.

[0064] Example 23. A semiconductor device according to Example 22, wherein the transistor cell includes a first load terminal region extending to the main surface of the semiconductor substrate, and wherein a first depth is lower than the bottom depth of the first load terminal region.

[0065] Example 24. According to the semiconductor device of Example 22, the semiconductor device further includes a body contact portion that makes ohmic contact with the body reinforcement region, wherein a first depth is below the bottom side of the body contact portion.

[0066] Example 25. According to the semiconductor device of Example 21, the gate trench includes: elongated segments extending parallel to each other and a vertical segment extending perpendicular to the elongated segments and forming a connection between two adjacent elongated segments within the elongated segments.

[0067] Example 26. A semiconductor device according to Example 25, wherein a body layer having a reference second conductivity type doped is directly adjacent to a vertical segment.

[0068] This specification relates to semiconductor portions doped with dopants of “first” and “second” conductivity types. The first conductivity type can be n-type, and the second conductivity type can be p-type, or vice versa. It is well known that insulated-gate field-effect transistors (IGFETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs), can be n-channel or p-channel MOSFETs, depending on the doping type or polarity of the source and drain regions. For example, in an n-channel MOSFET, the source and drain regions are doped with n-type dopants. In a p-channel MOSFET, the source and drain regions are doped with p-type dopants. As will be clearly understood, in the context of this specification, doping types are interchangeable. If a particular current path is described using directional language, the description is to be understood only as indicating the path and not the polarity of current flow, i.e., whether current flows from the source to the drain (and vice versa). The accompanying drawings may include polarity-sensitive components, such as diodes. As will be clearly understood, specific arrangements of these polarity-sensitive components are given as examples and can be reversed to achieve the described function, depending on whether the first conductivity type refers to n-type or p-type.

[0069] For ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" are used to explain the position of one element relative to a second element. These terms are intended to cover different orientations of the device in addition to those depicted in the figures. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the specification, the same term refers to the same element.

[0070] As used herein, the terms “having,” “containing,” “including,” “comprising,” etc., are open-ended terms that indicate the presence of the said element or feature but do not exclude additional elements or features. The articles “a” and “said” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0071] Given the variations and applications described above, it should be understood that the present invention is not limited to the foregoing description or the accompanying drawings. Rather, the invention is limited only by examples and their legal equivalents.

Claims

1. A method for forming a semiconductor device (100), the method comprising: A semiconductor substrate (102) with a superjunction structure is formed, the superjunction structure comprising a plurality of superjunction pillars (110) alternating in conductivity type along the lateral direction of the semiconductor substrate (102). as well as A plurality of transistor cells are formed in the active region of the semiconductor substrate (102), each of the transistor cells being configured to control a vertical current flowing through the superjunction structure. The transistor unit includes forming a first load terminal region (118) extending to the main surface (104) of the semiconductor substrate (102) and a body region at least partially below the first load terminal region, wherein the first load terminal region (118) is a first conductivity type region and the body region is a second conductivity type region. The formation of the body region includes forming a body layer (116) extending from the main surface (104) of the semiconductor substrate (102). The dopant distribution of the second conductivity type dopant in the body layer (116) increases as it moves from the main surface (104) to the semiconductor substrate (102), until the dopant distribution reaches its maximum value at a first depth from the main surface (104). The first depth is lower than the bottom depth of the first load terminal area (118).

2. The method according to claim 1, in, Forming the body layer (116) includes: performing a first implantation step and activating and outwardly diffusing the dopant atoms implanted through the first implantation step, and The activation of the dopant atoms implanted through the first implantation step is accomplished by one or more thermal treatment steps that simultaneously form additional features of the semiconductor device (100).

3. The method according to claim 1 or 2, in, Forming the plurality of transistor units includes forming a gate trench (121) extending into the main surface (104) of the semiconductor substrate (102). The first implantation step is performed before the gate trench (121) is formed.

4. The method according to claim 3, in, Meanwhile, the one or more thermal processing steps used to form additional features of the semiconductor device (100) are performed after the gate trench (121) is formed.

5. The method according to claim 4, in, Meanwhile, the one or more heat treatment steps used to form additional features of the semiconductor device (100) include any of the following: Thermal oxidation step for forming the gate dielectric in the gate trench (121); A recrystallization step following the deposition of material used to form the gate electrode in the gate trench (121); as well as An annealing step for forming a sacrificial oxide is performed after the formation of the gate trench (121).

6. The method according to any one of claims 3 to 5, in, Forming the first load terminal region (118) includes performing a second implantation step after forming the gate trench (121), and The heat treatment step performed after the formation of the gate trench (121) includes an annealing step, which activates and diffuses the dopant atoms implanted through the first implantation step and the second implantation step simultaneously.

7. The method according to any one of claims 3 to 6, further comprising: A bulk reinforcement region (126) is formed within the bulk layer (116), the bulk reinforcement region (126) having a higher concentration of a second conductivity type dopant than the bulk region; and A body contact portion is formed that makes ohmic contact with the body reinforcement region (126). Wherein, the first depth is lower than the bottom side of the body contact portion.

8. The method according to claim 7, in, The gate trench (121) is formed to include: elongated segments extending parallel to each other and a vertical segment extending perpendicular to the elongated segments and forming a connection between two adjacent elongated segments in the elongated segments. The body reinforcement region (126) extends closer to the vertical segment than the first load terminal region (118).

9. A semiconductor device, comprising: A semiconductor substrate (102) having a superjunction structure, the superjunction structure comprising a plurality of superjunction pillars (110) alternating in conductivity type along the lateral direction of the semiconductor substrate (102). as well as A plurality of transistor cells are located in the active region of the semiconductor substrate (102), each of the transistor cells being configured to control a vertical current flowing through the superjunction structure. Each of the transistor units includes a first load terminal region (118) extending to the main surface (104) of the semiconductor substrate (102) and a body region at least partially below the first load terminal region, wherein the first load terminal region (118) is a first conductivity type region and the body region is a second conductivity type region; Specifically, for each of the body regions, the dopant distribution of the second conductivity type dopant increases as it moves from the main surface (104) into the semiconductor substrate (102), until the dopant distribution reaches its maximum value at a first depth from the main surface (104), and The first depth is lower than the bottom depth of the first load terminal area (118).

10. The semiconductor device according to claim 9, in, The semiconductor device (100) includes a body layer (116) extending to the main surface (104). The body region is formed by the body layer (116), and The semiconductor device (100) further includes: A bulk enhancement region (126) is formed within the bulk layer (116) and extends to the main surface (104), the bulk enhancement region (126) having a higher concentration of a second conductivity type dopant than the bulk region; and The body contact portion that is in ohmic contact with the body reinforcement region (126), Wherein, the first depth is lower than the bottom side of the body contact portion.

11. The semiconductor device according to claim 10, in, Each of the transistor units includes a gate trench (121). The gate trench (121) includes: elongated segments extending parallel to each other and a vertical segment extending perpendicular to the elongated segments and forming a connection between two adjacent elongated segments within the elongated segments. The body reinforcement region (126) extends closer to the vertical segment than the first load terminal region (118).

12. A method of forming a semiconductor device (100), the method comprising: A semiconductor substrate (102) with a superjunction structure is formed, the superjunction structure comprising a plurality of superjunction pillars (110) alternating in conductivity type along the lateral direction of the semiconductor substrate (102). as well as A plurality of transistor cells are formed in the active region of the semiconductor substrate (102), each of the transistor cells being configured to control a vertical current flowing through the superjunction structure. The transistor unit comprises: A plurality of gate trenches (121) are formed in the main surface (104) of the semiconductor substrate (102). Forming a body region adjacent to the gate trench (121); and A bulk enhancement region (126) is formed adjacent to the bulk region, the bulk enhancement region (126) having a higher concentration of second conductivity type dopant than the bulk region. The formation of the volume region and the formation of the volume enhancement region (126) include: A body layer (116) is formed, the body layer (116) extending from the main surface (104) into the semiconductor substrate (102), and having a reference second conductivity type doping throughout the body layer (116); and A partial compensation region is formed in the body layer (116), wherein the reference second conductivity type doping is partially compensated by the first conductivity type dopant. The bulk enhancement region (126) is provided by an uncompensated portion of the bulk layer (116) having doped with the reference second conductivity type, and The body region is formed by the partial compensation region of the body layer (116).

13. The method according to claim 12, in, Forming the body layer (116) includes performing a first pre-gate formation implantation step prior to forming the plurality of gate trenches (121), wherein the dopant dose of the first pre-gate formation implantation step is selected to generate the reference second conductivity type doping in the body layer (116).

14. The method according to claim 13, in, The partial compensation region forming the body layer (116) includes performing a second pre-gate formation implantation step after the first pre-gate formation implantation step and before forming the plurality of gate trenches (121). The second pre-gate formation implantation step is a mask implantation step in which a first conductivity type dopant is implanted in the region where the gate trench (121) will be formed.

15. The method according to claim 14, in, The first pre-gate formation implantation step and the second pre-gate formation implantation step each implant dopant atoms to a first target depth below the main surface (104) of the semiconductor substrate (102).

16. The method of claim 15, further comprising: After the gate trench (121) is formed, the dopant atoms implanted through the first pre-gate formation implantation step and the second pre-gate formation implantation step are activated. The activation of the dopant atoms implanted through the first pre-gate formation implantation step and the second pre-gate formation implantation step is accomplished by one or more thermal treatment steps that simultaneously form additional features of the semiconductor device (100).

17. The method according to any one of claims 12 to 16, in, Forming the transistor unit includes forming a first load terminal region extending to the main surface (104) of the semiconductor substrate (102), wherein the dopant distribution of a second conductivity type dopant in the bulk layer increases as it moves from the main surface (104) into the semiconductor substrate (102) until the dopant distribution reaches a maximum at a first depth from the main surface (104), and wherein the first depth is below the bottom depth of the first load terminal region.

18. The method of claim 17, further comprising: A body contact portion is formed in ohmic contact with the body reinforcement region (126), wherein the first depth is lower than the bottom side of the body contact portion.

19. The method according to any one of claims 12 to 18, wherein, The gate trench (121) is formed to include: elongated segments extending parallel to each other and vertical segments extending perpendicular to the elongated segments and forming a connection between two adjacent elongated segments in the elongated segments.

20. The method according to claim 19, wherein, The body layer (116) having the reference second conductivity type doping is directly adjacent to the vertical segment.

21. A semiconductor device, comprising: A semiconductor substrate (102) having a superjunction structure, the superjunction structure comprising a plurality of superjunction pillars (110) alternating in conductivity type along the lateral direction of the semiconductor substrate (102). as well as A plurality of transistor cells in the active region of the semiconductor substrate (102), each of the transistor cells being configured to control a vertical current flowing through the superjunction structure; A body layer (116) extends from the main surface (104) of the semiconductor substrate (102) in the active region and has a reference second conductivity type doping. The transistor unit includes a plurality of gate trenches (121) in the main surface (104) of the semiconductor substrate (102), a body region adjacent to the gate trenches (121), and a body enhancement region (126) adjacent to the body region. The body enhancement region (126) has a higher concentration of a second conductivity type dopant than the body region. The bulk enhancement region (126) is formed by a portion of the bulk layer (116) having the reference second conductivity type doping, and The body region is formed by a partial compensation region of the body layer (116), wherein the reference second conductivity type doping is partially compensated by the first conductivity type dopant.

22. The semiconductor device according to claim 21, in, The dopant distribution of the second conductivity type dopant in the body layer (116) includes a maximum value at a first depth from the main surface (104), and wherein the dopant distribution of the first conductivity type dopant in the partial compensation region of the body layer (116) includes a maximum value at the first depth from the main surface (104).

23. The semiconductor device according to claim 22, in, The transistor unit includes a first load terminal (118) region extending to the main surface (104) of the semiconductor substrate (102), wherein the first depth is lower than the bottom depth of the first load terminal region.

24. The semiconductor device according to claim 22 or 23, in, The semiconductor device (100) further includes a body contact portion that makes ohmic contact with the body contact region. Wherein, the first depth is lower than the bottom side of the body contact portion.

25. The semiconductor device according to any one of claims 21 to 24, in, The gate trench (121) includes: elongated segments extending parallel to each other and vertical segments extending perpendicular to the elongated segments and forming a connection between two adjacent elongated segments in the elongated segments.

26. The semiconductor device according to claim 25, in, The body layer (116) having the reference second conductivity type doping is directly adjacent to the vertical segment.

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