Molded core substrate for embedded component
By directly embedding electronic components through a molded core substrate process and encapsulating them with mold materials, the complexity and cost issues of drilling and cavity filling of FR4 cores in existing technologies have been solved, enabling lower-cost and higher-density integrated circuit manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ADVANCED MICRO DEVICES INC
- Filing Date
- 2024-06-10
- Publication Date
- 2026-04-24
AI Technical Summary
Existing technologies require drilling holes in the FR4 core to form cavities and filling them with dielectric material when manufacturing hybrid integrated circuit devices, which leads to complex manufacturing, high costs, and uneven thickness.
The molding core substrate process is adopted, which directly embeds electronic components on the substrate and encapsulates them with mold material, avoiding drilling and cavity filling steps, and using mold material to achieve uniform thermal expansion coefficient and stiffness.
It achieves lower cost, more uniform thickness and higher component integration density, reduces manufacturing complexity and material costs, and improves the uniformity of electrical connections.
Smart Images
Figure CN121925999A_ABST
Abstract
Description
Technical Field
[0001] The embodiments disclosed herein generally relate to integrated circuit packaging of active and passive electronic components, and more specifically to embedding components in a molded core substrate of an integrated circuit package. Background Technology
[0002] Hybrid integrated circuit (IC) device packages incorporate both active components (e.g., transistors, oscillators, counters, registers, memories, integrated voltage regulators (IVRs)) and passive components (e.g., core inductors, deep trench capacitors, and other passive components) into a single IC device package. This IC device package may consist of a substrate with a central region of a fiber-reinforced (FR4) core shaped in various ways to accommodate the placement of these components, providing electrical interconnections between the components and external connections to them. After the components are mounted and connected, the FR4 core containing the connected components can be encapsulated to produce the hybrid IC device package.
[0003] Electrical interconnections between components can be achieved through metal layers and traces, plated vias (PTH), and conductive vias. External connections can be made to contact pads exposed on the external surface of the encapsulated substrate of the hybrid IC device package. Summary of the Invention
[0004] In one example of this disclosure, an integrated circuit (IC) molded core substrate includes multiple components having circuit connections on a first and / or second side. A molded material surrounds the multiple components, wherein a first and second surface of the molded material is coplanar with the circuit connections. Copper pattern interconnects the circuit connections.
[0005] In one example of this disclosure, an integrated circuit (IC) includes a molded core substrate having multiple components having circuit connections on a first and / or second side. A molding material surrounds the multiple components, wherein a first and second surface of the molding material is coplanar with the circuit connections. Copper pattern interconnects the circuit connections. An IC package includes the IC molded core substrate. External connections on the IC package are coupled to connections of the multiple components in the molded core substrate.
[0006] In one example of this disclosure, a method for manufacturing a molded core substrate for an integrated circuit (IC) includes using a carrier panel. A release film is laminated on one side of the carrier panel. A first copper seed layer is applied over the release film. An electronic component is placed on the first copper seed layer. A mold material is applied around and over the electronic component. The mold material is cured. The mold material is ground to be planar with the top of the electronic component. The release film and carrier panel are removed from the first copper seed layer. The first copper seed layer is etched. Holes are formed in the cured mold material. A second copper seed layer is applied over the cured mold material and the surface of the formed holes. A copper blanket is applied over the second copper seed layer and in the formed holes. The formed holes are plugged to create plated through-holes (PTHs). A portion of the copper blanket is removed, but the remaining portion is left for the PTHs and component connection pads. A multilayer dielectric film is laminated over the PTHs and component connection pads. Through-holes are formed through the laminated multilayer dielectric film to the PTHs and component connection pads. Attached Figure Description
[0007] To gain a more detailed understanding of the above-described features of the invention, a more specific description of the invention, which has been briefly summarized above, can be obtained by referring to examples, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical examples of the invention and should therefore not be considered as limiting the scope of the invention, as the invention may allow for other equivalent embodiments.
[0008] Figure 1 A representative schematic front view cross-sectional layout of a prior art hybrid integrated circuit (IC) device using a fiber-reinforced (FR4) substrate core in which components are embedded is illustrated.
[0009] Figure 2 A representative schematic frontal cross-sectional layout of a molded core substrate according to an example is illustrated, which has a molded material for encapsulating active and passive components used in hybrid integrated circuit (IC) devices.
[0010] Figures 3A to 3D , Figure 4A , Figure 4B , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C and Figure 8 An example is given for forming the representation based on the example. Figure 2 A schematic frontal cross-sectional layout of the process steps for molding the core substrate of an IC device.
[0011] Figure 9 A schematic frontal cross-sectional layout of a stacked molded core substrate is illustrated according to the example.
[0012] Figure 10 An example is given of an integrated circuit package. Figure 2A schematic frontal cross-sectional layout of an IC device.
[0013] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures, and lowercase letters are added where elements are substantially the same. It is conceivable that elements of one embodiment can be advantageously incorporated into other embodiments. Detailed Implementation
[0014] refer to Figure 1 This paper depicts a representative schematic front cross-sectional layout of a prior art hybrid integrated circuit (IC) device using a fiber-reinforced (FR4) substrate core in which components are embedded. The IC device, typically represented by the numeral 100, is usually manufactured using a fiber-reinforced epoxy (FR4) core 102, requiring the creation of cavities 104 within the FR4 core for embedding (placing) multiple components 106 therein. These cavities 104 are then filled with a dielectric 108 having a high coefficient of thermal expansion (CTE). Having multiple components 106 within a single cavity 104 is challenging due to placement accuracy requirements and component displacement during its manufacturing process.
[0015] Creating cavities in FR4 core material requires laser drilling (expensive), and the number of cavities drilled scales depending on the number of devices and components embedded within them. Typically, multilayer dielectric films are used to fill the cavities. In one example, the multilayer dielectric film comprises an organic stacked film. In another example, the multilayer dielectric film comprises an adhesive-coated polyester (PET) film. Adhesive-coated polyester (PET) films can have a CTE of less than about 40 ppm / K at 150 degrees Celsius. In one example, the multilayer dielectric film is an ABF film. ABF – “Ajinomoto laminated film” – is a registered trademark of Ajinomoto Co., Ltd. When multilayer dielectric films (i.e., lamination) are used to fill cavities, undulations or thickness variations are created, resulting in inhomogeneities in dielectric thickness above the devices and components within the cavity. The stiffness of FR4 material derives from the presence of glass fiber bundles. When these fibers are cut or removed to create cavities, the overall stiffness of the core is weakened.
[0016] Based on the teachings of this disclosure, a molded core substrate is used instead of an FR4 core in an IC device for mounting in an IC package. Figure 10Compared to existing technologies, using FR4 cores requires drilling holes to create cavities for placing electronic components (subtractive manufacturing), and then filling these cavities to contain the components. Molded core substrates have active and passive electronic components placed on a substrate, which are then encapsulated with a molding material (additive manufacturing). The molding process allows for the embedding of a large number of components, typically 50 to 100, within the molded core substrate. The molding process eliminates the need for FR4 cores and avoids the expensive and technically challenging steps of creating and filling cavities in an FR4 substrate required for existing IC device packaging. Using molded core substrates instead of current FR4 cores enables the large-scale integration of voltage regulators, inductors, deep trench capacitors, and other active and passive electronic components into easily manufactured and cost-effective IC products. Multiple molded core substrates, each with active and passive electronic components, can be manufactured as panels, encapsulated with a molding material, cured, and then individually diced for inclusion in IC packages.
[0017] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of features of these examples. They are not intended to provide an exhaustive description of the following examples, nor are they intended to limit the scope of the claims. Furthermore, the illustrated examples need not possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described. Referring now to the drawings, the details of the examples are representative layouts schematically illustrated. The same elements in the drawings will be indicated by the same numerals, and similar elements will be indicated by the same numerals with different lowercase letter suffixes.
[0018] refer to Figure 2 The illustration depicts a representative schematic front cross-sectional layout of a molded core substrate according to an example, the molded core substrate having a molded material encapsulating electronic components used in hybrid integrated circuit (IC) devices. The molded core substrate (generally indicated by the numeral 200) may include a plurality of electronic components 206 encapsulated in molded material 210. The molded core substrate 200 can be used to manufacture hybrid IC device packages.
[0019] The benefits and advantages of using molded material instead of FR4 cores are: With a molded core substrate, the molded material can be used to achieve the desired stiffness and coefficient of thermal expansion (CTE). The CTE of the molded material is essentially the same across the entire device compared to the combination of RF4 and cavity-filling materials used in the prior art. There is no need for costly drilling into unwanted FR4 cores to form cavities. Instead of drilling cavities into FR4 cores and filling them with dielectric materials (e.g., multilayer dielectric films such as ABF), components are embedded using a molding process. Conductive pads or bumps on the components are exposed using a mold-grinding process. Standard bumped wafer components can be used without the need for customized surface finish / pad geometry for embedding. Better thickness tolerance control is achieved because the components are placed on a carrier and rely on the mold-grinding process to achieve uniform flat surfaces.
[0020] The advantages of using a molded core substrate are: lower CTE (less than approximately 10 ppm CTE per degree Celsius) and higher stiffness compared to manufacturing processes using FR4 cores, where cavity filling with multilayer dielectric films increases the CTE of the composite core. Costly laser cavity drilling and laminators are avoided, resulting in lower manufacturing process costs. Material costs are lower compared to cavity filling with FR4 drilled cores using multilayer dielectric films. The difficulties of filling cavities with multilayer dielectric films or prepregs, which can introduce voids during lamination processes, are avoided. There is a larger allowance for die offset during component encapsulation. The uniformity of via and multilayer dielectric film thickness above the component is better, with molding and polishing processes providing uniform core thickness and flatness. It allows for scaling up to more components, which is limited by the existing FR4 cavity drilling and filling capabilities. Mold materials can be designed to achieve low CTE and high molded core substrate stiffness. The flexibility of customizing core thickness, rather than being forced to use the approximately 200-micron increments available with FR4 core materials, is provided.
[0021] Figures 3A to 3D , Figure 4A , Figure 4B , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C and Figure 8 An example is given for forming the representation based on the example. Figure 2 A schematic front cross-sectional layout of the process steps for manufacturing a molded core substrate for an IC device. According to the teachings of this disclosure, the process for manufacturing a molded core substrate 200 for a hybrid IC device can begin from a carrier panel 312 ( Figure 3A The carrier panel 312 can be, for example, but not limited to, a glass, ceramic, or metal substrate. Stainless steel / metal with a heat release film can also be used. The release film 314 can be laminated onto the surface of the carrier panel 312. Figure 3BRelease film 314 can be used to peel carrier panel 312 from molded core substrate 200 in subsequent manufacturing steps. Figure 5B ).
[0022] Copper seed layer 316 and reference 318 are added to the surface of release film 314. Figure 3C Using reference 318 helps ensure accurate placement of components on the copper seed layer 316. Optionally, an encapsulation layer 320 may be added over the copper seed layer 316 and can be planarized using reference 318. Figure 3D For example, but not limited to, copper seed layer 316 can be used. Figure 4A Alignment marks on the surface, for example, using reference 318, are used to accurately position component 422. After attaching component 422 to the copper seed layer 316, mold material 424 can be used to encapsulate component 422. Figure 4B Mold material 424 (e.g., epoxy / filler composite) may have a low coefficient of thermal expansion (CTE) and high modulus to replicate conventional cores. The mold material may be formed in a compression mold.
[0023] Once cured, the mold material 424 can be ground to expose the top side of the component 422. Figure 5A The mold grinding process can make the top of part 422 planar. Next, the release film 314 can be peeled off from the copper seed layer 316 using, for example, but not limited to, laser, thermal release, and photocuring with ultraviolet light. Figure 5B The carrier panel 312 can be removed by etching the copper seed layer 316, and then the encapsulation layer 320 can be removed by solvent cleaning to expose the bottom of the component 422 (connection 522) and the reference 318. Figure 5C ).
[0024] Holes 626 can be formed in the cured mold material 424 to form through holes. Figure 6A Hole 626 can be formed by drilling, laser cutting, or other suitable techniques. A copper seed layer 628 can be formed on the top and bottom of the mold material 424 and inside the hole 626 to form a plated through-hole (PTH). Figure 6B Copper blanket 630 can be electroplated onto copper seed layer 628 and into hole 626. Figure 6C To aid in further steps: grinding the plugs 732 to planarize them with copper blanket 630. The plugs 732 can be formed in the holes 626 using organic resin, paste printing, or liquid dispensing, and the copper blanket 630 can be attached to the PTH pads 734 formed after the subtractive etching of the copper blanket 630. Reference points 318 used for component placement accuracy can be removed during subtractive etching because they are no longer needed. Figure 7B Multilayer dielectric films 736 can be laminated on the top and bottom surfaces of mold material 424. Figure 7CSubsequently, vias 840 can be formed in the multilayer dielectric film 736 for external connections to components 422 of the mold material 424 during the substrate manufacturing process. Figure 8 ).
[0025] refer to Figure 9 The illustration depicts a schematic front-view cross-sectional layout representing a stacked molded core substrate according to an example. The stacked molded core substrate, typically represented by the numeral 900, may include at least two molded core substrates 200 (two are shown), each of which may include a plurality of electronic components 206 encapsulated in a mold material 210. The stacked molded core substrates 900 can be used to fabricate higher-density hybrid IC device packages because more components can be accommodated in a smaller horizontal footprint. The component connection pads 922 of each of the at least two molded core substrates 200 may be connected to connections 940 (e.g., standard metallization and photolithography processes) and external connections 1042 made through vias 840. Figure 10 Interconnection. The molded core substrate 200 and / or 900 can be packaged into hybrid IC device products using other standard manufacturing processes.
[0026] refer to Figure 10 It depicts, according to the example, a representation of an integrated circuit package. Figure 2 A schematic front cross-sectional layout of an IC device. An IC molded core substrate 200 having components 206 is fabricated within an IC package 1044. The IC package 1044 has external connections 1042 coupled to the components of the IC molded core substrate 200, such as, but not limited to, ball grid arrays, pad grid arrays, and pin grid arrays.
[0027] As will be understood and benefited by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, apparatus, or computer-programmed products. Therefore, aspects may take the form of entirely hardware implementations, entirely software implementations (including firmware, resident software, microcode, etc.), or implementations combining software and hardware aspects, all of which may generally be referred to herein as “circuit,” “module,” or “system.” Furthermore, aspects may take the form of computer program products embodied in one or more computer-readable media having computer-readable program code embodied thereon.
[0028] The techniques described above can be described in the following non-limiting embodiments.
[0029] Example 1. An integrated circuit (IC) molded core substrate, the IC molded core comprising: a plurality of components, the plurality of components having circuit connections on a first side and / or a second side; A mold material surrounding the plurality of components, wherein the first and second surfaces of the mold material are coplanar with the circuit connections; and copper patterns interconnecting the circuit connections.
[0030] Example 2. IC molded core substrate according to Example 1, wherein the mold material has a low coefficient of thermal expansion (CTE).
[0031] Example 3. The IC molded core substrate according to Example 1, wherein the mold material is formed in a compression mold.
[0032] Example 4. The IC molded core substrate according to Example 1, wherein the plurality of components are selected from the group consisting of: integrated voltage regulator, inductor and deep trench capacitor.
[0033] Example 5. According to Example 1, the IC molded core substrate further includes electroplated through holes in the mold material from its first surface to its second surface.
[0034] Example 6. According to Example 1, the IC molded core substrate further includes a multilayer dielectric film, the multilayer dielectric film including an adhesive-coated polyester layer laminated to the first surface and the second surface of the mold material.
[0035] Example 7. According to the IC molding core substrate of Example 6, the IC molding core substrate further includes through holes in the multilayer dielectric film laminated to the first surface and / or the second surface of the mold material.
[0036] Example 8. An IC molded core substrate according to Example 7, wherein the plurality of components in the molded core substrate are connected through the through-holes.
[0037] Example 9. An integrated circuit (IC) comprising: a molded core substrate having: a plurality of components having circuit connections on a first side and / or a second side thereof; a molded material surrounding the plurality of components, wherein a first surface and a second surface of the molded material are coplanar with the circuit connections; and copper patterns interconnecting the circuit connections; an IC package including the IC molded core substrate; and external connections on the IC package coupled to the circuit connections of the plurality of components in the molded core substrate.
[0038] Example 10. The IC according to Example 9, wherein the IC package comprises at least two molded core substrates.
[0039] Example 11. According to the IC of Example 9, the external connectors on the IC package are selected from the group consisting of: ball grid array, pad grid array and pin grid array.
[0040] Example 12. A method for manufacturing a molded core substrate for an integrated circuit (IC), the method comprising: laminating a release film on one side of a carrier panel; applying a first copper seed layer over the release film; placing an electronic component on the first copper seed layer; applying a mold material around and over the electronic component; curing the mold material; grinding the mold material to be planar with the top of the electronic component; removing the release film and the carrier panel from the first copper seed layer; etching the first copper seed layer; forming a hole in the mold material; applying a second copper seed layer on the surface of the cured mold material and the formed hole; applying a copper blanket over the second copper seed layer and in the formed hole; plugging the formed hole to create a plated through-hole (PTH); removing a portion of the copper blanket, but leaving the remaining portion of the copper blanket for the PTH and component connection pads; laminating a multilayer dielectric film over the PTH and component connection pads; and forming a through-hole through the multilayer dielectric film to the PTH and the component connection pads.
[0041] Example 13. The method according to Example 12, wherein the carrier panel is selected from any of the following groups: glass substrate, ceramic substrate and metal substrate.
[0042] Example 14. The method according to Example 12, wherein the step of removing the carrier panel from the molded core substrate includes peeling the release film from the first copper seed layer.
[0043] Example 15. The method according to Example 14, wherein the release film is peeled off from the first copper seed layer using a laser.
[0044] Example 16. The method according to Example 14, wherein the release film is peeled off from the first copper seed layer by thermal release.
[0045] Example 17. The method according to Example 14, wherein the release film is peeled off from the first copper seed layer by photocuring with ultraviolet light.
[0046] Example 18. The method according to Example 12, wherein the copper blanket is applied over the second copper seed layer and into the formed hole by electroplating.
[0047] Example 19. The method according to Example 12, the method further comprising the step of: electroplating a reference having alignment marks thereon onto the first copper seed layer for placing electronic components using the alignment marks of the reference.
[0048] Example 20. The method according to Example 19, the method further includes the step of removing the reference by subtractive etching after placing the electronic component.
[0049] While the foregoing describes embodiments of the present invention, other and further embodiments of the present invention may be designed without departing from the basic scope of the present invention, and the scope of the present invention is defined by the appended claims.
Claims
1. An integrated circuit (IC) molded core substrate, the IC molded core substrate comprising: Multiple components, the multiple components having circuit connections on their first and / or second sides; A mold material surrounding the plurality of components, wherein a first surface and a second surface of the mold material are coplanar with the circuit connection; and Copper patterns, which interconnect the circuit connections.
2. The IC molded core substrate according to claim 1, wherein the mold material has a low coefficient of thermal expansion (CTE).
3. The IC molded core substrate according to claim 1, wherein the mold material is formed in a compression mold.
4. The IC molded core substrate according to claim 1, wherein the plurality of components are selected from the group consisting of: integrated voltage regulators, inductors, and deep trench capacitors.
5. The IC molding substrate according to claim 1, wherein the IC molding substrate further includes electroplated through holes in the mold material from its first surface to its second surface.
6. The IC molding substrate according to claim 1, wherein the IC molding substrate further comprises a multilayer dielectric film, the multilayer dielectric film comprising an adhesive-coated polyester layer laminated to the first surface and the second surface of the molding material.
7. The IC molding core substrate according to claim 6, wherein the IC molding core substrate further comprises through-holes in the multilayer dielectric film laminated to the first surface and / or the second surface of the mold material.
8. The IC molded core substrate according to claim 7, wherein the plurality of components in the molded core substrate are connected through the through-hole.
9. An integrated circuit (IC), said IC comprising: Molded core substrate, the molded core substrate having Multiple components, wherein the multiple components have circuit connections on their first and / or second sides, Mold material, the mold material surrounding the plurality of components, wherein a first surface and a second surface of the mold material are coplanar with the circuit connection; and Copper patterns, wherein the copper patterns interconnect the circuit connections; An IC package, wherein the IC package includes the IC molded core substrate; and The external connections on the IC package are coupled to the circuit connections of the plurality of components in the molded core substrate.
10. The IC of claim 9, wherein the IC package comprises at least two molded core substrates.
11. The IC of claim 9, wherein the external connector on the IC package is selected from the group consisting of: ball grid array, pad grid array, and pin grid array.
12. A method for manufacturing a molded core substrate for an integrated circuit (IC), the method comprising: A release film is laminated onto one side of the carrier panel; A first copper seed layer is applied over the release film; The electronic components are placed on the first copper seed layer; Apply mold material around and above the electronic components; Solidify the mold material; The mold material is ground to be flat with the top of the electronic component; Remove the release film and the carrier panel from the first copper seed layer; Etch the first copper seed layer; Holes are formed in the mold material; A second copper seed layer is applied to the surface of the cured mold material and the formed hole; A copper blanket is applied above the second copper seed layer and into the formed holes; The formed holes are blocked to create plated through-holes (PTHs); Remove a portion of the copper blanket, but leave the remaining portion for PTH and component connection pads; A multilayer dielectric film is laminated over the PTH and component connection pads; and A through-hole is formed that passes through the multilayer dielectric film to reach the PTH and the component connection pad.
13. The method of claim 12, wherein the carrier panel is selected from any one of the group consisting of: glass substrate, ceramic substrate, and metal substrate.
14. The method of claim 12, wherein the step of removing the carrier panel from the molded core substrate includes peeling the release film from the first copper seed layer.
15. The method according to claim 12, further comprising the following steps: A reference having alignment marks is electroplated onto the first copper seed layer for placing electronic components using the alignment marks on the reference.