Wheel speed acquisition method and circuit with high robustness

Abstract

The invention belongs to the field of airborne computer embedded design, and provides a high-robustness wheel speed acquisition method and circuit, and the method comprises the steps: enabling a wheel speed sensor to be connected to a DC power supply access composed of a pull-up / pull-down resistor, so as to provide a drive current; sequentially carrying out overvoltage clamping, first-order band-pass filtering, differential mode interference filtering and second-order low-pass filtering on a differential signal output by the sensor; 5 V reference voltage is amplified and superposed, so that the signal is raised to 0 V or above; square waves are generated through hysteresis comparison, and the FPGA carries out anti-shake and counting to obtain a wheel speed frequency value. And simultaneously executing open circuit detection and BIT excitation self-detection. The circuit comprises a driving unit, a filtering unit, an amplifying unit, a comparing unit, an FPGA unit and a self-checking unit. Through triple filtering, level lifting, digital anti-shake and an isolation type BIT mechanism, the anti-interference capability and reliability are remarkably improved, a special chip is not needed, the cost is reduced by about 12%, and the method is suitable for high-safety scenes such as airplane braking, skid resistance and automatic driving.

Description

Technical Field

[0001] This invention belongs to the field of embedded design of airborne computers and relates to a wheel speed acquisition method and circuit with high robustness. Background Technology

[0002] In the design of airborne electronic products, ensuring flight safety is always the primary objective. Wheel speed data acquisition is closely related to multiple critical scenarios such as braking, anti-skid, traction control, autopilot, and ground operations. Therefore, highly reliable and accurate wheel speed data acquisition has become one of the important requirements for ensuring flight safety, improving handling performance, and optimizing maintenance management. Furthermore, wheel speed data is widely used in aircraft navigation and landing processes. For example, during takeoff and landing, accurate wheel speed information helps the aircraft accurately align with the runway and achieve a safe touchdown. Therefore, highly reliable and accurate wheel speed data acquisition has become an important technical requirement for ensuring flight safety, improving handling performance, and optimizing maintenance management.

[0003] Achieving highly reliable wheel speed data acquisition requires not only high-precision sensors but also stable power supply, excellent anti-interference capabilities, and robustness in complex airborne electromagnetic environments to ensure normal operation under various conditions. Simultaneously, as equipment develops towards lower costs and sustainability, higher demands are being placed on the overall system cost.

[0004] Current mainstream design methods often use dedicated frequency acquisition chips to acquire and process wheel speed data. However, these methods suffer from poor robustness, high cost, and susceptibility to interference, frequently resulting in wheel speed value jumps and signal distortion in practical applications. Therefore, there is an urgent need for a wheel speed acquisition circuit that can withstand the harsh electromagnetic interference environment on board, possesses strong anti-interference capabilities, and is more cost-effective, in order to improve the overall reliability and economy of airborne systems. Summary of the Invention

[0005] To address the problems of susceptibility to interference, fluctuating measured values, lack of fault diagnosis capabilities, and high cost in existing wheel speed signal acquisition methods, this invention provides a highly robust wheel speed acquisition method. This method is particularly suitable for applications with stringent reliability requirements for wheel speed signals, such as aircraft brake control, anti-skid systems, traction control, autopilot, and ground operations.

[0006] Specifically, the method includes the following steps: S1. Connect the wheel speed sensor to the DC power supply path composed of a pull-up resistor and a pull-down resistor to provide static drive current for the wheel speed sensor. The pull-up resistor is connected to the +15V power supply, and the pull-down resistor is connected to the analog ground AGND. S2. The differential signal output by the wheel speed sensor is sequentially subjected to overvoltage clamping, first-order bandpass filtering, differential mode interference filtering, and second-order low-pass filtering. S3. Amplify the filtered differential signal and superimpose the reference voltage to raise the overall output signal to above 0V; S4. The raised single-ended signal is sent to the hysteresis comparator to generate a square wave pulse, and the square wave pulse is input to the FPGA for anti-jitter processing and frequency counting to obtain the wheel speed frequency value. S5. During the wheel speed signal acquisition process, open circuit detection and BIT excitation self-test are performed simultaneously.

[0007] Furthermore, the FPGA performs minimum pulse width determination on the input square wave pulse, and determines that the square wave pulse is a valid signal when the duration of the high and low levels exceeds a set time.

[0008] Furthermore, the open-circuit detection method includes: When the positive terminal voltage of the wheel speed sensor is within the first threshold range, it is determined to be a normal connection; when the positive terminal voltage exceeds the first threshold range and reaches the second threshold range, it is determined to be an open circuit.

[0009] Furthermore, the method for BIT stimulus self-checking includes: Under FPGA control, the comparator outputs a low level to turn on the isolation diode, injecting a 1kHz square wave excitation signal into the positive terminal of the wheel speed sensor; in non-self-test mode, the comparator outputs a high level to reverse-bias the isolation diode and cut it off, thus electrically isolating the excitation path from the main signal path.

[0010] This invention also provides a wheel speed acquisition circuit with high robustness, including a drive current output unit, a signal preprocessing unit, a signal conditioning unit, a pulse generation unit, a frequency acquisition unit, and a self-test diagnostic unit.

[0011] The drive current output unit is used to connect the wheel speed sensor to the DC power supply path consisting of pull-up resistors and pull-down resistors. The signal preprocessing unit performs overvoltage clamping, first-order bandpass filtering, differential mode interference filtering, and second-order low-pass filtering sequentially on the differential signal output by the wheel speed sensor. The signal conditioning unit is used to amplify the filtered differential signal and superimpose a reference voltage to raise the overall output signal to above 0V; The pulse generation unit is used to convert the boosted single-ended signal into a square wave pulse; The frequency acquisition unit is used to receive square wave pulses and perform anti-jitter processing and frequency counting; The self-test diagnostic unit is used to simultaneously perform open-circuit detection and BIT-stimulated self-test during the data acquisition process.

[0012] Furthermore, the drive current output unit includes: The parallel pull-up resistors R1 and R2 are connected between the +15V power supply and the positive terminal of the wheel speed sensor, respectively. The parallel pull-down resistors R3 and R4 are connected between the negative terminal of the wheel speed sensor and the analog ground AGND, respectively.

[0013] Furthermore, the signal preprocessing unit includes: An overvoltage protection circuit, connected between the positive and negative terminals of the wheel speed sensor, includes diodes V1 and V2 connected in reverse parallel to limit the amplitude of the differential signal within a set amplitude range. A first-order bandpass filter, comprising cascaded high-pass and low-pass RC networks, with a passband range of 5.3 Hz to 49.8 kHz; The differential mode interference filtering circuit is connected across the input terminal of the differential amplifier N1 via a 10nF capacitor C5; The second-order low-pass filter consists of an operational amplifier N2 and a symmetrical RC network, with a cutoff frequency of 124.5kHz.

[0014] Furthermore, the signal conditioning unit includes: The precision instrumentation amplifier N1 is externally connected to a 10kΩ gain resistor Rg; A reference voltage source is connected to the bias terminal of the precision instrumentation amplifier N1, and provides a 5V reference voltage through a voltage divider formed by resistors R24 and R25.

[0015] Furthermore, the pulse generation unit includes: Hysteresis comparator N3 is connected to feedback resistor R14, and its hysteresis range is configured through the feedback resistor R14. The output of the hysteresis comparator N3 is connected to the FPGA input pin Wheel_Speed_FPGA1.

[0016] Furthermore, the self-diagnostic unit includes: The open-circuit detection sub-circuit includes voltage divider resistors R18 and R19, voltage follower N4B, and ADC, used to acquire the positive terminal voltage of the wheel speed sensor. The BIT excitation sub-circuit includes a comparator N5B, an isolation diode V3, and a control signal terminal IO_Wheel_Speed_BIT_CTR_5V, which is used to turn on in self-test mode and inject a 1kHz square wave excitation signal into the positive terminal of the wheel speed sensor.

[0017] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least: 1. High anti-interference capability: Through triple filtering (first-order bandpass + differential mode rejection + second-order low-pass), signal level boosting, hysteresis comparison and FPGA anti-jitter synergy, it effectively suppresses common-mode / differential-mode interference in harsh airborne electromagnetic environments and avoids wheel speed jumps; 2. High reliability and testability: Integrated open-circuit detection and isolated BIT excitation functions, supporting real-time monitoring of sensor status and online self-testing of the data acquisition link; 3. Low-cost implementation: No dedicated frequency acquisition chip or external excitation circuit is required. All functions are completed using general-purpose analog devices and FPGA logic, reducing the overall cost by approximately 12%. 4. Compact structure and strong compatibility: The method and circuit architecture are highly matched, and it is suitable for a variety of excitation wheel speed sensors to meet the high safety requirements of aircraft braking, anti-skid, autopilot and other scenarios.

[0018] In summary, this invention can effectively filter out common-mode and differential-mode clutter in airborne environments and improve system reliability through multiple protection and self-testing mechanisms, reducing costs by approximately 12% compared to traditional solutions. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the highly robust wheel speed acquisition method of the present invention; Figure 2 This is a schematic diagram illustrating the principle of the highly robust wheel speed acquisition method of the present invention. Figure 3 This is a schematic diagram of the highly robust wheel speed acquisition circuit of the present invention; Figure 4 This is a circuit diagram of the wheel speed acquisition circuit with high robustness of the present invention; Figure 5 It is the wheel speed signal input waveform of the wheel speed sensor; Figure 6 It is the signal amplified by the instrument's operational amplifier; Figure 7 It outputs a square wave signal after hysteresis comparison. Detailed Implementation

[0021] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0022] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features of the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] This invention provides a robust wheel speed acquisition method, see [link to relevant documentation]. Figure 1 and Figure 2 As shown, the method includes the following steps: S1. Connect the wheel speed sensor to the DC power supply path composed of a pull-up resistor and a pull-down resistor to provide the wheel speed sensor with a static drive current of 8~10mA. The pull-up resistor is connected to the +15V power supply, and the pull-down resistor is connected to the analog ground AGND. S2. The differential signal output by the wheel speed sensor is sequentially subjected to overvoltage clamping, first-order bandpass filtering, differential mode interference filtering, and second-order low-pass filtering. S3. Amplify the filtered differential signal and superimpose the reference voltage to raise the overall output signal to above 0V; S4. The raised single-ended signal is sent to the hysteresis comparator to generate a square wave pulse, and the square wave pulse is input to the FPGA for anti-jitter processing and frequency counting to obtain the wheel speed frequency value. S5. During the wheel speed signal acquisition process, open circuit detection and BIT excitation self-test are performed simultaneously.

[0024] Furthermore, the overvoltage clamping is achieved by diodes V1 and V2 connected in reverse parallel to limit the amplitude of the differential signal within a set amplitude range (e.g., ±0.7V). The first-order bandpass filter is composed of a cascaded high-pass filter and a low-pass filter, allowing signals within a set frequency band (5.3Hz to 49.8kHz) to pass through; The differential mode interference filtering is achieved by connecting capacitor C5 across the input of the differential amplifier, forming a differential mode low-pass characteristic with a cutoff frequency of approximately 1.64kHz. The second-order low-pass filter is composed of an operational amplifier N2 and a symmetrical RC network, with a cutoff frequency of 124.5kHz.

[0025] Furthermore, the FPGA performs minimum pulse width determination on the input square wave pulse, and determines that the square wave pulse is a valid signal when the duration of the high and low levels exceeds a set time (e.g., 50μs).

[0026] Furthermore, the open-circuit detection method includes: When the positive terminal voltage of the wheel speed sensor is within the first threshold range (e.g., around 9.4V), it is determined to be a normal connection. When the positive terminal voltage exceeds the first threshold range and reaches the second threshold range (e.g., rises to around 14V), it is determined to be an open circuit.

[0027] Furthermore, the method for BIT stimulus self-checking includes: Under FPGA control, the comparator outputs a low level to turn on the isolation diode, injecting a 1kHz square wave excitation signal into the positive terminal of the wheel speed sensor; in non-self-test mode, the comparator outputs a high level to reverse-bias the isolation diode and cut it off, thus electrically isolating the excitation path from the main signal path.

[0028] It should be noted that since the anode of the isolation diode V3 is connected to the positive terminal of the sensor (normal operating voltage is about 9.4V) and the cathode is connected to the output terminal of the comparator N5B; when N5B outputs a high level of +15V, the diode is under reverse voltage (9.4V < 15V), so it is cut off and no current is injected, thus not affecting the original wheel speed signal.

[0029] This invention also provides a wheel speed acquisition circuit with high robustness, see [link to relevant documentation]. Figure 2 and Figure 3 As shown, it includes a drive current output unit, a signal preprocessing unit, a signal conditioning unit, a pulse generation unit, a frequency acquisition unit, and a self-test diagnostic unit.

[0030] The drive current output unit is used to connect the wheel speed sensor to the DC power supply path consisting of pull-up resistors and pull-down resistors. The signal preprocessing unit performs overvoltage clamping, first-order bandpass filtering, differential mode interference filtering, and second-order low-pass filtering sequentially on the differential signal output by the wheel speed sensor. The signal conditioning unit is used to amplify the filtered differential signal and superimpose a reference voltage to raise the overall output signal to above 0V; The pulse generation unit is used to convert the boosted single-ended signal into a square wave pulse; The frequency acquisition unit is used to receive square wave pulses and perform anti-jitter processing and frequency counting; The self-test diagnostic unit is used to simultaneously perform open-circuit detection and BIT-stimulated self-test during the data acquisition process.

[0031] Further, see Figure 4As shown, the drive current output unit includes: a pull-up resistor R1 and a pull-up resistor R2 connected in parallel, which are respectively connected between the +15V power supply Vcc and the positive terminal of the wheel speed sensor; and a pull-down resistor R3 and a pull-down resistor R4 connected in parallel, which are respectively connected between the negative terminal of the wheel speed sensor and the analog ground AGND.

[0032] Specifically, since the wheel speed sensor is an excitation type sensor, it requires an 8~10mA static current to operate. Through the drive current output unit, it is possible to generate excitation without the help of external circuits. When the sensor is connected to the power supply circuit, it can provide the drive current required for the sensor to operate while detecting open circuits.

[0033] More specifically, the current that this circuit can provide to the wheel speed sensor is: ; Where Rs is the load value of the wheel speed sensor itself, and the wheel speed acquisition input signal is shown in [reference needed]. Figure 5 As shown.

[0034] Further, see Figure 4 As shown, the signal preprocessing unit includes an overvoltage protection circuit, a first-order bandpass filter, a differential-mode interference filtering circuit, and a second-order low-pass filter.

[0035] (1) Overvoltage protection circuit: Since the output amplitudes of different wheel speed sensors are inconsistent, some sensors have relatively large voltages at high frequencies. Therefore, adding a clamping circuit (i.e., overvoltage protection circuit) can prevent the circuit from being damaged by excessively high input signals when the speed is high, thus greatly improving the robustness of the circuit. Specifically, the overvoltage protection circuit is connected between the positive and negative terminals of the wheel speed sensor, including diodes V1 and V2 connected in reverse parallel, which limits the amplitude of the differential signal to a set amplitude range (e.g., ±0.7V).

[0036] (2) The first-order bandpass filter consists of a cascaded high-pass RC network (R5 / C1, R6 / C2) and a low-pass RC network (R7 / C3, R8 / C4), with a passband range of 5.3Hz to 49.8kHz. Specifically, this first-order bandpass filter is a bandpass filter with a DC blocking capacitor. A high-pass filter with a cutoff frequency of f_H is designed using resistors and DC blocking capacitors, and a low-pass filter with a cutoff frequency of f_L is designed using resistors and capacitors. Connecting the high-pass filter and the low-pass filter in series yields a bandpass filter, which allows signals within a certain frequency band to pass through.

[0037] More specifically, this first-order bandpass filter is a bandpass filter with a DC blocking capacitor, and a cutoff frequency of f_ is designed using resistors and the DC blocking capacitor. H A high-pass filter is then designed using resistors and capacitors, with a cutoff frequency of f_. LA low-pass filter is formed by combining R5 and C1, and R6 and C2. A high-pass filter is formed by combining R7 and C3, and R8 and C4. Connecting the high-pass and low-pass filters in series yields a band-pass filter, which only allows signals within the frequency band f_L~f_H to pass through, where f=1 / (2π*R*C). Calculations show that signals with frequencies from 5.3Hz to 49.823kHz can pass through the band-pass filter circuit without attenuation.

[0038] (3) The differential interference filtering circuit is connected across the input terminal of the differential amplifier N1 via a (10nF) capacitor C5. Specifically, considering that the signal output by the sensor may be attenuated, this invention amplifies the output of the sensor by introducing a differential proportional amplifier circuit composed of a precision instrumentation amplifier, which has the characteristics of strong output signal and strong anti-interference capability, and can improve the anti-interference capability of the circuit.

[0039] Meanwhile, since the wheel speed signal output by the sensor is generally a differential signal, the first-order filtering module mainly filters out common-mode interference but does not filter out differential-mode interference. Therefore, this invention introduces a differential-mode interference filtering capacitor inside the amplifier circuit, so that high-frequency differential-mode interference is directly short-circuited to the negative input terminal through the positive input terminal, and will not affect the subsequent circuit. Since the differential-mode capacitor needs to filter out high-frequency differential-mode interference signals, and the capacitance value determines the cutoff frequency of the differential-mode filter, the capacitance value is selected as 10nF in this invention.

[0040] Considering that the subsequent hysteresis comparison module needs to set a comparison threshold to compare the processed wheel speed signal and convert it into a periodic pulse signal for wheel speed calculation, this invention introduces a reference voltage to ensure higher robustness of the signal input to the hysteresis comparison, thereby boosting the overall signal on top of the amplification. Specifically, the differential amplifier circuit is set with a reference bias of 5V. This bias voltage boosts the overall output signal of the differential amplifier circuit, adjusting the original zero-crossing sine signal to a signal where the entire output signal is above 0V, avoiding comparisons near zero voltage and improving the circuit's anti-interference performance.

[0041] More specifically, the differential mode interference filtering circuit involves the following three parts: (1) Compensation and amplification of signal attenuation at the sensor output: In the amplification section, a matching resistor R9 is designed, with one end connected to pin 1 of the instrumentation amplifier and the other end connected to pin 8 of the instrumentation amplifier, to amplify the input signal between -0.7V and 0.7V. The formula for calculating the amplification factor is as follows: A= ; Where Rg is 10K, the amplification factor A is calculated to be 5.94, which means that the input signal is amplified by 5.94 times.

[0042] (2) Differential mode interference filtering: Since the wheel speed signal output by the sensor is generally a differential signal, the first-order filtering module mainly filters out common mode interference, but does not filter out differential mode interference. This invention introduces a differential mode interference filtering circuit so that high-frequency differential mode interference is directly short-circuited to the negative input terminal through the positive input terminal, and will not affect the subsequent circuit. Otherwise, once the signal with differential mode interference is amplified, it will have a significant impact on the circuit.

[0043] Since differential-mode capacitors are needed to filter out high-frequency interference signals, and the three-dimensional capacitance value determines the cutoff frequency of the differential-mode filter, in this invention, the positive terminal of C5 in the differential amplification section is connected to the positive input terminals of R7 and N1 (instrumentation amplifier), and the negative terminal of C5 is connected to the negative input terminals of R8 and N1 (instrumentation amplifier), thus forming a differential-mode filter. The capacitance value of the differential-mode capacitor C5 at both ends of the differential input is 10nF. The cutoff frequency at this time... The calculation formula is as follows: ; Calculations show that the differential filter cutoff frequency is 1.64kHz. When the frequency signal is higher than this frequency, the amplitude of the input differential signal will be attenuated accordingly.

[0044] (3) Introducing a DC component to improve circuit robustness: The differential amplifier circuit is set with a reference bias of 5V. This bias voltage raises the overall output signal of the differential amplifier circuit, adjusting the original zero-crossing sine signal to a signal of 0.8V~9.2V, avoiding comparisons near zero voltage, and improving the circuit's anti-interference performance. The signal after amplification by the instrument is shown in [image / description]. Figure 6 As shown.

[0045] (4) Second-order low-pass filter: Although a first-order bandpass filter and differential mode interference filtering circuit have been designed, considering the complex electromagnetic environment on the machine, there is still a certain amount of high-frequency interference. Based on the bandpass filter, this invention introduces a second-order active low-pass filter circuit composed of operational amplifier N2 and a symmetrical RC network (R10=R11, C7=C8) to perform low-pass filtering on the amplified single-ended signal, further filtering out high-frequency interference on the machine and achieving a cutoff frequency of 124.5kHz.

[0046] Specifically, since first-order filtering can filter out signals outside the 5.3Hz~49.823KHz frequency band, but the 5.3Hz~49.823KHz frequency band is relatively wide, there is often common-mode interference within the frequency band in the harsh environment on the machine. Since the differential-mode filtering at the back end cannot effectively filter it out, second-order filtering is required to further filter out high-frequency interference.

[0047] A second-order active low-pass filter circuit consists of an operational amplifier and discrete resistors and capacitors, such as... Figure 4As shown, it consists of R10, R11, C7, C8, and operational amplifier N2. One end of R10 is connected to R11 and C7, and the other end is connected to the output of instrumentation amplifier N1. The other end of R7 is connected to C8 and the positive terminal (pin 3) of N2. The other end of C8 is grounded, and the other end of C7 is connected to the output terminal (pin 1) and negative terminal (pin 2) of N2. One end of C9 and C10 is grounded, the other end of C9 is connected to +15V, and the other end of C10 is connected to -15V. In this invention, R10 and R11 have equal values, and C7 and C8 have equal values. Assuming R10 and R11 are valued as R, and C5 and C6 are valued as C, then the current equation at point M is: ; The equation for the current at point N is: ; In summary, the cutoff frequency can be obtained. for: ; The cutoff frequency was calculated to be 124.53 kHz.

[0048] Further, see Figure 4 As shown, the signal conditioning unit includes a precision instrumentation amplifier N1 and a reference voltage source.

[0049] The precision instrumentation amplifier N1 is externally connected to a 10kΩ gain resistor Rg, and its amplification factor is 5.94. A reference voltage source is connected to the bias terminal of the precision instrumentation amplifier N1, and a 5V reference voltage is provided through a voltage divider formed by resistors R24 and R25. This makes the output signal range 0.8V to 9.2V.

[0050] Further, see Figure 4 As shown, the pulse generation unit includes a hysteresis comparator N3, which is connected to a feedback resistor R14, and its hysteresis range is configured through the feedback resistor R14; the output of the hysteresis comparator N3 is connected to the FPGA input pin Wheel_Speed_FPGA1.

[0051] Specifically, in order to prevent the frequency acquisition circuit from jumping around the comparison threshold, this invention designs a hysteresis comparator N3. The signal output from the differential amplifier is sent to the hysteresis comparator N3, which is composed of a voltage comparator, which can effectively prevent inaccurate comparison caused by waveform instability.

[0052] More specifically, such as Figure 4As shown, one end of resistor R12 is connected to pin 1 of the output of N2 in the second-order filter, and the other end is connected to the negative input of comparator N3. One end of R13 is connected to the comparison reference source, and the other end is connected to the positive input of comparator N3. R14 serves as a feedback resistor, with one end connected to the positive input of comparator N3 and the other end connected to pin 2 of the output of comparator N3. At the same time, it is pulled up through R15.

[0053] It is important to note here that the wheel speed signal outside the cutoff frequency will experience significant amplitude attenuation after second-order low-pass filtering. This attenuation characteristic should be fully considered; the comparator threshold should be designed to be lower than the attenuated amplitude. Otherwise, the problem of abrupt changes in the wheel speed acquisition value will still occur. The signal after hysteresis comparison is shown below. Figure 7 As shown.

[0054] Furthermore, the FPGA logic is designed as follows: The square wave signal output from the hysteresis comparator enters the FPGA and is acquired by the FPGA. The FPGA logic uses a counting method to acquire the wheel speed signal, starting recording at the rising edge of the input signal and ending the count at the next rising edge, then starting the next count. Simultaneously, the FPGA logic performs debouncing processing on all input square wave signals. The maximum actual operating frequency of the wheel speed is 3600Hz. The debouncing time for high and low levels is set to 50µs. Only when the duration of a high or low level exceeds 50µs will the logic consider it as 1 or 0; signals shorter than this time width are considered invalid. When the input signal is invalid, the logic's debouncing output value remains the value of the previous cycle.

[0055] More specifically, the FPGA logic stores the count value in a register, which is then read by the software. The software calculates the input signal frequency based on the read count value. The details are as follows: ; In the formula: f3 is the sampling frequency, Hz; The software counting frequency is 60MHz; cnt is the count value.

[0056] In the FPGA logic, all input square wave signals are debouncing. The actual operating frequency of the wheel speed is up to 3600Hz. The debouncing time for high and low levels in the logic is set to 50us. Only when the duration of high and low levels exceeds 50us will the logic consider it as 1 or 0. Signals with a duration shorter than this are considered invalid signals. When the input signal is invalid, the debouncing output value of the logic remains the value of the previous cycle.

[0057] Further, see Figure 4 As shown, the self-test diagnostic unit includes an open-circuit detection sub-circuit and a BIT excitation sub-circuit.

[0058] The open-circuit detection sub-circuit includes voltage divider resistors R18 and R19, a voltage follower N4B, and an ADC, used to acquire the positive terminal voltage of the wheel speed sensor. The BIT excitation sub-circuit includes a comparator N5B, an isolation diode V3, and a control signal terminal IO_Wheel_Speed_BIT_CTR_5V, used to conduct in self-test mode and inject a 1kHz square wave excitation signal into the positive terminal of the wheel speed sensor.

[0059] Specifically, the purpose of the BIT excitation circuit design is to verify the correctness of the frequency signal acquisition circuit of the takeoff and landing control unit. This is achieved by applying an excitation signal to the positive line of the wheel speed through a logic-controlled comparator. A diode is designed between the positive line signal of the wheel speed and the comparator. During normal acquisition, the comparator outputs a +15V voltage, the diode does not conduct, and the positive line signal of the wheel speed and the comparator are in a high-impedance state. The circuit responds to external input signals. The purpose of the open-circuit detection circuit design is to detect whether the wheel speed sensor is open-circuited. This is achieved by dividing and sampling the positive line voltage of the wheel speed sensor.

[0060] For more details, see Figure 4 As shown, the open-circuit detection circuit is designed to detect whether the wheel speed sensor is open-circuited. This is achieved by dividing and sampling the positive voltage of the wheel speed sensor, specifically as follows: one end of resistor R16 is connected to the positive terminal of the sensor, and the other end is connected to R17 and the positive terminal of comparator N3. The other end of R17 is grounded. The output of N3 is connected back to the negative input terminal, forming a follower circuit. Simultaneously, the comparison result is transmitted to the A / D conversion module for conversion and reported to the processor to obtain the monitoring results in real time. In this invention, when the wheel speed sensor is normally connected, its positive voltage is approximately 9.4V; when the wheel speed sensor is open-circuited, its positive voltage is approximately 14V. By sampling the positive voltage, the open-circuit detection can be achieved.

[0061] The purpose of the BIT excitation circuit design is to verify the correctness of the frequency signal acquisition circuit. The specific implementation method is as follows: A 5V power supply is divided by resistors R18 and R19 to generate an excitation reference voltage, which is connected to the negative terminal of comparator N4. The logic output control signal is connected to the positive terminal of comparator N4. Pin 1 of the comparator N4's output is pulled up by resistor R20 and then connected in series with resistor R21. The other end of R21 is connected to the cathode of the reverse diode V3. The positive terminal of V3 is connected to the positive terminal of the sensor input, serving as the excitation source. Under normal circumstances, the FPGA output is high, the comparator output is open, the diode is not conducting, and no excitation occurs. When excitation is needed, the FPGA outputs low at a certain frequency, causing the comparator output to go low, the diode conducts, and the positive terminal of the diode is pulled low. Subsequently, the FPGA outputs high again, causing the diode to deconduct, resulting in a high output, forming a 1kHz square wave for excitation.

[0062] The wheel speed acquisition input signal, the amplified output signal of the instrument operational amplifier, and the square wave output signal after hysteresis comparison are respectively as follows: Figures 5-7 As shown, when Figure 7 The logic requires that the duration of the high / low level of the Chinese wave be longer than 50µs to be recognized as a valid signal. If the duration is less than 50µs, the corresponding signal will be filtered out by the logic.

[0063] The embodiments of the present invention achieve the following technical effects: 1. Comprehensive functional modules: It includes nine functional modules, namely drive current output, first-order filtering, overvoltage protection, differential amplification, second-order filtering, hysteresis comparison, FPGA logic debouncing and frequency counting, BIT excitation and open circuit detection, forming a complete wheel speed signal processing link.

[0064] 2. Self-powered design: The drive current output module does not require an external excitation circuit. It directly connects the sensor to the power supply circuit, providing the sensor with the 8~10mA static drive current required for operation, and can detect fault status by changing the positive terminal voltage when the circuit is open.

[0065] 3. Overvoltage protection mechanism: An interlocking circuit is designed. When the wheel speed is too high and the sensor output signal voltage is too large, the diode connected in reverse parallel will limit the input signal amplitude to within ±0.7V to prevent overvoltage damage at high speed and improve circuit robustness.

[0066] 4. Compensation and amplification measures: To address the issue of sensor output signal attenuation, a precision instrumentation amplifier is used for gain adjustment, and a 5V reference bias is superimposed to raise the overall signal to a non-zero level range (e.g., 0.8V~9.2V), avoiding false triggering caused by comparisons near the zero level.

[0067] 5. Triple filtering mechanism: A triple filtering system including first-order bandpass filtering, differential-mode interference filtering, and second-order low-pass filtering is constructed to effectively suppress common-mode and differential-mode noise in the airborne environment and significantly improve circuit robustness.

[0068] 6. DC bias boost: Introducing a 5V DC bias boosts the overall signal after differential amplification, ensuring that all signals are above zero level and reducing the risk of misjudgment caused by fluctuations near zero.

[0069] 7. Hysteresis Comparison Design: A hysteresis comparator is introduced into the frequency acquisition circuit, which allows for the configuration of a hysteresis window to prevent fluctuations in the wheel speed signal near the threshold from causing jumps in the acquired value and to enhance anti-interference capability.

[0070] 8. FPGA Anti-jitter Logic: Unlike traditional hardware filtering methods, anti-jitter logic is added to the FPGA. A minimum pulse width discrimination threshold is set (e.g., 50μs). Only when the duration of the square wave high and low levels exceeds this threshold is it considered a valid signal, further reducing external glitches and interference.

[0071] 9. Real-time Open Circuit Detection: Real-time monitoring of sensor open circuits is achieved by using the voltage at the positive terminal of the voltage divider wheel speed sensor. The voltage is approximately 9.4V during normal connection and rises to approximately 14V during open circuit. The processor uses this voltage to determine the fault status, improving circuit testability.

[0072] 10. Customized isolation mechanism: The open circuit detection module is designed with a customized isolation mechanism to ensure that the detection circuit will not affect the main signal path and maintain the purity of the wheel speed signal.

[0073] 11. BIT Excitation Self-Test Function: By using a logic-controlled comparator to inject a 1kHz square wave excitation signal into the sensor's positive line, an online self-test (BIT) is achieved for the wheel speed acquisition link, further improving the circuit's testability and reliability.

[0074] 12. Isolated excitation circuit: The BIT excitation generation module has an internal isolation mechanism. The excitation signal path is electrically isolated from the main signal path through isolation diodes, so as to avoid the influence of the excitation circuit itself on the wheel speed signal.

[0075] Obviously, those skilled in the art should understand that the electronic components or steps of the above-described embodiments of the present invention can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the embodiments of the present invention are not limited to any particular combination of hardware and software.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A highly robust wheel speed acquisition method, characterized in that, include: The wheel speed sensor is connected to a DC power supply path consisting of a pull-up resistor and a pull-down resistor to provide a static drive current for the wheel speed sensor. The pull-up resistor is connected to a +15V power supply, and the pull-down resistor is connected to analog ground AGND. The differential signal output by the wheel speed sensor is sequentially subjected to overvoltage clamping, first-order bandpass filtering, differential mode interference filtering, and second-order low-pass filtering. The filtered differential signal is amplified and a reference voltage is superimposed to raise the overall output signal to above 0V; The raised single-ended signal is sent to a hysteresis comparator to generate a square wave pulse, and the square wave pulse is input to the FPGA for anti-jitter processing and frequency counting to obtain the wheel speed frequency value. During the wheel speed signal acquisition process, open circuit detection and BIT excitation self-test are performed simultaneously.

2. The wheel speed acquisition method with high robustness according to claim 1, characterized in that, The FPGA performs minimum pulse width determination on the input square wave pulse, and determines that the square wave pulse is a valid signal when the duration of the high and low levels exceeds a set time.

3. The robust wheel speed acquisition method according to claim 1, characterized in that, The open-circuit detection method includes: When the positive terminal voltage of the wheel speed sensor is within the first threshold range, it is determined to be a normal connection; when the positive terminal voltage exceeds the first threshold range and reaches the second threshold range, it is determined to be an open circuit.

4. The wheel speed acquisition method with high robustness according to claim 1, characterized in that, The method for BIT incentive self-checking includes: Under FPGA control, the comparator outputs a low level to turn on the isolation diode, injecting a 1kHz square wave excitation signal into the positive terminal of the wheel speed sensor; in non-self-test mode, the comparator outputs a high level to reverse-bias the isolation diode and cut it off, thus electrically isolating the excitation path from the main signal path.

5. A wheel speed acquisition circuit with high robustness, characterized in that, include: The drive current output unit is used to connect the wheel speed sensor to a DC power supply path consisting of a pull-up resistor and a pull-down resistor. The signal preprocessing unit is used to sequentially perform overvoltage clamping, first-order bandpass filtering, differential mode interference filtering, and second-order low-pass filtering on the differential signal output by the wheel speed sensor. The signal conditioning unit is used to amplify the filtered differential signal and superimpose a reference voltage to raise the overall output signal to above 0V. The pulse generation unit is used to convert the boosted single-ended signal into a square wave pulse; The frequency acquisition unit is used to receive square wave pulses and perform anti-jitter processing and frequency counting. The self-test diagnostic unit is used to simultaneously perform open circuit detection and BIT-stimulated self-test during the data acquisition process.

6. The wheel speed acquisition circuit according to claim 5, characterized in that, The drive current output unit includes: The parallel pull-up resistors R1 and R2 are connected between the +15V power supply and the positive terminal of the wheel speed sensor, respectively. The parallel pull-down resistors R3 and R4 are connected between the negative terminal of the wheel speed sensor and the analog ground AGND, respectively.

7. The wheel speed acquisition circuit according to claim 5, characterized in that, The signal preprocessing unit includes: An overvoltage protection circuit, connected between the positive and negative terminals of the wheel speed sensor, includes diodes V1 and V2 connected in reverse parallel to limit the amplitude of the differential signal within a set amplitude range. A first-order bandpass filter, comprising cascaded high-pass and low-pass RC networks, with a passband range of 5.3 Hz to 49.8 kHz; The differential mode interference filtering circuit is connected across the input terminal of the differential amplifier N1 via a 10nF capacitor C5; The second-order low-pass filter consists of an operational amplifier N2 and a symmetrical RC network, with a cutoff frequency of 124.5kHz.

8. The wheel speed acquisition circuit according to claim 5, characterized in that, The signal conditioning unit includes: The precision instrumentation amplifier N1 is externally connected to a 10kΩ gain resistor Rg; A reference voltage source is connected to the bias terminal of the precision instrumentation amplifier N1, and provides a 5V reference voltage through a voltage divider formed by resistors R24 and R25.

9. The wheel speed acquisition circuit according to claim 5, characterized in that, The pulse generation unit includes: Hysteresis comparator N3 is connected to feedback resistor R14, and its hysteresis range is configured through the feedback resistor R14. The output of the hysteresis comparator N3 is connected to the FPGA input pin Wheel_Speed_FPGA1.

10. The wheel speed acquisition circuit according to claim 5, characterized in that, The self-test diagnostic unit includes: The open-circuit detection sub-circuit includes voltage divider resistors R18 and R19, voltage follower N4B, and ADC, used to acquire the positive terminal voltage of the wheel speed sensor. The BIT excitation sub-circuit includes a comparator N5B, an isolation diode V3, and a control signal terminal IO_Wheel_Speed_BIT_CTR_5V, which is used to turn on in self-test mode and inject a 1kHz square wave excitation signal into the positive terminal of the wheel speed sensor.

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