FPGA-based timing generator resolution and linearity enhancement method and system

Abstract

The application discloses a kind of FPGA-based timing generator resolution and linearity promotion method and system, belong to automatic test equipment technical field.For the problem that existing FPGA timing generator is difficult to consider high resolution, large dynamic range and high linearity, the application adopts multi-phase clock and carry chain coarse, fine delay line to form three-stage time interpolation architecture, to realize picosecond-level interpolation of large dynamic range with very few logic resources;At the same time, the actual physical delay is obtained by constructing a time measurement channel in the chip, and is transmitted to the host computer to execute the selection algorithm, and the target delay code with the smallest integral nonlinear error is selected to update the delay code table.The application effectively overcomes the nonlinear deviation caused by the underlying hardware wiring, significantly improves the accuracy of timing edge placement and the system test rate, and is mainly used for generating high-precision timing signals in digital integrated circuit automatic test equipment.

Description

Technical Field

[0001] This invention relates to the field of automated test equipment (ATE) technology for digital integrated circuits, and more specifically, to a method and system for improving the resolution and linearity of a timing generator based on FPGA. Background Technology

[0002] In automated test equipment (ATE) for digital integrated circuits, the timing generator is the core module that drives the chip under test (DUT) and acquires its performance parameters. Its key performance indicators include test rate, edge placement resolution, and linearity. With modern digital circuit clock cycles entering the picosecond range, extremely high demands are placed on the resolution and accuracy (linearity) of the timing generator. Existing technologies mainly employ three methods to implement timing generators, but all have significant limitations:

[0003] First, the vernier method. This method uses two oscillator waveforms with a small phase difference ΔT (such as S...). f With S s This is achieved by continuously accumulating fine delays. While it offers good resolution and linearity, the generation of fine delays is accompanied by a significant output delay (i.e.,...). This results in a significant drop in test rate, making it unsuitable for ATE systems that require continuous test signal generation.

[0004] Second, the multiphase clock method. This method uses a multiphase clock generator to divide the master clock period into equal parts to achieve sub-period interpolation. However, in FPGA implementation, it is limited by the inherent physical resource limit of the clock management unit (such as MMCM), and can only output a limited number of clocks, making it difficult to achieve high resolution; moreover, the wiring paths of each phase clock to the multiplexer are different, which can easily lead to deterioration of output linearity.

[0005] Third, the programmable delay line method. This method utilizes cascaded logic resources within the FPGA (such as lookup tables (LUTs) or carry chains (CARRY8). While it can generate picosecond-level delays, its resolution is limited by the physical fixed delay value of the basic unit. Furthermore, covering the entire clock cycle dynamic range requires a massive amount of logic resources, significantly reducing channel scalability. It also tends to increase integral nonlinearity (INL) errors due to differences in the FPGA's underlying layout and routing.

[0006] In summary, existing timing generator technologies cannot simultaneously meet the comprehensive requirements of modern ATE systems for high test rates, picosecond-level high resolution, high linearity, low resource consumption, and high channel scalability. There is an urgent need in this field for an optimized timing generator technology that can take into account the above-mentioned core performance indicators. Summary of the Invention

[0007] The purpose of this invention is to address the aforementioned problems in the prior art by providing a method and system for improving the resolution and linearity of a timing generator based on FPGA. It employs a three-level time interpolation architecture consisting of a multi-phase clock and an FPGA carry chain to achieve a large dynamic range and high resolution with low resource consumption. Furthermore, it innovatively introduces a host computer-based "measurement-selection" closed-loop optimization algorithm, which effectively corrects the nonlinear errors caused by the underlying physical wiring without adding additional hardware.

[0008] To achieve the aforementioned objectives, this invention employs the following technical solution: a method for improving the resolution and linearity of a timing generator based on FPGA, wherein the timing generator is used for generating test waveforms in integrated circuit automated test equipment, including the step of generating a target delay signal according to a delay code table, comprising the following steps:

[0009] Using the timing generator channel configured inside the FPGA, a delay signal based on a three-level time interpolation architecture is generated according to the initial delay code table. The three-level time interpolation architecture includes a multi-phase clock generator cascaded in sequence, a coarse delay line constructed based on the FPGA carry chain structure, and a fine delay line constructed based on the combination of the FPGA carry chain structure and a multiplexer.

[0010] By using the timing measurement channel configured inside the FPGA, the delay signal output by the timing generator channel is sampled and measured to obtain the actual delay value corresponding to the full delay code;

[0011] The actual delay value is transmitted to the host computer, which then runs a preset selection algorithm to select the set of target delay values ​​with the smallest integral nonlinearity error and their corresponding target delay codes from the actual delay values ​​based on the target resolution and target delay line length.

[0012] The target delay code is sent to the FPGA to update the delay code table of the timing generator channel and output the timing signal with linearity correction.

[0013] Furthermore, the steps of generating a delayed signal based on a three-level time interpolation architecture using a timing generator channel configured inside the FPGA include:

[0014] A coarse delay generator is used to generate coarse delays that are integer multiples of the master clock cycle, thereby expanding the dynamic range of timing generation.

[0015] The master clock period is evenly divided using a multiphase clock generator to generate the first-level sub-period time interpolation signal.

[0016] The coarse delay line constructed based on the carry chain structure is used to perform the second-level time interpolation on the first-level sub-cycle time interpolation signal, and its single-level delay step covers the single-level resolution of the multi-phase clock generator.

[0017] The signal from the second-stage time interpolation is used to perform the third-stage time interpolation by using a fine delay line constructed based on a carry chain structure and a multiplexer combination. Its single-stage delay step covers the single-stage resolution of the coarse delay line.

[0018] Furthermore, in the step of performing second-stage time interpolation using a coarse delay line constructed based on a carry chain structure, different signal transmission paths are selected by configuring a multiplexer inside the carry chain structure, so that the input signal is output directly or after passing through a specified delay unit sequence, thereby obtaining a coarse delay signal with high delay consistency.

[0019] Furthermore, in the step of performing third-stage time interpolation using a fine delay line constructed based on a carry chain structure and a multiplexer, multiple intermediate signals with fixed small delay differences are drawn from different delay stages of the carry chain structure, and the multiple intermediate signals are input to a multiplexer constructed by FPGA lookup table mapping. High-resolution fine delay signals are achieved by gating the output, and configurable delay values ​​of multiple orders of magnitude are generated by cascading fine delay lines.

[0020] Furthermore, the steps for obtaining the actual delay value using the time measurement channel configured inside the FPGA include:

[0021] The single-stage resolution of the tapped delay line inside the FPGA is calibrated. The tapped delay line is an input / output delay primitive unit with built-in self-calibration function.

[0022] The output signal of the timing generator channel is sampled at the edge using the calibrated tapped delay line;

[0023] Change the delay code of the timing generator channel, record and obtain the different tap values ​​generated by the corresponding output signal in the tap delay line;

[0024] The actual delay value corresponding to different delay codes is calculated by multiplying the absolute value of the difference between the tap values ​​by the calibrated single-level resolution.

[0025] Furthermore, the step of selecting the target delay value by running a preset selection algorithm on the host computer includes:

[0026] Select an initial value from the measured actual delay values ​​as the starting point for constructing the ideal delay sequence;

[0027] Using the starting point as a reference and the preset target resolution as a step value, calculate the ideal delay value sequence corresponding to the target delay line length;

[0028] Traverse the ideal delay value sequence, select the actual delay value with the smallest deviation from each ideal delay value from all measured actual delay values, combine them into a candidate delay value set, and record the delay code sequence corresponding to the set;

[0029] Calculate the integral nonlinearity error range for each set of candidate delay values;

[0030] Iterate through all the measured actual delay values ​​that can be used as the starting point of the sequence, repeat the above calculation steps, compare and output the delay code sequence corresponding to the minimum integral nonlinearity error range as the target delay code.

[0031] An FPGA-based timing generator system is provided to implement the aforementioned method for improving the resolution and linearity of timing generators. The system includes an FPGA and a host computer.

[0032] The FPGA internally includes a timing generator channel, a timing measurement channel, and a communication interface. The timing generator channel comprises a coarse delay generator, a multiphase clock generator, a coarse delay line constructed based on the FPGA carry chain structure, a fine delay line constructed based on the FPGA carry chain structure and a multiplexer, and a delay code storage unit, used to generate high-resolution timing signals with a large dynamic range based on the delay code table. The timing measurement channel is used to perform physical delay measurement on the timing signals generated by the timing generator channel to obtain the actual delay data corresponding to the full delay code.

[0033] The host computer establishes a data connection with the FPGA through a communication interface to receive actual delay data, executes a preset selection and optimization algorithm to extract the optimized delay code with the minimum integral nonlinearity error, and writes the optimized delay code into the delay code storage unit through the communication interface to complete the system linearity correction.

[0034] Furthermore, the timing generator channel also includes a D flip-flop. The output of the coarse delay generator is connected to the enable input of the D flip-flop, and the output of the fine delay line is connected to the clock input of the D flip-flop. The D flip-flop is used to sample the enable signal output by the coarse delay generator at the trigger edge of the fine delay line output signal, and output the final target timing edge signal.

[0035] Furthermore, the time measurement channel specifically includes at least one cascaded IDELAY3 input / output delay primitive unit, which provides a multi-level tapped delay line array to achieve picosecond-level high-precision edge sampling of the timing signal under test.

[0036] Furthermore, the communication interface is a high-speed PCIe interface based on the TCP / IP protocol, which is used to ensure low-latency transmission of measurement data and control commands between the FPGA and the host computer.

[0037] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0038] 1. Overcoming resource bottlenecks while balancing high resolution and large dynamic range: This invention constructs a three-stage time interpolation architecture consisting of a "multi-phase clock - CARRY8 coarse delay line - CARRY8 fine delay line". Compared to the traditional solution of simply cascading delay lines to cover the entire clock cycle, this architecture can cover the dynamic range of the entire clock cycle with minimal logic resources, while achieving a fine resolution on the order of 10~20ps, greatly increasing the number of test channels that a single FPGA can support.

[0039] 2. Overcoming the limitations of low-level routing and significantly improving timing linearity: Addressing the inherent nonlinear physical defects caused by fixed-layout routing in FPGAs, this invention innovatively proposes a "measurement-selection" closed-loop mechanism. By internally constructing a time measurement channel based on IDELAY3 to obtain the actual physical delay, the host computer algorithm selects the delay code combination with the smallest integral nonlinearity error (INL) from a massive number of delay values ​​according to the target resolution, perfectly correcting the inherent nonlinear deviation of the hardware.

[0040] 3. Eliminate output delay and ensure high test rate of ATE: Unlike the traditional vernier method, which requires accumulating multiple clock cycles to obtain fine phase, the interpolation architecture of this invention can directly complete the signal gating and edge output at the sub-cycle to picosecond level within the current clock cycle, effectively eliminating huge time delay and fully meeting the needs of continuous and high-speed testing of ATE system.

[0041] 4. Possesses environmental adaptability and strong engineering portability: This invention relies entirely on standard logic units within the FPGA (such as CARRY8, LUT, etc.), eliminating the reliance on external high-precision dedicated analog chips. Simultaneously, the "measurement-selection" mechanism supports online automatic system calibration, effectively compensating for timing drift caused by variations in process, voltage, and temperature (PVT), significantly improving the long-term stable operation capability of the equipment under complex working conditions. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the output waveform of the existing vernier method, demonstrating the traditional timing generation principle of the vernier method.

[0043] Figure 2 This is a schematic diagram of a multiphase clock generator based on existing technology, demonstrating the principle of the traditional multiphase clock method;

[0044] Figure 3 This is a schematic diagram of a programmable delay line in the prior art, illustrating the principle of a conventional programmable delay line;

[0045] Figure 4 This is an overall architecture diagram of the timing generator of the present invention, which shows the three-level timing interpolation architecture proposed in the present invention;

[0046] Figure 5 This is a timing flowchart of the timing generator of the present invention, which shows the generation and sampling timing of signals at each stage in the architecture of the present invention;

[0047] Figure 6 This is a schematic diagram of the existing CARRY8 structure, which is an inherent low-level hardware logic resource inside Ultrascale and higher series FPGA chips;

[0048] Figure 7 This is a diagram of the CARRY8 coarse delay line architecture of the present invention, which shows the second-level interpolation architecture based on the carry chain design of the present invention;

[0049] Figure 8 This is a diagram of the CARRY8 fine delay line architecture of the present invention, which shows the third-stage interpolation architecture of the present invention based on carry chain and multiplexer.

[0050] Figure 9 This is a diagram illustrating the linearity improvement scheme of the timing generator of the present invention, showing the "measurement-selection" closed-loop correction system scheme of the present invention;

[0051] Figure 10 This is a flowchart of the selection algorithm of the present invention, which shows the specific software logic of the host computer performing delay code optimization;

[0052] Figure 11 This is a schematic diagram of the selection algorithm effect of the present invention, which intuitively shows the linearity optimization effect before and after algorithm correction;

[0053] Figure 12 This is a graph showing the change of the IDELAY3 delay value with the tap value, illustrating the test results of calibrating the resolution of the measurement channel according to the present invention.

[0054] Figure 13 The diagram shows the performance test results of the multiphase clock generator and CARRY8 coarse delay line of the present invention, demonstrating the actual test performance of the first two stages of the architecture of the present invention.

[0055] Figure 14 This is a performance test chart of the CARRY8 fine delay line and timing generator before selection, showing the initial performance of the third-level architecture and system before calibration.

[0056] Figure 15 This is a performance test chart after the timing generator of the present invention is selected, which shows the final optimization result after the closed-loop correction scheme of the present invention is executed. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0058] Those skilled in the art should understand that, in the disclosure of this invention, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0059] The purpose of this invention is to overcome the bottlenecks in existing technologies regarding test rate, resolution, linearity, and resource utilization. In existing time series generation methods, Figure 1 The diagram illustrates the principle of the vernier method's output waveform. Although this method can produce picosecond-level delays, its output delay increases significantly proportionally with increasing resolution (i.e., ...). It is not suitable for continuously generating test signals. Figure 2 This is a schematic diagram of a multiphase clock generator. Due to the limited number of internal clock management units in the FPGA, its resolution is low, and wiring differences can easily lead to a decrease in linearity. Figure 3 This is a schematic diagram of a programmable delay line. To cover the full clock cycle dynamic range, this scheme requires cascading with massive amounts of logic resources, significantly reducing the system's channel scalability. Furthermore, Figure 6 The diagram shows the inherent CARRY8 structure of Ultrascale and higher series FPGAs, which is the underlying carry chain logic resource for building the high-precision delay line of this invention.

[0060] To address the aforementioned technical problems, this invention discloses a method and system for improving the resolution and linearity of a timing generator based on FPGA. This method and system can be widely applied to automated test equipment (ATE) for digital integrated circuits to generate high-precision timing waveform signals required for chip testing. This addresses the limitations of existing vernier methods (corresponding to...). Figure 1 ), multiphase clock method (corresponding to) Figure 2 ), Programmable delay line method (corresponding to) Figure 3The present invention addresses the shortcomings of not being able to simultaneously achieve high resolution, high linearity, low resource consumption, and high test rate. It achieves picosecond-level high-resolution timing generation through a three-level time interpolation architecture. At the same time, it significantly improves the linearity of timing generation through a closed-loop mechanism of full delay measurement and optimal delay code selection, while reducing FPGA resource consumption and improving multi-channel scalability.

[0061] Example 1: Detailed Implementation of Hardware Architecture for FPGA-Based Timing Generator System

[0062] This system includes a Field-Programmable Gate Array (FPGA) and a host computer. The FPGA and host computer establish a bidirectional data connection through a communication interface. The FPGA internally includes a timing generator channel, a timing measurement channel, and a communication interface. The timing generator channel is the core functional unit, used to generate high-precision timing signals; the timing measurement channel is used for calibration measurement of the full delay value; and the communication interface is used for data interaction with the host computer. The overall architecture corresponds to the attached diagram. Figure 9 Diagram of a scheme to improve the linearity of a timing generator.

[0063] 1. Specific implementation of the timing generator channel

[0064] The timing generator channel, along the signal transmission direction, sequentially includes a coarse delay generator, a multi-phase clock generator, a CARRY8 coarse delay line, a CARRY8 fine delay line, a delay code storage unit, and a D flip-flop. The overall hardware architecture corresponds to the attached... Figure 4 Overall architecture diagram of the timing generator, with corresponding timing execution flow attached. Figure 5 Timing flow chart for timing generator.

[0065] Coarse Delay Generator: Implemented using a synchronous counter built from the FPGA's internal registers. The counter's clock input is connected to the system's main clock, and its counting bit width is configured according to the required maximum test cycle. The coarse delay generator's input is connected to the coarse delay control code output from the delay code storage unit. This control code is used to set the counting threshold. When the counter counts to the threshold, it outputs a high-level enable signal CDG0 to the enable input of the D flip-flop, achieving a coarse delay that is an integer multiple of the main clock cycle, thus extending the overall dynamic range of the timing generator.

[0066] Multiphase clock generator: Implemented using the Mixed Mode Clock Manager (MMCM) within the FPGA, corresponding to... Figure 2The input of the MMCM is connected to the system master clock, which is used to evenly divide the 360° phase of the master clock period into N multi-phase clock signals with equal phase differences. N is a positive integer greater than or equal to 2. In this embodiment, N is 4. The MMCM outputs four multi-phase clock signals with phases of 0°, 90°, 180°, and 270°, respectively. All four clock signals are connected to the input of the multiplexer. The control terminal of the multiplexer is connected to the multi-phase clock delay code output by the delay code storage unit, which is used to select the corresponding phase clock signal MPG0 output according to the delay code, realizing the first-stage sub-cycle time interpolation. The single-stage interpolation step is master clock period / N.

[0067] CARRY8 coarse delay line: Constructed based on the cascaded CARRY8 carry chain units within the FPGA. The internal hardware structure of the CARRY8 unit corresponds to... Figure 6 The cascaded architecture of coarse delay lines corresponds to Figure 7 The CARRY8 unit is an 8-bit carry chain logic unit built into Xilinx Ultrascale and higher series FPGAs. It contains 8 cascaded multiplexers MUXCY0~MUXCY7, as well as corresponding carry outputs CO0~CO7, data inputs DI0~DI7, selectors S0~S7, and carry input CIN.

[0068] In this embodiment, the CARRY8 coarse delay line is composed of 5 cascaded CARRY8 units. The CIN terminal of each CARRY8 unit is connected to the output terminal of the previous stage. The CIN terminal of the first CARRY8 unit is connected to the output terminal MPG0 of the multiphase clock generator. The MUXCY7 multiplexer of each CARRY8 unit is configured with two-way selection mode: the first path is a direct path, where the input signal is input from the CIN terminal and output directly from the output terminal of MUXCY7 via the DI7 terminal; the second path is a full delay path, where the input signal is input from the CIN terminal, passes through all delay units from MUXCY0 to MUXCY6 in sequence, is output from the CO6 terminal, and is then connected to the input terminal of MUXCY7.

[0069] Each CARRY8 unit's selection terminal connects to the coarse delay line control code output from the delay code storage unit, used to select the corresponding path and achieve a fixed-step delay output. The delay step of a single-stage CARRY8 coarse delay line covers the single-stage interpolation step of the multiphase clock generator, achieving the second-stage sub-nanosecond time interpolation, and the output signal CC80 is sent to the input terminal of the CARRY8 fine delay line.

[0070] CARRY8 fine delay line: constructed based on the combination of CARRY8 carry chain unit and multiplexer within the FPGA, corresponding to... Figure 8The CARRY8 fine delay line consists of at least one cascaded delay unit, each delay unit including one CARRY8 unit and one 4-to-1 multiplexer.

[0071] In a single-stage delay unit, the CIN terminal of the CARRY8 unit is connected to the output signal of the previous stage, and the CIN terminal of the first-stage CARRY8 unit is connected to the output terminal CC80 of the CARRY8 coarse delay line. Four intermediate signals are drawn from the four carry output terminals CO1, CO3, CO5, and CO7 of the CARRY8 unit. These four intermediate signals correspond to the outputs of the 1st, 3rd, 5th, and 7th stage delay units within the CARRY8 unit, respectively, and there is a fixed, slight delay difference between them. All four intermediate signals are connected to the input terminals of a 4-to-1 multiplexer. The control terminal of the multiplexer is connected to the fine delay line control code output from the delay code storage unit, used to select the signal output of the corresponding tap based on the control code.

[0072] In this embodiment, the 4-to-1 multiplexer is synthesized using a six-input lookup table (LUT6) within the FPGA. A single-stage multiplexer occupies only one LUT6 logic unit, resulting in extremely low resource consumption. The delay step of the single-stage CARRY8 fine delay line covers the single-stage delay step of the CARRY8 coarse delay line, achieving third-stage picosecond-level time interpolation. The output signal FC80 is then sent to the clock input of the D flip-flop.

[0073] Delay code storage unit: Implemented using the FPGA's internal block memory (BRAM) or register group, it stores all delay control codes required by the timing generator, including control codes corresponding to the coarse delay generator, multiphase clock generator, CARRY8 coarse delay line, and CARRY8 fine delay line. The delay code table can be updated online via the target delay code sent by the host computer.

[0074] D Flip-Flops: Implemented using the FPGA's internal register resources, the D input of the D flip-flop is connected to a high level, the enable input is connected to the enable signal CDG0 output from the coarse delay generator, the clock input is connected to the signal FC80 output from the CARRY8 fine delay line, and the output is the final output EDGE0 of the timing generator. The D flip-flop samples the CDG0 signal on the rising edge of the FC80 signal. When CDG0 is high, the output EDGE0 generates a rising edge, completing the generation of the target timing edge and outputting a high-precision timing signal that meets the test requirements.

[0075] 2. Specific implementation of the time measurement channel

[0076] The timing measurement channel utilizes the IDELAY3 input / output delay primitive unit within the FPGA to construct the edge sampling measurement circuit, resulting in a system architecture with improved overall linearity. Figure 9The IDELAY3 unit is a 512-stage tapped programmable delay line built into the Xilinx FPGA, featuring built-in self-calibration capabilities and enabling picosecond-level delay resolution.

[0077] In this embodiment, to cover the full dynamic range of the timing generator, a multi-level IDELAY3 unit cascade is used to construct the measurement channel. The delay value of a single-level IDELAY3 unit changes with the tap value, corresponding to the attached... Figure 12 The IDELAY3 delay value varies with the tap value. The dynamic range of a single IDELAY3 unit is 1.96ns, and the total measurement range after cascading completely covers the period range of the system master clock. The input of the time measurement channel is connected to the output of the timing generator channel, EDGE0, for high-precision sampling of the edge signal output by the timing generator. By changing the delay tap value of the IDELAY3 unit, the position of the timing signal edge can be captured and the corresponding tap value recorded. By changing the delay code of the timing generator and repeating the sampling measurement, the tap values ​​corresponding to different delay codes can be obtained. Through the calibrated single-tap resolution, the actual delay value corresponding to different delay codes can be calculated.

[0078] 3. Specific implementation of the communication interface

[0079] The communication interface is implemented using a high-speed PCIe interface based on the TCP / IP protocol. The PCIe interface core is integrated inside the FPGA and establishes a physical connection with the host computer through the PCIe bus to realize bidirectional data transmission between the FPGA and the host computer: uploading the full actual delay value obtained by the time measurement channel to the host computer, and simultaneously receiving the optimal target delay code issued by the host computer and writing it into the delay code storage unit to complete the update of the delay code table.

[0080] Example 2: Specific Implementation of the Host Computer Functional Module

[0081] The host computer is a computer device with data processing capabilities, containing a built-in delay data processing module and a selection algorithm module. The delay data processing module receives the measured delay values ​​uploaded by the FPGA and performs data sorting, deduplication, and preprocessing. The selection algorithm module executes a preset optimization algorithm to select the target delay code set with the smallest integral nonlinearity error (INL) at the target resolution from the full set of measured delay values. The algorithm execution flow can be found in [reference needed]. Figure 10 (The text is not entirely accurate, and the accompanying images are only briefly abbreviated due to space limitations.)

[0082] The specific execution steps of the selection algorithm are as follows:

[0083] 1. Data preprocessing: Sort the full measured delay values ​​raw_data uploaded by FPGA in ascending order, and record the original delay code corresponding to each delay value to obtain the sorted delay value array data and the corresponding delay code array code;

[0084] 2. Initialize parameters: Set the optimal INL range best_INL to positive infinity, initialize the optimal delay value array best_data and the optimal delay code array best_code; Input target parameters: target delay line length N, target resolution tau_goal;

[0085] 3. Traverse all sequence starting points: Take the kth value in the sorted delay value array as the sequence starting point, where k ranges from 1 to nN, and n is the total number of measured delay values;

[0086] 4. Constructing a candidate sequence: Starting with the k-th delay value, and combining the target resolution tau_goal and the target length N, construct an ideal delay value sequence. The l-th value of the ideal delay value sequence is data[k]+(l-1). tau_goal, l ranges from 1 to N; iterates through each value in the ideal delay value sequence, matches the actual delay value with the smallest deviation from the ideal value from the sorted delay value array, and generates a candidate delay value array pick_data and a corresponding candidate delay code array pick_code;

[0087] 5. Error Calculation: Calculate the integral nonlinear error INL of the candidate delay value array pick_data. The formula for calculating INL is: INL[l]=(pick_data[l]-pick_data[1]) / tau_goal-(l-1), where l ranges from 1 to N; calculate the range of INL for the candidate sequence, which is the difference between the maximum and minimum values ​​of the INL array.

[0088] 6. Optimal value update: If the INL range of the current candidate sequence is less than best_INL, then update best_INL to the current INL range, and at the same time assign pick_data to best_data and pick_code to best_code.

[0089] 7. After the traversal is complete, the best delay code array best_code is output and sent to the FPGA as the target delay code to update the delay code storage unit.

[0090] The pseudocode for the selection algorithm is as follows:

[0091] def optimize_delay_codes(raw_data, raw_code, target_length, target_resolution):

[0092] # Raw actual delay value array: raw_data, raw actual delay code array: raw_code

[0093] # Target delay line length: target_length, target resolution: target_resolution

[0094] sorted_pairs = sorted(zip(raw_data, raw_code), key=lambda x: x[0])

[0095] data = [pair[0] for pair in sorted_pairs]

[0096] code = [pair[1] for pair in sorted_pairs]

[0097] n = len(data)

[0098] best_inl_range = float('inf')

[0099] best_data = []

[0100] best_code = []

[0101] for k in range(n - target_length + 1):

[0102] pick_data = [0.0] target_length

[0103] pick_code = [0] target_length

[0104] pick_data[0] = data[k]

[0105] pick_code[0] = code[k]

[0106] pos = k

[0107] for l in range(1, target_length):

[0108] ideal_value = pick_data[0] + l target_resolution

[0109] min_error = float('inf')

[0110] for j in range(pos + 1, n):

[0111] current_error = (data[j] - ideal_value) / target_resolution

[0112] if abs(current_error) <abs(min_error):

[0113] min_error = current_error

[0114] pick_data[l] = data[j]

[0115] pick_code[l] = code[j]

[0116] pos = j

[0117] # Calculate the range of integral nonlinearity error (INL) for this selection combination.

[0118] inl_values ​​= []

[0119] for l in range(target_length):

[0120] inl = (pick_data[l] - pick_data[0]) / target_resolution - l

[0121] inl_values.append(inl)

[0122] current_inl_range = max(inl_values) - min(inl_values)

[0123] # Record the optimal combination with the smallest error range

[0124] if current_inl_range <best_inl_range:

[0125] best_inl_range = current_inl_range

[0126] best_data = list(pick_data)

[0127] best_code = list(pick_code)

[0128] return best_data, best_code

[0129] The optimization effect of the above selection algorithm corresponds to Figure 11 The multiple delay values ​​of the CARRY8 coarse delay line are combined into a high-density delay sequence after being staggered by the fine delay line. After being filtered by the selection algorithm, the nonlinear error is greatly eliminated while retaining the high resolution, resulting in a delay sequence with excellent linearity.

[0130] Example 3: Specific Implementation Steps of the Method for Improving the Resolution and Linearity of Timing Generators

[0131] The method for improving the resolution and linearity of the timing generator of the present invention specifically includes the following steps:

[0132] 1. System initialization: After the FPGA is powered on, it completes the self-calibration and initialization of the MMCM and IDELAY3 units, loads the initial delay code table into the delay code storage unit, completes the link training of the PCIe communication interface, and establishes a stable data connection with the host computer.

[0133] 2. Three-stage interpolation timing generation: The timing generator channel generates a delayed signal based on a three-stage time interpolation architecture according to the initial delay code table. The specific process is as follows:

[0134] 2.1 The coarse delay generator, after completing the counting of the corresponding clock cycle according to the coarse delay control code, outputs the enable signal CDG0 to the D flip-flop;

[0135] 2.2 The multiphase clock generator selects the clock signal output of the corresponding phase according to the multiphase clock delay code to complete the first-stage sub-cycle time interpolation;

[0136] 2.3 The CARRY8 coarse delay line outputs the second-stage sub-nanosecond time interpolation of the input signal based on the coarse delay line control code.

[0137] 2.4 The CARRY8 fine delay line performs a third-level picosecond-level time interpolation on the input signal according to the fine delay line control code, and then outputs the trigger signal FC80 to the clock terminal of the D flip-flop;

[0138] 2.5 The D flip-flop samples the CDG0 signal on the rising edge of the FC80 signal and outputs the target timing edge signal. The overall timing flow corresponds to... Figure 5 ;

[0139] 3. Full Delay Value Measurement: Through the time measurement channel, traverse all delay codes of the timing generator, perform edge sampling on the output signal corresponding to each delay code, and obtain the actual delay value corresponding to each delay code. The specific process is as follows:

[0140] 3.1 Calibrate the single-tap resolution of the IDELAY3 cell: Instantiate two IDELAY3 cells located in even-numbered slices and odd-numbered slices respectively. Set the delay value of the IDELAY3 cell in the even-numbered slice to 0 and the delay value of the IDELAY3 cell in the odd-numbered slice to a preset fixed value. Read the CNTVALUEOUT output value of the two cells and calculate the single-tap resolution.

[0141] 3.2 Traverse all delay codes of the timing generator, sample the output edge signal corresponding to each delay code through the IDELAY3 unit, and record the corresponding tap value;

[0142] 3.3 Based on the difference in tap values ​​and the resolution of a single tap, the actual delay value corresponding to each delay code is calculated, and the measurement of the total delay value is completed.

[0143] 4. Optimal delay code selection: The FPGA uploads all measured delay values ​​to the host computer via the PCIe interface. The host computer runs a preset selection algorithm to select the set of target delay values ​​with the smallest INL and the corresponding target delay code from the full set of delay values ​​based on the target resolution and target delay line length.

[0144] 5. Delay Code Table Update and Linearity Correction: The host computer sends the selected target delay code to the FPGA via the PCIe interface. The FPGA writes the target delay code into the delay code storage unit, completing the update of the delay code table. The timing generator channel outputs timing signals based on the updated delay code table, completing linearity correction and realizing high-resolution, high-linearity timing generation.

[0145] Example 4: Preferred Example and Testing Verification

[0146] In this preferred embodiment, the FPGA uses a Xilinx XCKU060FFVA1156-2-I chip, and the system main clock frequency is set to 200MHz, corresponding to a clock period of 5ns.

[0147] 1. Core module parameter configuration

[0148] Multiphase clock generator: Generates four multiphase clocks with phases of 0°, 90°, 180°, and 270° using an MMCM. The single-stage interpolation step is 1.25ns. Actual performance corresponds to... Figure 13 (a) Performance test chart of the multiphase clock generator, with a measured resolution of 1230.3ps and an INL range of -92.4ps to 176.4ps;

[0149] CARRY8 coarse delay line: Employs 5-stage cascaded CARRY8 units, with measured performance corresponding to... Figure 13 (b) Performance test chart of CARRY8 coarse delay line. The measured single-stage delay step is 318.8ps, the total dynamic range is 1276.8ps, and the INL range is 0.0ps~25.2ps;

[0150] CARRY8 fine delay line: Employs cascaded two-stage delay units to generate 16 different delay values, with measured performance corresponding to... Figure 14 The (a)CARRY8 fine delay line performance test chart shows that the measured single-stage delay step is 16.4ps, the total dynamic range is 281.4ps, and the INL range is -16.8ps to 37.8ps.

[0151] Time measurement channel: Employs a cascaded 4-stage IDELAY3 unit, with a single-tap resolution of 4.2 ps after calibration and a total measurement range of 7.84 ns, fully covering the 5 ns master clock cycle. The linear characteristics of IDELAY3 correspond to... Figure 12 The graph shows how the IDELAY3 delay value changes with the tap value.

[0152] 2. Verification of test results

[0153] Performance before selection: The original performance of the timing generator after combining the three-level interpolation architecture. Figure 14 (b) Performance test chart of timing generator before selection, with original resolution of 16.4ps, total dynamic range of 5245.8ps, which can fully cover 200MHz main clock cycle, and INL range of -151.2ps~256.2ps;

[0154] Post-selection performance: After optimization using the selection algorithm of this invention, with a target resolution of 49.7 ps and a target delay line length of 100, the performance of the timing generator corresponding to the optimal delay code set obtained by selection is shown in the attached figure. Figure 15 Performance test results after timing generator selection show that the INL range has been optimized to -16.8ps to 21.0ps, and the linearity has been improved by more than an order of magnitude, verifying the effectiveness of the proposed solution.

[0155] Corresponding Appendix Figure 11The selection algorithm shows that the dynamic range of the coarse delay line of CARRY8 is T_dr1. After combining multiple delay values ​​of the fine delay line of CARRY8, a high-resolution combined delay value is obtained with a dynamic range of T_dr2. After optimization by the selection algorithm, a high-linearity delay value sequence is obtained with a dynamic range of T_dr3. While ensuring high resolution, the linearity is greatly improved.

[0156] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0157] Although this document uses a considerable amount of technical terminology, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention.

[0158] This invention is not limited to the preferred embodiments described above. Anyone can derive other products in various forms under the guidance of this invention. However, regardless of any changes made to their shape or structure, any technical solution that is the same as or similar to this invention falls within the protection scope of this invention.

Claims

1. A method for improving the resolution and linearity of a timing generator based on FPGA, wherein the timing generator is used for generating test waveforms in an integrated circuit automated test equipment, comprising the step of generating a target delay signal according to a delay code table, characterized in that, Includes the following steps: Using the timing generator channel configured inside the FPGA, a delay signal based on a three-level time interpolation architecture is generated according to the initial delay code table; the three-level time interpolation architecture includes a multi-phase clock generator cascaded in sequence, a coarse delay line constructed based on the FPGA carry chain structure, and a fine delay line constructed based on the combination of the FPGA carry chain structure and a multiplexer. Using the time measurement channel configured inside the FPGA, the delay signal output by the timing generator channel is sampled and measured to obtain the actual delay value corresponding to the full delay code; The actual delay value is transmitted to the host computer, which runs a preset selection algorithm to select a set of target delay values ​​and their corresponding target delay codes from the actual delay values ​​based on the target resolution and target delay line length. The target delay code is sent to the FPGA to update the delay code table of the timing generator channel and output a timing signal with linearity correction. The step of obtaining the actual delay value using the time measurement channel configured inside the FPGA includes: The single-stage resolution of the tapped delay line inside the FPGA is calibrated. The tapped delay line is an input / output delay primitive unit with built-in self-calibration function. The output signal of the timing generator channel is sampled at the edge using the calibrated tap delay line; Change the delay code of the timing generator channel, record and obtain the different tap values ​​generated by the output signal corresponding to different delay codes in the tap delay line; The actual delay value corresponding to different delay codes is calculated by multiplying the absolute value of the difference between the tap values ​​by the calibrated single-level resolution.

2. The method for improving the resolution and linearity of a timing generator according to claim 1, characterized in that, The steps for generating a delayed signal based on a three-level time interpolation architecture using a timing generator channel configured inside the FPGA include: A coarse delay generator is used to generate coarse delays that are integer multiples of the master clock cycle, thereby expanding the dynamic range of timing generation. The master clock period is evenly divided using a multiphase clock generator to generate the first-level sub-period time interpolation signal. The first-stage sub-cycle time interpolation signal is used to perform second-stage time interpolation using a coarse delay line constructed based on a carry chain structure, and its single-stage delay step covers the single-stage resolution of the multi-phase clock generator. The signal of the second-stage time interpolation is used to perform a third-stage time interpolation by using a fine delay line constructed based on a carry chain structure and a multiplexer combination, and its single-stage delay step covers the single-stage resolution of the coarse delay line.

3. The method for improving the resolution and linearity of a timing generator according to claim 2, characterized in that, In the second-stage time interpolation step using a coarse delay line constructed based on a carry chain structure, different signal transmission paths are selected by configuring a multiplexer inside the carry chain structure, so that the input signal is output directly or after passing through a specified delay unit sequence, in order to obtain a coarse delay signal with high delay consistency.

4. The method for improving the resolution and linearity of a timing generator according to claim 2, characterized in that, In the third-stage time interpolation step using a fine delay line constructed based on a carry chain structure and a multiplexer, multiple intermediate signals with fixed small delay differences are drawn from different delay stages of the carry chain structure, and the multiple intermediate signals are input to a multiplexer constructed by FPGA lookup table mapping. High-resolution fine delay signals are achieved by gating the output, and configurable delay values ​​of multiple orders of magnitude are generated by cascading fine delay lines.

5. The method for improving the resolution and linearity of a timing generator according to claim 1, characterized in that, The steps for selecting the target delay value by running a preset selection algorithm on the host computer include: Select an initial value from the measured actual delay values ​​as the starting point for constructing the ideal delay sequence; Using the starting point as a reference and the preset target resolution as a step value, calculate the ideal delay value sequence corresponding to the target delay line length; Traverse the ideal delay value sequence, select the actual delay value with the smallest deviation from each ideal delay value from all measured actual delay values, combine them into a candidate delay value set, and record the delay code sequence corresponding to the set; Calculate the integral nonlinearity error range for each set of candidate delay values; Iterate through all the measured actual delay values ​​that can be used as the starting point of the sequence, repeat the above calculation steps, compare and output the delay code sequence corresponding to the minimum integral nonlinear error range as the target delay code.

6. A timing generator system based on FPGA, characterized in that, For implementing the method for improving the resolution and linearity of a timing generator as described in any one of claims 1 to 5, the system includes an FPGA and a host computer; The FPGA is internally configured with a timing generator channel, a timing measurement channel, and a communication interface. The timing generator channel includes a coarse delay generator, a multiphase clock generator, a coarse delay line constructed based on the FPGA carry chain structure, a fine delay line constructed based on the FPGA carry chain structure and a multiplexer combination, and a delay code storage unit, used to generate high-resolution timing signals with a large dynamic range according to the delay code table. The timing measurement channel is used to perform physical delay measurement on the timing signals generated by the timing generator channel to obtain the actual delay data corresponding to the full delay code. The host computer establishes a data connection with the FPGA through the communication interface to receive the actual delay data, execute a preset selection and optimization algorithm to extract the optimized delay code with the minimum integral nonlinearity error, and write the optimized delay code into the delay code storage unit through the communication interface to complete the system linearity correction.

7. The timing generator system according to claim 6, characterized in that, The timing generator channel also includes a D flip-flop. The output of the coarse delay generator is connected to the enable terminal of the D flip-flop, and the output of the fine delay line is connected to the clock terminal of the D flip-flop. The D flip-flop is used to sample the enable signal output by the coarse delay generator at the trigger edge of the fine delay line output signal, and output the final target timing edge signal.

8. The timing generator system according to claim 6, characterized in that, The time measurement channel specifically includes at least one cascaded IDELAY3 input / output delay primitive unit, which provides a multi-level tapped delay line array to achieve picosecond-level high-precision edge sampling of the timing signal under test.

9. The timing generator system according to claim 6, characterized in that, The communication interface is a high-speed PCIe interface based on the TCP / IP protocol, which is used to ensure low-latency transmission of measurement data and control commands between the FPGA and the host computer.

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