A high-precision ADC linearity test method and system

Abstract

The application discloses a high-precision ADC linearity test method and system, comprising the following steps: inputting a plurality of signal differences to an ADC through a control signal generator, a voltage source, an operator and a channel of a multiplexer, and obtaining a group of output code bits of each signal difference; summing and subtracting two preset signal differences, and summing and subtracting the output code bits of the two preset signal differences, to obtain summing and subtracting results; determining a multivariate linear equation group according to a preset segmented nonlinear model containing a parameter to be solved, the summing and subtracting results and the output code bits; obtaining an optimal solution by solving the equation group, and determining integral nonlinear errors and differential nonlinear errors of the ADC according to the optimal solution and the preset segmented nonlinear model. The application can calculate common-mode and differential-mode of integral nonlinearity and differential nonlinearity, can reduce the precision requirement of an input signal, can greatly shorten test time and sampling points, and has simple system structure, fast algorithm running speed and wide application prospect.

Description

Technical Field

[0001] This invention belongs to the field of high-speed and high-precision analog-to-digital conversion technology, specifically relating to a high-precision ADC linearity testing method and system. Background Technology

[0002] Integral nonlinearity error refers to the error value at the point where the error between the analog value and the true value is largest across all numerical points of an analog-to-digital converter (ADC), representing the absolute error of the measurement. Differential nonlinearity error, on the other hand, refers to the maximum difference between two adjacent scale points of the ADC, also called differential nonlinearity error. It reflects the local microscopic nonlinearity across the entire measurement range. Both are important static parameters of the ADC, jointly reflecting its linearity. A common testing method for both is the code density method, which involves feeding a sinusoidal or ramp signal with 3-4 bits higher precision than the ADC under test into the ADC. After the ADC acquires a large number of data points, the step width of the ADC output curve is estimated based on the density distribution of the output code bits and compared with the ideal width.

[0003] However, the traditional methods for measuring differential (differential) and integral nonlinear errors require an exponential increase in the number of sampling points required as the ADC bit depth increases. This leads to excessively long testing times for high-precision ADCs. Furthermore, high-precision ADC nonlinear testing places extremely high demands on the accuracy of the signal generator, requiring it to be 3-4 bits higher than the ADC under test. In 2018, Chen Tao proposed the USER-SMILE scheme to measure nonlinearity. This scheme first uses a nonparametric piecewise model to analyze the ADC's nonlinearity, then uses an adder to apply a high-precision bias voltage to the DAC (Digital Converter) as the excitation source. By measuring the ADC output before and after bias, the difference in integral nonlinearity error at each code point related to the bias voltage is obtained, thus determining the ADC's integral and differential nonlinear errors. However, the USER-SMILE scheme also requires the signal generator to have at least the same accuracy as the ADC under test. Additionally, the USER-SMILE method cannot measure the common-mode component of the nonlinear error. Summary of the Invention

[0004] To address the aforementioned problems in related technologies, this invention provides a high-precision ADC linearity testing method and system. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a high-precision ADC linearity testing method applied to a testing system. The system includes two multiplexers, an arithmetic logic unit (ALU) connected to the two multiplexers for signal processing, a signal generator for outputting an adjustable signal, a voltage source for outputting a bias voltage signal, and an ADC connected to the outputs of the two multiplexers. Each multiplexer includes four input signals: the sum of the adjustable signal and the bias voltage signal, the bias voltage signal, the adjustable signal, and a ground signal. The method includes:

[0006] By controlling the channels of the signal generator, the voltage source, the arithmetic unit, and the two multiplexers, multiple signal differences are input to the ADC respectively, and a set of output code bits for each signal difference is obtained;

[0007] The summation and difference are calculated for two preset signal differences among the plurality of signal differences, and the summation and difference are calculated for the output code points corresponding to the two preset signal differences to obtain the summation and difference results;

[0008] A system of multivariate linear equations is determined based on a pre-defined piecewise nonlinear model containing the parameters to be solved, the summation and difference results, and the output code points.

[0009] The optimal solution for the parameters to be solved is obtained by solving the system of multivariate linear equations. Based on the optimal solution and the preset piecewise nonlinear model, the integral nonlinear error and differential nonlinear error of the ADC are determined.

[0010] The present invention also provides a high-precision ADC linearity testing system, the system comprising:

[0011] The system comprises two multiplexers, an arithmetic logic unit (ALU) connected to the two multiplexers for signal processing, a signal generator for outputting an adjustable signal, a voltage source for outputting a bias voltage signal, and an ADC connected to the outputs of the two multiplexers. Each multiplexer includes four input signals. When the ALU is an adder, the ADC is a differential ADC with two inputs. The two inputs of the adder are connected to the outputs of the signal generator and the voltage source, respectively. The output of the adder is connected to the first input of each multiplexer. The output of the voltage source is also connected to the second input of each multiplexer. The output of the signal generator is also connected to the third input of each multiplexer. The fourth input of each multiplexer is connected to ground. Furthermore, the output of one multiplexer is connected to one input of the differential ADC, and the output of the other multiplexer is connected to the other input of the differential ADC.

[0012] The present invention has the following beneficial technical effects:

[0013] The testing method provided by this invention significantly reduces the number of sampling points required for measuring differential and integral nonlinear errors, greatly shortening the measurement time and reducing the accuracy requirements of the input signal. Furthermore, this invention can simultaneously calculate the differential and common-mode components of the nonlinearity, thereby improving the accuracy of the test. It achieves low-cost, high-efficiency, and high-precision ADC linearity testing.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] Figure 1 An exemplary output curve of a 3-bit ADC provided for an embodiment of the present invention;

[0016] Figure 2 A nonlinear error diagram of an exemplary successive approximation ADC provided for embodiments of the present invention;

[0017] Figure 3 A schematic diagram of an exemplary high-precision ADC linearity testing system provided in an embodiment of the present invention;

[0018] Figure 4 This is a flowchart of a high-precision ADC linearity testing method provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0022] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0023] Figure 1 The image shows the output curve of a 3-bit ADC, with the horizontal axis representing the input voltage and the vertical axis representing the output code bits of the ADC. For an ideal single-ended input ADC, its mathematical model can be expressed as Equation 1: Input = Output code bits * Least Significant Bit Voltage + 1 / 2 Least Significant Bit Voltage + Noise; where input represents the voltage value input to the ADC, Least Significant Bit Voltage represents the analog voltage value corresponding to the least significant bit of the output code bits, and noise includes quantization noise and thermal noise, with amplitudes between -1 / 2 * Least Significant Bit Voltage and 1 / 2 * Least Significant Bit Voltage; where this equation corresponds to... Figure 1 The blue dashed line represents the error. Due to non-ideal effects, the output curve of an ADC will exhibit non-linear deviation. Integral non-linearity error refers to the error value at the point where the analog value and the true value are largest across all numerical points, representing the absolute error of the measurement. Differential non-linearity error refers to the maximum difference between two adjacent scale points of the ADC. The conversion voltage is the midpoint voltage when two adjacent code points switch. During measurement, DNL(C) can be denoted as the differential non-linearity error of each code point in the output code point C, equal to the difference between the left and right conversion voltages corresponding to the output code point C in the actual output curve minus the voltage difference in the ideal curve. After measurement, the maximum absolute value of the function DNL(C) is taken as the ADC differential non-linearity error. Similarly, INL(C) can be denoted as the integral non-linearity error of each code point, equal to the difference between the conversion voltage of the actual output curve and the corresponding conversion voltage of the ideal curve, while the ADC integral non-linearity error is taken as the maximum absolute value of the function INL(C). At this point, the mathematical model of the ADC can be expressed as Equation 2: Input = Output code bit * Least Significant Bit Voltage + INL (Output code bit) + 1 / 2 Least Significant Bit Voltage + Noise; This equation corresponds to Figure 1 The solid red line in the middle.

[0024] For example, Figure 2 The figures shown are typical DNL(C) and INL(C) curves for a successive approximation ADC. Figure 2As shown, the curve mainly changes with the change of the high-order bits of the output code position C. Simultaneously, with the change of the low-order bits of the output code position C, the nonlinear curve will change within a small range around the change caused by the high-order bits. Therefore, the pre-defined piecewise nonlinear model proposed in this invention divides the INL(C) curve into three parts: a discrete function of the integral nonlinear error of each code position of the output code position C with respect to the median code position of C, a discrete function of the high-order bits, and a high-power function with respect to the low-order bits. The sum of these three is the original INL(C) curve. For example, when the output code position C is 12 bits, the first four bits are the high-order bits of the output code position C, the middle four bits are the median code position of the output code position C, and the last four bits are the low-order bits of the output code position C. The pre-defined piecewise nonlinear model expresses INL(C) as Equation 3: Here, the high-order bit error is a function derived solely from the mapping of the high-order bits of the output code bits, and the median bit error is a function derived solely from the mapping of the median bits of the output code bits. This model reduces the 2^N unknowns of the INL function to 2^N of the high-order bit error. H One unknown, 2% of the median error I There are 2 unknowns, and K unknown coefficients for the low-order error, totaling 2 H +2 I +K unknowns, where H represents the number of high-order bits in the output code and I represents the number of median bits in the output code. For example, K is 2.

[0025] Here, the unknowns of the model in Equation 3 can be summarized as an error vector, namely: Error Vector = [High-order error (0), High-order error (1), ..., Median error (0), Median error (1), ..., 1st-order coefficient, 2nd-order coefficient]. When C is 12 bits, and these 12 code bits are divided into 4-4-4 segments (the first 4 is the high-order bit, the second 4 is the median bit, and the third 4 is the low-order bit), and K is 2, this error vector is a 34-dimensional vector. That is, the model in Equation 3 uses these 34 unknowns to represent all 4096 INL(C). According to the above, the model in Equation 3 can be expressed as: INL(C) = Coefficient (C) · [Error Vector] T Where T is the transpose symbol, and coefficients (C) are the coefficient vectors of each code point, and coefficients (C) are also 34-dimensional vectors. By definition, we have: After completing the statistical calculation of the error vector, INL(C) can be reconstructed based on the coefficients (C).

[0026] This application provides a high-precision ADC linearity testing method. The method is applied to a testing system, which includes two multiplexers (multi-bit selectors), an arithmetic unit connected to the two multiplexers for signal processing, a signal generator (e.g., a digital-to-analog converter DAC) for outputting an adjustable signal, a voltage source for outputting a bias voltage signal, and an ADC connected to the outputs of the two multiplexers. Each multiplexer includes four input signals: a sum of the adjustable signal and the bias voltage signal, the bias voltage signal, the adjustable signal, and a ground signal.

[0027] In some embodiments, the arithmetic unit can be a subtractor based on an operational amplifier, and the ADC can be a single-input ADC, wherein the input of the subtractor is connected to the output of each multiplexer, and the output is connected to the input of the ADC, for performing addition and subtraction combinations of corresponding signals, and inputting the added and subtracted signals into the ADC.

[0028] In some embodiments, the arithmetic unit may be an adder, and the ADC may be a dual-input differential ADC. For example, the structure of the test system may be as follows: Figure 3 As shown. In Figure 3 In this configuration, the two inputs of the adder are connected to the outputs of the signal generator and the voltage source, respectively. The output of the adder is connected to the first input of each multiplexer, the output of the voltage source is connected to the second input of each multiplexer, the output of the signal generator is connected to the third input of each multiplexer, and the fourth input of each multiplexer is connected to ground. Furthermore, the output of one multiplexer is connected to one input of a differential ADC, and the output of another multiplexer is connected to the other input of the differential ADC. The following will use... Figure 3 The method of the present invention will be described using the test system shown as an example.

[0029] Figure 4 This is a flowchart of a high-precision ADC linearity testing method provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the method includes the following steps:

[0030] S101. By controlling the channels of the signal generator, voltage source, arithmetic unit and two multiplexers, multiple signal differences are input to the ADC respectively, and a set of output code bits for each signal difference is obtained.

[0031] In this embodiment of the invention, the sum of the adjustable signal and the bias voltage signal, the bias voltage signal, the adjustable signal, and the ground signal are numbered sequentially as 1, 2, 3, and 4. Here, number 1 represents the sum of the adjustable signal and the bias voltage signal (abbreviated as sum signal), number 2 represents the bias voltage signal, number 3 represents the adjustable signal, and number 4 represents the ground signal.

[0032] For example, the multiple signal differences can be the following 6 signal differences: the first signal difference between inputs 3 and 4, denoted as (3,4); the second signal difference between inputs 3 and 2, denoted as (3,2); the third signal difference between inputs 1 and 4, denoted as (1,4); the fourth signal difference between inputs 2 and 3, denoted as (2,3); the fifth signal difference between 4 and 3, denoted as (4,3); and the sixth signal difference between inputs 4 and 1, denoted as (4,1).

[0033] Here, when the above 6 signal differences are input into the ADC respectively, the ADC outputs 6 sets of output code bits that correspond one-to-one, and the number of bits in these 6 sets of output code bits is the same.

[0034] S102. Summing and subtracting two preset signal differences from multiple signal differences, and simultaneously summing and subtracting the output code points corresponding to the two preset signal differences to obtain the summation and subtraction results.

[0035] Here, each signal difference in the input ADC satisfies a preset relationship equation with its corresponding set of output code bits. For example, for the input signal difference (3,4), the preset relationship equation between this signal difference (3,4) and its corresponding set of output code bits C1 can be expressed by Equation 4: (3,4) = (output code bit C1 - zero code bit) * Least Significant Bit Voltage + INL(output code bit C1) + 1 / 2 Least Significant Bit Voltage + Noise 1. That is, Equation 4 is the preset relationship equation corresponding to the signal difference (3,4). Similarly, for the signal difference (3,2), the preset relationship equation between this signal difference (3,2) and its corresponding output code bit C2 can be expressed by Equation 5: (3,2) = (output code bit C2 - zero code bit) * Least Significant Bit Voltage + INL(output code bit C2) + 1 / 2 Least Significant Bit Voltage + Noise 2. That is, Equation 5 is the preset relationship equation corresponding to the signal difference (3,2). The preset relationship equations between other signal differences and their corresponding output code bits are similar and will not be listed here.

[0036] For example, when there are multiple signal differences as described above (6 signal differences), the preset relational equation corresponding to signal difference (3,4) can be subtracted from the preset relational equation corresponding to signal difference (3,2); the preset relational equation corresponding to signal difference (1,4) can be subtracted from the preset relational equation corresponding to signal difference (3,4); the preset relational equation corresponding to signal difference (2,3) can be subtracted from the preset relational equation corresponding to signal difference (4,3); the preset relational equation corresponding to signal difference (4,3) can be subtracted from the preset relational equation corresponding to signal difference (4,1); and the preset relational equation corresponding to signal difference (3,4) can be subtracted from the preset relational equation corresponding to signal difference (3,2). Suppose we sum the relational equation with the preset relational equation corresponding to the signal difference (2,3), sum the preset relational equation corresponding to the signal difference (3,4) with the preset relational equation corresponding to the signal difference (4,1), sum the preset relational equation corresponding to the signal difference (4,3) with the preset relational equation corresponding to the signal difference (3,2), and sum the preset relational equation corresponding to the signal difference (4,3) with the preset relational equation corresponding to the signal difference (1,4). In this way, we get 8 intermediate relational equations. The left side of the equal sign of these 8 intermediate relational equations is the bias voltage signal (i.e., the bias voltage value).

[0037] For example, subtracting the preset relational equation corresponding to signal difference (3,4) from the preset relational equation corresponding to signal difference (3,2) yields an intermediate relational equation, such as Equation Six: Bias Voltage - (Output Code Point C1 - Output Code Point C2) * Least Significant Bit Voltage + Noise = INL(Output Code Point C1) - INL(Output Code Point C2). Since noise cannot be canceled by addition and subtraction, the result of subtracting noise 2 from noise 1 is used to summarize the noise. As another example, summing the preset relational equation corresponding to signal difference (3,4) from the preset relational equation corresponding to signal difference (2,3) yields an intermediate relational equation, such as Equation Seven: -Bias Voltage - (Output Code Point C1 + Output Code Point C3 - 2 * Zero Code Point) * Least Significant Bit Voltage + Noise = INL(Output Code Point C1) + INL(Output Code Point C3). Since noise cannot be canceled by addition and subtraction, the result of subtracting noise from the two equations is used to summarize the noise.

[0038] S103. Based on the preset piecewise nonlinear model containing the parameters to be solved and the summation and difference results, determine the multivariate linear equation system.

[0039] Here, the preset piecewise nonlinear model containing the parameters to be solved (Equation 1 above) and the output code points can be substituted into each corresponding intermediate relation equation to obtain a multivariate linear equation containing the parameters to be solved. The parameters to be solved in this multivariate linear equation are the same as the parameters to be solved in the preset piecewise nonlinear model. All the obtained multivariate linear equations are combined into a multivariate linear equation system.

[0040] For example, for signal differences (3,4) and (3,2), a common intermediate relationship equation is Equation 6 above: Bias voltage - (output code point C1 - output code point C2) * least significant bit voltage + noise = INL(output code point C1) - INL(output code point C2); and the integral nonlinearity error of the output code point C1 of signal difference (3,4) can be expressed as Equation 8 using a preset piecewise nonlinear model: The integral nonlinear error of the output code point C2 of the signal difference (3,4) can be expressed as Equation 9 using a preset piecewise nonlinear model: Therefore, substituting equations eight and nine into equation six, we obtain equation ten:

[0041] Ignoring the term "-(output code bit C1-output code bit C2)*least significant bit voltage" on the left side of equation ten, we get equation eleven: Equation eleven is the obtained multivariate linear equation. Using this principle, we can obtain eight multivariate linear equations that correspond one-to-one with the eight intermediate relational equations mentioned above. These eight multivariate linear equations constitute a system of multivariate linear equations.

[0042] S104. Obtain the optimal solution for the parameters to be solved by solving the system of multivariate linear equations. Based on the optimal solution and the preset piecewise nonlinear model, determine the integral nonlinear error and differential nonlinear error of the ADC.

[0043] In some embodiments, the least squares method can be used to solve the system of multivariate linear equations to obtain a set of optimal solutions for the parameters to be solved.

[0044] In some embodiments, heuristic algorithms can be used to solve the system of multivariate linear equations to obtain a set of optimal solutions for the parameters to be solved.

[0045] Here, after obtaining a set of optimal solutions, these optimal solutions can be substituted into a preset piecewise nonlinear model to obtain an optimized preset piecewise nonlinear model. Then, the six sets of output code positions corresponding to the six signal differences mentioned above are substituted into the optimized preset piecewise nonlinear model to calculate the integral nonlinear error corresponding to each set of output code positions, thus obtaining six integral nonlinear errors. The maximum integral nonlinear error among the six obtained integral nonlinear errors is taken as the integral nonlinear error of the ADC. In addition, since the integral nonlinear error corresponding to each set of output code positions is composed of the integral nonlinear errors corresponding to each code position in that set of output code positions, the difference between the integral nonlinear errors between each pair of adjacent code positions in the set of output code positions corresponding to each of the six integral nonlinear errors can be calculated to obtain multiple differences of the integral nonlinear error. The maximum value among all obtained differences is taken as the differential nonlinear error of the ADC.

[0046] The testing method provided by this invention significantly reduces the number of sampling points required for measuring differential and integral nonlinear errors, greatly shortening the measurement time and reducing the accuracy requirements of the input signal. Furthermore, this invention can simultaneously calculate the differential and common-mode components of the nonlinearity, thereby improving the accuracy of the test. It achieves low-cost, high-efficiency, and high-precision ADC linearity testing.

[0047] The following is based on the above. Figure 3 For example, we will use a specific example to illustrate the above method.

[0048] Step 1: Reset the DAC and multiplexers. Adjust the two multiplexers to specific channels. For a differential input ADC, the converted signal is the voltage difference between the positive and negative input terminals. If the positive signal is connected to the negative input terminal while the positive terminal is grounded, the output value is approximately equal to the inverse of the output value when the signal is connected to the positive input terminal while the negative terminal is grounded. Here, the multiplexers connected to the positive and negative terminals of the ADC each have 4 input signals: the sum of the DAC and bias voltage generated by the adder, the bias voltage signal, the adjustable DAC signal, and the ground signal. Adjusting the control bit level of the multiplexers allows inputting the difference between any two of the above four signals. Numbering these four signals 1, 2, 3, and 4 respectively, we can set the actual input signal of the differential input ADC as input (positive, negative), where positive and negative are the signal numbers selected by the two multiplexers.

[0049] Step 2: Control the DAC output to generate a ramp signal from 0 to the reference voltage, and record the ADC output.

[0050] Step 3: Repeat steps 1 and 2 above. Scan the six sets of signals: input (3,4), input (3,2), input (1,4), input (2,3), input (4,3), and input (4,1), and record the corresponding output code positions. The input (positive, negative) = (output code position - zero code position) * least significant bit voltage + INL (output code position) + 1 / 2 least significant bit voltage + noise.

[0051] Step 4: Combine the signals described in Step 3 and sum and subtract them respectively. The results are: input (3,4)-input (3,2), input (1,4)-input (3,4), input (2,3)-input (4,3), input (4,3)-input (4,1), input (3,4)+input (2,3), -input (3,4)-input (4,1) (i.e., input (3,4)+input (4,1)), input (4,3)+input (3,2), -input (4,3)-input (1,4) (i.e., input (4,3)+input (1,4)). All results are bias voltages, where "-" represents a minus sign and "+" represents a plus sign. Taking input (3,4) - input (3,2) as an example, let the two output code points be code point C1 and code point C2 respectively. Substituting them into the equation in step three, the left side of the equation is: Input (3,4) - Input (3,2) = Bias Voltage; the right side of the equation is (Output code point C1 - Output code point C2) * Least Significant Bit Voltage + INL(Output code point C1) - INL(Output code point C2) + Noise 1 - Noise 2. After simplification, it becomes: Bias Voltage - (Output code point C1 - Output code point C2) * Least Significant Bit Voltage + Noise = INL(Output code point C1) - INL(Output code point C2), where: Noise includes Noise 1 and Noise 2. Since noise cannot be canceled out by addition and subtraction, it is only referred to as noise here. Similarly, for the input (3,4) + input (2,3) combination, we have: Bias voltage - (output code bit C1 + output code bit C3 - 2 * zero code bit) * Least significant bit voltage + noise = INL(output code bit C1) + INL(output code bit C3). For the input (3,4) - input (4,1) combination, we have: Bias voltage - (output code bit C1 + output code bit C4 - 2 * zero code bit) * Least significant bit voltage + noise = INL(output code bit C1) + INL(output code bit C4).

[0052] Step 5: Decompose the nonlinearity of each output code bit according to the piecewise nonlinear model to obtain a system of eight multivariate linear equations.

[0053] Step Six: Solve the system of linear equations using the least squares method. At this point, the left side of the equation represents the known bias voltage and noise. Ignoring the noise, it can be denoted as... The right side shows a linear combination of the coefficients of high-order error, median error, and low-order error. Therefore, step six can be denoted as solving: After simplification, the result of the least squares method is approximately equal to the generalized inverse of the coefficient matrix of the parameters to be solved, multiplied by the error vector.

[0054] Step 7: Based on the piecewise nonlinear model, reconstruct the difference nonlinear error and the integral nonlinear error to complete the solution.

[0055] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-precision ADC linearity testing method, characterized in that, The system is applied to a testing system, which includes two multiplexers, an arithmetic unit connected to the two multiplexers for performing signal operations, a signal generator for outputting adjustable signals, a voltage source for outputting bias voltage signals, and an ADC connected to the outputs of the two multiplexers; each multiplexer includes four input signals. The method includes: the sum of the adjustable signal and the bias voltage signal, the bias voltage signal, the adjustable signal, and the ground signal; the method comprises: By controlling the channels of the signal generator, the voltage source, the arithmetic unit, and the two multiplexers, multiple signal differences are input to the ADC respectively, and a set of output code bits for each signal difference is obtained; The summation and difference are calculated for two preset signal differences among the plurality of signal differences, and the summation and difference are calculated for the output code points corresponding to the two preset signal differences to obtain the summation and difference results; A system of multivariate linear equations is determined based on a pre-defined piecewise nonlinear model containing the parameters to be solved, the summation and difference results, and the output code points. The optimal solution for the parameters to be solved is obtained by solving the system of multivariate linear equations. Based on the optimal solution and the preset piecewise nonlinear model, the integral nonlinear error and differential nonlinear error of the ADC are determined. The preset piecewise nonlinear model is used to divide the integral nonlinear error of the output code bit into: the discrete function of the integral nonlinear error with respect to the middle bit of the output code bit, the discrete function of the high bit of the code bit, and the high-order power function of the low bit of the code bit.

2. The high-precision ADC linearity testing method according to claim 1, characterized in that, The step of determining the integral nonlinear error and differential nonlinear error of the ADC based on the optimal solution and the preset piecewise nonlinear model includes: Substituting the optimal solution into the preset piecewise nonlinear model yields an optimized preset piecewise nonlinear model; Substitute each group of output code points corresponding to the multiple signal differences into the optimized preset piecewise nonlinear model to calculate the integral nonlinear error corresponding to each group of output code points. The integral nonlinear error and differential nonlinear error of the ADC are determined based on the obtained integral nonlinear error.

3. The high-precision ADC linearity testing method according to claim 2, characterized in that, The integral nonlinearity error corresponding to each group of output code points is composed of the integral nonlinearity errors corresponding to each code point in that group of output code points; the step of determining the integral nonlinearity error and differential nonlinearity error of the ADC based on the obtained integral nonlinearity error includes: The maximum integral nonlinear error among the obtained integral nonlinear errors is taken as the integral nonlinear error of the ADC. Calculate the difference between the integral nonlinearity errors of each pair of adjacent code bits in a set of output code bits corresponding to each obtained integral nonlinearity error, and obtain multiple differences of the integral nonlinearity error. The maximum value among all the obtained differences is taken as the differential nonlinear error of the ADC.

4. The high-precision ADC linearity testing method according to claim 1, characterized in that, Each signal difference satisfies a preset relationship equation with its corresponding set of output code points; the process of summing and subtracting two preset signal differences from the plurality of signal differences, and simultaneously summing and subtracting the output code points corresponding to the two preset signal differences, to obtain the summation and subtraction results includes: Among the multiple preset relational equations that correspond one-to-one with the multiple signal differences, the summation and difference of the two preset relational equations corresponding to the two preset signal differences are used to obtain the corresponding intermediate relational equations; the intermediate relational equations are used to characterize the relationship between the bias voltage signal and the integral nonlinear error of the output code.

5. The high-precision ADC linearity testing method according to claim 4, characterized in that, The process involves determining a system of multivariate linear equations based on a pre-defined piecewise nonlinear model containing the parameters to be solved, the summation and difference results, and the output code points. Substituting the preset piecewise nonlinear model containing the parameters to be solved, and the output code points into each corresponding intermediate relation equation, yields a multivariate linear equation containing the parameters to be solved. All the obtained multivariate linear equations are combined into a system of multivariate linear equations.

6. The high-precision ADC linearity testing method according to claim 1, characterized in that, The process of obtaining the optimal solution for the parameters to be solved by solving the system of multivariate linear equations includes: The optimal solution for the parameters to be solved is obtained by solving the system of multivariate linear equations using the least squares method.

7. The high-precision ADC linearity testing method according to claim 4, characterized in that, The plurality of signal differences include: a first signal difference between the adjustable signal and the ground signal, a second signal difference between the adjustable signal and the bias voltage signal, a third signal difference between the sum signal and the ground signal, a fourth signal difference between the bias voltage signal and the adjustable signal, a fifth signal difference between the ground signal and the adjustable signal, and a sixth signal difference between the ground signal and the sum signal; The two preset signal differences include: the first signal difference and the second signal difference, the third signal difference and the first signal difference, the fourth signal difference and the fifth signal difference, the fifth signal difference and the sixth signal difference, the first signal difference and the fourth signal difference, the first signal difference and the sixth signal difference, the fifth signal difference and the second signal difference, and the fifth signal difference and the third signal difference.

8. The high-precision ADC linearity testing method according to claim 7, characterized in that, The step of summing and subtracting the two preset relational equations corresponding to two preset signal differences in the plurality of preset relational equations corresponding to the plurality of signal differences to obtain the corresponding intermediate relational equations includes: The difference between the preset relational equation corresponding to the first signal difference and the preset relational equation corresponding to the second signal difference is used to obtain an intermediate relational equation. The difference between the preset relational equation corresponding to the third signal difference and the preset relational equation corresponding to the first signal difference is used to obtain an intermediate relational equation. Subtract the preset relational equation corresponding to the fourth signal difference from the preset relational equation corresponding to the fifth signal difference to obtain an intermediate relational equation. Subtract the preset relational equation corresponding to the fifth signal difference from the preset relational equation corresponding to the sixth signal difference to obtain an intermediate relational equation. Summing the preset relational equation corresponding to the first signal difference with the preset relational equation corresponding to the fourth signal difference yields an intermediate relational equation. Summing the preset relational equation corresponding to the first signal difference with the preset relational equation corresponding to the sixth signal difference yields an intermediate relational equation. Summing the preset relational equation corresponding to the fifth signal difference with the preset relational equation corresponding to the second signal difference yields an intermediate relational equation. Summing the preset relational equation corresponding to the fifth signal difference with the preset relational equation corresponding to the third signal difference yields an intermediate relational equation.

9. A high-precision ADC linearity testing system, characterized in that, The system is used to implement the steps of the method according to any one of claims 1-8, wherein the system comprises: The system comprises two multiplexers, an arithmetic logic unit (ALU) connected to the two multiplexers for signal processing, a signal generator for outputting an adjustable signal, a voltage source for outputting a bias voltage signal, and an ADC connected to the outputs of the two multiplexers. Each multiplexer includes four input signals. When the ALU is an adder, the ADC is a differential ADC with two inputs. The two inputs of the adder are connected to the outputs of the signal generator and the voltage source, respectively. The output of the adder is connected to the first input of each multiplexer. The output of the voltage source is also connected to the second input of each multiplexer. The output of the signal generator is also connected to the third input of each multiplexer. The fourth input of each multiplexer is connected to ground. Furthermore, the output of one multiplexer is connected to one input of the differential ADC, and the output of the other multiplexer is connected to the other input of the differential ADC.

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