A dv / dt tolerance test circuit and method for power devices

Abstract

The application relates to a dv / dt tolerance test circuit and method for a power device, which comprises a gate large-current driving circuit and a main circuit; the main circuit comprises MOS3, a device to be tested, a driving pulse generator V GS , a capacitor C2, resistors R G and R4, and a high-voltage direct-current voltage source V2; the gate large-current driving circuit is connected with the gate of MOS3, is used for controlling the fast turn-on and turn-off of MOS3, clamping the gate voltage of MOS3 at a safe value, and adjusting the size of dv / dt of the main circuit; at the moment of the turn-on of MOS3, one end of the capacitor C2 is forced to be grounded, so that the voltage across the capacitor C2 is rapidly applied to the device to be tested, and then a large dv / dt pulse voltage is generated. The application has higher reliability, the size of the dv / dt pulse voltage can be adjusted, the observation mode of indirect measurement has low precision requirement on the test equipment, the cost of the test equipment can be greatly reduced, and the realizability is high.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a circuit and method for testing the dv / dt withstand capability of power devices. Background Technology

[0002] Power semiconductor devices are core components of power electronic devices, and ensuring their high reliability, high performance, and low energy consumption is crucial. Silicon carbide MOSFETs have seen rapid development in the past decade due to their superior performance and are widely used in the new energy industry. Because of their high switching speed—with switching times on the order of tens of nanoseconds—Silicon carbide MOSFETs exhibit very high drain voltage change rate (dv / dt) and drain current change rate (di / dt) during switching. The high dv / dt experienced by the switch and the machine can reduce the winding insulation capacity or cause degradation of the device's edge terminals within a certain period. Simultaneously, high dv / dt can cause mis-conduction in power devices in the circuit, leading to a short circuit to ground in the input power supply, generating a large breakdown current, and ultimately damaging the device.

[0003] The dv / dt withstand capability test circuit for power devices needs to generate very high dv / dt values ​​and test the device under test's high dv / dt surge withstand capability. A modular Marx generator for dv / dt testing of power semiconductor devices is available, with the test circuit structure as follows: Figure 1 As shown, this test circuit achieves adjustable dv / dt values ​​through multiple modular power MOSFETs. Utilizing the unidirectional conductivity of diodes, the switching states of multiple capacitors connected in series and parallel are controlled by adjusting the switching states of the MOSFETs. This causes the voltages across the capacitors to stack, generating high voltage transients and a customizable high dv / dt value. Figure 2 As shown, a novel circuit structure is disclosed that utilizes the secondary breakdown of avalanche BJTs to generate extremely high dv / dt for evaluating the impact of high dv / dt on silicon carbide MOSFETs. Voltage pulse energy is stored in a top capacitor, and four silicon avalanche transistor (BJT) totem-pole configurations are stacked. By controlling the conduction of the top avalanche BJT, the three lower avalanche BJTs undergo secondary breakdown, generating the desired high dv / dt. Two Schottky diodes in the output circuit form an "OR" circuit structure, allowing the drain-source bias voltage to be rapidly applied to the device under test. Figure 3 As shown, a test circuit for inducing a high dv / dt on a device under test is disclosed. This test circuit forces one end of capacitor C2 to ground, causing the voltage across the capacitor to be rapidly applied to the device under test, resulting in a large dv / dt voltage pulse. The obtained dv / dt is limited only by the parasitic parameters of the main circuit and is largely determined by the voltage across capacitor C2 and the turn-on speed of the MOSFET (Q1).

[0004] for Figure 1 The technical solution, under the requirement of a constant bus voltage, has a maximum dv / dt value that is limited by the MOSFET's turn-on speed, resulting in a relatively small dv / dt value. Figure 2 and Figure 3 The technical solution uses avalanche BJT, which has poor adjustability of dv / dt value. Moreover, in order to evaluate the dv / dt tolerance of the device under test, the above technical solutions require the use of ultra-high precision oscilloscopes and voltage probes, which places very high demands on the accuracy of the test equipment and is very expensive.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a circuit and method for testing the dv / dt withstand capability of power devices, thus solving the problems existing in the prior art.

[0007] The objective of this invention is achieved through the following technical solution: a dv / dt withstand capability test circuit for power devices, comprising a gate high-current drive circuit and a main circuit; the main circuit includes a switching transistor MOS3, a device under test (DUT), and a drive pulse generator V. GS Capacitor C2, Resistor R G And R4, and a high-voltage DC voltage source V2; the positive terminal of the high-voltage DC voltage source V2 is connected to the drain of the switching transistor MOS3 through resistor R4, and the negative terminal is grounded; the drive pulse generator V GS One end is connected to resistor R G One end is connected to the gate of the device under test (DUT), and the other end is connected to the source of the DUT. The drain of the DUT and the source of the switching transistor MOS3 are both grounded, and the source is connected to the drain of the switching transistor MOS3 through capacitor C2.

[0008] The high-current gate drive circuit is connected to the gate of the switching transistor MOS3. It is used to charge and discharge the parasitic capacitance inside the switching transistor MOS3, enabling the switching transistor MOS3 to turn on and off quickly, and to discharge instantaneous overcurrent to prevent the gate voltage of the switching transistor MOS3 from being broken down by a large gate voltage. It also clamps the gate voltage of the switching transistor MOS3 to a safe value and adjusts the turn-on speed of the switching transistor MOS3, thereby adjusting the dv / dt of the main circuit. At the instant that the switching transistor MOS3 turns on, the end of capacitor C2 connected to MOS3 is forcibly grounded, so that the voltage across capacitor C2 is quickly applied to the drain and source terminals of the device under test (DUT), thereby generating a large dv / dt pulse voltage to test the dv / dt withstand capability of the DUT.

[0009] It also includes a leakage current detection and discharge branch, which includes a drive pulse generator V. GS4 MOSFET4 (switching transistor), R (resistor) G4 and R5;

[0010] Drive pulse generator V GS4 One end is grounded, and the other end is connected to a resistor R. G4 The gate of the switching transistor MOS4 is connected to the gate of the switching transistor MOS4. The drain of the switching transistor MOS4 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the drain of the switching transistor MOS3. The source of the switching transistor MOS4 is grounded. The capacitor C2 flows through the leakage current detection discharge branch of the device under test (DUT) to form a loop. When the switching transistor MOS3 is turned off and the switching transistor MOS4 is turned on, the capacitor C2 discharges at a low rate through the loop containing the resistor R5, the switching transistor MOS4, and the device under test (DUT). Then, by connecting an oscilloscope or sampling circuit across the drain and source terminals of the device under test (DUT) to detect the change in the drain and source voltage of the DUT, and comparing the voltage change across the device under test (DUT) at the same time, the leakage current change of the device under test after a large dv / dt impact can be indirectly reflected. This allows the determination of whether the applied high dv / dt impact pulse stress has caused the device under test (DUT) to age, and thus the determination of the dv / dt tolerance of the device under test.

[0011] The leakage current detection discharge branch eliminates the need for real-time testing of the dv / dt withstand capability of the device under test (DUT) during the high dv / dt impact phase. This separates the detection phase from the high dv / dt impact phase. During the detection phase, the detection circuit current is small, the discharge rate is low, and the discharge current is primarily determined by the DUT's leakage current. Resistor R5 limits the discharge current of C2 when a short-circuit fault occurs in the DUT, protecting other components in the circuit from burnout. Simultaneously, it increases the detection circuit loss during the detection phase, facilitating control over the discharge time required for C2. During aging tests, the non-destructive aging of the DUT can also be determined by the magnitude of the drain-source voltage drop over the same period.

[0012] The gate high-current drive circuit includes a high-voltage DC voltage source V1 and a drive pulse generator V1. GS1 Resistors R1, R2, R3, R G1 and R G3 MOSFET1;

[0013] The positive terminal of the high-voltage DC power source V1 is connected to the drain of the switching transistor MOS1 through resistor R1, and the negative terminal is grounded. One end of resistor R2 and capacitor C1 are both connected to the drain of the switching transistor MOS1, and the other end is grounded. One end of resistor R3 is connected to the gate of the switching transistor MOS3, and the other end is grounded. The source of the switching transistor MOS1 is connected to resistor R... G3 Connect the gate of the switching transistor MOS3 to drive the pulse generator V. GS1 One end is connected to resistor R G1 One end is connected to the gate of switching transistor MOS1, and the other end is connected to the source of switching transistor MOS1. Capacitor C1 stores energy and quickly charges the parasitic capacitance inside switching transistor MOS3 at the moment switching transistor MOS1 is turned on, enabling switching transistor MOS3 to turn on quickly. Resistor R... G3 Used to adjust the turn-on speed of MOS3, thereby adjusting the dv / dt of the main circuit. MOS1 ensures the reliable turn-on and turn-off of MOS3.

[0014] The gate high-current drive circuit also includes a drive pulse generator V. GS2 Resistance R G2 With the switching transistor MOS2;

[0015] The drive pulse generator V GS2 One end is connected to resistor R G2 The gate of the switch MOS2 is connected to the other end, and the drain of the switch MOS2 is connected to the source of the switch MOS1. The source of the switch MOS2 is grounded. Resistor R3 and switch MOS2 provide a discharge path for the parasitic input capacitance inside MOS3 when switch MOS1 is turned off. The single-phase half-bridge structure of the switch MOS1 and MOS2 ensures the reliable turn-on and turn-off of switch MOS3.

[0016] The gate high current drive circuit also includes a voltage clamping component, which is connected between the gate and source of the switching transistor MOS3. When the gate voltage of the switching transistor MOS3 is low, the voltage clamping component is in the off state. When the gate voltage of the switching transistor MOS3 reaches the reverse breakdown voltage of the voltage clamping component, the voltage clamping component quickly changes from a high resistance state to a low resistance conduction state to discharge the instantaneous overcurrent and clamp the gate voltage of the switching transistor MOS3 at a safe value.

[0017] A method for testing the dv / dt withstand capability of power devices, the method comprising a preparation stage, a high dv / dt impact stage, and a detection stage;

[0018] The high dv / dt impact phase includes:

[0019] After the parasitic capacitance inside the device under test (DUT) is fully discharged during the preparation phase, the switching transistor MOS1 is turned on and the switching transistor MOS2 is turned off. This causes a sudden voltage change across capacitor C1, which is in a discharge state. A large induced current is generated to charge the parasitic capacitance inside the switching transistor MOS3, causing the switching transistor MOS3 to quickly turn on due to the gate voltage rapidly increasing and exceeding the threshold voltage.

[0020] When MOS4 is turned off, and the gate voltage of MOS3 reaches the reverse breakdown voltage or operating voltage of the voltage clamping component, the voltage clamping component rapidly changes from a high resistance state to a low resistance state and turns on, discharging the instantaneous overcurrent and clamping the gate voltage of MOS3 at a safe value to prevent MOS3 from being broken down. When MOS3 turns on, it forces the end of capacitor C2 connected to MOS3 to ground, so that the voltage across capacitor C2 is rapidly applied to the two ends of the device under test (DUT), thereby generating a large dv / dt pulse voltage stress to test the dv / dt withstand capability of the DUT.

[0021] The preparation phase includes:

[0022] When MOS1 is turned off and MOS2 is turned on, the gate of MOS3 is grounded and turned off. The parasitic capacitance inside MOS3 discharges, and capacitor C1 is charged. At the same time, MOS4 is turned off. One end of capacitor C2 is connected to the positive terminal of the high voltage DC voltage source V2 through R4, and the other end is grounded through the parasitic body diode of the DUT. The voltage of the high voltage DC voltage source V2 is directly applied to the two ends of capacitor C2 through R4, and capacitor C2 is charged. The parasitic drain-source capacitance of the device under test discharges.

[0023] The detection phase includes:

[0024] The control switch MOS1 is turned off, MOS2 is turned on, and the gate of MOS3 is grounded and in the off state. The control switch MOS4 is turned on. Capacitor C2 is applied to the two ends of the device under test (DUT) through resistor R5 and MOS4. The leakage current of the DUT slowly discharges, and the voltage change across the DUT is detected by an oscilloscope or sampling circuit. By comparing the voltage change across the DUT at the same time, it is determined whether the applied high dv / dt impact stress has caused the DUT to age.

[0025] This invention has the following advantages: a dv / dt withstand capability test circuit and method for power devices, which has higher reliability, adjustable dv / dt pulse voltage magnitude, and the indirect measurement observation method can not only detect the maximum dv / dt withstand capability of the device under test, but also detect the non-destructive aging of the device under test under high dv / dt impact. It does not require high precision of the test equipment, can significantly reduce the cost of test equipment, and is highly feasible. Attached Figure Description

[0026] Figure 1 This is a circuit diagram of prior art 1;

[0027] Figure 2 This is a circuit diagram of prior art 2;

[0028] Figure 3 This is a circuit diagram of prior art 3;

[0029] Figure 4 This is a timing diagram of the measurement cycle circuit of the present invention;

[0030] Figure 5 This is a circuit diagram of the present invention;

[0031] Figure 6 A schematic diagram of the current flow direction during the preparation stage of this invention;

[0032] Figure 7 This is a schematic diagram of the current flow direction during the high dv / dt impact stage of the present invention;

[0033] Figure 8 This is a schematic diagram of the current flow direction during the detection stage of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided below with reference to the accompanying drawings is not intended to limit the scope of protection of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The present invention will be further described below with reference to the accompanying drawings.

[0035] This invention specifically relates to a dv / dt withstand capability test circuit for power devices. To evaluate the dv / dt withstand capability of power devices, a high dv / dt voltage pulse generated by a high-current gate drive method controlled by a power MOSFET is adjustable. A new detection branch is introduced to periodically and indirectly measure the leakage current of the device under test to observe its variation. The high-current gate drive method enables rapid turn-on of the controlled MOSFET to generate extremely high dv / dt values. A voltage clamping component is added to protect the controlled MOSFET from breakdown while achieving high-current gate drive. The magnitude of the dv / dt pulse voltage is adjustable by introducing a variable gate resistor.

[0036] like Figure 4 As shown, each measurement cycle consists of three stages: a preparation stage, a high dv / dt impact stage, and a detection stage. The preparation stage adjusts the operating state of the main components; the high dv / dt impact stage applies high dv / dt voltage stress to the device under test (DUT); and the detection stage measures the leakage current of the DUT. Before each high dv / dt impact or detection, the preparation stage must be entered to adjust the operating state of the main components and ensure that the parasitic capacitance of the DUT is fully discharged, avoiding interference with subsequent stages. The measurement cycle varies depending on the specific circumstances, typically ranging from a few minutes to several days, or even longer. A single measurement process may contain multiple measurement cycles; a leakage current detection of the DUT is required before the first measurement cycle to obtain the initial leakage current status of the device.

[0037] like Figure 5 As shown, the device under test in this invention takes a silicon carbide MOSFET as an example. It consists of two high-voltage DC voltage sources (V1 and V2), two voltage divider resistors (R1 and R2), two power resistors (R3 and R5), one current-limiting resistor R4, and four gate resistors (R4, R5, R6). G1 R G2 R G R G4 A variable gate resistor R G3 Two capacitors (C1 and C2), four drive pulse generators (V GS1 V GS2 V GS V GS4 It consists of a voltage clamping component.

[0038] Capacitor C1 stores the energy of the current pulse, rapidly charging the gate parasitic capacitance of MOSFET3 (internal parasitic input capacitance, including the gate-source and gate-drain parasitic capacitances of the MOSFET) at the instant MOSFET1 turns on, enabling it to turn on quickly. Because R1 is very large and R3 is very small, The large gate current of MOS3 is provided by capacitor C1.

[0039] The voltage clamping component is connected between the gate and source of the switching transistor MOS3. When the gate voltage of the switching transistor MOS3 is low, the voltage clamping component is in the off state. When the gate voltage of the switching transistor MOS3 reaches the reverse breakdown voltage or operating voltage of the voltage clamping component, the voltage clamping component quickly changes from a high resistance state to a low resistance conduction state to discharge the instantaneous overcurrent and clamp the gate voltage of the switching transistor MOS3 to a safe value.

[0040] The voltage clamping components include a transient voltage suppressor (TVS), an electrostatic discharge diode (EDS), a limiting circuit, or a voltage clamping circuit. This invention uses a TVS as an example. The TVS protects the MOS3 transistor from a large gate voltage induced by a large current pulse, preventing it from breaking down the gate oxide layer of the MOS3. When the gate voltage is low, the TVS is in the off state (high resistance state), not affecting the normal operation of the circuit. When the gate voltage reaches the reverse breakdown voltage of the TVS, the TVS rapidly changes from a high resistance state to a low resistance conduction state, discharging the instantaneous overcurrent and clamping the gate voltage of the MOS3 to a lower, safer value.

[0041] Variable gate resistance R G3 The dv / dt ratio of the main circuit is adjusted by regulating the turn-on speed of MOS3. R3 and MOS2 provide a discharge path for the parasitic capacitance when MOS1 is off. The single-phase half-bridge connection of MOS1 and MOS2 ensures reliable turn-on and turn-off of MOS3. The device under test (DUT) is connected in reverse in the circuit. When MOS3 is off, the body diode inside the DUT is forward-biased, and the end of C2 connected to the DUT is grounded. At the instant MOS3 turns on, the end of C2 connected to MOS3 is forcibly grounded, so that the voltage across capacitor C2 is quickly applied to the drain and source terminals of the DUT, resulting in a large dv / dt pulse voltage. Therefore, dv / dt is only limited by the parasitic parameters of the main circuit and is largely determined by the voltage across capacitor C2 and the turn-on speed of MOS3.

[0042] The branch containing R5 and MOS4 forms the leakage current detection discharge branch for the device under test (DUT). Capacitor C2 flows through this branch, forming a loop, and discharges at a low rate. By detecting the voltage change across the DUT, the leakage current change after a high dv / dt stress is indirectly measured, thus determining the DUT's dv / dt tolerance. The leakage current of the DUT is typically in the nanoamp to microamp (nA-μA) range, making direct detection difficult. Since the capacitance of C2 is constant (Q = C × U = I × t), this invention introduces an additional leakage current detection stage and a leakage current detection discharge branch through a staged detection method. Capacitor C2 then flows through the DUT again through the leakage current detection discharge branch, forming a loop. By controlling the turn-on of MOS4, C2 is turned on at a low rate, slowly discharging through the DUT's leakage current. Whether the DUT has aged can be determined by comparing the time required for C2 to discharge through the DUT before and after applying high dv / dt stress. During the testing phase, MOS1 is off, MOS2 is on, MOS3 is off, and MOS4 is on. C2 slowly discharges through the circuit containing R5, MOS4, and the DUT. The voltage change across the DUT is detected using an oscilloscope or sampling circuit. By comparing the voltage change across the DUT with the voltage change over the same time interval, it is determined whether the applied high dv / dt impact stress has caused aging of the DUT. The discharge time of capacitor C2 can be relatively long during this phase, and the accuracy requirements for testing equipment such as oscilloscopes and probes are not high, making it easy to implement.

[0043] The leakage current detection discharge branch eliminates the need for real-time testing of the dv / dt withstand capability of the device under test (DUT) during the high dv / dt impact phase. This separates the detection phase from the high dv / dt impact phase. During the detection phase, the detection circuit current is small, the discharge rate is low, and the discharge current is primarily determined by the DUT's leakage current. Resistor R5 limits the discharge current of C2 when a short-circuit fault occurs in the DUT, protecting other components in the circuit from burnout. Simultaneously, it increases the detection circuit loss during the detection phase, facilitating control over the discharge time required for C2. During aging tests, the non-destructive aging of the DUT can also be determined by the magnitude of the drain-source voltage drop over the same period.

[0044] Furthermore, the switching transistor MOS4 in the leakage current detection and discharge branch does not have very high requirements for switching speed, so a relay or IGBT device can be used instead.

[0045] The table below shows the correspondence between the timing states and MOSFET switching states during the measurement cycle, where 0 represents the off state and 1 represents the on state.

[0046] MOS1 MOS2 MOS3 MOS4 DUT Preparation stage 0 1 0 0 0 High dv / dt impact phase 1 0 1 0 0 Preparation stage 0 1 0 0 0 Testing phase 0 1 0 1 0

[0047] When the circuit is in the preparation stage, the main current flow direction in the circuit is as follows: Figure 6As shown. At this time, MOS1 is off, MOS2 is on, causing MOS3 to be grounded and in the off state, and MOS4 is off. Capacitor C1 charges, the parasitic gate capacitance of MOS3 discharges, capacitor C2 charges, the parasitic body diode of the device under test is forward-biased, and the parasitic drain-source capacitance of the device under test discharges.

[0048] When the circuit is in the high dv / dt impact stage, the main current flow direction in the circuit is as follows: Figure 7 As shown in the diagram. At this time, MOS1 is turned on, MOS2 is turned off, the gate voltage of MOS3 rapidly rises above the threshold voltage and turns on, and MOS4 is turned off. The voltage across capacitor C1 changes abruptly and is in a discharging state, generating a large induced current to charge the gate capacitance of MOS3, causing MOS3 to quickly turn on. When the gate voltage of MOS3 reaches the TVS breakdown voltage, the TVS rapidly changes from a high-resistance state to a low-resistance state and turns on, discharging the instantaneous overcurrent and clamping the gate voltage of MOS3 to a safe value, preventing MOS3 from being broken down. When MOS3 is turned on, the end of capacitor C2 connected to MOS3 is forcibly grounded, and the voltage across capacitor C2 is rapidly applied to the drain and source terminals of the device under test, generating a large dv / dt impact stress.

[0049] When the circuit is in the detection phase, the main current flow direction in the circuit is as follows: Figure 8 As shown. At this time, MOS1 is off, MOS2 is on, MOS3 is off due to its gate being grounded, and MOS4 is on. Capacitor C1 is charging, and the voltage across capacitor C2 is applied to the drain-source terminals of the device under test (DUT) through R5 and MOS4, slowly discharging through the leakage current of the DUT. By connecting an oscilloscope or sampling circuit to the drain-source terminals of the DUT to detect the voltage change across the DUT, and comparing the voltage change values ​​across the DUT at the same time intervals, it can be determined whether the applied high dv / dt impact stress has caused aging of the DUT, thus determining the dv / dt tolerance of the power device under test.

[0050] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A circuit for testing the dv / dt withstand capability of power devices, characterized in that: It includes a high-current gate drive circuit and a main circuit; the main circuit includes a switching transistor MOS3, a device under test (DUT), and a drive pulse generator V. GS Capacitor C2, Resistor R G And R4, and a high-voltage DC voltage source V2; the positive terminal of the high-voltage DC voltage source V2 is connected to the drain of the switching transistor MOS3 through resistor R4, and the negative terminal is grounded; the drive pulse generator V GS One end is connected to resistor R G One end is connected to the gate of the device under test (DUT), and the other end is connected to the source of the DUT. The drain of the DUT and the source of the switching transistor MOS3 are both grounded, and the source is connected to the drain of the switching transistor MOS3 through capacitor C2. The gate high-current drive circuit is connected to the gate of the switching transistor MOS3. It is used to charge and discharge the parasitic capacitance inside the switching transistor MOS3, enabling the switching transistor MOS3 to turn on and off quickly, and to discharge instantaneous overcurrent, preventing the gate voltage of the switching transistor MOS3 from being broken down by a large gate voltage, clamping the gate voltage of the switching transistor MOS3 to a safe value, and adjusting the turn-on speed of the switching transistor MOS3, thereby adjusting the magnitude of dv / dt of the main circuit. At the instant that the switching transistor MOS3 is turned on, one end of capacitor C2 connected to MOS3 is forcibly grounded, so that the voltage across capacitor C2 is quickly applied to the drain and source terminals of the device under test (DUT), thereby generating a large dv / dt pulse voltage to test the dv / dt withstand capability of the DUT. It also includes a leakage current detection and discharge branch, which includes a drive pulse generator V. GS4 MOSFET4 (switching transistor), R (resistor) G4 and R5; Drive pulse generator V GS4 One end is grounded, and the other end is connected to a resistor R. G4 The gate of the switching transistor MOS4 is connected to the gate of the switching transistor MOS4. The drain of the switching transistor MOS4 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the drain of the switching transistor MOS3. The source of the switching transistor MOS4 is grounded. The capacitor C2 flows through the leakage current detection discharge branch to form a loop through the device under test (DUT). When the switching transistor MOS3 is turned off and the switching transistor MOS4 is turned on, the capacitor C2 discharges at a low rate through the circuit containing the resistor R5, the switching transistor MOS4, and the device under test (DUT). By detecting the voltage change across the device under test (DUT), the dv / dt withstand capability of the device under test (DUT) can be determined. The gate high-current drive circuit includes a high-voltage DC voltage source V1 and a drive pulse generator V1. GS1 Resistors R1, R2, R3, R G1 and R G3 MOSFET1; The positive terminal of the high-voltage DC power source V1 is connected to the drain of the switching transistor MOS1 through resistor R1, and the negative terminal is grounded. One end of resistor R2 and capacitor C1 are both connected to the drain of the switching transistor MOS1, and the other end is grounded. One end of resistor R3 is connected to the gate of the switching transistor MOS3, and the other end is grounded. The source of the switching transistor MOS1 is connected to resistor R... G3 Connect the gate of the switching transistor MOS3 to drive the pulse generator V. GS1 One end is connected to resistor R G1 One end is connected to the gate of switching transistor MOS1, and the other end is connected to the source of switching transistor MOS1. Capacitor C1 stores the energy of the current pulse, which quickly charges the parasitic capacitance inside switching transistor MOS3 at the moment switching transistor MOS1 is turned on, enabling switching transistor MOS3 to turn on quickly. Resistor R G3 Used to adjust the turn-on speed of MOS3, thereby adjusting the dv / dt of the main circuit. MOS1 ensures the reliable turn-on and turn-off of MOS3. The gate high current drive circuit also includes a voltage clamping component, which is connected between the gate and source of the switching transistor MOS3. When the gate voltage of the switching transistor MOS3 is low, the voltage clamping component does not work. When the gate voltage of the switching transistor MOS3 reaches the reverse breakdown voltage or operating voltage of the voltage clamping component, the voltage clamping component quickly changes from a high resistance state to a low resistance conduction state to discharge the instantaneous overcurrent and clamp the gate voltage of the switching transistor MOS3 at a safe value.

2. The dv / dt withstand capability test circuit for power devices according to claim 1, characterized in that: The gate high-current drive circuit also includes a drive pulse generator V. GS2 Resistance R G2 With the switching transistor MOS2; The drive pulse generator V GS2 One end is connected to resistor R G2 The gate of the switch MOS2 is connected to the other end, and the drain of the switch MOS2 is connected to the source of the switch MOS1. The source of the switch MOS2 is grounded. Resistor R3 and switch MOS2 provide a discharge path for the parasitic input capacitance inside switch MOS3 when switch MOS1 is turned off. The single-phase half-bridge structure of switch MOS1 and MOS2 ensures the reliable turn-on and turn-off of switch MOS3.

3. A method for testing the dv / dt withstand capability of power devices, characterized in that: The testing method includes a preparation phase, a high dv / dt impact phase, and a detection phase. The high dv / dt impact phase includes: After the parasitic capacitance inside the device under test (DUT) is fully discharged during the preparation phase, the switching transistor MOS1 is turned on and the switching transistor MOS2 is turned off. This causes a sudden voltage change across capacitor C1, which is in a discharge state. A large induced current is generated to charge the parasitic capacitance inside the switching transistor MOS3, causing the switching transistor MOS3 to quickly turn on due to the gate voltage rapidly increasing and exceeding the threshold voltage. When MOS4 is turned off, and the gate voltage of MOS3 reaches the reverse breakdown voltage or operating voltage of the voltage clamping component, the voltage clamping component rapidly changes from a high resistance state to a low resistance state and turns on, discharging the instantaneous overcurrent and clamping the gate voltage of MOS3 at a safe value to prevent MOS3 from being broken down. When MOS3 is turned on, it will force the end of capacitor C2 connected to MOS3 to ground, so that the voltage across capacitor C2 is rapidly applied to the two ends of the device under test (DUT), thereby generating a large dv / dt pulse voltage stress to test the dv / dt withstand capability of the DUT. The preparation phase includes: When MOS1 is turned off and MOS2 is turned on, the gate of MOS3 is grounded and turned off. The parasitic capacitance inside MOS3 discharges and capacitor C1 is charged. At the same time, MOS4 is turned off. One end of capacitor C2 is connected to the positive terminal of high voltage DC voltage source V2 through R4, and the other end is grounded through the parasitic body diode of the DUT. The voltage of high voltage DC voltage source V2 is directly applied to both ends of capacitor C2 through R4, capacitor C2 is charged, and the parasitic drain-source capacitance of the device under test discharges. The detection phase includes: The control switch MOS1 is turned off, MOS2 is turned on, and the gate of MOS3 is grounded and in the off state. The control switch MOS4 is turned on. Capacitor C2 is applied to the drain and source terminals of the device under test (DUT) through resistor R5 and MOS4. The leakage current of the DUT discharges at a low rate. The voltage change across the DUT is detected by an oscilloscope or sampling circuit. By comparing the voltage change across the DUT at the same time, it is determined whether the applied high dv / dt impact pulse stress has caused the DUT to age.

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