Current mirror circuit, biasing circuit and electronic equipment

Abstract

The invention discloses a current mirror circuit, a bias circuit and electronic equipment. The current mirror circuit comprises a voltage bias circuit, a buffer circuit, a follower circuit and a current source, the buffer circuit comprises a mirror image output unit and a negative feedback unit; the current source inputs reference current to the voltage bias circuit, the voltage bias circuit provides voltage bias for the buffer circuit, first mirror current in proportion to the reference current is generated on the buffer circuit, and second mirror current in proportion to the first mirror current is generated through the follower circuit; the negative feedback unit generates a negative feedback signal when the voltage of the connection part of the follower circuit and the buffer circuit deviates from the preset target voltage, so that the voltage of the connection part of the follower circuit and the buffer circuit is maintained at the target voltage based on the negative feedback information, and the voltage of the connection part of the follower circuit and the buffer circuit is maintained at the target voltage. Therefore, the same effect as a buffer is added between the input and the output of the current mirror circuit, and stable current bias is rapidly established.

Description

Technical Field

[0001] This application relates to the field of sensor technology, specifically to a current mirror circuit, a bias circuit, and an electronic device. Background Technology

[0002] Current mirrors are widely used in analog and hybrid circuits and are one of the most basic unit circuits. Their function is to replicate the reference current of one branch in a circuit to other branches to reduce errors caused by changes in voltage, temperature, etc. Therefore, the performance of the current mirror affects the performance of the entire circuit.

[0003] Existing current mirror circuits mainly consist of basic current mirror structures and cascode current mirrors. When using a basic current mirror structure to provide current bias to the components in a matrix, the large parasitic capacitance between the gate and drain of the transistors in the right-side output current branch of the current mirror results in a very long charging and discharging time when relying on the reference current input from the left-side branch. With a cascode current mirror, since the left-side branch includes MA and MC, and the right-side branch includes MB and MD, and another transistor ME is connected at the source-drain connection of the two MOSFETs (MB and MD) in the right-side branch, when the voltage across the gate-drain parasitic capacitance of ME drops, the gate-drain parasitic capacitance of MD must be discharged first before the gate voltage of MD can drop to charge the gate-drain parasitic capacitance of ME. This process is time-consuming and has a very slow response speed.

[0004] Therefore, existing current mirror circuits cannot quickly establish a stable current bias. Summary of the Invention

[0005] To address the aforementioned issues, embodiments of this application provide a current mirror circuit, a bias circuit, and an electronic device that can quickly establish a stable current bias.

[0006] In a first aspect, embodiments of this application provide a current mirror circuit, including: a voltage bias circuit, a buffer circuit, a follower circuit, and a current source;

[0007] The buffer circuit includes a mirror output unit and a negative feedback unit, wherein the mirror output unit is connected to the negative feedback unit;

[0008] The current source is connected to the voltage bias circuit and inputs a reference current to the voltage bias circuit;

[0009] The voltage bias circuit is used to provide a voltage bias to the buffer circuit and generate a first mirror current on the buffer circuit that is proportional to the reference current.

[0010] The follower circuit is connected to the mirror output unit and the negative feedback unit respectively, and generates a second mirror current that is proportional to the first mirror current;

[0011] The negative feedback unit is used to generate a negative feedback signal when the voltage at the connection between the follower circuit and the buffer circuit deviates from the preset target voltage, so as to maintain the voltage at the connection between the follower circuit and the buffer circuit at the target voltage.

[0012] According to the current mirror circuit provided in this application, the voltage bias circuit includes a first transistor and a second transistor, the mirror output unit includes a third transistor, and the negative feedback unit includes a fourth transistor.

[0013] According to the current mirror circuit provided in this application, a mirror structure is formed based on the connection between the first transistor, the second transistor, the third transistor and the fourth transistor.

[0014] According to the current mirror circuit provided in this application, the transistor connection relationships include:

[0015] The drain of the first transistor is connected to the current source, and the drain of the first transistor is also connected to the gate of the first transistor.

[0016] The source of the first transistor is connected to the drain of the second transistor, the drain of the second transistor is also connected to the gate of the second transistor, and the source of the second transistor is grounded.

[0017] According to the current mirror circuit provided in this application, the transistor connection relationships also include:

[0018] The gate of the first transistor is connected to the gate of the third transistor, providing a stable voltage bias to the gate of the third transistor so that a first mirror current is formed on the third transistor.

[0019] The source of the third transistor is connected to the drain of the fourth transistor, the drain of the fourth transistor is also connected to the gate of the fourth transistor, the gate of the fourth transistor is also connected to the follower circuit, and the source of the fourth transistor is grounded.

[0020] According to the current mirror circuit provided in this application, the follower circuit includes a fifth transistor, the gate of the fifth transistor is connected to the gate of the fourth transistor, the source of the fifth transistor is grounded, and the second mirror current is formed at the drain of the fifth transistor.

[0021] According to the current mirror circuit provided in this application, the first ratio of the width-to-length ratio of the first transistor to the width-to-length ratio of the third transistor is equal to the second ratio of the width-to-length ratio of the second transistor to the width-to-length ratio of the fourth transistor.

[0022] According to the current mirror circuit provided in this application, the ratio of the reference current to the first mirror current is equal to the first ratio or the second ratio;

[0023] The ratio of the first mirror current to the second mirror current is equal to the third ratio of the width-to-length ratio of the fourth transistor to the width-to-length ratio of the fifth transistor.

[0024] Secondly, embodiments of this application provide a bias circuit, the bias circuit including a bias transistor and a current mirror circuit as provided in the first aspect, wherein the second mirror current output by the current mirror circuit is used to feed the bias transistor.

[0025] Thirdly, embodiments of this application also provide an electronic device that includes the current mirror circuit provided in the first aspect.

[0026] The current mirror circuit provided in this application includes a voltage bias circuit, a buffer circuit, a follower circuit, and a current source. The buffer circuit includes a mirror output unit and a negative feedback unit. The current source inputs a reference current to the voltage bias circuit. The voltage bias circuit provides a voltage bias to the buffer circuit and generates a first mirror current proportional to the reference current on the buffer circuit. Then, a second mirror current proportional to the first mirror current is generated through the follower circuit. With the help of the negative feedback unit, a negative feedback signal is generated when the voltage at the connection between the follower circuit and the buffer circuit deviates from the preset target voltage, so that the voltage at the connection between the follower circuit and the buffer circuit is maintained at the target voltage. Thus, the same effect as adding a buffer is achieved between the input and output of the current mirror circuit, thereby realizing the rapid establishment of a stable current bias. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the circuit structure that provides current bias to each element in the matrix using a basic current mirror.

[0029] Figure 2 This is a schematic diagram illustrating the parasitic capacitance crosstalk and charging / discharging problems of a basic current mirror.

[0030] Figure 3 This is a schematic diagram of the improved current mirror circuit proposed in the prior art;

[0031] Figure 4 This is one of the structural schematic diagrams of the current mirror circuit provided in the embodiments of this application;

[0032] Figure 5 This is a second schematic diagram of the current mirror circuit provided in the embodiments of this application;

[0033] Figure reference numerals: 10 is voltage bias circuit; 20 is buffer circuit; 21 is mirror output unit; 22 is negative feedback unit; 30 is follower circuit; 40 is current source; M1 is first transistor; M2 is second transistor; M3 is third transistor; M4 is fourth transistor; M5 is fifth transistor. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0035] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for the purpose of simplicity and clarity and does not inherently define the relationship between the various embodiments and / or configurations discussed.

[0036] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application. Moreover, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0037] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0038] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0039] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed description. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0040] As described in the background section, the inventors discovered that when the gate-drain parasitic capacitance of the transistor on the output mirror current side causes a change in the gate voltage of the transistor, the existing current mirror circuit cannot quickly establish a stable current bias.

[0041] Specifically, Figure 1This is a schematic diagram of the circuit structure for providing current bias to the various components in the matrix using a basic current mirror. Figure 2 This is a schematic diagram illustrating the principle of parasitic capacitance crosstalk and charging / discharging problems in a basic current mirror, referencing... Figure 1 When using a current mirror structure to provide current bias to each element (such as a pixel unit in a pixel array) in a matrix, a number of current mirror structures equal to or an integer multiple of the number of elements in the matrix needs to be configured, i.e., the number of current mirror structures is k×m×n, where k, m, and n are all positive integers. For example... Figure 2 As shown in (a), parasitic capacitance exists between the gate and drain of the transistor in the branch of the output current on the right side of the current mirror structure. Figure 1 In the application scenario shown, the parasitic capacitances between the gate and drain of all the right-side branch transistors are connected in parallel, ultimately resulting in a very large parasitic capacitance.

[0042] Continue to refer to Figure 2 (a) When the drain voltage of the right-side transistor rises or falls, the gate voltage is also pulled up or down due to the parasitic capacitance, causing instability at the gate-drain short circuit of the left-side transistor, i.e., introducing crosstalk, which prevents the current mirror from providing a stable current bias. To solve this problem, existing technology uses a larger input reference current to charge or discharge the parasitic capacitance. However, because the capacitance of this parasitic capacitance is large, it takes a very long time to charge or discharge it using the reference current input from the left branch of the current mirror, i.e., the current mirror establishes a stable current bias very slowly. Increasing the reference current means that the parasitic capacitance of the transistor will also increase. Furthermore, research has found that the actual current that can charge and discharge the parasitic capacitance is not the reference current itself, but a portion of it, ΔI, such as... Figure 2 As shown in (b). Therefore, the above solution cannot effectively solve the problem caused by parasitic capacitance.

[0043] Understandably, adding a buffer between the left and right branches of the current mirror could solve the crosstalk and charging / discharging problems caused by parasitic capacitance. However, adding a buffer to the current mirror structure would cause the gate voltages of the two transistors to be different (op-amp offset), thus preventing the current mirror from outputting a mirrored current. Specifically, a common method is to connect a decoupling capacitor at the reference voltage. Although decoupling capacitors, especially those with large on-chip capacitance, can effectively reduce crosstalk, their charge loss in this process needs to be compensated by bias current. If the compensation is not timely, it will cause the bias voltage to drift.

[0044] Based on this, refer to Figure 3Existing technologies also propose using a common-source, common-gate current mirror (the left branch includes transistors MA and MC, and the right branch includes transistors MB and MD), and connecting another transistor ME (with its gate connected at the source-drain junction of MB and MD) to achieve a function similar to a buffer + current mirror, in order to solve the problems of crosstalk caused by parasitic capacitance and slow stable bias setup speed (slow charging and discharging of parasitic capacitance). The newly added transistor acts as a source follower.

[0045] However, this study found that, since the source follower only has unidirectional driving capability, the improved structure can only achieve a fast response to the rise of the ME gate voltage, but cannot respond quickly when the ME gate voltage drops. Specifically, when the voltage across the ME gate-drain parasitic capacitor rises, the voltage across the MD gate-drain parasitic capacitor can respond quickly, causing the MD gate voltage to rise. This leads to an increase in the current in the MD-opened path, which discharges the ME gate-drain parasitic capacitor until the ME gate voltage drops back to a stable level. However, when the voltage across the ME gate-drain parasitic capacitor drops, the MD gate-drain parasitic capacitor needs to be discharged first before the MD gate voltage can drop to charge the ME gate-drain parasitic capacitor. This process is time-consuming and the response speed is very slow. In other words, when the ME gate voltage drops, the improved current mirror structure still cannot quickly establish a stable current bias, resulting in a slow overall establishment speed of the stable current bias.

[0046] Based on this, embodiments of this application propose a current mirror circuit, a bias circuit, and an electronic device. The current mirror circuit includes a voltage bias circuit, a buffer circuit, a follower circuit, and a current source. The buffer circuit includes a mirror output unit and a negative feedback unit. The current source inputs a reference current to the voltage bias circuit. The voltage bias circuit provides a voltage bias to the buffer circuit and generates a first mirror current proportional to the reference current on the buffer circuit. Then, a second mirror current proportional to the first mirror current is generated through the follower circuit. With the help of the negative feedback unit, a negative feedback signal is generated when the voltage at the connection between the follower circuit and the buffer circuit deviates from a preset target voltage, so that the voltage at the connection between the follower circuit and the buffer circuit is maintained at the target voltage. Thus, the same effect as adding a buffer is achieved between the input and output of the current mirror circuit, thereby realizing the rapid establishment of a stable current bias.

[0047] It should be noted that the order of description in the following embodiments is not intended to limit the preferred order of embodiments. Although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be performed in a different order than that shown in the figures.

[0048] See Figure 4 , Figure 4 This is one of the structural schematic diagrams of the current mirror circuit provided in this application. According to... Figure 4The current mirror circuit includes a voltage bias circuit 10, a buffer circuit 20, a follower circuit 30, and a current source 40. The buffer circuit 20 includes a mirror output unit 21 and a negative feedback unit 22. One end of the mirror output unit 21 is connected to one end of the negative feedback unit 22, and the other end of the negative feedback unit 22 is grounded.

[0049] The current source 40 is connected to the voltage bias circuit 10, and the current source 40 can input a reference current to the voltage bias circuit 10, which is denoted as I. tot .

[0050] Voltage biasing circuit 10 can provide voltage bias to buffer circuit 20 and generate a first mirror current proportional to the reference current on buffer circuit 20, wherein the reference current I tot The specific ratio between the current and the first mirror current is determined by the ratio between the size of the transistor in the voltage bias circuit 10 and the size of the transistor in the buffer circuit 20.

[0051] The follower circuit 30 is connected to the mirror output unit 21 and the negative feedback unit 22 respectively, and can generate a second mirror current proportional to the first mirror current. The second mirror current is denoted as I. out The first mirror current and the second mirror current I out The specific ratio between them is determined by the ratio between the size of the transistor in the buffer circuit 20 and the size of the transistor in the follower circuit 30.

[0052] When the voltage at the connection between the follower circuit 30 and the buffer circuit 20 deviates from the preset target voltage, the negative feedback unit 22 generates a negative feedback signal to maintain the voltage at the connection between the follower circuit 30 and the buffer circuit 20 at the target voltage.

[0053] It is understood that the current source 40 in this embodiment does not need to input a large reference current to the voltage bias circuit 10. It only needs to provide a reference current so that the voltage bias circuit 10 can provide a stable voltage bias to the buffer circuit 20. This avoids the problem of increased parasitic capacitance caused by increased input reference current and improves the driving capability of the current mirror circuit.

[0054] Driven by the stable voltage bias provided by the voltage bias circuit 10, the buffer circuit 20 forms a first-stage mirror current, i.e., the first mirror current, on its mirror output unit 21. Relying on the following effect of the follower circuit 30, a second-stage mirror current, i.e., the second mirror current, is formed on the follower circuit 30. The specific ratios of the reference current, the first mirror current, and the second mirror current are determined by the ratios between the sizes of the transistors in the voltage bias circuit, the buffer circuit, and the follower circuit.

[0055] More specifically, when the voltage at the connection point between the follower circuit 30 and the buffer circuit 20 deviates from the preset target voltage, such as when the voltage across the parasitic capacitance between the gate and drain of the transistor in the follower circuit 30 changes, the negative feedback unit 22 generates a negative feedback signal. When the voltage at the connection point between the follower circuit 30 and the buffer circuit 20 is higher than the target voltage, the negative feedback signal discharges the parasitic capacitance between the gate and drain of the transistor in the follower circuit, thereby causing the voltage at the connection point between the follower circuit 30 and the buffer circuit 20 to drop back to the target voltage; when the voltage at the connection point between the follower circuit 30 and the buffer circuit 20 is lower than the target voltage, the negative feedback signal charges the parasitic capacitance between the gate and drain of the transistor in the follower circuit, thereby causing the voltage at the connection point between the follower circuit 30 and the buffer circuit 20 to rise back to the target voltage.

[0056] The current mirror circuit provided in this application includes a voltage bias circuit, a buffer circuit, a follower circuit, and a current source. The buffer circuit includes a mirror output unit and a negative feedback unit. The current source inputs a reference current to the voltage bias circuit. The voltage bias circuit provides a voltage bias to the buffer circuit and generates a first mirror current proportional to the reference current on the buffer circuit. Then, a second mirror current proportional to the first mirror current is generated through the follower circuit. With the help of the negative feedback unit, a negative feedback signal is generated when the voltage at the connection between the follower circuit and the buffer circuit deviates from the preset target voltage, so that the voltage at the connection between the follower circuit and the buffer circuit is maintained at the target voltage. Thus, the same effect as adding a buffer is achieved between the input and output of the current mirror circuit, thereby realizing the rapid establishment of a stable current bias.

[0057] Reference Figure 5 , Figure 5 This is a second schematic diagram of the current mirror circuit provided in the embodiments of this application. The voltage bias circuit 10 includes a first transistor M1 and a second transistor M2, the mirror output unit 21 includes a third transistor M3, and the negative feedback unit 22 includes a fourth transistor M4. The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 all operate in the saturation region.

[0058] Specifically, this can be understood as follows: based on the connections between the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, a mirror structure is formed. The transistor connections include: the drain of the first transistor M1 is connected to the current source 40, and the drain of the first transistor M1 is also connected to the gate of the first transistor M1. The source of the first transistor M1 is connected to the drain of the second transistor M2, and the drain of the second transistor M2 is also connected to the gate of the second transistor M2. The source of the second transistor M2 is grounded.

[0059] The transistor connections also include: the gate of the first transistor M1 is connected to the gate of the third transistor M3, providing a stable voltage bias to the gate of the third transistor M3 so that a first mirror current is formed on the third transistor M3. The source of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the fourth transistor M4 is also connected to the gate of the fourth transistor M4, the gate of the fourth transistor M4 is also connected to the follower circuit 30, and the source of the fourth transistor M4 is grounded.

[0060] Therefore, it can be understood that a stable voltage bias at the gate of the third transistor M3 forms a first mirror current I3 in the open path of the third transistor M3.

[0061] like Figure 5 As shown, the capacitance formed by the connection between the gate and drain of the fifth transistor M5 in the follower circuit 30 is the parasitic capacitance.

[0062] The voltage at the gate of the fourth transistor M4 is equal to the voltage at the connection point between the follower circuit 30 and the buffer circuit 20, i.e., the voltage at node M.

[0063] It is understood that, in this embodiment, the AC negative feedback signal sent by the negative feedback unit 22 is the AC current ΔI4 on the open path of the fourth transistor M4.

[0064] It is understandable that when the voltage across the parasitic capacitor in the follower circuit 30 changes, the voltage at the gate of the fourth transistor M4 will also change synchronously, so as to perform negative feedback regulation on the voltage at the connection between the follower circuit 30 and the buffer circuit 20, and stabilize it to the target voltage.

[0065] Specifically, when the voltage across the parasitic capacitor rises, the gate voltage of the fourth transistor M4 rises synchronously. At this time, since the fourth transistor M4 is operating in the saturation region, the voltage V of the fourth transistor M4... GS4 Rise ΔV GS4 The current I4 in the path where the fourth transistor M4 is turned on will rise sharply.

[0066]

[0067] Where, μ n C represents the electron mobility of the fourth transistor M4. ox For parasitic capacitance, W4 is the width of the fourth transistor M4, L4 is the length of the fourth transistor M4, and V... th The target voltage.

[0068] With the gate voltage of the third transistor M3 remaining constant, the first mirror current I3 in the open path of the third transistor M3 remains unchanged. Based on the node current law, an AC current ΔI4 will flow out of node M (the connection point between the follower circuit 30 and the buffer circuit 20) due to the parasitic capacitance. Please refer to... Figure 5 The direction of this current is taken as positive. That is, at this time, node M is in a discharging state, that is, the parasitic capacitance is in a discharging state, the voltage of node M decreases, and the voltage of the gate in the fourth transistor M4 decreases synchronously until the current I4 is equal to the first mirror current I3, that is, until the voltage of the gate in the fourth transistor M4 (the voltage at the connection between the follower circuit 30 and the buffer circuit 20) drops back to the target voltage, that is, ΔI4 returns to zero.

[0069] Similarly, when the voltage across the parasitic capacitor decreases, the gate voltage of the fourth transistor M4 decreases synchronously. At this time, since the fourth transistor M4 is operating in the saturation region, the voltage V of the fourth transistor M4... GS4 As the current decreases, the current I4 in the path where the fourth transistor M4 is turned on will drop sharply.

[0070] With the gate voltage of the third transistor M3 remaining constant, the first mirror current I3 in the open path of the third transistor M3 remains constant. Based on the node current law, an alternating current -ΔI4 will be injected into node M (the connection between the follower circuit 30 and the buffer circuit 20). It can be understood that the negative sign indicates the direction of the alternating current ΔI4. That is, node M is in a charging state, i.e., the parasitic capacitance is charging, the voltage of node M increases, and the gate voltage of the fourth transistor M4 increases synchronously until the current I4 equals the first mirror current I3, i.e., until the gate voltage of the fourth transistor M4 (the voltage at the connection between the follower circuit 30 and the buffer circuit 20) rises back to the target voltage, i.e., ΔI4 returns to zero.

[0071] Understandably, this is based on the nodal current law: I4=I3±ΔI4.

[0072] Therefore, it can be understood that when the voltage at the connection point between the follower circuit 30 and the buffer circuit 20 deviates from the preset target voltage—for example, when the voltage across the parasitic capacitor in the follower circuit 30 changes—the negative feedback unit 22 generates a negative feedback signal. This negative feedback signal discharges the parasitic capacitor in the follower circuit 30 when the voltage at the connection point is higher than the target voltage, thereby causing the voltage at the connection point to drop back to the target voltage. Conversely, when the voltage at the connection point is lower than the target voltage, the parasitic capacitor in the follower circuit 30 is charged, thereby causing the voltage at the connection point to rise back to the target voltage.

[0073] Furthermore, it can be understood that the target voltage is the gate voltage of the fourth transistor M4 that enables I4 = I3.

[0074] This application embodiment utilizes a negative feedback unit to generate a negative feedback signal when the voltage at the connection between the follower circuit and the buffer circuit deviates from the preset target voltage, so that the voltage at the connection between the follower circuit and the buffer circuit is maintained at the target voltage. This achieves the same effect as adding a buffer between the input and output of the current mirror circuit, thereby enabling the rapid establishment of a stable current bias.

[0075] Optionally, the follower circuit 30 includes a fifth transistor M5, wherein the gate of the fifth transistor M5 is connected to the gate of the fourth transistor M4, the source of the fifth transistor M5 is grounded, and a second mirror current is formed at the drain of the fifth transistor M5.

[0076] Understandably, referring to Figure 5 Based on the trans-linear loop (which utilizes the nonlinear characteristics of transistors and feedback loops to realize the functions of complex analog circuits), the relationship between transistor voltages can be obtained:

[0077] V GS1 +V GS2 =V GS3 +V GS4 =V GS3 +V GS5

[0078] Among them, V GS1 V is the voltage of the first transistor. GS2 V is the voltage of the second transistor. GS3 V is the voltage of the third transistor. GS4 V is the voltage of the fourth transistor. GS5 This is the voltage of the fifth transistor.

[0079] Combining the relationship between transistor voltages and Figure 3 As can be seen from the corresponding transistors, in this embodiment of the application, the fifth transistor M5 is connected to the gate of the fourth transistor M4 (the source of the third transistor M3 and the drain of the fourth transistor M4), which is equivalent to Figure 3 With the gate of transistor M5 connected to point b, a corresponding second mirror current can be formed at the drain of the fifth transistor M5. Since the gate and drain of the fourth transistor M4 are shorted, it can be understood as an equivalent resistance of 1 / gm, which greatly reduces the time constant of node M and accelerates the charging and discharging speed of node M.

[0080] Optionally, the rise and fall of the voltage across the parasitic capacitance between the gate and drain of the fifth transistor M5 is the same as described above, and will not be repeated here.

[0081] Optionally, in this embodiment, the first ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the third transistor M3 is equal to the second ratio of the width-to-length ratio of the second transistor M2 to the width-to-length ratio of the fourth transistor M4, that is:

[0082] (W1 / L1) / (W3 / L3)=(W2 / L2) / (W4 / L4)

[0083] Wherein, W1 is the width of the first transistor M1, L1 is the length of the first transistor M1, W2 is the width of the second transistor M2, L2 is the length of the second transistor M2, W3 is the width of the third transistor M3, L3 is the length of the third transistor M3, W4 is the width of the fourth transistor M4, and L4 is the length of the fourth transistor M4.

[0084] Optionally, in this embodiment, the ratio of the reference current to the first mirror current is equal to a first ratio or a second ratio, and the ratio of the first mirror current to the second mirror current is equal to a third ratio of the width-to-length ratio of the fourth transistor to the width-to-length ratio of the fifth transistor, that is:

[0085] I TOT / I3=(W1 / L1) / (W3 / L3)=(W2 / L2) / (W4 / L4)

[0086] I3 / I OUT =(W4 / L4) / (W5 / L5)

[0087] Where W5 is the width of the fifth transistor M5, and L5 is the length of the fifth transistor M5.

[0088] Therefore, the current mirror circuit of this application embodiment not only eliminates the need for a large input reference current to enhance driving capability, but also solves the problems of crosstalk and slow charging / discharging speed caused by parasitic capacitance in the transistor at the output terminal (the charging and discharging speeds of parasitic capacitance are both slower than...). Figure 3 The circuit structure shown is fast, especially in terms of charging speed. It achieves the effect of adding a buffer between the input and output of the current mirror circuit, and at the same time realizes the current mirror output capability, thus enabling the rapid establishment of a stable current bias.

[0089] Optionally, embodiments of this application also provide a bias circuit. This bias circuit includes a bias transistor and a fast-establishment current mirror circuit as described above, wherein the second mirror current output by the current mirror circuit is used to feed the bias transistor.

[0090] For example, the bias transistor can be a transistor in a pixel unit.

[0091] Optionally, this application also provides an electronic device that includes a rapidly established current mirror circuit as described above.

[0092] Although embodiments of this application have been shown and described herein, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A current mirror circuit, characterized in that, The current mirror circuit includes: a voltage bias circuit, a buffer circuit, a follower circuit, and a current source; The buffer circuit includes a mirror output unit and a negative feedback unit, wherein the mirror output unit is connected to the negative feedback unit; The current source is connected to the voltage bias circuit and inputs a reference current to the voltage bias circuit; The voltage bias circuit is used to provide a voltage bias to the buffer circuit and generate a first mirror current on the buffer circuit that is proportional to the reference current. The follower circuit is connected to the mirror output unit and the negative feedback unit respectively, and generates a second mirror current that is proportional to the first mirror current; The negative feedback unit is used to generate a negative feedback signal when the voltage at the connection between the follower circuit and the buffer circuit deviates from the preset target voltage, so as to maintain the voltage at the connection between the follower circuit and the buffer circuit at the target voltage.

2. The current mirror circuit according to claim 1, characterized in that, The voltage bias circuit includes a first transistor and a second transistor, the mirror output unit includes a third transistor, and the negative feedback unit includes a fourth transistor.

3. The current mirror circuit according to claim 2, characterized in that, A mirror structure is formed based on the connection between the first transistor, the second transistor, the third transistor, and the fourth transistor.

4. The current mirror circuit according to claim 3, characterized in that, The transistor connections include: The drain of the first transistor is connected to the current source, and the drain of the first transistor is also connected to the gate of the first transistor. The source of the first transistor is connected to the drain of the second transistor, the drain of the second transistor is also connected to the gate of the second transistor, and the source of the second transistor is grounded.

5. The current mirror circuit according to claim 4, characterized in that, The connection relationships of transistors also include: The gate of the first transistor is connected to the gate of the third transistor, providing a stable voltage bias to the gate of the third transistor so that a first mirror current is formed on the third transistor. The source of the third transistor is connected to the drain of the fourth transistor, the drain of the fourth transistor is also connected to the gate of the fourth transistor, the gate of the fourth transistor is also connected to the follower circuit, and the source of the fourth transistor is grounded.

6. The current mirror circuit according to any one of claims 2-5, characterized in that, The follower circuit includes a fifth transistor, the gate of which is connected to the gate of the fourth transistor, the source of which is grounded, and the drain of which forms the second mirror current.

7. The current mirror circuit according to claim 6, characterized in that, The first ratio of the width-to-length ratio of the first transistor to the width-to-length ratio of the third transistor is equal to the second ratio of the width-to-length ratio of the second transistor to the width-to-length ratio of the fourth transistor.

8. The current mirror circuit according to claim 7, characterized in that, The ratio of the reference current to the first mirror current is equal to the first ratio or the second ratio; The ratio of the first mirror current to the second mirror current is equal to the third ratio of the width-to-length ratio of the fourth transistor to the width-to-length ratio of the fifth transistor.

9. A bias circuit, characterized in that, The bias circuit includes a bias transistor and a current mirror circuit according to any one of claims 1-8, wherein the second mirror current output by the current mirror circuit is used to feed the bias transistor.

10. An electronic device, characterized in that, The electronic device includes a current mirror circuit as described in any one of claims 1-8.

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