Processor and computing task processing method

Abstract

The invention provides a processor and a computing task processing method, and relates to the technical field of data processing. The high-performance computing unit plate is used for executing a high-performance computing task; the active defense mechanism control plate is respectively connected with the processor main memory and the high-performance computing unit plate through an on-chip bus; the active defense mechanism control module comprises an active defense arbitration unit which is configured to receive a user request and execute authority verification and data preprocessing according to the user request; the task scheduling unit is connected to the active defense arbitration unit and is configured to execute differentiated task scheduling according to the authority verification result of the active defense arbitration unit; the basic calculation unit is connected to the task scheduling unit and is configured to execute a calculation task of an unauthorized user; and the calculation result output cache module is respectively connected with the basic calculation unit, the high-performance calculation unit plate and the processor main memory, and is configured to gather calculation results and write the calculation results into the processor main memory.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a processor and a method for processing computing tasks. Background Technology

[0002] With the rapid development of artificial intelligence and high-performance computing technologies, high-performance processors have been widely used in data centers, cloud computing platforms, scientific computing, and other fields. These applications typically require handling concurrent computing requests from multiple users. Therefore, high-performance processors not only need to provide powerful computing capabilities but also need effective resource management and security protection to ensure the rational allocation of computing resources and the stable operation of the system. Especially in multi-tenant environments, how to prevent unauthorized users from maliciously occupying core computing resources while ensuring a normal user experience for legitimate users has become a critical technical problem that urgently needs to be solved in the design of high-performance processors.

[0003] To manage and protect the computing resources of high-performance processors, existing technologies typically employ software-level access control mechanisms. Specifically, current solutions implement user permission management at the operating system or virtualization layer, using software programs running on the host CPU to authenticate and verify user requests. When a user initiates a computing request, the host CPU first executes a permission verification program, querying the user permission table stored in system memory to determine if the user has permission to access high-performance computing resources. For requests that pass permission verification, the host CPU schedules the task to be executed on the high-performance processor; for requests that fail permission verification, the system directly returns an access denied error message. This software-based permission management approach is widely used in traditional computing environments.

[0004] However, the above-mentioned existing technical solutions have the following drawbacks: First, permission verification and task scheduling rely entirely on the software execution of the Host CPU. In high-concurrency scenarios, a large number of permission verification requests will significantly increase the computing burden of the Host CPU, causing system performance bottlenecks. Second, software-level permission verification has inherent security vulnerabilities. Malicious users can bypass permission checks through various software attack methods and illegally occupy high-performance computing resources.

[0005] Therefore, how to process user computing requests more efficiently has become an urgent problem to be solved in the industry. Summary of the Invention

[0006] This invention provides a processor and a computing task processing method to address the problem of how to process user computing requests more efficiently in the prior art.

[0007] This invention provides a processor, comprising: Processor main memory; High-performance computing unit module, used to perform high-performance computing tasks; The active defense mechanism control module is connected to the processor main memory and the high-performance computing unit module respectively via an on-chip bus; The active defense mechanism control module includes: The proactive defense arbitration unit is configured to receive user requests and perform permission verification and data preprocessing in parallel based on the user requests. A task scheduling unit, connected to the proactive defense arbitration unit, is configured to perform differentiated task scheduling based on the permission verification result of the proactive defense arbitration unit. A basic computing unit, connected to the task scheduling unit, is configured to execute computing tasks for users without permissions; The calculation result output cache module is connected to the basic computing unit, the high-performance computing unit module and the processor main memory respectively, and is configured to aggregate the calculation results and write them to the processor main memory. The task scheduling unit is configured to: schedule computing tasks to the high-performance computing unit module for execution when the user has access permissions; and schedule computing tasks to the basic computing unit for execution when the user does not have access permissions.

[0008] According to a processor provided by the present invention, the active defense arbitration unit is connected to an external memory, and the active defense arbitration unit includes: The input request extraction and verification module, as the request entry point, is configured to separate user identification information and instruction data in the user request; The permission verification path is connected to the input request extraction and verification module, which includes a user identification information parsing module, a hash algorithm encryption and decoding module, and a MIG IP and permission recognition and confirmation module connected in sequence. The user identification information parsing module is configured to perform number system conversion and format alignment on the extracted user identification information. The hash algorithm plus cryptographic decoding module is configured to use a specific cryptographic hash function to calculate the converted identity information and generate the physical address index of the user's permission table in the memory; The MIG IP is configured to read the user permission table from the memory according to the calculated address, and the permission recognition and confirmation module is configured to output the permission verification result to the task scheduling unit; The data synchronization path, connected to the input request extraction and verification module, includes an instruction data caching module, a UUID generation module, and a data synchronization module connected in sequence, and is configured to send the instruction data, UUID, and user identification information to the task scheduling unit after performing time-series synchronization. The instruction data cache module is configured to temporarily store the separated instructions and data to be processed. The UUID generation module is configured to generate a unique UUID for the user request based on the current clock cycle and a random seed; The data synchronization module is configured to receive the UUID, instruction data, and user identification information, and perform timing alignment operations. While waiting for the permission verification channel to output the permission determination signal, it maintains the integrity of the data packet and sends the synchronized data packet to the task scheduling unit.

[0009] According to a processor provided by the present invention, the task scheduling unit is connected to an external SD card, and the task scheduling unit includes: The task scheduling arbitration FSM state machine is connected to the active defense arbitration unit and serves as the core control logic; A high-performance computing interface module connects the task scheduling arbitration FSM state machine with the high-performance computing unit module, and includes a high-performance computing unit module state reading module and a high-performance computing unit task sending module. The illegal request log storage module is connected to the task scheduling arbitration FSM state machine and is configured to generate log information and write it to the SD card when the user does not have access rights.

[0010] According to a processor provided by the present invention, the basic computing unit integrates ALU, FPU, SFU and LSU underlying computing resources; The basic computing unit is configured to: upon receiving an unauthorized task instruction distributed by the task scheduling unit, invoke the underlying computing resources to perform iterative calculations, and send the results of the iterative calculations to the calculation result output cache module.

[0011] According to a processor provided by the present invention, the active defense mechanism control module further includes a high-performance computing task result receiving module, which is connected between the high-performance computing unit module and the computing result output cache module; The calculation result output caching module is configured to: use the task's UUID to verify the source of the received calculation result; after the verification is successful, map the result and write it into the processor's main memory.

[0012] According to a processor provided by the present invention, the hash algorithm encryption and decoding module is configured to: use an encrypted hash function to perform calculations on user identification information to generate the physical address offset of the user's permission table in the memory; The permission verification path and the data synchronization path work in parallel, and the data synchronization module is configured to ensure that the permission verification result and the task data arrive at the task scheduling unit synchronously.

[0013] According to a processor provided by the present invention, the scheduling logic of the task scheduling arbitration FSM state machine is as follows: When an authorization signal is received, the feedback from the status reading module of the high-performance computing unit module is read. If the status is idle, the task sending module of the high-performance computing unit is triggered to send the task to the high-performance computing unit module. When an unauthorized signal is received, the task is sent to the basic computing unit, and the illegal request log storage module is triggered to work at the same time.

[0014] According to a processor provided by the present invention, the task scheduling arbitration FSM state machine includes the following working states: The system is in a receiving state, waiting for and receiving the authorization verification result and synchronized task data from the active defense arbitration unit. The scheduling status is determined by selecting the execution path based on the permission verification result. If the user has permission, the status of the high-performance computing unit module is queried and the module is scheduled. If the user does not have permission, the module is directly scheduled to the basic computing unit. Log status: Generates log records containing timestamps, user identification information, and request content for unauthorized requests.

[0015] The UUID generation module is configured to generate a 128-bit unique identifier based on timestamps and random numbers, which is used throughout the entire task processing flow. The computational efficiency of the basic computing unit is reduced by at least one order of magnitude compared to the high-performance computing unit module.

[0016] The present invention also provides a computing task processing method based on any one of the processors described in the present invention, comprising: The input request extraction and verification module of the active defense arbitration unit receives user requests, separates user identification information and instruction data, sends the user identification information to the authorization verification channel, and sends the instruction data to the data synchronization channel. After parsing the user identification information, the permission verification path performs a hash calculation to obtain the storage address. The user permission table is then read according to the storage address via MIG IP, and the permission recognition and confirmation module generates the permission verification result. The data synchronization path caches the instruction data, generates a unique UUID for the user request, and packages the UUID, instruction data, and user identification information into a synchronization data packet; When the permission verification result indicates that the user has permission and there is an idle unit in the high-performance computing unit module, the UUID and instruction data in the synchronization data packet are sent to the high-performance computing unit module for execution. When the permission verification result is no permission, the UUID and instruction data in the synchronization data packet are sent to the basic computing unit to perform iterative calculation; The illegal request log storage module receives the unauthorized signal from the task scheduling arbitration FSM state machine in the task scheduling unit, extracts the user identification information and request content from the synchronization data packet, generates a log record containing a timestamp, and writes it to the SD card. The calculation result output cache module receives the calculation results from the high-performance computing unit module or the basic computing unit, extracts the target UUID carried in the calculation result, and performs a matching verification between the target UUID and the UUID. After the matching verification is successful, the calculation result is written to the corresponding address in the processor's main memory according to the UUID mapping relationship.

[0017] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the computing task processing method described above.

[0018] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the computing task processing method as described above.

[0019] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the computing task processing method as described above.

[0020] The processor and computing task processing method provided by this invention, by setting up an independent active defense mechanism control module inside the high-performance processor, sinks the user permission verification and task scheduling functions originally undertaken by the host CPU to the hardware level. The active defense arbitration unit within this control module can perform permission verification and data preprocessing in parallel. The task scheduling unit schedules the computing tasks of authorized users to the high-performance computing unit module for execution based on the permission verification results, while scheduling the computing tasks of unauthorized users to the basic computing unit within the control module for execution. This hardware-level differentiated scheduling mechanism not only eliminates the permission management burden of the host CPU and the security vulnerabilities at the software level, but also avoids exposing the system security boundary and effectively consumes the time cost of potential attackers by providing "downgrade services" of the basic computing unit to unauthorized users instead of direct denial. At the same time, since permission verification, task scheduling and computing execution are all completed within the same processor, the system latency caused by cross-processor interaction is significantly reduced, thereby improving the overall processing efficiency while ensuring system security. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the processor structure provided by the present invention; Figure 2 The detailed architecture of the active defense mechanism control module kernel for the high-performance processor provided by this invention; Figure 3 The overall system application flow of the high-performance processor architecture with active defense architecture provided by this invention; Figure 4 The application flowchart of the active defense mechanism control module kernel of the high-performance processor provided by this invention; Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0024] Figure 1 This is a schematic diagram of the processor structure provided by the present invention, as shown below. Figure 1 As shown, it includes: Processor main memory; High-performance computing unit module, used to perform high-performance computing tasks; The active defense mechanism control module is connected to the processor main memory and the high-performance computing unit module respectively via an on-chip bus; The active defense mechanism control module includes: The proactive defense arbitration unit is configured to receive user requests and perform permission verification and data preprocessing in parallel based on the user requests. A task scheduling unit, connected to the proactive defense arbitration unit, is configured to perform differentiated task scheduling based on the permission verification result of the proactive defense arbitration unit. A basic computing unit, connected to the task scheduling unit, is configured to execute computing tasks for users without permissions; The calculation result output cache module is connected to the basic computing unit, the high-performance computing unit module and the processor main memory respectively, and is configured to aggregate the calculation results and write them to the processor main memory. The task scheduling unit is configured to: schedule computing tasks to the high-performance computing unit module for execution when the user has access permissions; and schedule computing tasks to the basic computing unit for execution when the user does not have access permissions.

[0025] In this application, the processor main memory is the main storage unit of the processor, used to store data to be processed, instructions, and calculation results.

[0026] The processor's main memory can be implemented using SRAM, eDRAM, or other high-speed storage media, and its storage capacity can be configured according to actual application needs, such as 16GB, 32GB, or larger. The processor's main memory interacts with other functional modules via an on-chip bus.

[0027] The high-performance computing unit (HPU) is the core computing power unit of the processor, responsible for executing various high-performance computing tasks. This unit can contain multiple parallel computing cores, such as GPU cores, TPU cores, DSP cores, or dedicated ASIC computing units. Each computing core can execute computing tasks independently or work together to complete complex parallel computations. The computing resources of the HPU are the processor's most valuable computing resources and require careful allocation and protection.

[0028] The active defense mechanism control module is connected to the processor's main memory and the high-performance computing unit module via an on-chip bus. The on-chip bus can be implemented using high-speed interconnect protocols such as AXI, ACE, and CHI to ensure high bandwidth and low latency data transmission.

[0029] The core function of the active defense mechanism control module is to sequentially receive all pending instructions and related pending data sent by users to the heterogeneous processors, determine whether the user ID of the current input request has the calling permission of the high-performance computing unit module through a series of complex mechanisms, and schedule the computing task to the corresponding computing unit according to the permission status.

[0030] In addition, this section also needs to verify and check task requests and related calculation results, and complete the real-time generation of request / illegal request logs for administrators to analyze and process later.

[0031] The active defense mechanism control module contains four main functional units: active defense arbitration unit, task scheduling unit, basic computing unit, and computing result output cache module.

[0032] The proactive defense arbitration unit, acting as the first line of defense in request processing, is configured to receive all computation requests sent by users sequentially. User requests can be various types of computational tasks, including matrix operation requests, neural network inference requests, image processing requests, etc.

[0033] The core function of the proactive defense arbitration unit is to execute two key operations in parallel: permission verification and data preprocessing. Permission verification authenticates the identity of the user initiating the request, determining whether the user has the right to access high-performance computing resources. Data preprocessing formats the computational instructions and data in the request, preparing them for subsequent task scheduling. The parallel execution of these two operations effectively reduces processing latency and improves system response speed.

[0034] The task scheduling unit is connected to the output of the proactive defense arbitration unit and is responsible for receiving the permission verification results and preprocessed task data. The core function of the task scheduling unit is to determine whether a task request is illegal based on the user's permission status and to schedule it to the appropriate computing unit.

[0035] Differentiated scheduling is the key innovation of this invention. Its working principle is as follows: When the task scheduling unit receives a signal indicating that the user has access rights, it schedules the user's computing task to the high-performance computing unit for execution, so that legitimate users can make full use of high-performance computing resources; when it receives a signal indicating that the user does not have access rights, the task scheduling unit will not simply refuse service, but will schedule the computing task to the basic computing unit for execution.

[0036] The basic computing unit is a dedicated computing module integrated within the active defense mechanism control panel, connected to the task scheduling unit. The basic computing unit is designed to execute computing tasks for unauthorized users, but its computing power is intentionally limited to a low level.

[0037] First, the basic computing unit avoids exposing system information that might be exposed by a direct denial of service; second, by providing inefficient computing services, it can consume the time and resources of potential attackers; and finally, it is difficult for attackers to determine whether their request has been identified as an illegal request based on the difference in response time or result.

[0038] The calculation result output cache module is a unified interface for result aggregation and output, connecting to the basic computing unit, the high-performance computing unit module, and the processor main memory.

[0039] The calculation result output caching module is responsible for verifying the UUID and the corresponding calculation result information, caching the calculation results from the basic calculation unit and the high-performance calculation unit, and then responding to the requesting user.

[0040] Regardless of whether the computation task is executed by the high-performance computing unit or the basic computing unit, the result will be processed uniformly by the computation result output cache module, which ensures the consistency of the external interface.

[0041] When a user requests access to the system, the proactive defense arbitration unit first receives and performs preliminary processing. Then, based on the authorization verification result, the task scheduling unit distributes the task to the corresponding computing unit. Finally, the computing result is returned to the user through the computing result output cache module. The entire process forms a complete security protection closed loop.

[0042] This embodiment implements a hardware-level security protection mechanism by setting up an independent active defense mechanism control module within the processor. This mechanism can effectively protect high-performance computing resources from unauthorized access, and at the same time, avoid the information leakage risk caused by simple denial-of-service attacks through differentiated scheduling strategies, significantly improving the security and reliability of the processor.

[0043] Optionally, the active defense arbitration unit is connected to an external memory, and the active defense arbitration unit includes: The input request extraction and verification module, as the request entry point, is configured to separate user identification information and instruction data in the user request; The permission verification path is connected to the input request extraction and verification module, which includes a user identification information parsing module, a hash algorithm encryption and decoding module, and a MIG IP and permission recognition and confirmation module connected in sequence. The user identification information parsing module is configured to perform number system conversion and format alignment on the extracted user identification information. The hash algorithm plus cryptographic decoding module is configured to use a specific cryptographic hash function to calculate the converted identity information and generate the physical address index of the user's permission table in the memory; The MIG IP is configured to read the user permission table from the memory according to the calculated address, and the permission recognition and confirmation module is configured to output the permission verification result to the task scheduling unit; The data synchronization path, connected to the input request extraction and verification module, includes an instruction data caching module, a UUID generation module, and a data synchronization module connected in sequence, and is configured to send the instruction data, UUID, and user identification information to the task scheduling unit after performing time-series synchronization. The instruction data cache module is configured to temporarily store the separated instructions and data to be processed. The UUID generation module is configured to generate a unique UUID for the user request based on the current clock cycle and a random seed; The data synchronization module is configured to receive the UUID, instruction data, and user identification information, and perform timing alignment operations. While waiting for the permission verification channel to output the permission determination signal, it maintains the integrity of the data packet and sends the synchronized data packet to the task scheduling unit.

[0044] The task scheduling unit is connected to an external SD card, and the task scheduling unit includes: The task scheduling arbitration FSM state machine is connected to the active defense arbitration unit and serves as the core control logic; A high-performance computing interface module connects the task scheduling arbitration FSM state machine with the high-performance computing unit module, and includes a high-performance computing unit module state reading module and a high-performance computing unit task sending module. The illegal request log storage module is connected to the task scheduling arbitration FSM state machine and is configured to generate log information and write it to the SD card when the user does not have access rights.

[0045] Figure 2 The detailed architecture of the active defense mechanism control module kernel for the high-performance processor provided by this invention is as follows: Figure 2 As shown, the active defense arbitration unit is connected to an external memory, which stores a user permission table containing key information such as the user identifier of all users, whether they have high-performance computing permissions, and the effective and expiration times of permissions.

[0046] The proactive defense arbitration unit consists of three main parts: an input request extraction and verification module, an authorization verification path, and a data synchronization path.

[0047] The input request extraction and verification module serves as the request entry point for the entire proactive defense arbitration unit, responsible for validating the user request format and extracting key information. User requests typically arrive in the form of data packets, consisting of a request header and a request body. The input request extraction and verification module first verifies the data packet format to confirm its integrity and legitimacy. Verification includes, but is not limited to, checking the data packet length, checksum matching, and protocol version support. After successful verification, the module extracts two types of key information from the request: user identification information and instruction data. User identification information can be a user ID, user token, digital certificate, or other information that uniquely identifies the user; instruction data includes specific calculation instructions (such as matrix multiplication instructions, convolution operation instructions, etc.) and data to be processed.

[0048] The authorization verification pathway connects to the input request extraction and verification module, and specifically processes user identification information. This pathway includes four sequentially connected functional modules: The user identifier identity information parsing module is the first module in the authorization verification path. It parses the requesting user ID information and preprocesses the extracted user identifier identity information. Since user identifiers from different sources may use different encoding formats (such as ASCII, UTF-8, Base64, etc.) and data formats (such as decimal, hexadecimal, binary, etc.), this module needs to perform unified number system conversion and format alignment operations. For example, it converts hexadecimal user IDs to binary format, or converts string-based IDs to fixed-length numeric representations. Format alignment ensures that subsequent processing modules can process user identifiers in a unified format.

[0049] The hash algorithm encryption and decoding module receives the formatted user identification information and is responsible for performing a specific encrypted hash function on the requesting user ID key to obtain the storage address of the permission information corresponding to the requesting user ID in the memory. The hash function can be SHA-256, SHA-512, MD5, or other cryptographically secure hash algorithms. The core function of this module is to map the user identifier to the physical address index of the permission table in memory. In specific implementation, the low bits of the hash value can be used as the address offset, or the address index can be obtained by performing a bitwise AND operation between the hash value and a preset mask. This hash-based address mapping method can achieve permission query with O(1) time complexity, which greatly improves the verification efficiency.

[0050] MIG IP (Memory Interface Generator IP) is an interface controller connecting on-chip logic and external memory, responsible for reading memory. This module initiates a read request to the memory based on the physical address index calculated by the hash algorithm and cryptographic decoding module. MIG IP supports burst transfer mode, enabling the reading of multiple consecutive data entries at once, improving memory access efficiency. The content read is the user's record in the permission table, including user permission level, access control list, permission activation and deactivation times, etc.

[0051] The permission identification and confirmation module receives the read user permission information and is responsible for determining whether the current requesting user ID has the permission to access the high-performance computing unit based on the "user permission table". The determination logic can be configured according to actual needs, such as: checking whether the user's permission level meets the minimum requirements for accessing the high-performance computing unit; verifying whether the current time is within the validity period of the user's permission (between the permission's effective and expiration time); confirming whether the user's access attempts have exceeded the limit, etc. The permission identification and confirmation module finally outputs a boolean type permission verification result (permission granted / no permission) and sends the result to the task scheduling unit.

[0052] The data synchronization path and the authorization verification path operate in parallel, responsible for processing instruction data. This path includes three functional modules: The instruction data caching module is responsible for temporarily storing the instructions and data to be processed separated from the input request extraction and verification module. It caches the calculation instructions and data requested by the user. The cache uses a FIFO (First-In, First-Out) structure to ensure data order. The cache depth can be configured according to system latency and throughput requirements, typically ranging from 16 to 64 entries.

[0053] The UUID generation module generates a globally unique identifier for each user request, used to generate a unique task ID (UUID) corresponding to that request task, to meet the requirements of full-process task tracking. The generation of the UUID (Universally Unique Identifier) ​​is based on the current clock cycle and a random seed provided by the hardware random number generator. Specifically, the implementation can adopt the UUID version 4 standard to generate a 128-bit random identifier. The UUID serves as the unique identifier for the task throughout the entire task processing flow, used for task tracking, result matching, and security auditing.

[0054] The data synchronization module is the last module in the data synchronization path. It is responsible for synchronizing information such as instructions, data, UUIDs, and requesting user IDs, eliminating interference caused by timing issues. This module receives UUIDs, instruction data, and user identification information, assembling them into a complete synchronization data packet. Crucially, the data synchronization module needs to wait for the authorization verification path to complete verification and output an authorization determination signal, ensuring that the authorization verification result and task data arrive at the task scheduling unit synchronously. This timing alignment mechanism avoids race conditions and guarantees the correctness of the system.

[0055] This embodiment achieves efficient permission verification and data preprocessing mechanisms through detailed design of the internal structure of the proactive defense arbitration unit. The parallel dual-path design fully utilizes hardware parallelism and reduces processing latency; the hash-based permission query mechanism ensures high efficiency in verification; and the timing synchronization mechanism ensures the correctness and stability of the system.

[0056] More specifically, the task scheduling unit is connected to an external SD card, which is used to store request / illegal request logs for subsequent analysis and processing by the administrator.

[0057] The core of the task scheduling unit is the task scheduling arbitration FSM (Finite State Machine) state machine, which serves as the control center for the entire scheduling logic. The task scheduling arbitration FSM state machine receives the permission verification results and synchronization data packets from the proactive defense arbitration unit, determines whether a request is illegal based on the user's permission status, and schedules it to the appropriate computing unit. Furthermore, the task scheduling arbitration FSM state machine also needs to generate request / illegal request logs.

[0058] The high-performance computing interface module connects the task scheduling arbitration FSM state machine and the high-performance computing unit module, and is responsible for managing the interaction with high-performance computing resources. This module contains two sub-modules: The high-performance computing unit (HPC) module is responsible for reading the real-time idle status of the HPCs within the module. This module uses a dedicated status query interface to periodically or on-demand read operational parameters such as busy / idle status, queue depth, and temperature information for each computing unit. Status information can be granular down to the individual computing core or represent the overall status of the entire module. The read status information is fed back to the Task Scheduling Arbitration (FSM) state machine, serving as a crucial basis for scheduling decisions.

[0059] The high-performance computing unit (HPU) task sending module is responsible for sending requests and pending data to the HPU module. When the FSM state machine decides to schedule a task to the HPU, this module sends the UUID, instructions, and pending data from the synchronization data packet out via a high-speed interface. The sending process may involve data format conversion, protocol encapsulation, and other operations to ensure that the data can be correctly received and processed by the HPU.

[0060] The illegal request log storage module is connected to the output of the Task Scheduling Arbitration (FSM) state machine and is responsible for uploading logs to the SD card for storage. This module is triggered when the FSM state machine determines that a user lacks access rights. The illegal request log storage module extracts key information such as user identification, request content, and request time from the synchronization data packets to generate structured log records. The log format can be JSON, XML, or a custom binary format, including fields such as timestamp, user ID, request type, and reason for rejection.

[0061] The generated logs are written to an external SD card via the SD card interface controller for persistent storage, facilitating subsequent analysis and processing by the administrator. The SD card was chosen for its large capacity, low cost, and ease of replacement, making it suitable for storing large amounts of security log data.

[0062] The FSM state machine selects different execution paths based on the permission verification result. When permission is granted, it interacts with the outside world through the high-performance computing interface module. When permission is denied, it triggers log recording and forwards the task to the basic computing unit.

[0063] This embodiment implements an intelligent task distribution mechanism through a well-designed task scheduling unit. The FSM state machine provides clear control logic; the high-performance computing interface module enables efficient interaction with external computing resources; and the illegal request log storage module provides complete security auditing functions. The three work together to ensure the system's efficiency and security.

[0064] Figure 3The overall system application flow of the high-performance processor architecture with active defense architecture provided by this invention is as follows: Figure 3 As shown, the user sends a request to the host for heterogeneous processor computing or data processing applications. The host CPU receives the current request instruction and the data to be processed, and then sends the instruction and the data to be processed to the main memory of the high-performance processor with an active defense architecture via the PCIe interface in the form of DMA. The active defense mechanism control module of the high-performance processor with active defense architecture uses a series of complex mechanisms to determine whether the user ID of the current input request has the calling authority of the high-performance computing unit module. If the user ID of the current input request does not have the calling permission of the high-performance computing unit module, the task scheduling unit will directly send the task to the basic computing unit to perform low-efficiency conventional iterative computing; otherwise, the task scheduling unit will send the task to an idle computing unit in the high-performance computing unit module to perform high-performance computing. After the high-performance / basic computing unit completes the corresponding calculation, the active defense mechanism control module checks and verifies the task request and related calculation results. Once confirmed to be correct, the calculation results are stored in the corresponding storage partition of the processor's main memory. The calculation results are then mapped to the corresponding memory storage partition on the host machine via the PCIe interface in the form of DMA. The high-performance heterogeneous processor with active defense architecture informs the host machine that "the calculation is complete". The CPU merges the currently received calculation results, performs a second check on the results, and sends the results to the corresponding requesting user ID terminal after confirming that the calculation is correct. Optionally, the basic computing unit integrates underlying computing resources such as ALU, FPU, SFU, and LSU. The basic computing unit is configured to: upon receiving an unauthorized task instruction distributed by the task scheduling unit, invoke the underlying computing resources to perform iterative calculations, and send the results of the iterative calculations to the calculation result output cache module.

[0065] In this application, the basic computing unit is an independent computing module within the active defense mechanism control module.

[0066] The basic computing unit integrates four underlying computing resources: ALU (Arithmetic Logic Unit), FPU (Floating Point Unit), SFU (Special Function Unit), and LSU (Load Store Unit).

[0067] The ALU is responsible for performing basic arithmetic operations (addition, subtraction, multiplication, and division) and logical operations (AND, OR, NOT, and XOR). The ALU can handle integer operations and supports various data widths, including 8-bit, 16-bit, 32-bit, and 64-bit. In basic computing units, the number and performance of ALUs are intentionally limited; for example, only 2-4 ALUs are configured, and their operating frequency is relatively low.

[0068] The FPU is specifically designed for floating-point arithmetic, supporting both single-precision (32-bit) and double-precision (64-bit) floating-point operations. The FPU can perform floating-point addition, subtraction, multiplication, division, square roots, trigonometric functions, and other operations. The number of FPUs in the basic computing unit is also limited, and some advanced floating-point instructions may not be supported.

[0069] SFUs are used to perform special mathematical function operations, such as transcendental functions (sin, cos, exp, log, etc.), reciprocals, and reciprocals of square roots. These operations are frequently used in scientific computing and graphics processing. The SFU functionality in basic computational units may be simplified, supporting only basic special functions.

[0070] The LSU (Load Unit) is responsible for data loading and storage operations, managing data transfer between the computing unit and the storage system. The LSU comprises loading and storage units and supports different addressing modes and data alignment methods. Within the basic computing unit, the bandwidth and concurrency capabilities of the LSU are limited.

[0071] When the basic computing unit receives an unauthorized task instruction from the task scheduling unit, it initiates an iterative computation process. Iterative computation refers to completing a computation task by repeatedly calling underlying computing resources. For example, for a matrix multiplication task, the basic computing unit cannot process multiple matrix elements in parallel like a high-performance computing unit; instead, it needs to compute each element sequentially, and the computation of each element requires multiple calls to the ALU or FPU. This iterative approach intentionally reduces computational efficiency; a task that would take only a few milliseconds on a high-performance computing unit may take several seconds or even longer on a basic computing unit.

[0072] The results of iterative computation are similar in form to those of high-performance computing, both fulfilling the user-requested computation task. However, the basic computing unit may embed special markers or employ slightly different numerical precision in the results for subsequent security analysis. After computation, the basic computing unit sends the results, along with the task's UUID, to the computation result output cache module.

[0073] This embodiment provides a degraded service for unauthorized users by integrating a limited-function basic computing unit within the active defense mechanism control module. This design avoids the security risks associated with direct denial of service, effectively protects high-performance computing resources from abuse, and consumes the resources of potential attackers through inefficient iterative computation, thus achieving multi-layered security protection.

[0074] Optionally, the active defense mechanism control module further includes a high-performance computing task result receiving module, which is connected between the high-performance computing unit module and the computing result output cache module; The calculation result output caching module is configured to: use the task's UUID to verify the source of the received calculation result; after the verification is successful, map the result and write it into the processor's main memory.

[0075] In this application, the active defense mechanism control module also includes a high-performance computing task result receiving module, which is connected between the high-performance computing unit module and the computing result output cache module, and is responsible for receiving the computing results of the high-performance computing unit module.

[0076] The high-performance computing task result receiving module is responsible for receiving computation results from the high-performance computing unit module. After completing the task, the high-performance computing unit module returns the result data along with the task UUID. The format of the result data depends on the specific computation type and may be a scalar, vector, matrix, or more complex data structure. The high-performance computing task result receiving module needs to correctly parse these data formats and perform necessary format conversions.

[0077] The calculation result output caching module is the core module for result processing. It is responsible for verifying the UUID and the corresponding calculation result information, caching the calculation results from the basic computing unit and the high-performance computing unit, and then responding to the requesting user. This module receives calculation results from two different sources: high-performance computing results transmitted through the high-performance computing task result receiving module, and calculation results directly from the basic computing unit.

[0078] The UUID verification process is as follows: the calculation result output caching module maintains a UUID lookup table, recording the UUIDs of all currently processed tasks. When a calculation result is received, the module extracts the UUID carried in the result and matches it against the lookup table. If a matching UUID is found, it means that the result corresponds to a valid task request; if no match is found, it may indicate that the result has been tampered with or that a system anomaly has occurred.

[0079] UUID verification not only validates the validity of the results but also prevents misaligned or duplicate submissions. This verification mechanism is a crucial step in verifying and confirming task requests and related calculation results.

[0080] After successful verification, the calculation result output caching module performs mapping processing on the result based on the metadata associated with the UUID (such as the address information of the original request, data format requirements, etc.). The mapping includes operations such as address translation (converting the logical address of the task to the physical address of the processor's main memory), data format conversion (such as endianness conversion, data type conversion, etc.), and result encapsulation (adding necessary metadata or tags).

[0081] Finally, the processed result is written to a designated location in the processor's main memory, and then sent back to the requesting user. The write operation may use direct memory access to reduce CPU involvement and improve transfer efficiency. After the write is complete, the calculation result output cache module may send a completion notification or interrupt signal to notify the upper-layer application that the result is ready.

[0082] This embodiment manages computation results from different execution paths in a unified manner by setting up a dedicated result receiving and processing module. The UUID verification mechanism ensures the integrity and correctness of the results, and the mapping process guarantees that the results can be correctly returned to the request initiator. The entire mechanism improves the reliability and security of the system.

[0083] Optionally, the hash algorithm encryption and decoding module is configured to: use an encrypted hash function to calculate the user's identity information and generate the physical address offset of the user's permission table in the memory; The permission verification path and the data synchronization path work in parallel, and the data synchronization module is configured to ensure that the permission verification result and the task data arrive at the task scheduling unit synchronously.

[0084] In this application, the hash algorithm plus cryptographic decoding module uses a cryptographic hash function to calculate the user's identity information. The choice of cryptographic hash function needs to consider a balance between security and efficiency. Commonly used hash functions include SHA-256, SHA-512, MD5, and BLAKE2. Among them, SHA-256 provides a 256-bit hash output, offering good security and moderate computational complexity; while MD5 is no longer cryptographically secure, it can still be used in non-security-critical scenarios due to its efficiency; BLAKE2 is a new generation hash function that provides better performance while maintaining high security.

[0085] First, the user identification information is padded to meet the input requirements of the hash function. Then, the padded data is divided into blocks, and each block is sequentially input into the hash function's compression function. Finally, the processing results of all blocks are merged to obtain the final hash value. The generated hash value is used as the physical address offset of the user's permission table in memory. This is precisely the implementation of the hash algorithm encryption and decoding module, which performs a specific encrypted hash function calculation on the requesting user ID key to obtain the storage address of the permission information corresponding to that requesting user ID in memory.

[0086] Address mapping can be implemented in several ways. Direct mapping uses the low-order bits of the hash value as the address offset. Modulo mapping uses the hash value modulo the size of the permission table to ensure that the address does not go out of bounds. Segmented mapping divides the hash value into multiple segments, each corresponding to a different region of the permission table. This hash-based address mapping avoids linear search and achieves permission lookup with O(1) time complexity.

[0087] The parallel operation mechanism of the authorization verification path and the data synchronization path is the key design of this invention to improve processing efficiency.

[0088] After obtaining the necessary data from the input request extraction and verification module, the two pathways immediately begin parallel processing. The permission verification pathway performs user authentication, including ID parsing, hash calculation, storage access, and permission determination; simultaneously, the data synchronization pathway performs data preparation, including instruction caching, UUID generation, and data packaging.

[0089] The data synchronization module plays a crucial coordinating role in parallel processing, ensuring that the authorization verification results and task data arrive at the task scheduling unit synchronously. This module contains a synchronization barrier responsible for synchronizing instructions, data, UUIDs, request user IDs, and other information, eliminating interference caused by timing issues.

[0090] In practice, the data synchronization module may include two input ports and corresponding handshake signals: one port waits for the completion signal and authorization result of the authorization verification path, and the other port receives the completion signal and data packet of data preparation. Only when both ports receive valid signals will the data synchronization module send the merged information to the task scheduling unit.

[0091] The advantages of this parallel processing mechanism are that it makes full use of hardware resources, and permission verification and data preparation are carried out simultaneously, reducing the overall processing time; the modular design allows each path to be optimized independently, improving the maintainability of the system; and the synchronization mechanism ensures data consistency and avoids race conditions and data corruption.

[0092] This embodiment significantly improves the processing efficiency of the proactive defense arbitration unit by optimizing the implementation of the hash algorithm and the parallel processing mechanism. The fast permission lookup based on hashing and the parallel dual-path processing enable the system to minimize the performance impact on normal computing tasks while ensuring security.

[0093] Optionally, the scheduling logic of the task scheduling arbitration FSM state machine is as follows: When an authorization signal is received, the feedback from the status reading module of the high-performance computing unit module is read. If the status is idle, the task sending module of the high-performance computing unit is triggered to send the task to the high-performance computing unit module. When an unauthorized signal is received, the task is sent to the basic computing unit, and the illegal request log storage module is triggered to work at the same time.

[0094] The task scheduling arbitration FSM state machine includes the following working states: The system is in a receiving state, waiting for and receiving the authorization verification result and synchronized task data from the active defense arbitration unit. The scheduling status is determined by selecting the execution path based on the permission verification result. If the user has permission, the status of the high-performance computing unit module is queried and the module is scheduled. If the user does not have permission, the module is directly scheduled to the basic computing unit. Log status: Generates log records containing timestamps, user identification information, and request content for unauthorized requests.

[0095] The Task Scheduling Arbitration FSM state machine contains three main working states: Receive state (waiting for and receiving the permission verification result and synchronized task data from the active defense arbitration unit), Scheduling state (selecting the execution path based on the permission verification result), and Log state (generating log records containing timestamps, user identification information, and request content for unauthorized requests).

[0096] In this application, during the scheduling state, the scheduling logic of the FSM state machine is divided into two execution branches based on the received permission signals: When an authorization signal is received, the FSM first reads the feedback from the high-performance computing unit (HMU) module's status reading module to obtain the real-time idle status of the computing unit. If the status is idle, the HMU task sending module is triggered to send tasks to the HMU module.

[0097] When an unauthorized signal is received, the FSM sends the task to the basic computing unit and simultaneously triggers the illegal request log storage module. The task scheduling arbitration FSM state machine generates request / illegal request logs, which include key information such as timestamps, user identification information, and request content. The illegal request log storage module uploads these logs to the SD card for storage.

[0098] This embodiment achieves precise task distribution control and complete security auditing functions by explicitly defining the scheduling logic and state transitions of the FSM state machine.

[0099] Optionally, the UUID generation module is configured to generate a 128-bit unique identifier based on a timestamp and a random number, which is used throughout the entire task processing flow; The computational efficiency of the basic computing unit is reduced by at least one order of magnitude compared to the high-performance computing unit module.

[0100] In this application, the UUID generation module is configured to generate a 128-bit unique identifier based on a timestamp and a random number, which is used throughout the entire task processing flow. The timestamp records the precise time when the UUID is generated, and the random number is provided by a hardware random number generator, ensuring global uniqueness. The generated UUID is used for full-process task tracking, result matching, and security auditing.

[0101] The computational efficiency of the basic computing unit is at least an order of magnitude lower than that of the high-performance computing unit. This performance difference is reflected in: computational throughput being limited to less than 10% of that of the high-performance computing unit; significantly reduced parallelism; significantly lower clock frequency; limited memory bandwidth; and simplified instruction set functionality. This design ensures that legitimate users obtain full performance, while illegitimate users, although they can obtain computational results, do so at extremely low efficiency, effectively protecting system resources.

[0102] This embodiment enhances the system's security and resource protection capabilities through the UUID mechanism and performance differentiation design.

[0103] In one alternative embodiment, Figure 4 The application flowchart of the active defense mechanism control module kernel of the high-performance processor provided by this invention is as follows: Figure 4 As shown, it includes: The processor active defense mechanism control module receives the user's processor calculation request. The input request extraction and verification module receives the request and performs preliminary format verification on the request (checking whether it contains necessary fields such as user identifier). Then, it extracts the request user identifier ID, calculation instructions and corresponding data to be processed from the request. The user ID parsing module receives the extracted request user ID, performs format and base conversion on the ID, and then the hash algorithm and cryptographic decoding module performs a specific encrypted hash function on the request user ID keyword to obtain the storage address of the permission information corresponding to the request user ID in the memory; the MIG IP reads the corresponding storage address in the memory and sends the permission reading result to the permission recognition and confirmation module. The instruction and data caching module caches the calculation instructions and data to be processed requested by the user, respectively. After caching is completed, the UUID generation module generates a unique task ID (UUID) corresponding to the request task for full-process task tracking. Subsequently, the data synchronization module synchronizes the instructions, data, UUID, request user ID and other information and sends them to the task arbitration FSM state machine. The permission identification and confirmation module determines whether the current requesting user ID has the permission to call the high-performance computing unit module based on the read "user permission table" (which adopts a hash structure and includes user identifier, whether the user has high-performance computing permission, permission effective and expiration time, etc.). (No permission includes situations such as "explicitly marked as not allowed", "no user record found", "permission expired", etc.) and sends the check result to the task arbitration FSM state machine. The Task Scheduling Arbitration (FSM) state machine determines whether a task request is illegal based on the user's permissions and schedules it to the appropriate computing unit (basic computing unit / high-performance computing unit). If it is an illegal request, the corresponding illegal request log must also be updated. The FSM consists of three steps: S0, receiving instructions, data, UUID, requesting user ID, and whether the user has access permissions; S1, if the current request has access permissions to the high-performance computing unit, the high-performance computing unit module reads the real-time idle status of the high-performance computing unit in the module and sends the current computing UUID, instructions, and corresponding pending data to the high-performance computing unit module via the high-performance computing unit task sending module. If the current request does not have access permissions to the high-performance computing unit, the current computing UUID, instructions, and corresponding pending data are directly sent to the basic computing unit for computation; S2, generating request / illegal request logs and calling the illegal request log storage module to upload the logs to the SD card for storage, so that the processor administrator can access them in real time later. After the computation task is completed, the basic computing unit directly transmits the UUID and the corresponding computation result to the computation result output cache module; while the computation result of the high-performance computing unit is received by the high-performance computing task result receiving module and then sent to the computation result output cache module for temporary storage. The calculation result output caching module re-verifies the UUID and the corresponding calculation result information. After ensuring that there are no errors, it stores the calculation results in the corresponding storage partitions of the processor's main memory in sequence, and then responds to the requesting user. Optionally, the computational task processing method in this application includes: The input request extraction and verification module of the active defense arbitration unit receives user requests, separates user identification information and instruction data, sends the user identification information to the authorization verification channel, and sends the instruction data to the data synchronization channel. After parsing the user identification information, the permission verification path performs a hash calculation to obtain the storage address. The user permission table is then read according to the storage address via MIG IP, and the permission recognition and confirmation module generates the permission verification result. The data synchronization path caches the instruction data, generates a unique UUID for the user request, and packages the UUID, instruction data, and user identification information into a synchronization data packet; When the permission verification result indicates that the user has permission and there is an idle unit in the high-performance computing unit module, the UUID and instruction data in the synchronization data packet are sent to the high-performance computing unit module for execution. When the permission verification result is no permission, the UUID and instruction data in the synchronization data packet are sent to the basic computing unit to perform iterative calculation; The illegal request log storage module receives the unauthorized signal from the task scheduling arbitration FSM state machine in the task scheduling unit, extracts the user identification information and request content from the synchronization data packet, generates a log record containing a timestamp, and writes it to the SD card. The calculation result output cache module receives the calculation results from the high-performance computing unit module or the basic computing unit, extracts the target UUID carried in the calculation result, and performs a matching verification between the target UUID and the UUID. After the matching verification is successful, the calculation result is written to the corresponding address in the processor's main memory according to the UUID mapping relationship.

[0104] In this application, firstly, the input request extraction and verification module of the active defense arbitration unit sequentially receives all user requests, performs user request format verification, and extracts key information. User requests may come from multiple channels: network interface, local application programming interface, command line interface, etc. Requests are encapsulated in a specific protocol format, including a request header and a request body. The input request extraction and verification module parses the request packet, performs format and integrity verification, and then separates two key parts: user identification information and instruction data. The user identification information is sent to the entry point of the authorization verification path, and the instruction data is sent to the entry point of the data synchronization path. This separation allows the two paths to process their respective tasks in parallel.

[0105] Secondly, the authorization verification process begins processing user identification information. The user ID parsing module parses the requesting user ID information and performs format standardization processing on the identification information, including character encoding conversion, number system conversion, and length alignment. The processed standardized ID is then sent to the hash algorithm and cryptographic decoding module, where a specific encrypted hash function is executed to calculate the storage address in memory for the authorization information corresponding to the requesting user ID.

[0106] A hash function (such as SHA-256) converts a variable-length user ID into a fixed-length hash value. A portion of the hash value (such as the lower 32 bits) serves as the offset of the storage address. The MIG IP is responsible for reading from the memory and initiating a read request based on this address. The memory stores a user permission table containing key information such as the user identifiers of all users, whether they have high-performance computing permissions, and the effective and expiration times of their permissions. After reading the data at the corresponding address, the MIG IP passes it to the permission identification and confirmation module. This module determines whether the requesting user ID has the permission to call the high-performance computing unit based on the "user permission table," and finally generates a boolean-type permission verification result.

[0107] Simultaneously with permission verification, data synchronization is processed. The instruction data caching module caches the computation instructions and pending data of the user request, maintaining their original format for subsequent processing. The UUID generation module generates a unique task ID (UUID) corresponding to the requested task to meet the requirements of full-process task tracking. The UUID generation algorithm ensures global uniqueness: extracting the current system timestamp as the time part of the UUID; obtaining a random number from the hardware random number generator as the random part of the UUID; and optionally adding a node identifier to further guarantee uniqueness.

[0108] The generated UUID, along with the command data and user identification information, is sent to the data synchronization module. The data synchronization module synchronizes the commands, data, UUID, requesting user ID, and other information, removing interference caused by timing issues, and packages all information into a synchronization data packet.

[0109] Next, the Task Scheduling Arbitration (FSM) state machine determines whether the request is illegitimate based on the user's permissions and performs differentiated scheduling. When the permission verification result indicates that the user has the necessary permissions, the FSM state machine first queries the status of the high-performance computing unit module.

[0110] The high-performance computing unit status reading module reads the real-time idle status of the high-performance computing units.

[0111] If an idle computing unit exists, the FSM state machine extracts the UUID and instruction data from the synchronization data packet and sends the request and pending data to the high-performance computing unit module through the high-performance computing unit task sending module.

[0112] When the permission verification result is "no permission," the FSM state machine executes a different process. It directly sends the UUID and instruction data from the synchronization data packet to the basic computing unit. After receiving the task, the basic computing unit begins iterative computation. The iterative computation deliberately uses inefficient algorithms and limited resources, significantly extending the computation time.

[0113] Meanwhile, the task scheduling arbitration FSM state machine generates request / illegal request logs, triggering the illegal request log storage module. This module extracts user identification information and request content, adds the current timestamp, and generates structured log records.

[0114] The illegal request log storage module uploads the logs to the SD card for storage, so that the administrator can analyze and process them later.

[0115] Finally, the calculation result output caching module is responsible for receiving and verifying the results. It may receive results from two sources: the high-performance computing task result receiving module receives the calculation results from the high-performance computing unit module, or the results directly returned by the basic computing unit.

[0116] Regardless of the source, the result carries a corresponding UUID (target UUID). The calculation result output caching module verifies the UUID and the corresponding calculation result information, extracts the target UUID, and matches and verifies it with the original UUID generated when the task was created.

[0117] The matching process includes: integrity verification, confirming that all bits of the UUID match; timing verification, confirming that the return time of the result is reasonable; and anti-replay verification, confirming that the result corresponding to the UUID has not been processed.

[0118] After the matching verification passes, the module determines the processor's main memory address where the result should be written based on the UUID mapping relationship, writes the calculation result to the corresponding address in the processor's main memory, and then responds to the requesting user. The write operation may involve: address mapping, converting logical addresses to physical addresses; data format conversion, ensuring that the data format meets the requirements of main memory; and atomic writing, ensuring the atomicity and consistency of data writing.

[0119] In this application, the entire processing flow forms a complete closed loop, from request reception, permission verification, task scheduling, computation execution to result return. Each step has a clear functional positioning and interface definition, ensuring the modularity and maintainability of the system. The entire process realizes the verification and validation of task requests and related computation results, and completes the real-time generation of request / illegal request logs. Through this carefully designed processing flow, the system achieves a balance between efficient normal service and effective security protection.

[0120] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 5As shown, the electronic device may include: a processor 510, a communications interface 520, a memory 530, and a communication bus 540, wherein the processor 510, the communications interface 520, and the memory 530 communicate with each other through the communication bus 540. The processor 510 can call logical instructions in the memory 530 to execute a computational task processing method, which includes: the input request extraction and verification module of the active defense arbitration unit receiving a user request, separating user identification information and instruction data, sending the user identification information to the authorization verification path, and sending the instruction data to the data synchronization path; After parsing the user identification information, the permission verification path performs a hash calculation to obtain the storage address. The user permission table is then read according to the storage address via MIG IP, and the permission recognition and confirmation module generates the permission verification result. The data synchronization path caches the instruction data, generates a unique UUID for the user request, and packages the UUID, instruction data, and user identification information into a synchronization data packet; When the permission verification result indicates that the user has permission and there is an idle unit in the high-performance computing unit module, the UUID and instruction data in the synchronization data packet are sent to the high-performance computing unit module for execution. When the permission verification result is no permission, the UUID and instruction data in the synchronization data packet are sent to the basic computing unit to perform iterative calculation; The illegal request log storage module receives the unauthorized signal from the task scheduling arbitration FSM state machine in the task scheduling unit, extracts the user identification information and request content from the synchronization data packet, generates a log record containing a timestamp, and writes it to the SD card. The calculation result output cache module receives the calculation results from the high-performance computing unit module or the basic computing unit, extracts the target UUID carried in the calculation result, and performs a matching verification between the target UUID and the UUID. After the matching verification is successful, the calculation result is written to the corresponding address in the processor's main memory according to the UUID mapping relationship.

[0121] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0122] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being able to be stored on a non-transitory computer-readable storage medium, the computer program being executed by a processor, the computer being able to execute the computational task processing method provided by the above methods, the method including: the input request extraction and verification module of the active defense arbitration unit receiving a user request, separating user identification information and instruction data, sending the user identification information to the authorization verification path, and sending the instruction data to the data synchronization path; After parsing the user identification information, the permission verification path performs a hash calculation to obtain the storage address. The user permission table is then read according to the storage address via MIG IP, and the permission recognition and confirmation module generates the permission verification result. The data synchronization path caches the instruction data, generates a unique UUID for the user request, and packages the UUID, instruction data, and user identification information into a synchronization data packet; When the permission verification result indicates that the user has permission and there is an idle unit in the high-performance computing unit module, the UUID and instruction data in the synchronization data packet are sent to the high-performance computing unit module for execution. When the permission verification result is no permission, the UUID and instruction data in the synchronization data packet are sent to the basic computing unit to perform iterative calculation; The illegal request log storage module receives the unauthorized signal from the task scheduling arbitration FSM state machine in the task scheduling unit, extracts the user identification information and request content from the synchronization data packet, generates a log record containing a timestamp, and writes it to the SD card. The calculation result output cache module receives the calculation results from the high-performance computing unit module or the basic computing unit, extracts the target UUID carried in the calculation result, and performs a matching verification between the target UUID and the UUID. After the matching verification is successful, the calculation result is written to the corresponding address in the processor's main memory according to the UUID mapping relationship.

[0123] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it implements a computational task processing method provided by the above methods. The method includes: an input request extraction and verification module of an active defense arbitration unit receiving a user request, separating user identification information and instruction data, sending the user identification information to an authorization verification path, and sending the instruction data to a data synchronization path. After parsing the user identification information, the permission verification path performs a hash calculation to obtain the storage address. The user permission table is then read according to the storage address via MIG IP, and the permission recognition and confirmation module generates the permission verification result. The data synchronization path caches the instruction data, generates a unique UUID for the user request, and packages the UUID, instruction data, and user identification information into a synchronization data packet; When the permission verification result indicates that the user has permission and there is an idle unit in the high-performance computing unit module, the UUID and instruction data in the synchronization data packet are sent to the high-performance computing unit module for execution. When the permission verification result is no permission, the UUID and instruction data in the synchronization data packet are sent to the basic computing unit to perform iterative calculation; The illegal request log storage module receives the unauthorized signal from the task scheduling arbitration FSM state machine in the task scheduling unit, extracts the user identification information and request content from the synchronization data packet, generates a log record containing a timestamp, and writes it to the SD card. The calculation result output cache module receives the calculation results from the high-performance computing unit module or the basic computing unit, extracts the target UUID carried in the calculation result, and performs a matching verification between the target UUID and the UUID. After the matching verification is successful, the calculation result is written to the corresponding address in the processor's main memory according to the UUID mapping relationship.

[0124] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0125] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A processor, characterized in that, include: Processor main memory; High-performance computing unit module, used to perform high-performance computing tasks; The active defense mechanism control module is connected to the processor main memory and the high-performance computing unit module respectively via an on-chip bus; The active defense mechanism control module includes: The proactive defense arbitration unit is configured to receive user requests and perform permission verification and data preprocessing in parallel based on the user requests. A task scheduling unit, connected to the proactive defense arbitration unit, is configured to perform differentiated task scheduling based on the permission verification result of the proactive defense arbitration unit. A basic computing unit, connected to the task scheduling unit, is configured to execute computing tasks for users without permissions; The calculation result output cache module is connected to the basic computing unit, the high-performance computing unit module and the processor main memory respectively, and is configured to aggregate the calculation results and write them to the processor main memory. The task scheduling unit is configured to: schedule computing tasks to the high-performance computing unit module for execution when the user has access permissions; and schedule computing tasks to the basic computing unit for execution when the user does not have access permissions.

2. The processor according to claim 1, characterized in that, The active defense arbitration unit is connected to an external memory, and the active defense arbitration unit includes: The input request extraction and verification module, as the request entry point, is configured to separate user identification information and instruction data in the user request; The permission verification path is connected to the input request extraction and verification module, which includes a user identification information parsing module, a hash algorithm encryption and decoding module, and a MIG IP and permission recognition and confirmation module connected in sequence. The user identification information parsing module is configured to perform number system conversion and format alignment on the extracted user identification information. The hash algorithm plus cryptographic decoding module is configured to use a specific cryptographic hash function to calculate the converted identity information and generate the physical address index of the user's permission table in the memory; The MIG IP is configured to read the user permission table from the memory according to the calculated address, and the permission recognition and confirmation module is configured to output the permission verification result to the task scheduling unit; The data synchronization path, connected to the input request extraction and verification module, includes an instruction data caching module, a UUID generation module, and a data synchronization module connected in sequence, and is configured to send the instruction data, UUID, and user identification information to the task scheduling unit after performing time-series synchronization. The instruction data cache module is configured to temporarily store the separated instructions and data to be processed. The UUID generation module is configured to generate a unique UUID for the user request based on the current clock cycle and a random seed; The data synchronization module is configured to receive the UUID, instruction data, and user identification information, and perform timing alignment operations. While waiting for the permission verification channel to output the permission determination signal, it maintains the integrity of the data packet and sends the synchronized data packet to the task scheduling unit.

3. The processor according to claim 1, characterized in that, The task scheduling unit is connected to an external SD card, and the task scheduling unit includes: The task scheduling arbitration FSM state machine is connected to the active defense arbitration unit and serves as the core control logic; A high-performance computing interface module connects the task scheduling arbitration FSM state machine with the high-performance computing unit module, and includes a high-performance computing unit module state reading module and a high-performance computing unit task sending module. The illegal request log storage module is connected to the task scheduling arbitration FSM state machine and is configured to generate log information and write it to the SD card when the user does not have access rights.

4. The processor according to claim 1, characterized in that, The basic computing unit integrates ALU, FPU, SFU and LSU underlying computing resources; The basic computing unit is configured to: upon receiving an unauthorized task instruction distributed by the task scheduling unit, invoke the underlying computing resources to perform iterative calculations and send the results of the iterative calculations to the calculation result output cache module.

5. The processor according to claim 1, characterized in that, The active defense mechanism control module also includes a high-performance computing task result receiving module, which is connected between the high-performance computing unit module and the computing result output cache module; The calculation result output caching module is configured to: use the task's UUID to verify the source of the received calculation result; after the verification is successful, map the result and write it into the processor's main memory.

6. The processor according to claim 2, characterized in that, The hash algorithm encryption and decoding module is configured to: use an encrypted hash function to calculate the user's identity information and generate the physical address offset of the user's permission table in the memory; The permission verification path and the data synchronization path work in parallel, and the data synchronization module is configured to ensure that the permission verification result and the task data arrive at the task scheduling unit synchronously.

7. The processor according to claim 3, characterized in that, The scheduling logic of the task scheduling arbitration FSM state machine is as follows: When an authorization signal is received, the feedback from the status reading module of the high-performance computing unit module is read. If the status is idle, the task sending module of the high-performance computing unit is triggered to send the task to the high-performance computing unit module. When an unauthorized signal is received, the task is sent to the basic computing unit, and the illegal request log storage module is triggered to work at the same time.

8. The processor according to claim 3, characterized in that, The task scheduling arbitration FSM state machine includes the following working states: The system is in a receiving state, waiting for and receiving the authorization verification result and synchronized task data from the active defense arbitration unit. The scheduling status is determined by selecting the execution path based on the permission verification result. If the user has permission, the status of the high-performance computing unit module is queried and the module is scheduled. If the user does not have permission, the module is directly scheduled to the basic computing unit. Log status: Generates log records containing timestamps, user identification information, and request content for unauthorized requests.

9. The processor according to claim 2, characterized in that, The UUID generation module is configured to generate a 128-bit unique identifier based on timestamps and random numbers, which is used throughout the entire task processing flow. The computational efficiency of the basic computing unit is reduced by at least one order of magnitude compared to the high-performance computing unit module.

10. A method for processing computational tasks based on the processor according to any one of claims 1-9, characterized in that, include: The input request extraction and verification module of the active defense arbitration unit receives user requests, separates user identification information and instruction data, sends the user identification information to the authorization verification channel, and sends the instruction data to the data synchronization channel. After parsing the user identification information, the permission verification path performs a hash calculation to obtain the storage address. The user permission table is then read based on the storage address via MIG IP, and the permission recognition and confirmation module generates the permission verification result. The data synchronization path caches the instruction data, generates a unique UUID for the user request, and packages the UUID, instruction data, and user identification information into a synchronization data packet; When the permission verification result indicates that the user has permission and there is an idle unit in the high-performance computing unit module, the UUID and instruction data in the synchronization data packet are sent to the high-performance computing unit module for execution. When the permission verification result is no permission, the UUID and instruction data in the synchronization data packet are sent to the basic computing unit to perform iterative calculation; The illegal request log storage module receives the unauthorized signal from the task scheduling arbitration FSM state machine in the task scheduling unit, extracts the user identification information and request content from the synchronization data packet, generates a log record containing a timestamp, and writes it to the SD card. The calculation result output caching module receives the calculation results from the high-performance computing unit module or the basic computing unit, extracts the target UUID carried in the calculation results, and performs matching and verification between the target UUID and the UUID. After the matching verification is successful, the calculation result is written to the corresponding address in the processor's main memory according to the UUID mapping relationship.

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