Chip security access control method, device and system and chip

Abstract

The invention discloses a chip security access control method, device and system and a chip. The control method comprises the following steps: when the chip is coupled with access equipment through a debugging interface, detecting an access request through the debugging interface and acquiring an access object of the access request; obtaining a first verification key or a second verification key based on an access object of the access request, and executing first verification or executing second verification based on the first verification; wherein the first verification key and the second verification key are generated based on a unique user identifier of an electronic device of the chip, the first verification key is associated with the first safety circuit, and the second verification key is associated with the second safety circuit; and controlling the first safety circuit or the second safety circuit to be switched on or switched off according to a result of the first verification or the second verification.

Description

Technical Field

[0001] This disclosure relates to the field of network security technology for chips, and more particularly to control methods, apparatus, systems, and chips for secure access to chips. Background Technology

[0002] As the main control unit of radar, the chip needs to be responsible for the network security requirements of radar products down to the chip level.

[0003] Chips require debug interfaces during design and manufacturing, typically JTAG (Joint Test Action Group) debug interfaces. JTAG is an international standard testing protocol used for system simulation, debugging, and internal chip testing. Debugging devices can connect to the chip through the debug interface to access it for testing or troubleshooting. However, this also makes the debug interface a natural backdoor. Without encryption protection, the chip's functionality will be completely exposed, and there is a possibility that chip data can be maliciously tampered with.

[0004] Existing security solutions for debugging interfaces are not compatible with the chip architecture of radar products and still have some security vulnerabilities. Furthermore, existing one-device-one-key security access schemes for electronic devices have high requirements for password storage capacity, making them unsuitable for the mass production and application scenarios of radar products.

[0005] The content in the background section is merely technology known to the public and does not represent existing technology in this field. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a method, apparatus, system, and chip for controlling secure access to a chip, so as to improve the security performance of the chip.

[0007] One aspect of this disclosure provides a control method for secure access to a chip, the chip including at least a debug interface, a main core circuit, a security control circuit, a first security circuit coupled between the debug interface and the main core circuit, and a second security circuit coupled between the first security circuit and the security control circuit; the control method includes: when the chip is coupled to an access device through the debug interface, detecting an access request and obtaining the access object of the access request via the debug interface; based on the access object of the access request, obtaining a first verification key or a second verification key, and performing a first verification or performing a second verification based on the first verification; wherein the first verification key and the second verification key are generated based on a unique user identifier of the electronic device of the chip, and the first verification key is associated with the first security circuit, and the second verification key is associated with the second security circuit; and controlling the first security circuit or the second security circuit to be turned on or off according to the result of the first verification or the second verification.

[0008] Optionally, the first verification key and the second verification key are generated based on the unique user identifier and a specific encryption key value of the electronic device corresponding to the chip; wherein, the specific encryption key value is obtained by encrypting the production information corresponding to the chip.

[0009] Optionally, the first verification key further includes a key value associated with the first security circuit, and the second verification key further includes a key value associated with the second security circuit.

[0010] Optionally, the first verification key includes a chip key and additional first indication data, the value of which is used to indicate the first security circuit; the second verification key includes a chip key and additional second indication data, the value of which is used to indicate the second security circuit; the chip key is generated based on the unique user identifier of the electronic device corresponding to the chip and the specific encryption key value, and uniquely corresponds to the unique user identifier of the electronic device.

[0011] Optionally, encryption is performed based on the production information corresponding to the chip and the key value associated with the first security circuit to obtain a first specific encryption key value associated with the first security circuit; encryption is performed based on the production information corresponding to the chip and the key value associated with the second security circuit to obtain a second specific encryption key value associated with the second security circuit; and a first verification key or a second verification key is obtained based on the unique user identifier of the electronic device corresponding to the chip and the first specific encryption key value or the second specific encryption key value.

[0012] Optionally, performing a first verification or a second verification based on the access object of the access request includes at least one of the following: when the access object of the access request is the main core circuit, performing the first verification; when the access object of the access request is the security control circuit, performing the first verification; or when the first security circuit is turned on, obtaining a second verification key and performing the second verification.

[0013] Optionally, controlling the first security circuit or the second security circuit to be turned on or off according to the result of the first verification or the second verification includes at least one of the following: determining whether the device key carried in the access request is consistent with the first verification key; if they are consistent, controlling the first security circuit to be turned on according to the first verification result; determining whether the device key carried in the access request is consistent with the second verification key; if they are consistent, controlling the second security circuit to be turned on according to the second verification result.

[0014] Optionally, the chip further includes a third security circuit coupled between the first security circuit and the second security circuit, and the control method further includes: after the first security circuit is turned on, performing a third verification on the access request, and turning on or off the third security circuit based on the result of the third verification.

[0015] Optionally, the control method includes at least one of the following: when the access object of the access request is the main core circuit, the third verification is performed on the basis that the first security circuit is turned on; when the access object of the access request is the security control circuit, the first verification is performed, or the third verification is performed on the basis that the first security circuit is turned on, or the second verification is performed on the basis that both the first security circuit and the third security circuit are turned on.

[0016] Optionally, the security control circuit performs the third verification or the second verification, wherein the security control circuit generates a random number corresponding to the third security circuit or the second security circuit, and generates and stores a verification public key based on the random number and the verification private key stored in the security control circuit; the random number is sent to the access device through the debugging interface, and the access device obtains the device public key corresponding to the third security circuit or the second security circuit based on the device private key corresponding to the third security circuit or the second security circuit and the random number, and returns the device public key to the security control circuit; the security control circuit compares the verification public key and the device public key to determine whether the verification public key and the device public key are consistent.

[0017] In another aspect of this disclosure, a control device for secure access to a chip is provided. The chip includes at least a debug interface and a main core circuit that performs chip functions. The control device further includes at least: a security control circuit adapted to protect and manage sensitive data; a first security circuit coupled between the debug interface and the main core circuit; a second security circuit coupled between the first security circuit and the security control circuit; and an access control circuit configured to, when the chip is coupled to an access device via the debug interface, detect an access request and obtain the access object of the access request via the debug interface; obtain a first verification key or a second verification key based on the access object of the access request, and perform a first verification or perform a second verification based on the first verification; control the first security circuit to be turned on or off according to the result of the first verification, or control the second security circuit to be turned on or off according to the result of the second verification; wherein the first verification key and the second verification key are generated based on a unique user identifier of the electronic device corresponding to the chip, and the first verification key is associated with the first security circuit, and the second verification key is associated with the second security circuit.

[0018] Optionally, the first verification key and the second verification key are generated based on the unique user identifier of the electronic device corresponding to the chip and a specific encryption key value; wherein, the specific encryption key value is obtained by encrypting the production information corresponding to the chip.

[0019] Optionally, the first verification key further includes a key value associated with the first security circuit, and the second verification key further includes a key value associated with the second security circuit.

[0020] Optionally, the access control circuit is configured to obtain a first verification key and perform the first verification when the access object of the access request is the main core circuit; and / or, when the access object of the access request is the security control circuit, obtain a first verification key and perform the first verification, or, based on the first security circuit being turned on, the verification circuit obtains a second verification key and performs a second verification.

[0021] Optionally, the access control circuit is configured to determine whether the device key carried in the access request is consistent with the first verification key, and if they are consistent, control the first security circuit to be turned on according to the first verification result; and / or, determine whether the device key carried in the access request is consistent with the second verification key, and if they are consistent, control the second security circuit to be turned on according to the second verification result.

[0022] Optionally, the access control circuit includes a verification circuit configured to store at least one of the first verification key and the second verification key.

[0023] Optionally, the verification circuit is configured to perform the first verification or the second verification, and control the first security circuit or the second security circuit to be turned on or off based on the result of the first verification or the second verification.

[0024] Optionally, the control device further includes: a third security circuit coupled between the first security circuit and the second security circuit, adapted to control access to the main core circuit; the access control circuit is further configured to perform a third verification on the access request after the first security circuit is turned on, and to turn on or off the third security circuit based on the obtained third verification result.

[0025] Optionally, the access control circuit includes: the security control circuit; the security control circuit is further configured to perform the third verification and control the on or off of the third security circuit; and / or perform the second verification and control the on or off of the second security circuit.

[0026] Optionally, the security control circuit is further configured to generate a random number corresponding to the security circuit, generate a verification public key based on the random number and the verification private key corresponding to the security circuit, and store it; send the random number to the access device through the debugging interface, and the access device obtains the device public key corresponding to the third security circuit or the second security circuit based on the device private key corresponding to the third security circuit or the second security circuit and the random number; and compare the verification public key with the device public key returned by the access device to determine whether the stored verification public key and the device public key are consistent.

[0027] Optionally, it further includes: a fourth safety circuit, which is coupled between the debugging interface and the first safety circuit, and is set to be normally closed before the chip debugging ends and normally open after the chip debugging ends.

[0028] Optionally, the first security circuit includes a first gate circuit; the second security circuit includes a second gate circuit.

[0029] Optionally, the debugging interface is a JTAG interface.

[0030] In another aspect of this disclosure, a control system for secure access to an electronic device is provided, comprising: a control device for performing secure access functions of the electronic device and a password generation device; wherein: the password generation device encrypts production information corresponding to the electronic device to generate a specific encryption key value, and generates a verification key based on the unique user identifier of the electronic device and the specific encryption key value; the control device is disposed in the electronic device, the electronic device is adapted to communicate directly or indirectly with the password generation device, and the control device is configured to store the verification key obtained by the electronic device from the password generation device, and to control access to the electronic device based on the verification key.

[0031] Optionally, the control device includes at least one security circuit, and the control device stores at least one verification key, wherein the verification key is associated with the security circuit.

[0032] Optionally, the verification key includes a chip key and additional indication data, wherein the chip key is generated based on the unique user identifier of the electronic device corresponding to the chip and the specific encryption key value, and uniquely corresponds to the unique user identifier of the electronic device, and the value of the indication data is used to indicate the associated security circuit.

[0033] Optionally, the password generation device is configured to encrypt based on the production information corresponding to the electronic device and a key value associated with the security circuit to obtain a specific encrypted key value corresponding to the security circuit; and to generate the verification key based on the specific encrypted key value and the unique user identifier of the electronic device.

[0034] In the chip security access control schemes based on the embodiments of this disclosure, when an access request via the debugging interface is detected, security verification is performed based on the access object of the access request. Through first and second verifications, it is determined whether the first and second security circuits coupled to the main core circuit and the security control circuit are turned on or off, thereby effectively controlling the access permissions of the chip's main core circuit and security control circuit. Since the access object is distinguished, security control circuits with higher security requirements require at least two levels of verification before access can be granted, preventing the leakage or tampering of sensitive data through the debugging interface.

[0035] In the optional control scheme, at least one verification key associated with at least one security circuit is used during the security verification process. This verification key is obtained based on the unique user identifier of the electronic device and a specific encryption key value, which is obtained by encrypting the production information corresponding to the electronic device. Each electronic device can obtain one or more verification keys corresponding to the security circuit in its security access control device. Even if the unique user identifier of the electronic device is accidentally exposed, the verification key is not easily obtained, thus improving the access security of the electronic device and the convenience of the electronic device manufacturing process.

[0036] Furthermore, since the key generation device generates specific encrypted key values ​​based on the production information corresponding to the electronic device, these specific encrypted key values ​​can be used to indicate some common attribute information of the electronic device and do not uniquely correspond to the device. The key generation device can store only the specific encrypted key values ​​and not the verification key. In this way, when the production volume of electronic devices is large, the storage space for electronic device keys can be greatly saved. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the description of the embodiments of this disclosure or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic diagram of a control device for secure chip access according to an embodiment of this disclosure is shown.

[0039] Figure 2 A schematic diagram of another chip security access control device is shown in an embodiment of this disclosure.

[0040] Figure 3 A schematic diagram of another chip security access control device is shown in an embodiment of this disclosure.

[0041] Figure 4 A schematic diagram of the structure of another chip security access control device according to an embodiment of the present disclosure is shown.

[0042] Figure 5 A schematic diagram of the structure of a chip according to an embodiment of this disclosure is shown.

[0043] Figure 6 A schematic diagram of the structure of a control system for secure access to electronic devices according to an embodiment of this disclosure is shown.

[0044] Figure 7A signaling flow diagram of a chip security access control method according to an embodiment of this disclosure is shown.

[0045] Figure 8 A signaling flow diagram of another chip security access control method in an embodiment of this disclosure is shown.

[0046] Figure 9 A schematic diagram of the signaling flow for a third verification of an access request by a security control circuit in an embodiment of this disclosure is shown. Detailed Implementation

[0047] Chip products typically include a main core circuit that performs the functions. In addition, to protect sensitive data, security control circuits can be incorporated into the chip to protect and manage this data. During chip design and manufacturing, system simulation, debugging, and internal chip testing are usually performed through a debugging interface.

[0048] Current chip security access protection solutions either verify in the cloud, are easily accessible, or require debugging equipment to be equipped with security cards. As mentioned in the background technology, these solutions still have some security vulnerabilities and are not suitable for the mass production and use scenarios of radar products, and cannot meet the unique requirements of radar electronic devices, such as the requirement for one device, one key.

[0049] For example, Chinese patent application CN117992327A discloses a method and system for secure chip debugging of intelligent connected devices. This scheme initiates an encrypted debugging request to a cloud device via a debugging interface. The cloud device verifies the request and performs debugging permission verification to generate a cloud authentication result. This scheme only discloses permission verification via the cloud device; however, the communication process may be eavesdropped on or tampered with, posing a security risk.

[0050] For example, Chinese patent application CN116185847 provides a secure debugging scheme for chips. This scheme includes an input security control unit, a secure debugging authentication unit, an access control authorization unit, a permission status storage unit, a debugging switch, and a debugging unit. The input security control unit generates a 256-bit intrinsic proprietary sequence based solely on the chip's unique serial number using the SM3 hash algorithm. When an external input sequence matches the intrinsic proprietary sequence, the secure debugging authentication phase begins. This scheme generates the intrinsic proprietary sequence locally on the device, and this intrinsic proprietary sequence corresponds only to the chip's unique serial number. Since the production and debugging of the device involves multiple processes, once the chip's unique serial number is obtained, the security defense will be compromised.

[0051] To address the aforementioned issues, the security protection scheme provided in this specification, upon detecting an access request via the debugging interface, obtains the access object of the access request and, based on the access object, obtains a first verification key or a second verification key, and performs a first verification or a second verification based on the first verification. Specifically, when it is detected that the access request needs to access the main core circuit, a first verification is performed based on the first verification key to determine whether to enable or disable the first security circuit coupled to the main core circuit; when it is detected that the access request needs to access the security control circuit, a first verification is performed first, and if the first verification passes, a second verification is further performed based on the second verification key to determine whether to enable or disable the second security circuit coupled to the security control circuit. Therefore, this scheme can effectively control the access permissions of the chip's main core circuit and security control circuit.

[0052] To enable those skilled in the art to better understand and implement this invention, the following detailed description of the concepts, solutions, and advantages of the embodiments of this disclosure is provided with reference to the accompanying drawings and in conjunction with specific application scenarios and through some specific examples.

[0053] Reference Figure 1 The schematic diagram shown illustrates the structure of a control device for secure chip access. Chip A01 can be a chip that performs at least one of the following functions: transmission, control, or drive. Chip A01 may include at least a debug interface A1, a main core circuit A2, and a security control circuit A3.

[0054] Chip A01 is adapted to be coupled to other access devices (e.g., access device C01) via debug interface A1 to perform data or instruction transfer. Access device C01 is used here as an example of any device that can connect to chip A01 via debug interface A1. Access device C01 may be a debug device or other devices with an interface matching debug interface A1. As an optional example, debug interface A1 may be a JTAG interface.

[0055] The main core circuit A2 in chip A01 contains the chip's main operating circuits and storage circuits, suitable for executing the set functions of chip A01. For example, in radar equipment, the main core circuit A2 can execute the control functions of chip A01, such as controlling the radar to emit lasers and detect echoes, generating point cloud data for environmental perception, etc.

[0056] The security control circuit A3 in chip A01 is configured to protect and manage sensitive data, such as data related to chip security. As an optional example, the security control circuit A3 can employ a standalone architecture design or have a separate processor and memory.

[0057] For radar products, the security control circuit A3 can be used to protect and manage sensitive data, perform encryption and decryption operations, and enable the radar product chip to support product-level network security functions. As an optional example, the security control circuit A3 can generate and verify digital signatures to ensure the authenticity of communication. In other embodiments, the security control circuit A3 can also store and manage digital certificates, security tokens, authentication credentials, and other sensitive data. As an optional example, the sensitive data may include user information, geographic location information, and password information used during chip communication. For example, it may include one or more of the following: radar user information, the radar's geographic location information, and verification information and password information required by the radar to transmit point cloud data to trusted users. It should be noted that this disclosure does not limit the specific type or content of sensitive data; any data protected and managed by the security control circuit can be considered sensitive data.

[0058] Since security control circuits are key components for protecting sensitive data and providing secure encryption functions, access to them needs to be strictly controlled to prevent data leakage and data tampering.

[0059] In some embodiments of this disclosure, reference is made to Figure 1 The chip security access control device B01 includes a first security circuit B1 and a second security circuit B2, which are connected in series. The first security circuit B1 is coupled between the debug interface A1 and the main core circuit A2, and is suitable for controlling access to the main core circuit A2. The second security circuit B2 is coupled between the first security circuit B1 and the security control circuit A3.

[0060] When an access request from access device C01 is detected transmitted via debug interface A1, control device B01 obtains the access object of the access request. For example, control device B01 can determine the access object to be accessed by reading the value of the access request setting data bits.

[0061] Next, the control device B01 obtains the first verification key or the second verification key based on the access object of the access request, and performs the first verification or performs the second verification based on the first verification.

[0062] In specific implementations, the control device may include access control circuitry for controlling access requests via the debug interface A1. For example... Figure 2 The schematic diagram shown is of a control device for secure access to a chip. The control device B02 may include a first security circuit B21, a second security circuit B22, and an access control circuit B20.

[0063] For details on the implementation of the first safety circuit B21 and the second safety circuit B22, please refer to [link / reference]. Figure 1 The control device B01 shown includes a first safety circuit B1 and a second safety circuit B2.

[0064] The access control circuit B20 can be configured to detect access requests and obtain the access object of the access request via the debugging interface A1 when the chip A02 is coupled to the access device C02 through the debugging interface A1; obtain a first verification key or a second verification key based on the access object of the access request, perform a first verification or perform a second verification based on the first verification; and control the first security circuit B11 to be turned on or off according to the result of the first verification, or control the second security circuit B22 to be turned on or off according to the result of the second verification.

[0065] The first verification key and the second verification key can be generated based on the unique user identifier of the electronic device corresponding to chip A02, and the first verification key is associated with the first security circuit B21, and the second verification key is associated with the second security circuit B22.

[0066] It should be noted that the access control circuit B20 can be one or more independent circuit structures; the components of the access control circuit B20 can also be distributed in the corresponding security circuits in the control device to perform access control on the corresponding security circuits; the access control circuit B20 can also be a circuit that performs other functions to perform partial or complete access control on access requests via the debugging interface A1, for example, it can be performed by a security control circuit; the access control circuit B20 can also be a partial access control performed by a part of a dedicated circuit structure, and another part of the circuit is distributed in the corresponding security circuit or in other circuits in the control device B02. The access control circuit B20 can also have some circuits distributed in the corresponding security circuit (e.g., the first security circuit B21 or the second security circuit B22), and some circuits distributed in other circuits in the control device, for example, distributed in the security control circuit A3. It is understood that only some examples are given above. In specific implementations, the access control circuit B20 can be a combination of some or all of the above implementation methods, as long as it enables the control device B02 to achieve secure control of access via the debugging interface A1.

[0067] Specifically, in some embodiments, the components of the access control circuit may be distributed within corresponding security circuits in the control device. For example, the components of the access control circuit may be distributed within at least one of a first security circuit and a second security circuit.

[0068] Continue to refer to Figure 1When the access request is determined to be directed to the main core circuit A2, the first security circuit B1 can obtain the first verification key and perform the first verification. Based on the obtained first verification result, it can either enable or disable the access. Specifically, during the first verification, the first security circuit B1 can compare the first verification key with the device key in the access request to determine if they match. If they match, the first security circuit B1 is enabled, granting access device C01 permission to access the main core circuit A2; otherwise, the first security circuit B1 is disabled, prohibiting access device C01 from accessing the main core circuit A2.

[0069] When the access request is directed to security control circuit A3, a secondary verification is required because access to security control circuit A3 needs to be strictly controlled.

[0070] First, the first security circuit B1 acquires the first verification key and performs the first verification, thereby turning the first security circuit B1 on or off. With the first security circuit B1 on, the second security circuit B2 acquires the second verification key and performs the second verification, thereby turning the second security circuit B2 on or off.

[0071] During the first verification, the first security circuit B1 compares the first verification key with the first device key in the access request to determine if they match. If they match, the first security circuit B1 is activated; otherwise, it is deactivated. During the second verification, the second security circuit B2 compares the second verification key with the second device key in the access request to determine if they match. If they match, the second security circuit B2 is activated; otherwise, it is deactivated. When both the first security circuit B1 and the second security circuit B2 are activated, access device C01 is granted permission to access security control circuit A3; otherwise, if either the first security circuit B1 or the second security circuit B2 is deactivated, access device C01 is prohibited from accessing security control circuit A3.

[0072] The first verification key or the second verification key can be stored in the security control circuit A3 or in other designated memory of the chip. Alternatively, the first verification key or the second verification key can be stored separately; for example, the first verification key can be stored in the first security circuit B1, and the second verification key can be stored in the second security circuit B2. The first verification key is associated with the first security circuit, and the second verification key is associated with the second security circuit; both are generated based on the unique user identifier and specific encryption key value of the electronic device corresponding to the chip. Specifically, the first verification key may also include a key value associated with the first security circuit, and the second verification key may also include a key value associated with the second security circuit.

[0073] In some implementations, the first verification key and the second verification key each include a chip key and additional indication data, the values ​​of which are used to indicate the first security circuit and the second security circuit, respectively. For example, the first verification key includes a chip key and additional first indication data, the value of which indicates the first security circuit; the second verification key includes a chip key and additional second indication data, the value of which indicates the second security circuit. In specific implementations, the first indication data and the second indication data may reside in the same data field, with different values ​​used to distinguish the indicated security circuit.

[0074] The chip key can be generated based on the unique user identifier of the electronic device corresponding to the chip and the specific encryption key value, and it uniquely corresponds to the unique user identifier of the electronic device.

[0075] In some embodiments, the specific encryption key value can be obtained by encrypting the production information corresponding to the chip. Specifically, this production information can be common attribute information that indicates the chip. For example, the specific encryption key value can be obtained by encrypting additional information such as the project, date, batch, and factory area corresponding to the chip or the electronic device assembled with the chip. The specific encryption key value does not correspond to a specific electronic device, but matches a specific batch of electronic devices. That is, there is only one corresponding specific encryption key value for the same batch of electronic devices. On the one hand, saving and recording only one specific encryption key value greatly reduces storage costs compared to saving and recording the key corresponding to each electronic device. On the other hand, since the specific encryption key value does not correspond to a specific electronic device, it can be used for transmission and storage between various stages of debugging and production without causing the electronic devices to lose security. In some embodiments, algorithms such as Advanced Encryption Standard (AES) can be used to encrypt the above-mentioned production information to form the specific encryption key value.

[0076] After obtaining a specific encrypted key value, it is combined with a unique user identifier (UID). Based on this UID and the specific encrypted key value, a chip key is obtained. Since there is a one-to-one correspondence between the unique user identifier (UID) and the electronic device, the obtained chip key also has a one-to-one correspondence with the electronic device on which the chip is assembled, or in other words, with the chip itself.

[0077] After obtaining the chip key, in some implementations, additional data fields can be provided on top of the chip key. For example, different field values ​​of the indicator data field can be used to indicate a specific security circuit. In one example, the verification key sets the VTID data field (VTID is the identifier name of this indicator field) on top of the chip key. If the value of the VTID data field is 310, it indicates a first security circuit; if the value of the VTID data field is 510, it indicates a second security circuit.

[0078] In some implementations, the production information can be first encrypted with a key associated with a specified security circuit to obtain a specific encrypted key associated with that security circuit. Then, a verification key corresponding to the specified security circuit can be generated based on the unique user identifier (UID) of the electronic device and the specific encrypted key. In some embodiments, the production information corresponding to the chip and the key associated with the first security circuit can be encrypted to obtain a first specific encrypted key associated with the first security circuit; or, the production information corresponding to the chip and the key associated with the second security circuit can be encrypted to obtain a second specific encrypted key associated with the second security circuit. Then, the first verification key can be obtained based on the unique user identifier of the electronic device corresponding to the chip and the first specific encrypted key; or, the second verification key can be obtained based on the unique user identifier of the electronic device corresponding to the chip and the second specific encrypted key.

[0079] In some embodiments of this disclosure, the access control circuitry may include a verification circuit. (See reference...) Figure 3 The control device B03 may include: a first safety circuit B31, a second safety circuit B32, and a verification circuit B35.

[0080] The first safety circuit B31 can be coupled between the debugging interface A1 and the verification circuit B35, and is suitable for controlling access to the main core circuit A2.

[0081] The second safety circuit B32 can be coupled between the first safety circuit B31, the verification circuit B35 and the safety control circuit A3.

[0082] The verification circuit B35 can be coupled to the debugging interface A1, the first security circuit B31, and the second security circuit B32 respectively. It is configured to perform a first verification or a second verification based on the access object of the access request when an access request from the access device C03 transmitted through the debugging interface A1 is detected. It can also turn on or off the first security circuit B31 based on the obtained first verification result, and turn on or off the second security circuit B32 based on the obtained second verification result.

[0083] As an optional example, the verification key can be stored in the verification circuit B35. In the first verification and the second verification, the verification circuit B35 can read the corresponding stored verification key according to different access objects and perform the first verification or the second verification.

[0084] As an optional example, in the default state, both the first security circuit B31 and the second security circuit B32 can be in the off state, and the security control circuit A3 and the main core circuit A2 are physically isolated from the access device C03. When an access request is detected from the access device C03 through the debug interface A1, the verification circuit B35 performs a corresponding verification based on the access object of the access request, and either turns on the corresponding security circuit or keeps the corresponding security circuit off according to the verification result, thereby effectively controlling the access permissions through the debug interface A1.

[0085] The following is a detailed description of a specific application scenario.

[0086] Access device C03 establishes a connection with chip A03 through debug interface A1 and sends an access request to chip A03 through debug interface A1. After detecting the existence of an access request, verification circuit B35 obtains the access object from the access request. For example, the access request may contain one or more specified data fields indicating the access object. Verification circuit B35 can determine the access object to be accessed by reading the values ​​of the corresponding data fields and comparing them. In other embodiments, access requests can also be monitored through debug interface A1 to extract the access object corresponding to the access request, and then the access object can be sent to verification circuit B35.

[0087] Next, the verification circuit B35 performs the corresponding security verification.

[0088] When the access target is the main core circuit A2, the verification circuit B35 extracts the first verification key and performs a first verification to obtain a first verification result. If the first verification result is successful, the first security circuit B31 is turned on, and the access device C03 can access the main core circuit A2 connected to the first security circuit B31. If the first verification result is a verification failure, the first security circuit B31 remains closed, and the access device C03 cannot access the main core circuit A2.

[0089] When the access target is security control circuit A3, verification circuit B35 first performs a first verification to obtain a first verification result. If the first verification result is a verification failure, verification circuit B35 keeps the first security circuit B31 in the closed state, and access device C03 cannot access security control circuit A3. If the first verification result is a verification success, it controls the first security circuit B31 to be turned on. At this time, verification circuit B35 further performs a second verification on the access request to obtain a second verification result. If the second verification result is a verification success, verification circuit B35 controls the second security circuit B32 to be turned on, and access device C03 can access security control circuit A3 connected to the second security circuit B32. If the second verification result is a verification failure, it keeps the second security circuit B32 in the closed state, and access device C03 will not be able to access security control circuit A3, and cannot read, write or modify the data stored in security control circuit A3.

[0090] As shown above, the first security circuit B31 and the verification circuit B35 can control external access devices' access to the main core circuit A2, preventing unauthorized manipulation of chip A03 and ensuring its secure operation. The verification circuit B35 performs at least two levels of verification. Only when both the first security circuit B31 and the second security circuit B32 are active can a path be established between the debug interface A1 and the security control circuit A3, allowing external devices to access the security control circuit A3. This prevents sensitive data from being leaked or tampered with through the debug interface A1, thus ensuring data security.

[0091] The first verification key can be associated with the first security circuit, and the second verification key can be associated with the second security circuit. Both can be generated based on the unique user identifier and specific encryption key value of the electronic device corresponding to the chip. Specifically, the first verification key can further include a key value associated with the first security circuit, and the second verification key can further include a key value associated with the second security circuit.

[0092] In some implementations, the first verification key and the second verification key may each include a chip key and additional indication data, the values ​​of which are used to indicate the first security circuit and the second security circuit, respectively.

[0093] The chip key can be generated based on the unique user identifier of the electronic device corresponding to the chip and the specific encryption key value, and it uniquely corresponds to the unique user identifier of the electronic device. The specific encryption key value is obtained by encrypting the production information corresponding to the chip. For example, the production information may include one or more common attribute information that can indicate the chip, such as the project to which the electronic device or chip belongs, the product batch, and the model. For example, the production information may include one or more of the following: project name, project identifier, project type, and the time information corresponding to the project (such as the time period or start time of the project); it may also include one or more of the following: customer name, customer identifier, and customer code; it may also include the product type, model, and batch set by the designer, developer, or manufacturer for the chip or electronic device. The specific encryption key value does not correspond to a specific electronic device, but matches a specific batch of electronic devices.

[0094] In other embodiments, the production information can be encrypted with key values ​​associated with designated security circuits to obtain a first specific encrypted key value associated with the first security circuit or a second specific encrypted key value associated with the second security circuit. Then, a first verification key associated with the first security circuit can be generated based on the unique user identifier (UID) of the electronic device and the first specific encrypted key value; alternatively, a second verification key associated with the second security circuit can be generated based on the unique user identifier (UID) of the electronic device and the second specific encrypted key value.

[0095] The system and method for generating the chip key will be described in detail later through specific embodiments, and will not be elaborated here.

[0096] Continue to refer to Figure 3 The verification circuit B35 can also employ other verification methods. Taking the first verification as an example, the verification circuit B35 sends a key generation request to the security control circuit A3. Based on the key generation request and the first verification key, the security control circuit A3 generates a first random number and a first verification public key based on the first random number and the first verification key. Then, it returns the first random number to the verification circuit B35. The verification circuit B35 transmits the first random number to the access device C03 through the debugging interface A1. The access device C03 obtains the first device public key based on the first random number and the first device key, and transmits the first device public key to the verification circuit B35 through the debugging interface A1. The verification circuit B35 compares whether the first public key and the first device public key are consistent to obtain the first verification result. Specifically, if the first public key and the first device public key are consistent, the first verification passes.

[0097] As an optional example, the first security circuit B31 may include: a first gate circuit (not shown).

[0098] As an optional example, the second security circuit B32 may include a second gate circuit (not shown).

[0099] The first gate circuit can be, for example, a first switch circuit, and the second gate circuit can be, for example, a second switch circuit.

[0100] In a specific implementation, the first switching circuit may include a first switch, and the second switching circuit may include a second switch. During use, both the first and second switches can be in a normally open state and, in response to a control signal received from the control terminal, switch to a closed state to activate the circuit. Specifically, the first and second switches can be electronic switches.

[0101] The control signal can be an analog signal or a digital signal, and it can be a level signal or a pulse signal. This disclosure does not limit the specific form of the control signal.

[0102] As an optional example, at least one control bit can be used to control the enabling and disabling of the first gate circuit. For example, when the control bit is 1, the first gate circuit is enabled; when the control bit is 0, the first gate circuit is disabled and in an open-circuit state.

[0103] In specific implementation, we will continue to refer to Figure 3 The chip security access control device B03 may further include a fourth security circuit B34, which may be coupled between the debug interface A1 and the first security circuit B31. As an optional example, the fourth security circuit B34 may include a fourth gate circuit (not shown), which may be set to a normally closed state before the chip debugging ends and to a normally open state after the chip debugging ends.

[0104] As an optional example, the fourth safety circuit B34 may include an electronic fuse (eFuse) or other programmable electronic fuse circuits. By applying a short current pulse to thermionic emission, current flows through a very small wire, causing the material in the wire to melt and create a permanent open circuit. This process is irreversible; once the eFuse has melted, it cannot be reprogrammed. In practical applications, the wire can serve as the fourth gate circuit.

[0105] During the research and development and production of the chip or electronic device, the wires in the eFuse are kept in a connected state. At the time of manufacture, the wires are melted, leaving them in a normally open state, thus physically disconnecting the main core circuit A2 and the security control circuit A3 from the debug interface A1. This prevents unauthorized devices from illegally accessing the chip A03 through the debug interface after the device leaves the factory.

[0106] In other embodiments of this disclosure, yet another control device for secure chip access is provided, such as... Figure 4 As shown, chip A04 includes a debug interface A1 and a main core circuit A2, wherein: chip A04 is adapted to be coupled to access device C04 through the debug interface A1, and the main core circuit A2 is configured to perform the functions of chip A02. As an optional example, the debug interface A1 can be a JTAG interface. Access device C04 is used here to illustrate any device that can connect to chip A04 through the debug interface A1; it could be a debugging device or other devices with an interface matching the debug interface A1.

[0107] Reference Figure 4 The secure access control device B04 may include: a first security circuit B41, a second security circuit B42, a third security circuit B43, a verification circuit B45, and a security control circuit B46, wherein:

[0108] The first safety circuit B41 is coupled between the debugging interface A1, the verification circuit B45 and the second safety circuit B42; the second safety circuit B42 is coupled between the first safety circuit B41 and the main core circuit A2; and the third safety circuit B43 is coupled between the second safety circuit B42 and the safety control circuit B46.

[0109] Verification circuit B45 is coupled to debug interface A1 and first security circuit B41 respectively. It is configured to perform a first verification when an access request from access device C04 is detected by debug interface A1, and to turn on or off the first security circuit B41 based on the obtained first verification result.

[0110] The security control circuit B46 is configured to perform a second verification on the access request when an access request from the access device C04 is detected by the debug interface A1 and the first security circuit B31 is turned on, and to turn on or off the second security circuit B42 based on the obtained second verification result; and to perform a third verification when the access request needs to reach the security control circuit B46, and to turn on or off the third security circuit B43 based on the obtained third verification result.

[0111] To enable those skilled in the art to better understand and implement it, its working principle is briefly described below:

[0112] By default, the first security circuit B41, the second security circuit B42, and the third security circuit B43 are all off. The security control circuit B46 and the main core circuit A2 are physically isolated from the access device C04 connected to the debugging interface A1. When an access request is detected from the access device C04 through the debugging interface A1, the verification circuit B45 performs a first verification based on the access object of the access request, and either turns on the first security circuit B41 or keeps the first security circuit B41 off according to the first verification result.

[0113] When the first verification result is successful, the security control circuit B46 further performs security verification based on the access object of the access request. Specifically, when the access object of the access request is the main core circuit A2, the security control circuit B46 performs a second verification on the access request and, based on the second verification result, either activates the second security circuit B42 or keeps it closed, thereby authorizing or prohibiting the access device C04 from accessing the main core circuit A2. When the access object of the access request is the security control circuit B46, and both the first security circuit B41 and the second security circuit B42 are activated, the security control circuit B46 further performs a third verification on the access request, controlling the third security circuit B43 to activate or remain closed. When the first security circuit B41, the second security circuit B42, and the third security circuit B43 are all activated, the access device C04 can access the security control circuit B46.

[0114] In a specific implementation, a data path can be established between the access device C04 and at least one of the main core circuit A2 and the security control circuit B46, based on the access object indicated by the access request of the access device C04 and the access permissions of the access device C04.

[0115] The following is a detailed description of a specific application scenario.

[0116] Access device C04 establishes a connection with chip A04 through debug interface A1 and sends an access request to chip A04 through debug interface A1. Verification circuit B45 detects the access request, performs a first verification, and obtains a first verification result. If the first verification result is successful, verification circuit B45 can output a control signal to control the first security circuit B41 to be turned on. If the first verification result is a failure, the first security circuit B41 remains in the closed state, and access device C04 cannot access chip A04.

[0117] If the first verification result is successful, the verification circuit B45 can send a trigger signal to the security control circuit B46. In response to the trigger signal, the security control circuit B46 performs a second verification on the access device C04 based on the access object of the access signal, obtaining a second verification result. The security control circuit B46 can parse the access information to obtain the access object of the access request; alternatively, the verification circuit B45 can parse the access information, extract the access object of the access request, and send it to the security control circuit B46.

[0118] When the second verification result is successful, the security control circuit B46 can output a control signal to activate the second security circuit B42. This establishes a data path between the access device C04 and the main core circuit A2, via the debug interface A1 to the first security circuit B41 and the second security circuit B42. The access device C04 can then access the main core circuit A2 through this data path.

[0119] When the second verification result is a verification failure, the second security circuit B42 remains in the off state. Thus, since there is no data path between the access device C04 and the main core circuit A2, the access device C04 cannot access the main core circuit A2, nor can it make any modifications to the chip's function, thereby ensuring the safe operation of chip A04.

[0120] When the access request targets security control circuit B46, and both the first and second verification results are successful, security control circuit B46 can perform a third verification on the access request. If the third verification result is successful, security control circuit B45 can output a control signal to activate the third security circuit B43. In this way, a data path can be established between access device C04 and security control circuit B46 via debugging interface A1 to the first security circuit B41, the second security circuit B42, and the third security circuit B43. Access device C04 can access security control circuit B46 via this data path.

[0121] If the third verification result is a verification failure, the third security circuit B43 remains in the off state. Therefore, the access device C04 cannot access the security control circuit B46.

[0122] As can be seen from the above embodiments, the control device distinguishes and verifies access requests based on the access object of the access request. For security control circuits with high security requirements, at least two layers of verification are performed. Only when all verifications pass can the access device reach the main core circuit or security control circuit through the data path connected by the security circuit and access the main core circuit or security control circuit within the permitted permission range. Therefore, it can prevent external access devices from illegally manipulating the chip or illegally obtaining sensitive data, realize effective control of access, and ensure the safe operation of the chip.

[0123] In some implementations, the device key included in the access request is adapted to the security circuit corresponding to the access object based on the access object of the access request.

[0124] For example, refer to Figure 1 , Figure 2 , Figure 3 or Figure 4 When the access request targets the main core circuit, the device key included in the access request can be a level-one key, suitable for comparison with a first verification key stored in the chip during the first verification. When the access request targets a security control circuit, the device key included in the access request can be a level-two key, suitable for comparison between the first device key and the chip's first verification key during the first verification, and for comparison between the second device key and the chip's second verification key during the second verification.

[0125] For example, refer to Figure 4 When the access request targets the core circuit, the device key included in the access request can be a level 2 key, suitable for comparing a first device key with a first verification key corresponding to a first security circuit to perform a first verification, and for comparing a second device key with a second verification key corresponding to a second security circuit to perform a second verification. When the access request targets a security control circuit, the device key included in the access request can be a level 3 key, suitable for comparing a first device key with a first verification key when performing the first verification; comparing a second device key with a second verification key when performing the second verification; and comparing a third device key with a third verification key when performing the third verification.

[0126] As an optional example, the first safety circuit B41, the second safety circuit B42, and the third safety circuit B43 may be gate circuits. In a specific embodiment, the gate circuit may be a switching circuit.

[0127] Continue to refer to Figure 4In some optional examples, the chip security access control device B04 may further include a fourth security circuit B44, including a fourth gate circuit (not shown), which may be coupled between the debug interface A1 and the first security circuit B41.

[0128] In some implementations, the fourth gate circuit can be set to a normally closed state before the debugging of chip A04 is completed, and set to a normally open state after the debugging of chip A04 is completed. As an optional example, the fourth safety circuit B44 may include an electronic fuse (eFuse).

[0129] In other embodiments, the security control circuit B46 may also perform security verification on the access request in the following manner, taking the third verification as an example:

[0130] Security control circuit B46 generates a third random number and, based on the third random number and the stored first verification private key, generates a first verification public key. Security control circuit B46 sends the third random number to access device C04 via debug interface A1. Access device C04 sends the first device private key and the first random number to a password generation device. After the password generation device generates the first device public key, access device C04 returns the first device public key to security control circuit B46. Security control circuit B46 compares the first verification public key with the first device public key. If the first verification public key and the first device public key match, the third verification result is determined to be successful; otherwise, the third verification result is determined to be a verification failure. As an optional example, the verification private key used to generate the verification public key can be a verification key corresponding to each security circuit. That is, when performing the first verification, the first verification public key corresponding to the first security circuit can be obtained based on the first verification key; when performing the second verification, the second verification public key corresponding to the second security circuit can be obtained based on the second verification key; and when performing the third verification, the third verification public key corresponding to the third security circuit can be obtained based on the third verification key.

[0131] To further improve chip security and reduce circuit area, chip security access control devices can be placed inside the chip.

[0132] Reference Figure 5 The schematic diagram of the chip structure shown in this embodiment of the disclosure indicates that chip A0 includes: a debug interface A1, a main core circuit A2, and a chip secure access control device B0, wherein: the debug interface A1 can be configured to be coupled to an access device (not shown). The main core circuit A2 can be configured to execute the functions of chip A0.

[0133] The debug interface A1 can be a JTAG interface. It is understood that the debug interface A1 can also be other types of interfaces, as long as chip testing or debugging can be achieved through the interface.

[0134] The access device may be a debugging device or other devices with an interface that matches the debugging interface A1. The specific structure or function of the access device is not limited in this embodiment.

[0135] The specific structure of the secure access control device B0 can be found in [reference]. Figures 1 to 4 The specific structure of the control device for secure access and its implementation in the corresponding embodiments will not be described in detail here.

[0136] As shown in the previous embodiment, chip A0 may further include a security control circuit (not shown), configured to protect and manage sensitive data. In specific implementations, the security control circuit may be located inside the chip security access control device B0, or it may be located outside the chip security access control device B0. For details, please refer to the foregoing examples, which will not be described in detail here.

[0137] Using a chip with the aforementioned chip security access control device in an electronic device can ensure that the electronic device operates more securely and can also prevent the leakage or tampering of sensitive data on the electronic device.

[0138] In practical applications, the chip can be used in electronic devices across various scenarios. For example, it can be used in radar, automotive platforms, or smart terminals such as mobile phones, tablets, and one or more other devices.

[0139] Furthermore, embodiments of this disclosure also provide a control system for secure access to electronic devices. These will be described in detail below through several examples.

[0140] Reference Figure 6 The diagram illustrates an exemplary structure of a control system for secure access to an electronic device. In some embodiments of this disclosure, the control system S0 may include a control device U0 for performing secure access functions and a password generation device K0. The control device U0 is disposed in the electronic device D0, and the electronic device D0 can communicate directly or indirectly with the password generation device K0.

[0141] Specifically, the password generation device K0 can encrypt the production information corresponding to the electronic device D0 to generate a specific encryption key value, and generate a chip key based on the unique user identifier of the electronic device D0 and the specific encryption key value. The generated chip key corresponds uniquely to the unique user identifier.

[0142] Control device U0 is located in electronic device D0. A chip key generated by password generation device K0 is acquired by electronic device D0 and stored in control device U0. Control device U0 controls access to electronic device D0 based on the chip key.

[0143] As a specific implementation, the device key generation process is detailed below:

[0144] After the password generation device K0 establishes a direct or indirect communication connection with the electronic device D0, it can obtain the unique user identifier of the electronic device D0 through the communication connection.

[0145] Furthermore, the password generation device K0 can further obtain the production information corresponding to the electronic device D0. In specific implementations, the production information corresponding to the electronic device D0 can be sent from the electronic device D0 to the password generation device K0, or it can be input to the password generation device K0 via other devices or methods. The specific encryption key value is obtained by encrypting the production information corresponding to the chip.

[0146] In some optional examples, the password generation device K0 can generate a specific encryption key value based on the production information corresponding to the electronic device D0, and generate a chip key for the electronic device D0 based on the specific encryption key value and the unique user identifier of the electronic device.

[0147] Specifically, this production information can be common attribute information that indicates the chip, such as additional information like the project, date, batch, and factory location corresponding to the chip or the electronic device equipped with the chip. As some optional examples, the additional information such as the project, date, batch, and factory location corresponding to the chip or the electronic device equipped with the chip can be encrypted to obtain a specific encrypted key value. This specific encrypted key value does not correspond to a specific electronic device, but rather matches a batch of specific electronic devices with the same aforementioned attribute information. That is, there is only one corresponding specific encrypted key value for the same batch of electronic devices. On the one hand, saving and recording only one specific encrypted key value greatly reduces storage costs compared to saving and recording the key corresponding to each electronic device; on the other hand, since this specific encrypted key value does not correspond to a specific electronic device, it can be used for transmission and storage between various stages of debugging and production without compromising the security of the electronic devices. In some embodiments, algorithms such as AES can be used to encrypt the above production information to form a specific encrypted key value.

[0148] In some optional examples, the control device U0 further includes at least one security circuit. In this case, the password generation device K0 can generate a verification key based on the electronic device's unique user identifier, the specific encryption key value, and the key value associated with the security circuit in the control device U0, and then send the verification key to the control device U0 for storage. The verification key is formed based on the chip key and associated with the security circuit. For example, the verification key corresponds one-to-one with the security circuit.

[0149] In some implementations, the password generation device K0 can add additional data fields based on the chip key, with each data field corresponding to at least one security circuit. By setting different values ​​in these additional data fields, verification keys corresponding to different security circuits are formed. In some implementations, refer to... Figure 6 The password generation device K0 can encrypt the production information corresponding to the electronic device D0 and a key value associated with at least one security circuit to obtain a specific encrypted key value corresponding to the security circuit. Further, a verification key can be generated based on the specific encrypted key value and the unique user identifier of the electronic device, and the verification key is associated with the corresponding security circuit (e.g., one or more of a first security circuit, a second security circuit, and a third security circuit).

[0150] To prevent potential attacks or eavesdropping during the device key generation process, in specific implementations, the electronic device and the password generation device can communicate through a dedicated network belonging to the manufacturer, maintainer, or owner of the electronic device. Through this dedicated network, a secure data channel is established between the electronic device and the password generation device before any data interaction occurs. Data transmission and information exchange are conducted through this secure data channel, preventing eavesdropping or attacks that could lead to the leakage of the device key.

[0151] This disclosure also provides specific examples of corresponding control methods for secure chip access. As described in the previous embodiments, the chip is adapted to be coupled to an access device via a debug interface. The chip may include a main core circuit that performs functions and a security control circuit that protects and manages sensitive data. The chip may also include a first security circuit and a second security circuit, which are sequentially coupled between the debug interface and the security control circuit, and the first security circuit is coupled to the main core circuit.

[0152] Based on the above circuit structure, in the embodiments of this disclosure, reference is made to... Figure 7 The following chip security access control method can be used to control access to devices connected through the debugging interface. The specific steps are as follows:

[0153] S100, detect the access request via the debugging interface and obtain the access object of the access request.

[0154] S200: Based on the access object of the access request, obtain a first verification key or a second verification key, and perform a first verification or perform a second verification based on the first verification.

[0155] The first verification key and the second verification key can be generated based on the unique user identifier of the electronic device of the chip, and the first verification key is associated with the first security circuit, and the second verification key is associated with the second security circuit.

[0156] S300, based on the result of the first verification or the second verification, control the first safety circuit or the second safety circuit to be turned on or off.

[0157] When the access request targets the main core circuit, the first verification is performed. As an optional example, the first verification can specifically take the following form: obtaining a first verification key and determining whether the device key carried in the access request matches the first verification key stored in the chip. The first verification key is associated with the first security circuit and is generated based on the unique user identifier of the electronic device corresponding to the chip and a specific encryption key value. The specific encryption key value can be obtained by encrypting the production information corresponding to the chip.

[0158] When the access request is directed to the security control circuit, since the security control circuit usually has a higher security level, it is often necessary to perform a second verification after the first verification passes.

[0159] As an optional example, when the access request targets the security control circuit, the following method can be used: Obtain a first verification key and determine whether the first device key carried in the access request matches the first verification key stored in the chip. If they match, the first verification passes, and the second verification continues. Obtain a second verification key and determine whether the second device key carried in the access request matches the second verification key stored in the chip. The first verification key is associated with the first security circuit, and the second verification key is associated with the second security circuit. A specific encryption key value is generated based on the unique user identifier of the electronic device corresponding to the chip and a specific encryption key value. The specific encryption key value is obtained by encrypting the production information corresponding to the chip.

[0160] In some embodiments of this disclosure, the chip may further include: a third security circuit coupled between the first security circuit, the second security circuit, and the security control circuit, and controlled by the security control circuit. Accordingly, refer to Figure 8 The method may further include the following steps:

[0161] S400, after the first security circuit is turned on, when the access object of the access request is the security control circuit, the third verification is performed, and when the third verification passes, the third security circuit is turned on.

[0162] In some embodiments of this disclosure, the security control circuit performs a third verification on the access request, which may include: determining whether the third device key carried in the access request is consistent with the third verification key stored in the chip.

[0163] In some embodiments of this disclosure, reference is made to Figure 9 The diagram shows the signaling flow of the security control circuit performing a third verification on the access request. This third verification can also be performed in the following manner:

[0164] S410, the security control circuit generates a third random number and generates a third verification public key based on the third random number and the third verification private key stored in the security control circuit.

[0165] S420, the security control circuit sends the third random number to the access device through the debugging interface, the access device sends the third device private key and the third random number to the password generation device, the password generation device generates the third device public key, and returns it to the security control circuit through the access device;

[0166] S430, the security control circuit compares the third verification public key with the third device public key to determine whether the third verification public key and the third device public key are consistent.

[0167] In practical implementation, the third verification result can be obtained based on whether the third verification public key and the third device public key are consistent. Specifically, if the third verification public key and the third device public key are consistent, the third verification is considered successful, and the third verification result is considered successful; otherwise, the verification is considered unsuccessful. The private key used to generate the public key can be the verification key corresponding to each security circuit. That is, during the third verification, the third verification public key corresponding to the third security circuit can be obtained based on the third verification key.

[0168] The specific implementation of the chip secure access control method in this disclosure embodiment can be adapted to the specific hardware structure. For details, please refer to the aforementioned chip secure access control device embodiment, which will not be described in detail here.

[0169] While the embodiments disclosed above are provided, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for controlling secure access to a chip, characterized in that, The chip includes at least a debug interface, a main core circuit, a security control circuit, a first security circuit coupled between the debug interface and the main core circuit, and a second security circuit coupled between the first security circuit and the security control circuit. The control method includes: When the chip is coupled to the access device through the debug interface, the access request is detected through the debug interface and the access object of the access request is obtained. Based on the access object of the access request, a first verification key or a second verification key is obtained, and a first verification is performed or a second verification is performed based on the first verification; wherein, the first verification key and the second verification key are generated based on the unique user identifier of the electronic device of the chip, and the first verification key is associated with the first security circuit, and the second verification key is associated with the second security circuit; Based on the result of the first verification or the second verification, control the first security circuit or the second security circuit to be turned on or off.

2. The control method according to claim 1, characterized in that, The first verification key and the second verification key are generated based on the unique user identifier and specific encrypted key value of the electronic device corresponding to the chip; The specific encryption key value is obtained by encrypting the production information corresponding to the chip.

3. The control method according to claim 2, characterized in that, The first verification key further includes a key value associated with the first security circuit, and the second verification key further includes a key value associated with the second security circuit.

4. The control method according to claim 3, characterized in that, The first verification key includes a chip key and additional first indication data, the value of which is used to indicate the first security circuit. The second verification key includes a chip key and additional second indication data, the value of which is used to indicate the second security circuit. The chip key is generated based on the unique user identifier of the electronic device corresponding to the chip and the specific encryption key value, and it uniquely corresponds to the unique user identifier of the electronic device.

5. The control method according to claim 3, characterized in that, Encryption is performed based on the production information corresponding to the chip and the key value associated with the first security circuit to obtain a first specific encryption key value associated with the first security circuit. Encryption is performed based on the production information corresponding to the chip and the key value associated with the second security circuit to obtain a second specific encryption key value associated with the second security circuit; Based on the unique user identifier of the electronic device corresponding to the chip and the first specific encryption key or the second specific encryption key, the first verification key or the second verification key is obtained.

6. The control method according to claim 1, characterized in that, The access object based on the access request, performing a first verification or performing a second verification based on the first verification includes at least one of the following: When the access request targets the main core circuit, the first verification is performed; When the access request targets the security control circuit, a first verification is performed; or when the first security circuit is turned on, a second verification key is obtained and a second verification is performed.

7. The control method according to claim 6, characterized in that, The step of controlling the first safety circuit or the second safety circuit to be turned on or off based on the result of the first verification or the second verification includes at least one of the following: Determine whether the device key carried in the access request is consistent with the first verification key. If they are consistent, control the first security circuit to be turned on according to the first verification result. Determine whether the device key carried in the access request is consistent with the second verification key. If they are consistent, control the second security circuit to be turned on according to the second verification result.

8. The control method according to claim 2, characterized in that, The chip further includes: a third security circuit coupled between the first security circuit and the second security circuit; the control method further includes: After the first security circuit is turned on, the access request is subjected to a third verification, and based on the result of the third verification, the third security circuit is turned on or off.

9. The control method according to claim 8, characterized in that, The control method includes at least one of the following: When the access request targets the main core circuit, the third verification is performed while the first security circuit is on. When the access request targets the security control circuit, a first verification is performed, or a third verification is performed if the first security circuit is turned on, or a second verification is performed if both the first security circuit and the third security circuit are turned on.

10. The control method according to claim 9, characterized in that, The third verification or the second verification is performed by the security control circuit, wherein the security control circuit generates a random number corresponding to the third security circuit or the second security circuit, and generates and stores a verification public key based on the random number and the verification private key stored in the security control circuit; The random number is sent to the access device through the debugging interface. The access device obtains the device public key corresponding to the third security circuit or the second security circuit based on the device private key corresponding to the third security circuit or the second security circuit and the random number, and returns the device public key to the security control circuit. The security control circuit compares the verification public key and the device public key to determine whether the verification public key and the device public key are consistent.

11. A control device for secure access to a chip, characterized in that, The chip includes at least a debug interface and a main core circuit that executes chip functions, and the control device includes at least: Security control circuits are suitable for protecting and managing sensitive data; A first safety circuit is coupled between the debug interface and the main core circuit; The second safety circuit is coupled between the first safety circuit and the safety control circuit; The access control circuit is configured to, when the chip is coupled to an access device via the debug interface, detect an access request and obtain the access object of the access request via the debug interface; based on the access object of the access request, obtain a first verification key or a second verification key, perform a first verification or perform a second verification based on the first verification; and control the first security circuit to be turned on or off according to the result of the first verification, or control the second security circuit to be turned on or off according to the result of the second verification; wherein the first verification key and the second verification key are generated based on the unique user identifier of the electronic device corresponding to the chip, and the first verification key is associated with the first security circuit, and the second verification key is associated with the second security circuit.

12. The control device according to claim 11, characterized in that, The first verification key and the second verification key are generated based on the unique user identifier of the electronic device corresponding to the chip and a specific encrypted key value; wherein, the specific encrypted key value is obtained by encrypting the production information corresponding to the chip.

13. The control device according to claim 12, characterized in that, The first verification key further includes a key value associated with the first security circuit, and the second verification key further includes a key value associated with the second security circuit.

14. The control device according to claim 11, characterized in that, The access control circuit is configured to obtain a first verification key and perform the first verification when the access object of the access request is the main core circuit; and / or, obtain a first verification key and perform the first verification when the access object of the access request is the security control circuit, or, based on the first security circuit being turned on, obtain a second verification key and perform a second verification.

15. The control device according to claim 14, characterized in that, The access control circuit is configured to determine whether the device key carried in the access request is consistent with the first verification key. If they are consistent, the first security circuit is controlled to be turned on according to the first verification result. And / or, Determine whether the device key carried in the access request is consistent with the second verification key. If they are consistent, control the second security circuit to be turned on according to the second verification result.

16. The control device according to claim 15, characterized in that, The access control circuit includes a verification circuit configured to store at least one of the first verification key and the second verification key.

17. The control device according to claim 16, characterized in that, The verification circuit is configured to perform the first verification or the second verification, and control the first security circuit or the second security circuit to be turned on or off based on the result of the first verification or the second verification.

18. The control device according to claim 14, characterized in that, The control device further includes: a third security circuit coupled between the first security circuit and the second security circuit, adapted to control access to the main core circuit; the access control circuit is further configured to perform a third verification on the access request after the first security circuit is turned on, and to turn on or off the third security circuit based on the obtained third verification result.

19. The control device according to claim 18, characterized in that, The access control circuit includes: the security control circuit; The security control circuit is further configured to perform the third verification and control the on or off state of the third security circuit; and / or perform the second verification and control the on or off state of the second security circuit.

20. The control device according to claim 19, characterized in that, The security control circuit is further configured to generate a random number corresponding to the third security circuit or the second security circuit, generate a verification public key based on the random number and the verification private key corresponding to the third security circuit or the second security circuit, and store it; send the random number to the access device through the debugging interface, and the access device obtains the device public key based on the device private key corresponding to the third security circuit or the second security circuit and the random number; And compare the verification public key with the device public key returned by the access device to determine whether the verification public key and the device public key are consistent.

21. The control device according to claim 11, characterized in that, Also includes: A fourth safety circuit is coupled between the debugging interface and the first safety circuit, and is set to a normally closed state before the chip debugging ends and to a normally open state after the chip debugging ends.

22. The control device according to claim 11, characterized in that, The first security circuit includes a first gate circuit; the second security circuit includes a second gate circuit.

23. The control device according to claim 11, characterized in that, The debugging interface is a JTAG interface.

24. A control system for secure access to electronic devices, characterized in that, include: A control device and a password generation device for performing secure access functions for electronic devices; wherein: The password generation device is configured to encrypt the production information corresponding to the electronic device, generate a specific encryption key value, and generate a verification key based on the unique user identifier of the electronic device and the specific encryption key value. The control device is disposed in an electronic device adapted to communicate directly or indirectly with the password generation device. The control device is configured to store the verification key obtained from the password generation device via the electronic device, and to control access to the electronic device based on the verification key.

25. The control system according to claim 24, characterized in that, The control device includes at least one security circuit, and the control device stores at least one verification key, wherein the verification key is associated with the security circuit.

26. The control system according to claim 25, characterized in that, The verification key includes a chip key and additional indication data. The chip key is generated based on the unique user identifier of the electronic device corresponding to the chip and the specific encryption key value, and uniquely corresponds to the unique user identifier of the electronic device. The value of the indication data is used to indicate the associated security circuit.

27. The control system according to claim 25, characterized in that, The password generation device is configured to encrypt the production information corresponding to the electronic device and the key value associated with the security circuit to obtain a specific encrypted key value corresponding to the security circuit; and to generate the verification key based on the specific encrypted key value and the unique user identifier of the electronic device.

28. A chip, characterized in that, include: The debugging interface is configured to be coupled to the access device; The main core circuit is configured to perform the functions of the chip. The control device for secure access to a chip according to any one of claims 11-23.

Images