Chip physical synthesis and layout routing method, system and storage medium
By performing a legalization operation on the unauthorized cell placement results in the physical synthesis stage in the placement and routing tool, the problems of low iteration efficiency, poor result consistency, and easy failure of optimization results in high-performance RISC-V processor design are solved, and a more efficient physical implementation process is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RIVAI TECH (SHENZHEN) CO LTD
- Filing Date
- 2026-03-31
- Publication Date
- 2026-08-04
AI Technical Summary
In high-performance RISC-V processor design, the integration process between physical synthesis and automatic placement and routing leads to problems such as low iteration efficiency, poor result consistency, easy failure of optimization results, and low physical environment compatibility, which are particularly pronounced at advanced process nodes.
The unvalidated cell layout results from the physical synthesis stage are directly used as input to the placement and routing tool, and the validation operation is performed in the placement and routing tool. Only the invalid cells are adjusted, keeping the relative positions between physical cells unchanged and reducing repeated placement steps.
It shortens the physical implementation cycle, improves the consistency of layout and routing results, reduces deviations caused by differences in tool algorithms, lowers the risk of failure of physical synthesis optimization results, and improves design efficiency and result stability.
Smart Images
Figure CN121936403B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a chip physical synthesis and placement routing method, system, and storage medium. Background Technology
[0002] In modern integrated circuit design, especially in the design of complex chips such as high-performance RISC-V processors and system-on-a-chip (SoC) at advanced process nodes, physical synthesis and automatic placement and routing (APR) are two core steps in the back-end physical implementation. The effectiveness of their integration directly determines the chip's timing, power consumption, area (PPA) performance, and physical convergence efficiency. Physical synthesis tools introduce physical awareness capabilities on top of logic synthesis, enabling them to optimize logic structure and perform preliminary cell placement in conjunction with placement planning, thus possessing stronger timing-driven optimization capabilities. Automatic placement and routing tools are responsible for completing the legal placement of standard cells, signal routing, and physical rule verification, making them a crucial step in achieving chip manufacturability.
[0003] Currently, the mainstream workflow for connecting physical synthesis and APR in the industry is to perform physical synthesis independently, and then rebuild the environment based on APR tools and repeat the process. The specific execution steps are as follows:
[0004] The physical synthesis tool independently completes logic optimization, floorplan formulation, and generates corresponding floorplan constraint files;
[0005] The automatic placement and routing tool is detached from the original physical synthesis environment and reconstructs the chip physical environment based solely on the aforementioned placement constraint file, including preliminary power network planning and physical constraint mapping.
[0006] The automatic placement and routing tool independently executes the complete global and detailed placement process for standard cells, covering the preliminary placement results in the physical synthesis phase;
[0007] The automatic placement and routing tool performs subsequent routing, physical rule checks, timing corrections and confirmations based on the repositioning. If the area and manufacturability requirements are not met, it needs to be returned to the physical synthesis tool for re-optimization, forming multiple iterations.
[0008] While the above process is a common design methodology in the industry, it exposes many core flaws in high-performance RISC-V processor custom design scenarios that involve large-scale designs, timing and congestion sensitivity, and high physical synthesis involvement. These flaws are further amplified at advanced process nodes, specifically manifested as follows:
[0009] (1) Low design iteration efficiency: The repeated placement operations of physical synthesis and automatic placement and routing greatly increase the overall time consumption of back-end physical implementation. In complex RISC-V processor designs, the repeated placement stage alone occupies a large amount of EDA tool running time, which prolongs the chip physical convergence cycle.
[0010] (2) Poor consistency of results between tools: There are essential differences in the core algorithms of physical synthesis tools and automatic placement and routing tools, including cell placement algorithms, congestion assessment models, timing delay calculation methods, etc., which leads to significant deviations between the cell layout after automatic placement and routing and the expected layout in the physical synthesis stage, resulting in unpredictable fluctuations in the chip's congestion distribution and timing performance.
[0011] (3) Physical synthesis optimization results are prone to failure: The timing optimization, congestion avoidance, and logic structure adjustment decisions made based on the initial layout during the physical synthesis stage can be completely disturbed or even covered by the repositioning of the automatic placement and routing tools, resulting in the loss of the previous optimization results and greatly increasing the difficulty of timing convergence of high-performance RISC-V processors.
[0012] (4) Low physical environment matching: The physical environment reconstructed by the automatic placement and routing tool deviates from the original physical synthesis environment, and cannot accurately match the optimization premise of the physical synthesis stage, which further aggravates the deviation of the placement result and increases the risk of physical rule violation.
[0013] The existence of the above problems means that the traditional interconnection process can no longer meet the high requirements of physical implementation efficiency, area performance and convergence stability for custom design of high-performance RISC-V processors. Therefore, there is an urgent need for a new chip physical synthesis and placement and routing method, system and storage medium to solve the above technical problems. Summary of the Invention
[0014] This invention provides a chip physical synthesis and placement / routing method, system, and storage medium, aiming to improve the consistency of chip cell placement, congestion, and timing results and shorten the physical implementation iteration cycle during the physical synthesis and placement / routing stages, thereby improving overall design efficiency. This invention is particularly suitable for advanced process node design scenarios involving large-scale designs, timing and congestion sensitivity, and high physical synthesis involvement.
[0015] In a first aspect, the present invention provides a physical synthesis and placement / routing method for a chip, the physical synthesis and placement / routing method comprising the following steps:
[0016] S1. Construct the power network of the chip to be designed based on the placement and routing tool, and insert the physical units and physical parameters required by the chip to be designed into the power network to obtain the initial design data.
[0017] S2. The initial design data is used as input to the physical synthesis tool, and the physical synthesis tool is used to place multiple standard cells of the chip to be designed to obtain preliminary placement results; wherein, the preliminary placement results include the placement coordinates of each standard cell;
[0018] S3. Based on the placement coordinates, extract the invalid cells from the multiple standard cells, use the invalid cells as input to the placement and routing tool, adjust the invalid cells based on the placement and routing tool, obtain the chip physical layout design result, and realize the physical synthesis and placement and routing of the chip to be designed.
[0019] Preferably, the physical parameters include physical constraint information, physical area planning information, and physical environment information.
[0020] Preferably, the illegal cell refers to the standard cell whose placement position does not meet the cell alignment constraints, row constraints, and overlap constraints of the layout and routing tool.
[0021] Preferably, when adjusting the illegal unit, the layout and routing tool makes the minimum position adjustment of the illegal unit while keeping the relative positions between the physical units unchanged.
[0022] Secondly, the present invention also provides a physical synthesis and placement / routing system for a chip, the physical synthesis and placement / routing system comprising:
[0023] The initial design module is used to construct the power network of the chip to be designed based on the placement and routing tool, insert the physical units and physical parameters required by the chip to be designed into the power network, and obtain the initial design data.
[0024] The placement module is used to take the initial design data as input to the physical synthesis tool, and place multiple standard cells of the chip to be designed through the physical synthesis tool to obtain preliminary placement results; wherein, the preliminary placement results include the placement coordinates of each standard cell;
[0025] The adjustment module is used to extract invalid cells from multiple standard cells according to the placement coordinates, use the invalid cells as input to the placement and routing tool, adjust the invalid cells based on the placement and routing tool, obtain the chip physical layout design result, and realize the physical synthesis and placement of the chip to be designed.
[0026] Preferably, the physical parameters include physical constraint information, physical area planning information, and physical environment information.
[0027] Preferably, the illegal cell refers to the standard cell whose placement position does not meet the cell alignment constraints, row constraints, and overlap constraints of the layout and routing tool.
[0028] Preferably, when adjusting the illegal unit, the layout and routing tool makes the minimum position adjustment of the illegal unit while keeping the relative positions between the physical units unchanged.
[0029] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a physical synthesis and placement / routing program for a chip stored in the memory and executable on the processor, wherein when the processor executes the physical synthesis and placement / routing program for the chip, it implements the steps of the physical synthesis and placement / routing method for the chip as described in any of the above embodiments.
[0030] Fourthly, the present invention also provides a computer-readable storage medium storing a physical synthesis and placement / routing program for a chip, wherein when the physical synthesis and placement / routing program for the chip is executed by a processor, it implements the steps in the physical synthesis and placement / routing method for a chip as described in any of the above embodiments.
[0031] Compared to existing technologies, this invention directly uses the cell placement results completed but not yet legalized during the physical synthesis phase as input to the place-and-route tool, and performs the legalization operation only within the place-and-route tool. This approach maximizes the retention of the physical synthesis tool's placement decisions during the place-and-route phase, thereby reducing the need for complete placement operations in the place-and-route tool and performing legalization only on invalid cells, significantly shortening the physical implementation cycle; improving the consistency between physical synthesis and place-and-route results, avoiding placement deviations due to differences in tool algorithms, and enhancing consistency in congestion and timing performance; reducing the risk of physical synthesis optimization failure, minimizing placement disturbances caused by repeated placement, and effectively retaining the optimization results from the physical synthesis phase in subsequent processes. Attached Figure Description
[0032] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:
[0033] Figure 1 This is a flowchart of the physical synthesis and placement and routing method for a chip provided in an embodiment of the present invention;
[0034] Figure 2 This is a schematic diagram of the physical synthesis and placement and routing system for a chip provided in an embodiment of the present invention;
[0035] Figure 3 This is a schematic diagram of the structure of the computer device provided in an embodiment of the present invention; Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0037] Example 1
[0038] Please refer to Figure 1 This invention provides a physical synthesis and placement / routing method for a chip, the method comprising the following steps:
[0039] S1. Construct the power network of the chip to be designed based on the placement and routing tool, and insert the physical units and physical parameters required by the chip to be designed into the power network to obtain the initial design data.
[0040] In this embodiment of the invention, the physical parameters include physical constraint information, physical area planning information, and physical environment information.
[0041] In this embodiment of the invention, when constructing the power network, a complete power distribution network (PDN) for the chip to be designed is built, including the main power line (VDD / VSS), branch power lines, and power contact (Pad) layout, to ensure that each functional module of the chip (such as the arithmetic unit, storage unit, and interface module) can obtain a stable power supply.
[0042] When inserting physical units, the physical units required by the chip to be designed are added to the chip layout, such as substrate contact units (used to avoid parasitic latch-up effects caused by substrate levitation and to ensure the stability of substrate potential), end cap units (must be placed at the edge of the core logic area to ensure uniformity of photolithography pattern density and prevent edge effects), decoupling units (used to suppress dynamic voltage drop and reduce power supply noise) and other non-logic functions but physical entities that ensure chip manufacturability and reliability.
[0043] When setting physical parameters, based on the functional requirements of the chip to be designed, define the rules for key areas on the chip layout. For example, set the layout area of the core computing module (such as the multiplier) as a dedicated area that other units are prohibited from intruding into; limit the I / O interface units to be arranged along the chip edge; clarify the fixed position of the storage macro cells (to avoid subsequent placement disturbances); and set the wiring channel width (to reserve signal transmission paths).
[0044] The initial design data is a DEF (Design Exchange Format) file, which records core information such as chip layout boundaries, power network topology, physical cell locations, and key area constraints.
[0045] S2. The initial design data is used as input to the physical synthesis tool, and the physical synthesis tool is used to place multiple standard cells of the chip to be designed to obtain preliminary placement results; wherein, the preliminary placement results include the placement coordinates of each standard cell.
[0046] In this embodiment of the invention, the standard units of the chip to be designed (such as NAND gates, flip-flops, multiplexers, etc., which constitute the basic units of operation, control, and storage logic) are globally placed based on the initial design data.
[0047] S3. Based on the placement coordinates, extract the invalid cells from the multiple standard cells, use the invalid cells as input to the placement and routing tool, adjust the invalid cells based on the placement and routing tool, obtain the chip physical layout design result, and realize the physical synthesis and placement and routing of the chip to be designed.
[0048] In this embodiment of the invention, the illegal cell refers to the standard cell whose placement position does not satisfy the cell alignment constraint, row constraint, and overlap constraint of the layout and routing tool.
[0049] Specifically, a standard cell that does not meet the overlap constraint refers to two or more standard cells whose physical areas overlap each other; a cell that does not meet the row constraint refers to a cell whose placement does not conform to the cell row boundary preset by the chip process; and a cell that does not meet the cell alignment constraint refers to a cell whose placement position exceeds the functional area / overall chip layout boundary defined in step S1.
[0050] In this embodiment of the invention, when adjusting the illegal cells, the placement and routing tool performs minimal positional adjustments while maintaining the relative positions between the physical cells. For example, when adjusting illegal cells, the relative positional relationship of all cells (including illegal and legal cells) remains unchanged (e.g., cell A is to the left of cell B, 10μm away, and this relative position is maintained after adjustment); only the illegal cells are moved to the nearest legal position (e.g., overlapping cells are laterally offset, and out-of-bounds cells are pulled back into the functional area), without changing the global layout topology; timing optimization or congestion optimization is not re-executed (only manufacturability is guaranteed, and the optimization results of step S2 are retained). This results in a fully legalized chip physical layout design, which is a DEF file. While satisfying the manufacturability rules of the placement and routing tool (no overlap, aligned row boundaries, no out-of-bounds), the timing optimization decisions of the physical synthesis stage are maximized. This invention effectively avoids congestion and timing result deviations caused by differences in placement algorithms between different tools by eliminating repeated placement steps in the placement and routing stage.
[0051] Compared to existing technologies, this invention directly uses the cell placement results completed but not yet legalized during the physical synthesis phase as input to the place-and-route tool, and performs the legalization operation only within the place-and-route tool. This approach maximizes the retention of the physical synthesis tool's placement decisions during the place-and-route phase, thereby reducing the need for complete placement operations in the place-and-route tool and performing legalization only on invalid cells, significantly shortening the physical implementation cycle; improving the consistency between physical synthesis and place-and-route results, avoiding placement deviations due to differences in tool algorithms, and enhancing consistency in congestion and timing performance; reducing the risk of physical synthesis optimization failure, minimizing placement disturbances caused by repeated placement, and effectively retaining the optimization results from the physical synthesis phase in subsequent processes.
[0052] Example 2
[0053] This invention also provides a chip physical synthesis and placement / routing system, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the physical synthesis and placement and routing system 200 for a chip provided in an embodiment of the present invention, which includes:
[0054] The physical integration and cabling system includes:
[0055] 201. Initial design module, used to construct the power network of the chip to be designed based on the placement and routing tool, insert the physical units and physical parameters required by the chip to be designed into the power network, and obtain the initial design data.
[0056] In this embodiment of the invention, the physical parameters include physical constraint information, physical area planning information, and physical environment information.
[0057] In this embodiment of the invention, when constructing the power network, a complete power distribution network (PDN) for the chip to be designed is built, including the main power line (VDD / VSS), branch power lines, and power contact (Pad) layout, to ensure that each functional module of the chip (such as the arithmetic unit, storage unit, and interface module) can obtain a stable power supply.
[0058] When inserting physical units, the physical units required by the chip to be designed are added to the chip layout, such as substrate contact units (used to avoid parasitic latch-up effects caused by substrate levitation and to ensure the stability of substrate potential), end cap units (must be placed at the edge of the core logic area to ensure uniformity of photolithography pattern density and prevent edge effects), decoupling units (used to suppress dynamic voltage drop and reduce power supply noise) and other non-logic functions but physical entities that ensure chip manufacturability and reliability.
[0059] When setting physical parameters, based on the functional requirements of the chip to be designed, define the rules for key areas on the chip layout. For example, set the layout area of the core computing module (such as the multiplier) as a dedicated area that other units are prohibited from intruding into; limit the I / O interface units to be arranged along the chip edge; clarify the fixed position of the storage macro cells (to avoid subsequent placement disturbances); and set the wiring channel width (to reserve signal transmission paths).
[0060] The initial design data is a DEF (Design Exchange Format) file, which records core information such as chip layout boundaries, power network topology, physical cell locations, and key area constraints.
[0061] 202. Placement module, used to take the initial design data as input to the physical synthesis tool, and place multiple standard cells of the chip to be designed through the physical synthesis tool to obtain preliminary placement results; wherein, the preliminary placement results include the placement coordinates of each standard cell.
[0062] In this embodiment of the invention, the standard units of the chip to be designed (such as NAND gates, flip-flops, multiplexers, etc., which constitute the basic units of operation, control, and storage logic) are globally placed based on the initial design data.
[0063] 203. Adjustment module, used to extract invalid cells from multiple standard cells according to the placement coordinates, use the invalid cells as input to the placement and routing tool, adjust the invalid cells based on the placement and routing tool, obtain the chip physical layout design result, and realize the physical synthesis and placement and routing of the chip to be designed.
[0064] In this embodiment of the invention, the illegal cell refers to the standard cell whose placement position does not satisfy the cell alignment constraint, row constraint, and overlap constraint of the layout and routing tool.
[0065] Specifically, a standard cell that does not meet the overlap constraint refers to two or more standard cells whose physical areas overlap each other; a cell that does not meet the row constraint refers to a cell whose placement does not conform to the cell row boundary preset by the chip process; and a cell that does not meet the cell alignment constraint refers to a cell whose placement position exceeds the functional area / overall chip layout boundary defined in step S1.
[0066] In this embodiment of the invention, when adjusting the illegal cells, the placement and routing tool performs minimal positional adjustments while maintaining the relative positions between the physical cells. For example, when adjusting illegal cells, the relative positional relationship of all cells (including illegal and legal cells) remains unchanged (e.g., cell A is to the left of cell B, 10μm away, and this relative position is maintained after adjustment); only the illegal cells are moved to the nearest legal position (e.g., overlapping cells are laterally offset, and out-of-bounds cells are pulled back into the functional area), without changing the global layout topology; timing optimization or congestion optimization is not re-executed (only manufacturability is guaranteed, and the optimization results of step S2 are retained). This results in a fully legalized chip physical layout design, which is a DEF file. While satisfying the manufacturability rules of the placement and routing tool (no overlap, aligned row boundaries, no out-of-bounds), the timing optimization decisions of the physical synthesis stage are maximized. This invention effectively avoids congestion and timing result deviations caused by differences in placement algorithms between different tools by eliminating repeated placement steps in the placement and routing stage.
[0067] The physical synthesis and placement and routing system 200 of the chip can implement the steps in the physical synthesis and placement and routing method of the chip as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.
[0068] Example 3
[0069] This invention also provides a computer device, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a physical synthesis and placement and routing program for a chip stored in the memory 302 and capable of running on the processor 301.
[0070] The processor 301 calls the chip physical synthesis and placement / routing program stored in the memory 302, and executes the steps in the chip physical synthesis and placement / routing method provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps:
[0071] S1. Construct the power network of the chip to be designed based on the placement and routing tool, and insert the physical units and physical parameters required by the chip to be designed into the power network to obtain the initial design data.
[0072] S2. The initial design data is used as input to the physical synthesis tool, and the physical synthesis tool is used to place multiple standard cells of the chip to be designed to obtain preliminary placement results; wherein, the preliminary placement results include the placement coordinates of each standard cell;
[0073] S3. Based on the placement coordinates, extract the invalid cells from the multiple standard cells, use the invalid cells as input to the placement and routing tool, adjust the invalid cells based on the placement and routing tool, obtain the chip physical layout design result, and realize the physical synthesis and placement and routing of the chip to be designed.
[0074] The computer device 300 provided in this embodiment of the invention can implement the steps in the chip physical synthesis and placement and routing method as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.
[0075] Example 4
[0076] This invention also provides a computer-readable storage medium storing a chip physical synthesis and placement and routing program. When the chip physical synthesis and placement and routing program is executed by a processor, it implements the various processes and steps in the chip physical synthesis and placement and routing method provided in this invention and can achieve the same technical effect. To avoid repetition, it will not be described again here.
[0077] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer programs or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0078] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0079] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.
[0080] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.
Claims
1. A method of physical synthesis and placement and routing of a chip, characterized by, The physical synthesis and placement / routing method includes the following steps: S1. Construct the power network of the chip to be designed based on the placement and routing tool, and insert the physical units and physical parameters required by the chip to be designed into the power network to obtain the initial design data. S2. The initial design data is used as input to the physical synthesis tool, and the physical synthesis tool is used to place multiple standard cells of the chip to be designed to obtain preliminary placement results; wherein, the preliminary placement results include the placement coordinates of each standard cell; S3. Extract the invalid cells from the multiple standard cells according to the placement coordinates, use the invalid cells as input to the placement and routing tool, adjust the invalid cells based on the placement and routing tool, and obtain the chip physical layout design result to realize the physical synthesis and placement and routing of the chip to be designed. The physical parameters include physical constraint information, physical area planning information, and physical environment information; When adjusting the illegal units, the layout and routing tool makes minimal position adjustments to the illegal units while keeping the relative positions between the physical units unchanged. The illegal cell refers to the standard cell whose placement does not meet the cell alignment constraints, row constraints, and overlap constraints of the layout and routing tool.
2. A system for physical synthesis and placement and routing of a chip, characterized by The physical integration and cabling system includes: The initial design module is used to construct the power network of the chip to be designed based on the placement and routing tool, insert the physical units and physical parameters required by the chip to be designed into the power network, and obtain the initial design data. The placement module is used to take the initial design data as input to the physical synthesis tool, and place multiple standard cells of the chip to be designed through the physical synthesis tool to obtain preliminary placement results; wherein, the preliminary placement results include the placement coordinates of each standard cell; An adjustment module is used to extract invalid cells from the plurality of standard cells according to the placement coordinates, use the invalid cells as input to the placement and routing tool, adjust the invalid cells based on the placement and routing tool, obtain the chip physical layout design result, and realize the physical synthesis and placement and routing of the chip to be designed; wherein, the invalid cell refers to the standard cell whose placement position does not meet the cell alignment constraint, row constraint, and overlap constraint of the placement and routing tool; The physical parameters include physical constraint information, physical area planning information, and physical environment information; When adjusting the illegal units, the layout and routing tool makes minimal position adjustments to the illegal units while keeping the relative positions between the physical units unchanged.
3. A computer device, comprising: include: A memory, a processor, and a physical synthesis and placement / routing program for a chip stored in the memory and executable on the processor, wherein the processor, when executing the physical synthesis and placement / routing program for the chip, implements the steps of the physical synthesis and placement / routing method for the chip as described in claim 1.
4. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a chip physical synthesis and layout routing program, and the chip physical synthesis and layout routing program, when executed by the processor, implements the steps in the chip physical synthesis and layout routing method of claim 1.