Nondestructive data reading method of ferroelectric memory

Abstract

The invention provides a non-destructive data reading method for a ferroelectric memory, and relates to the technical field of semiconductor memories, and the method comprises the steps: S1, applying a subthreshold reading voltage; s2, detecting a polarization response signal; s3, comparing and judging a logic state; the method has thorough non-destructiveness, the polarization direction of the ferroelectric capacitor cannot be overturned in the whole read operation process, and original storage data can be completely reserved. The write-back operation necessary for the traditional method is fundamentally eliminated. Delay and power consumption can be reduced, energy consumed by write-back operation is avoided, and dynamic power consumption is remarkably reduced; the read-write service life of the ferroelectric memory is greatly prolonged; and the design flexibility and robustness are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory technology, and more specifically, to a non-destructive data reading method for ferroelectric memory. Background Technology

[0002] Ferroelectric memories (FEMs) are a novel type of non-volatile memory that utilizes ferroelectric materials as the storage medium. They offer advantages such as high read / write speeds, low power consumption, a high number of erase / write cycles, and radiation resistance, making them ideal for embedded systems, IoT devices, data center caches, and aerospace applications. This contributes to the development of electronic systems towards high speed, low power consumption, and high reliability. The core of a FEM's storage cell is a ferroelectric capacitor, and its data storage mechanism stems from the unique bistable polarization characteristics of ferroelectric materials. Under the influence of an external electric field, the electric dipoles within the ferroelectric material align along the field direction, generating a polarization intensity P. When the external electric field is removed, the material retains a certain residual polarization intensity ±Pr. The state corresponding to -Pr is typically defined as logic "0," and the state corresponding to +Pr as logic "1." When writing data, a pulse voltage exceeding the coercive voltage ±Vc is applied across the ferroelectric capacitor, forcing its polarization state to flip to the target state. However, traditional FEM read operations suffer from a fundamental problem: the read operation is destructive. In traditional read operations, a voltage pulse sufficient to force the polarization state of a ferroelectric capacitor to flip to a reference direction, such as a logic "1", is applied. The original stored data is determined by detecting the amount of charge released or the resulting bit line voltage difference after comparison with the reference capacitor. If the original stored value is "1", the charge transfer during the flip is small; if the original stored value is "0", the charge transfer is large. This method results in the polarization state of the ferroelectric capacitor being uniformly rewritten to "1" after each read operation, regardless of the original data. Therefore, a "write-back" operation must follow each read operation to rewrite the read data back into the cell to restore its original state. This not only increases the total latency and power consumption of the read operation but also accelerates the fatigue aging of the ferroelectric material due to frequent polarization flips, affecting the durability of the memory.

[0003] Existing non-destructive readout methods for ferroelectric capacitors typically utilize ferroelectric field-effect transistors (FeFETs) or employ special circuits to sense minute signals at voltages far below the coercive voltage. However, these methods often suffer from poor process compatibility, weak and difficult-to-detect signals, or the need for complex reference circuits, making stable application in large-scale arrays difficult. Therefore, there is an urgent need for a non-destructive data readout method for ferroelectric memories that is clear in principle, easy to implement, and compatible with existing CMOS processes, in order to completely eliminate write-back operations, reduce read latency and power consumption, and improve the overall performance and reliability of the memory. Summary of the Invention

[0004] The present invention aims to solve the problems of poor process compatibility, weak signal that is difficult to detect, or the need for complex reference circuits in the non-destructive readout of existing ferroelectric capacitors.

[0005] To address the above problems, this invention provides a non-destructive data reading method for ferroelectric memory, comprising the following steps: Step S1: Apply a subthreshold read voltage; apply a read voltage V_read to the ferroelectric capacitor to be read. The absolute value of V_read is less than the absolute value of the coercivity voltage V_c of the ferroelectric material used in the ferroelectric capacitor, that is, |V_read|<|V_c|. Step S2: Detect the polarization response signal; before and after applying the reading voltage V_read, detect the change in physical signal ΔS caused by the change in polarization intensity of the ferroelectric capacitor; Step S3: Compare and determine the logic state; compare the detected signal change ΔS or its characteristics with a preset threshold or reference signal; based on the comparison result, determine that the logic value currently stored in the ferroelectric capacitor is either the first logic value "1" or the second logic value "0".

[0006] The present invention provides a non-destructive data reading method for ferroelectric memory, which, compared with the prior art, has the following beneficial effects, but is not limited to: This invention is completely non-destructive: because the read voltage is always lower than the coercive voltage, the polarization direction of the ferroelectric capacitor does not reverse during the entire read operation, and the original stored data is completely preserved. This fundamentally eliminates the "write-back" operation required by traditional methods.

[0007] This invention reduces latency and power consumption: by eliminating the write-back cycle, read operation time is significantly shortened, approaching the theoretical fastest read speed. Simultaneously, it avoids the energy consumed by write-back operations, significantly reducing dynamic power consumption.

[0008] This invention improves durability: read operations no longer trigger fatigue-induced polarization reversals, but only involve reversible linear or quasi-linear responses, greatly extending the read and write life of ferroelectric memories.

[0009] This invention improves design flexibility and robustness: Based on a well-defined physical model—the relationship between capacitance, polarization, and voltage—the read voltage V_read can be precisely designed and optimized according to specific material parameters and circuit performance, offering strong adaptability. It effectively suppresses process fluctuations and noise interference, improving read reliability and yield.

[0010] This invention has good compatibility: it does not require disruptive process changes, and the main improvements are in the design of the read voltage generation circuit and the sensitive amplifier, which are easy to implement and integrate on existing technology platforms.

[0011] Furthermore, the characteristics of the change ΔS include polarity and magnitude.

[0012] Furthermore, the physical signal change ΔS is the voltage signal change ΔV between the plates of the ferroelectric capacitor.

[0013] Further, step S2 specifically includes: before and after applying V_read, detecting the voltage signal change ΔV of one plate of the ferroelectric capacitor relative to the other plate, that is, the ferroelectric capacitor is in the initial polarization state P_initial, P_initial=±Pr, corresponding to an initial terminal voltage, which can be regarded as zero or a certain reference; after applying V_read, the polarization intensity changes along the small loop of the hysteresis loop to P_new, which causes the induced charge on the capacitor plate to change ΔQ, and the charge change is converted into a detectable voltage signal change ΔV=ΔQ / C, where C is the geometric capacitance value of the ferroelectric capacitor.

[0014] Furthermore, the determination logic in step S3 is as follows: if the polarity or sign of ΔV is detected to be in the first direction, then the determination storage logic is "0"; if the polarity of ΔV is in the second direction opposite to the first direction, then the determination storage logic is "1".

[0015] Furthermore, the amplitude of the read voltage V_read must satisfy a dual constraint condition: Constraint C1 is a non-destructive condition: |V_read| < |V_c|, ensuring that the polarization direction is not reversed.

[0016] Constraint C2 Detectability condition: The voltage signal change ΔV caused by V_read is greater than or equal to the smallest resolvable window V_SA of the signal detection module in the readout circuit, i.e., |ΔV|≥V_SA.

[0017] Furthermore, the calculation model for the voltage signal change ΔV is as follows: Calculate the geometric capacitance C of a ferroelectric capacitor: C = ε0 εr A / d, Where ε0 is the vacuum permittivity, εr is the relative permittivity of the ferroelectric material under high frequency or small signal conditions, A is the effective area of ​​the capacitor, and d is the thickness of the ferroelectric thin film. Calculate the change in polarization intensity ΔP: ΔP = P_new - P_initial, P=ε0 (εr-1) E+P_rem, where E is the electric field and P_rem is the remanent polarization; Calculate the equivalent charge change ΔQ: ΔQ = ΔP A.

[0018] Calculate the voltage signal change ΔV: ΔV = ΔQ / C = (ΔP) d) / (ε0 εr).

[0019] Furthermore, the method of applying the read voltage V_read is either a single fixed-level application, or a multi-level step voltage scan or a pulse sequence of a specific shape; The multi-stage step voltage scan application method for applying the read voltage V_read is specifically as follows: Step S2 includes detecting the corresponding signal change at each voltage level to obtain the response curve of the signal change versus the applied voltage; Step S3 includes determining the logic state stored in the ferroelectric capacitor by analyzing the characteristics of the response curve.

[0020] Furthermore, in step S2, each stage of voltage detection adopts a differential detection method; the ferroelectric capacitor to be read and a reference capacitor are respectively connected to the two input terminals of a differential amplifier; the same reading voltage V_read or a reading voltage with a definite relationship is applied to the ferroelectric capacitor and the reference capacitor. The reference capacitor is a ferroelectric capacitor with the same structure as the ferroelectric capacitor under test, and is preset and maintained in a fixed polarization state.

[0021] Furthermore, a ferroelectric memory includes a storage array comprising ferroelectric storage cells for reading operations using the above-described method; a read voltage generation circuit configured to generate a read voltage V_read whose absolute value is less than the coercivity voltage V_c of the ferroelectric material; and a signal detection and decision circuit configured to detect signal changes caused by the application of the read voltage V_read and determine the stored logic state accordingly. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the non-destructive data reading method for ferroelectric memory according to an embodiment of the present invention; Figure 2 The hysteresis loop model for ferroelectric capacitors; Figure 3 This is the hysteresis loop of the ferroelectric capacitor in the embodiment. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings showing multiple embodiments according to this application. It should be understood that the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments described in this application without creative effort will fall within the scope of protection of this application.

[0024] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing specific embodiments only and is not intended to limit this application; the terms "comprising," "including," "having," "containing," etc., in the description, claims, and accompanying drawings of this application are open-ended terms. Therefore, "comprising," "including," or "having" refers to, for example, a method or apparatus having one or more steps or elements, but is not limited to having only these one or more elements. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0025] In the description of this invention, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0026] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0027] It should be emphasized that when the term "comprising / including" is used in this specification, it is used to explicitly indicate the presence of the stated feature, integer, step, or component, but does not exclude the presence or addition of one or more other features, integers, steps, parts, or groups of features, integers, steps, or parts.

[0028] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0029] See Figures 1-3 A non-destructive data reading method for a ferroelectric memory according to an embodiment of the present invention includes the following steps: Step S1: Apply a subthreshold read voltage; apply a read voltage V_read to the ferroelectric capacitor to be read. The absolute value of V_read is less than the absolute value of the coercivity voltage V_c of the ferroelectric material used in the ferroelectric capacitor, that is, |V_read|<|V_c|; the application of this voltage causes the ferroelectric capacitor to operate in the non-saturated, non-flipping region of its hysteresis loop; Step S2: Detect the polarization response signal; Before and after applying the reading voltage V_read, detect the change in physical signal ΔS caused by the change in polarization intensity of the ferroelectric capacitor; the change ΔS is directly related to the initial residual polarization state +Pr or -Pr of the ferroelectric capacitor and the polarity of the reading voltage V_read.

[0030] Step S3: Compare and determine the logic state; compare the detected signal change ΔS or its characteristics with a preset threshold or reference signal; based on the comparison result, determine that the logic value currently stored in the ferroelectric capacitor is either the first logic value "1" or the second logic value "0".

[0031] Step S1 of this invention creates non-destructive detection conditions and forms the physical basis of the entire method, representing the minimum voltage required to permanently reverse the polarization direction. Applying a voltage V_read below this value means that the electric field strength is insufficient to overcome the potential barrier within the ferroelectric lattice, preventing the electric dipoles from collectively "jumping" to another steady state. Under this voltage, the ferroelectric capacitor does not remain absolutely stationary. Its electric dipoles will undergo reversible elastic shifts or tilts under the influence of the electric field, resulting in a small, continuous change ΔP in the macroscopic polarization intensity P based on the original remanent polarization +Pr or -Pr. This change corresponds to a small loop or linear response trajectory on the hysteresis loop starting from the remanent polarization point, rather than a large jump across the center of the loop.

[0032] Step S2 converts the microscopic polarization state, which cannot be directly observed, into a macroscopic electrical signal that can be measured and processed by the circuit. The change in physical signal ΔS detected in this step originates from the change in polarization intensity ΔP generated in step S1. According to electromagnetic principles, the change in polarization intensity of a ferroelectric material is equivalent to the change in its surface bound charge density.

[0033] Signal Conversion: For a parallel-plate capacitor structure, the polarization change ΔP directly causes a change (ΔQ) in the amount of induced free charge on the capacitor plates. This charge change can be converted into an easily measurable voltage signal change ΔV or current pulse ΔI through a circuit.

[0034] Step S3 performs a digital decision on the detected analog signal, outputting a determined logic value of "0" or "1", thus completing the information extraction for the read operation. This step utilizes the characteristics of the signal ΔS detected in step S2 for decision-making. The most important characteristic is polarity, such as the positive or negative sign of voltage changes. The decision logic can be very straightforward: The NDRO process of this invention is as follows: Apply subthreshold voltage (i.e., non-destructive detection) → Detect the polarity of a small signal → Decision. The process ends without write-back. This eliminates the time-consuming write-back cycle, significantly reduces read latency, avoids the energy consumption of high-voltage write-back after each read operation, prevents material fatigue caused by read operations, greatly extends device lifespan, and avoids the risk of data errors due to write-back failures.

[0035] This invention is completely non-destructive: because the read voltage is always lower than the coercive voltage, the polarization direction of the ferroelectric capacitor does not reverse during the entire read operation, and the original stored data is completely preserved. This fundamentally eliminates the "write-back" operation required by traditional methods.

[0036] This invention reduces latency and power consumption: by eliminating the write-back cycle, read operation time is significantly shortened, approaching the theoretical fastest read speed. Simultaneously, it avoids the energy consumed by write-back operations, significantly reducing dynamic power consumption.

[0037] This invention improves durability: read operations no longer trigger fatigue-induced polarization reversals, but only involve reversible linear or quasi-linear responses, greatly extending the read and write life of ferroelectric memories.

[0038] This invention improves design flexibility and robustness: Based on a well-defined physical model—the relationship between capacitance, polarization, and voltage—the read voltage V_read can be precisely designed and optimized according to specific material parameters and circuit performance, exhibiting strong adaptability. Employing differential detection and other circuit technologies effectively suppresses process fluctuations and noise interference, improving read reliability and yield.

[0039] This invention has good compatibility: the method can be combined with existing mainstream photosensitive array structures such as 1T1C or 2T2C without disruptive process changes. The main improvements are in the design of the read voltage generation circuit and the sensitive amplifier, which are easy to implement and integrate on existing technology platforms.

[0040] Furthermore, the characteristics of the change ΔS include polarity and magnitude.

[0041] The polarity characteristic directly corresponds to the stored logic state. Applying the same V_read, cells storing "0" and "1" produce ΔS with opposite polarities; for example, one raises the bit line voltage, and the other lowers it. This makes the decision logic simple, direct, and robust. The sensitive amplifier is essentially a high-performance comparator that makes a logic decision simply by detecting the sign (positive or negative), without needing to precisely measure the absolute value, greatly reducing circuit design complexity and the false positive rate.

[0042] The magnitude characteristic represents the absolute value of the signal strength, such as |ΔV| in millivolts. It must be large enough to distinguish it from circuit noise and process variations. This ensures the signal can be reliably detected by sensitive amplifiers in modern CMOS processes. The magnitude of ΔS directly affects the signal-to-noise ratio and yield of the read operation.

[0043] Furthermore, the physical signal change ΔS is preferably the voltage signal change ΔV between the plates of the ferroelectric capacitor.

[0044] Choosing ΔV as the signal allows for seamless integration with existing, highly mature and optimized sensitive amplifier technologies in memory architectures. This eliminates the need to develop entirely new, high-risk charge or current sensing circuits, significantly reducing the implementation threshold and design risk.

[0045] Voltage signals can be directly and losslessly sampled and amplified through amplifier nodes with high input impedance. Sensitive amplifiers can amplify millivolt-level ΔV to full-swing logic levels 0V or VDD within the picosecond to nanosecond range.

[0046] In contrast, detecting charge ΔQ requires a complex charge integrating amplifier, which is slower; detecting current ΔI requires a low-noise transimpedance amplifier and is more sensitive to parasitic capacitance.

[0047] Further, step S2 specifically includes: before and after applying V_read, detecting the voltage signal change ΔV of one plate of the ferroelectric capacitor relative to the other plate, that is, the ferroelectric capacitor is in the initial polarization state P_initial, P_initial=±Pr, corresponding to an initial terminal voltage, which can be regarded as zero or a certain reference; after applying V_read, the polarization intensity changes along the small loop of the hysteresis loop to P_new, which causes the induced charge on the capacitor plate to change ΔQ. Under the assumption that the capacitance value C is basically constant, that is, for small signal disturbances, this charge change is converted into a detectable voltage signal change ΔV=ΔQ / C.

[0048] This application establishes a complete, quantifiable, and predictable signal generation model. The root cause of the signal ΔV is the polarization intensity change ΔP, i.e., P_new - P_initial, rather than other interfering factors. The conversion mechanism links the microscopic polarization change with the macroscopic measurable charge ΔQ in the circuit through the electrostatic principle of polarization → surface bound charge → plate free charge. The final characterization uses the fundamental capacitor formula ΔV = ΔQ / C to convert the charge change into a directly detectable voltage change. It provides non-destructive quantitative criteria and design boundaries, enabling accurate modeling and optimization of the signal link.

[0049] Further, the determination logic in step S3 is as follows: if the polarity or sign of ΔV is detected to be in the first direction, for example, the voltage of the upper plate increases relative to the lower plate, then the storage logic is determined to be "0"; if the polarity of ΔV is in the second direction opposite to the first direction, for example, the voltage of the upper plate decreases relative to the lower plate, then the storage logic is determined to be "1". This polarity relationship is jointly determined by the application direction of V_read, the initial polarization direction of the ferroelectric capacitor, and the connection method of the detection circuit.

[0050] The rules clearly define the one-to-one correspondence between polarity and logic values. For example, "voltage increase = 0", "voltage decrease = 1". This avoids the "intermediate state" misjudgment problem that may occur in traditional DRO because DRO relies on the comparison of charge magnitudes, which has a fuzzy reference point. Binary decision: It guides circuit design towards the most reliable binary decision mode. A sensitive amplifier is essentially a "zero-crossing comparator" or a comparison with a fixed reference voltage. As long as the polarity of ΔV is clear, the amplifier output is a stable, unambiguous high or low level, fundamentally eliminating "metastability" or "readout errors".

[0051] Furthermore, the amplitude of the read voltage V_read must satisfy a dual constraint condition: Constraint C1 is a non-destructive condition: |V_read| < |V_c|, ensuring that the polarization direction is not reversed.

[0052] Constraint C2 Detectability condition: The signal change |ΔS| caused by V_read, such as |ΔV|, must be greater than or equal to the minimum resolvable window V_SA of the signal detection module such as the sensitive amplifier in the readout circuit, that is, |ΔS|≥V_SA.

[0053] Constraint C1 ensures that the polarization direction of the ferroelectric capacitor, the physical carrier of stored data, cannot be erased or altered, providing a mathematical guarantee for the fundamental commitment of "non-destructiveness." Constraint C2, |ΔS|≥V_SA, defines the lower limit of the method's engineering feasibility. It ensures that the physical signal generated by this safe operation can be reliably detected and identified by subsequent circuits, providing a performance guarantee for the "readable" functional requirement.

[0054] Furthermore, the calculation model for the voltage signal change ΔV is as follows: Calculate the geometric capacitance C of a ferroelectric capacitor: C = ε0 εr A / d, Where ε0 is the vacuum permittivity, εr is the relative permittivity of the ferroelectric material under high frequency or small signal conditions, A is the effective area of ​​the capacitor, and d is the thickness of the ferroelectric thin film. Calculate the change in polarization intensity ΔP: ΔP = P_new - P_initial. P_new can be obtained from the measured small-signal hysteresis loop of ferroelectric materials or through linear approximation, P = ε0. (εr-1) E+P_rem, where E is the electric field and P_rem is the remanent polarization; for a typical square hysteresis loop, in the interval |V|<|V_c|, ΔP can be approximated as having a linear relationship with V_read, and the slope has opposite signs depending on the initial polarization direction.

[0055] Calculate the equivalent charge change ΔQ: ΔQ = ΔP A.

[0056] Calculate the voltage signal change ΔV: ΔV = ΔQ / C = (ΔP) d) / (ε0 εr).

[0057] Therefore, ΔV is independent of the capacitance area A, but is directly related to the ferroelectric thin film thickness d, the material dielectric constant εr, and the polarization change ΔP.

[0058] This invention provides a precise measure of "non-destructive strength" and a design margin ΔP, which is a macroscopic measure of the reversible microscopic perturbations experienced by ferroelectric materials under subthreshold voltages. The model allows us to accurately calculate ΔP caused by each read operation, thereby quantitatively assessing how little "stress" the operation places on the material. During design, a quantified safety factor can be established between the destructive ΔP corresponding to V_c (~2Pr) and the read operation ΔP. For example, ensuring that the ΔP of the read operation is only 1 / 10 of the ΔP required for the flip. This allows reliability design to move from qualitative to quantitative. Accurate prediction and co-optimization of system-level performance are achieved in the early stages of chip design, without tape-out, based on material data and process parameters d, εr, to accurately predict the magnitude of ΔV. This allows circuit teams to design the gain and timing of sensitive amplifiers in advance, potentially leading to successful chip design in the first round, significantly shortening the development cycle and reducing costs.

[0059] Furthermore, it also includes a read voltage calibration step S0, used to determine the specific value of the read voltage V_read; step S0 includes: based on the physical parameters of the ferroelectric capacitor, the electrical characteristic parameters of the ferroelectric material, and the performance parameters of the signal detection module, by calculation or experimental testing, determining a voltage value that simultaneously satisfies the constraint conditions C1 and C2 as the read voltage V_read.

[0060] To adapt to different process nodes, different ferroelectric materials such as PZT, SBT, HfO2-based doped materials such as HZO, and different sensitive amplifier performance, the method includes a read voltage calibration step S050 to determine the optimal V_read value. This calibration step involves finding a V_read value that simultaneously satisfies constraints C1 and C2 as the operating voltage, based on the actual physical parameters of the ferroelectric capacitance (εr, d, V_c, etc.) and the measured resolution V_SA of the sensitive amplifier, through inverse solving of the computational model or through experimental scanning tests.

[0061] Furthermore, the reading voltage V_read can be applied in the form of a single fixed level application, or in the form of a multi-level stepped voltage scan or a pulse sequence of a specific shape. By monitoring the signal response curve during the multi-level scan process, the logic state can be distinguished more reliably and the noise immunity can be improved.

[0062] Single fixed-level application: This is the basic mode, embodying the core principles and highest speed potential of the method. Multi-stage stepped voltage scan / pulse sequence application: This is the enhanced mode, demonstrating the method's extremely high reliability and environmental adaptability. This signifies an upgrade in operating mode from a simple "on / off" stimulus to an intelligent "detector-response analysis" interaction.

[0063] Furthermore, the multi-stage step voltage scan application method for applying the read voltage V_read specifically involves: Step S2 includes detecting the corresponding signal change at each voltage level to obtain the response curve of the signal change versus the applied voltage; Step S3 includes determining the logic state stored in the ferroelectric capacitor by analyzing the characteristics of the response curve.

[0064] Traditional readings, including the single fixed-level mode of this invention, are "stimulus-single-point response-threshold decision" modes, which are essentially linear discriminations.

[0065] The "multi-level step-scanning + response curve analysis" model follows the pattern of "stimulus sequence - multidimensional response - pattern recognition," which is essentially a nonlinear feature discrimination. The upgrade transforms the reading process from a simple electrical measurement into a process of identifying the feature fingerprint of the physical state of ferroelectric units.

[0066] This invention can construct a multidimensional decision fortress, immune to various interferences, and the vulnerability of single-point decision: Although the polarity decision based on a single-point ΔV is more robust than traditional methods, it may still be interfered with by strong noise spikes of the same magnitude as the signal or abnormal responses caused by local defects.

[0067] Robustness of curve feature analysis: Extremely rich feature dimensions: Analyzable curve features include: overall shape, initial slope, inflection point voltage, saturation trend, area under the curve, symmetry, etc. Cells storing "0" and "1" exhibit systematic differences in these features in their response curves. Achieves true adaptive reading and cell health management.

[0068] Furthermore, in step S2, the detection at each voltage level adopts a differential detection method; the ferroelectric capacitor to be read and a reference capacitor are respectively connected to the two input terminals of a differential amplifier; the same reading voltage V_read or a reading voltage with a definite relationship is applied to the ferroelectric capacitor and the reference capacitor; the differential amplifier is used to amplify and output the difference between the signal changes generated by the ferroelectric capacitor and the reference capacitor.

[0069] The ferroelectric capacitor is paired with a reference capacitor and connected to both ends of the differential sensitive amplifier. The reference capacitor can be a "dummy" capacitor with the same structure as the ferroelectric capacitor (always in a fixed polarization state, such as the "0" state), or it can be a linear capacitor. After applying the same V_read, the voltage changes generated by the ferroelectric capacitor and the reference capacitor are different. The amplifier amplifies this difference for decision-making, thereby significantly improving the signal-to-noise ratio and decision accuracy.

[0070] Furthermore, the reference capacitor is a ferroelectric capacitor with the same structure as the ferroelectric capacitor under test, and is preset and maintained in a fixed polarization state.

[0071] Achieving ultimate common-mode noise suppression and environmental drift compensation, any environmental factors affecting the DUT, such as temperature changes, power supply fluctuations, mechanical stress, and timing jitter, will almost identically affect the adjacent, structurally identical reference capacitor in the same way and with the same amplitude, because the two are matched "ferroelectric" capacitors. In a differential amplifier, these common-mode interferences produce the same signal disturbances on both the DUT and the reference cell. When calculating the signal difference between the two (ΔV_DUT-ΔV_REF), these common-mode disturbances are almost perfectly canceled out. If a linear capacitor is used as a reference, its temperature coefficient and voltage coefficient differ from those of a ferroelectric capacitor, and the common-mode rejection ratio will be significantly reduced. This solution elevates the matching of the differential pair from the "circuit level" to the "physical material level," achieving optimal noise immunity.

[0072] A ferroelectric memory includes a storage array comprising ferroelectric storage cells for read operations performed by the method described above; a read voltage generation circuit configured to generate a read voltage V_read whose absolute value is less than the coercivity voltage V_c of the ferroelectric material; and a signal detection and decision circuit configured to detect signal changes caused by the application of the read voltage V_read and determine the stored logic state accordingly.

[0073] Because the device integrates read voltage generation and signal detection and decision circuitry optimized for subthreshold non-destructive reads, external users do not need to concern themselves with the complex internal operations. These specifications are testable and guaranteed, providing users with clear design expectations. System engineers can operate this ferroelectric memory using address, data, and control lines, just like using standard SRAM or Flash, without needing to design complex ferroelectric read control logic and sensitive analog detection circuits, significantly shortening product development cycles.

[0074] Achieving the optimal balance between power consumption, performance, and reliability, the internal circuitry is collaboratively optimized: Inside the chip, the read voltage generation circuit can precisely generate the optimal V_read, i.e., under the constraints of C1 and C2. The signal detection circuit, such as a high-precision differential sensitive amplifier, can be specifically optimized for the weak ΔV signal generated by this V_read. This deep collaborative optimization of the internal circuitry is unmatched by external discrete designs, enabling globally optimal energy efficiency and speed.

[0075] By eliminating interface losses and mismatches, all critical analog signals, such as V_read and ΔV, are transmitted on extremely short paths within the chip, avoiding noise, attenuation, and delay introduced by PCB-level traces and ensuring maximum core performance.

[0076] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.

Claims

1. A non-destructive data reading method for a ferroelectric memory, characterized in that, The steps are as follows: Step S1: Apply a subthreshold read voltage; apply a read voltage V_read to the ferroelectric capacitor to be read; the absolute value of V_read is less than the absolute value of the coercivity voltage V_c of the ferroelectric material used in the ferroelectric capacitor, that is, |V_read|<|V_c|. Step S2: Detect the polarization response signal; before and after applying the reading voltage V_read, detect the change in physical signal ΔS caused by the change in polarization intensity of the ferroelectric capacitor; Step S3: Compare and determine the logic state; compare the detected signal change ΔS or its characteristics with a preset threshold or reference signal; based on the comparison result, determine that the logic value currently stored in the ferroelectric capacitor is either the first logic value "1" or the second logic value "0".

2. The non-destructive data reading method for ferroelectric memory according to claim 1, characterized in that, The characteristics of the change ΔS include polarity and magnitude.

3. The non-destructive data reading method for ferroelectric memory according to claim 2, characterized in that, The physical signal change ΔS is the voltage signal change ΔV between the plates of the ferroelectric capacitor.

4. The non-destructive data reading method for ferroelectric memory according to claim 3, characterized in that, Step S2 specifically includes: before and after applying V_read, detecting the voltage signal change ΔV of one plate of the ferroelectric capacitor relative to the other plate, i.e., the ferroelectric capacitor is in the initial polarization state P_initial, P_initial=±Pr, corresponding to an initial terminal voltage; after applying V_read, the polarization intensity changes along the small loop of the hysteresis loop to P_new, which causes a change in the amount of induced charge on the capacitor plate ΔQ, and the charge change is converted into a detectable voltage signal change ΔV=ΔQ / C, where C is the geometric capacitance value of the ferroelectric capacitor.

5. The non-destructive data reading method for ferroelectric memory according to claim 4, characterized in that, The determination logic in step S3 is as follows: if the polarity or sign of ΔV is detected to be in the first direction, then the determination storage logic is "0"; if the polarity of ΔV is in the second direction opposite to the first direction, then the determination storage logic is "1".

6. The non-destructive data reading method for ferroelectric memory according to claim 5, characterized in that, The amplitude of the read voltage V_read must meet two constraints: Constraint C1 is a non-destructive condition: |V_read| < |V_c|, ensuring that the polarization direction is not reversed; Constraint C2 Detectability condition: The voltage signal change ΔV caused by V_read is greater than or equal to the smallest resolvable window V_SA of the signal detection module in the readout circuit, i.e., |ΔV|≥V_SA.

7. The non-destructive data reading method for ferroelectric memory according to claim 6, characterized in that, The calculation model for the voltage signal change ΔV is as follows: Calculate the geometric capacitance C of a ferroelectric capacitor: C = ε0 εr A / d, Where ε0 is the vacuum permittivity, εr is the relative permittivity of the ferroelectric material under high frequency or small signal conditions, A is the effective area of ​​the capacitor, and d is the thickness of the ferroelectric thin film. Calculate the change in polarization intensity ΔP: ΔP = P_new - P_initial, P=ε0 (εr-1) E+P_rem, where E is the electric field and P_rem is the remanent polarization; Calculate the equivalent charge change ΔQ: ΔQ = ΔP A; Calculate the voltage signal change ΔV: ΔV = ΔQ / C = (ΔP) d) / (ε0 εr).

8. The non-destructive data reading method for ferroelectric memory according to claim 4, characterized in that, The reading voltage V_read is applied in the form of a single fixed level application, or in the form of a multi-level step voltage scan or a pulse sequence of a specific shape. The multi-stage step voltage scan application method for applying the read voltage V_read is specifically as follows: Step S2 includes detecting the corresponding signal change at each voltage level to obtain the response curve of the signal change versus the applied voltage; Step S3 includes determining the logic state stored in the ferroelectric capacitor by analyzing the characteristics of the response curve.

9. The non-destructive data reading method for ferroelectric memory according to claim 8, characterized in that, In step S2, each voltage detection stage adopts a differential detection method; the ferroelectric capacitor to be read and a reference capacitor are respectively connected to the two input terminals of a differential amplifier; the same reading voltage V_read or a reading voltage with a definite relationship is applied to the ferroelectric capacitor and the reference capacitor; the reference capacitor is a ferroelectric capacitor with the same structure as the ferroelectric capacitor to be tested, and is preset and maintained in a fixed polarization state.

10. A ferroelectric memory, characterized in that, include: A storage array comprising a plurality of ferroelectric storage cells that are read by the method described in any one of claims 1 to 9; The read voltage generation circuit is configured to generate a read voltage V_read whose absolute value is less than the coercivity voltage V_c of the ferroelectric material; The signal detection and decision circuit is configured to detect signal changes caused by the application of read voltage V_read, and determine the stored logic state accordingly.

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