Operation method of memory, memory and memory system

Abstract

The embodiment of the invention provides an operation method of a memory, the memory and a storage system. The operation method comprises the following steps: obtaining at least one group of reading voltages; each group of reading voltage in the at least one group of reading voltage comprises an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value; the initial voltage value in each group of reading voltages is a preset reading voltage used for distinguishing two adjacent storage states of a storage unit of the memory; respectively executing reading operation based on the initial voltage value and the offset voltage value in the at least one group of reading voltage, and obtaining the number of the storage units of which the reading result corresponding to each voltage value meets a set condition; determining a difference value between two numbers corresponding to every two adjacent voltage values belonging to the same group of reading voltages; and determining an optimal reading voltage for distinguishing the two adjacent storage states based on the difference value.

Description

[0001] Case Analysis This application is a divisional application of the patent filed on October 20, 2022, with application number 202211288018.7 and entitled "An operating method for a memory, a memory and a storage system". Technical Field

[0002] This application relates to the field of memory technology, and in particular to a method for operating a memory, a memory, and a storage system. Background Technology

[0003] Recently, with the development of memory, memory can be either volatile or non-volatile. Non-volatile memory can retain data even when no power is applied, and therefore it is widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices, especially 3D NAND flash memory. 3D NAND flash memory achieves data storage by capturing and storing charge in the gate dielectric layer of its contained memory cells. However, as storage time increases, the charge in the gate dielectric layer of the memory cells slowly leaks out; and when the memory cells are repeatedly read, the charge in the gate dielectric layer of the memory cells is captured again, similar to programming. In any case, the change in the charge in the gate dielectric layer of the memory cells causes a change in the threshold voltage of the memory cells, thus affecting the correctness of reading the data stored in the memory cells. Summary of the Invention

[0004] In view of the above, this application provides a method for operating a memory, a memory, and a storage system to solve the aforementioned technical problems.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows: In a first aspect, embodiments of this application provide a method for operating a memory, including: At least one set of read voltages is obtained; each set of read voltages includes an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of the memory cell; Based on the initial voltage value and offset voltage value in the at least one set of read voltages, a read operation is performed to obtain the number of storage cells whose read results for each voltage value meet the set conditions. Determine the difference between the two quantities corresponding to every two adjacent voltage values ​​belonging to the same group of read voltages; The optimal read voltage for distinguishing the two adjacent memory states is determined based on the difference.

[0006] Secondly, embodiments of this application also provide a memory, including: a memory array, the memory array including memory cells; and peripheral circuitry coupled to the memory array and configured to control the memory array; The peripheral circuit is configured to perform the operation method described above.

[0007] Thirdly, embodiments of this application also provide a storage system, including: one or more of the aforementioned memories; and a memory controller coupled to the memories; the memory controller is configured to: send a first command to the memories; the memories are configured to: execute the aforementioned operation method in response to the first command.

[0008] Fourthly, embodiments of this application also provide a storage system, including: one or more memories; and a memory controller coupled to the memories; wherein, The memory controller is configured to: obtain at least one set of read voltages; each set of read voltages includes an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of the memory cell; and send corresponding read commands to a storage surface contained in the memory based on the initial voltage value and the offset voltage value in the at least one set of read voltages. The memory is configured to: read the corresponding storage surface in response to the corresponding read command; and send the read result of each storage cell in the storage surface to the memory controller; The memory controller is further configured to: receive the read result; count the number of memory cells whose read result for each voltage value satisfies a set condition; determine the difference between the two quantities corresponding to each pair of adjacent voltage values ​​belonging to the same group of read voltages; and determine the optimal read voltage for distinguishing the two adjacent memory states based on the difference.

[0009] Fifthly, embodiments of this application also provide a storage system, including: one or more memories; and a memory controller coupled to the memories; wherein, The memory controller is configured to: obtain at least one set of read voltages; each set of read voltages includes an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of the memory cell; and send corresponding read commands to a storage surface contained in the memory based on the initial voltage value and the offset voltage value in the at least one set of read voltages. The memory is configured to: read the corresponding memory surface in response to the corresponding read command; count the number of memory cells whose read results for each voltage value meet the set conditions; and send the count to the memory controller. The memory controller is further configured to: receive the quantity; determine the difference between the two quantities corresponding to every two adjacent voltage values ​​belonging to the same group of read voltages; and determine, based on the difference, an optimal read voltage for distinguishing the two adjacent memory states of the memory cell.

[0010] This application provides a memory operation method, a memory, and a memory system. The memory operation method includes: obtaining at least one set of read voltages; each set of read voltages includes an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent memory states of a memory cell; performing read operations based on the initial voltage value and the offset voltage value in the at least one set of read voltages to obtain the number of memory cells whose read results satisfy a set condition for each voltage value; determining the difference between the two quantities corresponding to every two adjacent voltage values ​​belonging to the same set of read voltages; and determining an optimal read voltage for distinguishing the two adjacent memory states based on the difference. The memory operation method provided in this application sets at least one set of read voltages containing multiple voltage values, performs read operations on the memory cells using each voltage value to obtain the number of read results satisfying a set condition; then, based on the difference between the quantities corresponding to every two adjacent voltage values ​​belonging to the same set of read voltages, determines an optimal read voltage for distinguishing the memory cells of the memory corresponding to the set of read voltages. By obtaining the optimal read voltage, the corresponding memory cell of the memory is read, which greatly increases the probability of correctly reading the data stored in the memory cell. Attached Figure Description

[0011] The aspects of this application can be best understood from the following specific embodiments when read in conjunction with the accompanying drawings. Note that, according to standard practice in industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0012] Figure 1 A block diagram of an exemplary system with memory in the related art is shown; Figure 2 A schematic diagram of an exemplary memory card with memory is shown; Figure 3 A schematic diagram showing an exemplary solid-state drive (SSD) with memory is shown; Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown; Figure 5 A side view showing a cross-section of an exemplary memory array containing NAND memory strings; Figure 6 A block diagram of an exemplary memory including a storage array and peripheral circuitry is shown. Figure 7 A flowchart illustrating the operation method of the memory provided in an embodiment of this application is shown; Figure 8 This diagram illustrates the threshold voltage distribution of any two adjacent memory states in a memory cell provided in an embodiment of this application. Figure 9 This illustration shows a schematic diagram of the relationship between the first set of read voltages provided in an embodiment of this application; Figure 10 This application illustrates the adoption of embodiments provided by the present application. Figure 9 The diagram shows the number of memory cells in each memory surface whose read results satisfy the set conditions when multiple voltage values ​​are read from a memory surface. Figure 11 This application provides an embodiment of the invention. Figure 10 A schematic diagram showing the difference between every two adjacent voltage values; Figure 12 This application provides a schematic diagram illustrating the differences with inflection points according to an embodiment of the present application. Figure 13 This illustration shows a relationship where, when the at least one set of reading voltages provided in this application includes a first set of reading voltages and a second set of reading voltages, the initial voltage value Vrdn1 contained in the first set of reading voltages is greater than the initial voltage value Vrdn2 contained in the second set of reading voltages. Figure 14 This diagram illustrates a flowchart of an implementation of the operation method provided in this application embodiment. Figure 15This diagram illustrates another implementation of the operation method provided in this application. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this application. Of course, these are merely examples and not limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0014] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (or more) other elements or features as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0015] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0016] Figure 1 A block diagram of an exemplary system with memory in the related art is shown. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. For example... Figure 1As shown, system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory 104. Specifically, the memory 104 may be any memory disclosed in this application, such as phase-change random access memory (PCRAM), three-dimensional NAND flash memory, etc.

[0017] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108, and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as on Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones in low duty cycle environments. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment, such as on solid-state drives (SSDs) or embedded multimedia cards (eMMCs), where SSDs or eMMCs are used as data storage for mobile devices in high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. Memory controller 106 can be configured to control the operation of memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0018] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products. Figure 2 In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a connector for connecting the memory card to a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 3 In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 302. The SSD may also include components for connecting the SSD to a host computer (e.g., Figure 1 The SSD connector 304 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. Furthermore, the memory controller 106 can also be configured to control erase, read, and write operations of the memory 104.

[0019] Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown. Figure 4As shown, memory 104 may include a memory array 401 and peripheral circuitry 402 coupled to the memory array 401. The memory array 401 may be a NAND flash memory array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0020] In some embodiments, each memory cell 406 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 406 is a multi-level cell (MLC) having four or more memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC)). (Cell). It should be noted that the memory states mentioned here are the same as the memory states of the memory cells in this application. Different types of memory cells have different numbers of memory states. For example, an SLC type memory cell has 2 memory states, which include one programming state and one erase state. Another example is an MLC type memory cell, which has 4 memory states, including one erase state and three programming states. Yet another example is a TLC type memory cell, which has 8 memory states, including one erase state and seven programming states. In some embodiments, a QLC type memory cell has 16 memory states, including one erase state and fifteen programming states.

[0021] like Figure 4As shown, each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. SSG 410 and DSG 412 can be configured to activate a selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of NAND memory strings 408 in the same block 404 are coupled via the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG412) or a deselection voltage (e.g., 0 volts (V)) to the corresponding DSG412 via one or more DSG lines 413 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG410) or a deselection voltage (e.g., 0V) to the corresponding SSG410 via one or more SSG lines 415.

[0022] like Figure 4As shown, NAND memory strings 408 can be organized into multiple blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 404 is a basic data unit with an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase memory cells 406 in a selected block 404, a source line 414 biased to the selected block 404 and unselected blocks 404 on the same plane as the selected block 404 can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 receives read and program operations. In some embodiments, memory cells 406 coupled to the same word line 418 are referred to as (physical) pages 420. A page 420 is a basic unit of data used for programming or reading operations, and the size of a page 420, measured in bits, can be related to the number of NAND memory strings 408 coupled by word lines 418 in a block 404. Each word line 418 may include multiple control gates (gate electrodes) at each memory cell 406 within the corresponding page 420, as well as gate lines coupling the control gates.

[0023] Figure 5 A side view of a cross-section of an exemplary memory array 401 including NAND memory cell strings 408 according to some aspects of this application is shown. Figure 5 As shown, the NAND memory cell string 408 can extend vertically through the memory stack layer 502 above the substrate 501. The substrate 501 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0024] The memory stack 502 may include alternating gate conductive layers 503 and gate-to-gate dielectric layers 504. The number of pairs of gate conductive layers 503 and gate-to-gate dielectric layers 504 in the memory stack 502 determines the number of memory cells 406 in the memory array 401. The gate conductive layers 503 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 503 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 503 includes a doped polysilicon layer. Each gate conductive layer 503 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack 502 as a DSG line 413, at the bottom of the memory stack 502 as an SSG line 415, or between DSG lines 413 and SSG lines 415 as a word line 418.

[0025] like Figure 5 As shown, the NAND memory cell string 408 includes a channel structure 505 extending vertically through the memory stack layer 502. In some embodiments, the channel structure 505 includes channel holes filled with one or more semiconductor materials and one or more dielectric materials. In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure 505 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0026] Return to reference Figure 4Peripheral circuitry 402 can be coupled to memory array 401 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. Peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413, and by sensing voltage and / or current signals from each target memory cell 406. Peripheral circuitry 402 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 402 includes a page buffer / sensor amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic unit 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional components may be included. Figure 7 Additional peripheral circuitry not shown.

[0027] Page buffer / sensor amplifier 604 can be configured to read data from memory array 401 and program (write) data to memory array 401 according to control signals from control logic unit 612. In one example, page buffer / sensor amplifier 604 can store a page of programming data (write data) to be programmed into a page 420 of memory array 401. In another example, page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 604 can also sense a low-power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 606 can be configured to be controlled by control logic unit 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generator 610.

[0028] The row decoder / word line driver 608 can be configured to be controlled by the control logic unit 612 and to select / deselect block 404 of the memory array 401 and to select / deselect word line 418 of block 404. The row decoder / word line driver 608 can also be configured to drive word line 418 using word line voltages generated from the voltage generator 610. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive SSG line 415 and DSG line 413. As described in detail below, the row decoder / word line driver 608 is configured to perform an erase operation on memory cell 406 coupled to one or more selected word lines 418. The voltage generator 610 can be configured to be controlled by the control logic unit 612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0029] Control logic unit 612 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 614 can be coupled to control logic unit 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 616 can be coupled to control logic unit 612 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 612, as well as to buffer status information received from control logic unit 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bit line driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 401.

[0030] Based on the storage system and memory described above, the charge stored in the storage cells changes over time and with repeated read operations, thus affecting the accuracy of data retrieval. Typically, an offset voltage from a preset read voltage offset table is added to the initial voltage value, and a set of offset voltages that can correctly read the data is found through repeated trials. After long-term storage, the storage cells in each storage page of the memory block have different threshold voltage offsets. Therefore, when reading large amounts of data, it is necessary to repeatedly poll the preset read voltage offset table, and then perform hardware and software decoding operations, which consumes a considerable amount of time. This reading process significantly impacts memory performance, especially for enterprise applications, causing Quality of Service (QoS) to fail to meet standards.

[0031] To solve the above technical problems, an embodiment of the present application provides an operation method for a memory. Specifically, as shown in Figure 7 the following, the operation method may include: S701: Obtain at least one set of read voltages; each set of read voltages in the at least one set of read voltages includes an initial voltage value and an offset voltage value having a certain offset relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage for distinguishing two adjacent storage states of the storage units of the memory.

[0032] It should be noted that the operation method for the memory provided by the embodiment of the present application is a method for determining an optimal read voltage. Here, the storage units of the memory can be of types such as SLC, MLC, TLC, QLC, etc. The two adjacent storage states mentioned can refer to any two adjacent storage states of any type of storage unit. That is to say, the operation method provided by the embodiment of the present application is applicable to determining the optimal read voltage for any two adjacent storage states.

[0033] Regarding how to distinguish two adjacent storage states of storage units, see, as shown in Figure 8 the following, which shows a schematic diagram of the threshold voltage distribution corresponding to any two adjacent storage states of storage units. In Figure 8 , the regions f1 and f2 surrounded by the dashed line respectively represent the threshold voltage distributions before the charge numbers of the storage units in the storage states P1 and P2 change. At this time, when reading data from the memory, the initial voltage value V_initial is applied to the storage units. It can be clearly seen that the initial voltage value V_initial is greater than the threshold voltage of the storage units corresponding to f1 and less than the threshold voltage of the storage units corresponding to f2. Therefore, before the charge number of the storage unit changes, when using the initial voltage value V_initial to read the storage unit in the storage state P1 or the storage state P2, it is possible to easily distinguish whether the storage unit is in the storage state P1 or the storage state P2, so as to obtain the data stored in the storage unit. However, during the use of the memory, as the usage time increases, the read interference, programming / erasing times, data retention ability, and cross temperature of the memory will all change, and the threshold voltages of each storage unit will also change accordingly. Figure 8 The regions f3 and f4 in Figure 8In the diagram, f3 and f4 show shifts and widening relative to f1 and f2, respectively. An overlap region between the two storage states appears near the initial voltage value Vinitial. When reading data from each storage cell using the initial voltage value Vinitial, storage state P2 in region 2 may be misidentified as storage state P1, and storage state P1 in region 1 may be misidentified as storage state P2. Furthermore, when the threshold voltage equals the initial voltage value Vinitial, it is also impossible to correctly determine whether the storage cell is in storage state P1 or storage state P2, increasing the probability of read errors.

[0034] As storage time and the number of reads increase, the threshold voltage deviation of the aforementioned storage cells is unavoidable. To obtain correct data reads, the memory incorporates an error correction code (ECC) function. It should be understood that the fewer the number of bits counted as errors, the fewer bits require ECC correction, thus increasing the probability of correct reads and reducing the required read time. Therefore, the corresponding read voltage is optimal. Figure 8 Regarding the threshold voltage distributions of two adjacent memory states shown, the number of bits with statistical errors is minimized when the read voltage V intersects at the intersection point M of the two memory states corresponding to f3 and f4. This read voltage V intersects at the optimal read voltage. This intersection point M can also be referred to as the valley position where the threshold voltage ranges corresponding to the two adjacent memory states overlap. In other words, the operation method provided in this application embodiment determines this valley position or the direction of the valley position to determine the optimal read voltage.

[0035] Here, the initial voltage value included in each set of read voltages can refer to a preset read voltage used to distinguish two adjacent memory states of the memory cell. This preset read voltage can be an empirical value or a default value configured at the time of manufacture, which is obtained through extensive simulation experiments before the memory leaves the factory. Each initial voltage value can distinguish two adjacent memory states during previous read operations.

[0036] In some embodiments, obtaining at least one set of read voltages may include: Determine at least one of the initial voltage values; Based on the first initial voltage value among the at least one initial voltage value, a first offset voltage value with a certain offset relative to the first initial voltage value is obtained by sequentially increasing or decreasing by equal offsets. A set of read voltages is obtained based on the first initial voltage value and the first offset voltage value; The at least one set of reading voltages is obtained based on the corresponding set of reading voltages for each group.

[0037] It should be noted that two adjacent memory states may have multiple initial voltage values ​​with a certain voltage difference during actual use. Based on the foregoing description, the initial voltage value may be an empirical value or a factory default value. Therefore, determining at least one initial voltage value here means obtaining multiple empirical values ​​or multiple default values ​​from factory testing.

[0038] After obtaining at least one initial voltage value, each of the at least one initial voltage value is offset to obtain an offset voltage value with a certain offset relative to each initial voltage value. In this way, each initial voltage value and its corresponding offset voltage value are combined to form a set of read voltages, ultimately obtaining at least one set of read voltages. Since the acquisition method for each set of read voltages is similar, only the first initial voltage value is used as an example for explanation. The first initial voltage value is any one of the at least one initial voltage values.

[0039] Specifically, based on the first initial voltage value, a first offset voltage value with a certain offset relative to the first initial voltage value is obtained by sequentially increasing or decreasing the offset by equal amounts; then, the first initial voltage value and the first offset voltage value are combined to form a set of reading voltages relative to the first initial voltage value.

[0040] For example, such as Figure 9 As shown. In Figure 9 In this example, assuming the initial voltage value is Vrdn, the offset voltage values ​​with a certain offset relative to the initial voltage value are, in sequence: Vrdn_1, Vrdn_2, Vrdn_3, and Vrdn_4. These offset voltage values ​​are located to the left of the initial voltage value Vrdn and decrease sequentially with equal offsets. It should be noted that this is only one example; the offset voltage values ​​can also increase sequentially with equal offsets to the right of the initial voltage value.

[0041] It should also be noted that for different initial voltage values ​​among the at least one initial voltage value, the offsets that yield the corresponding offset voltage values ​​can be equal or unequal.

[0042] For example, suppose the at least one initial voltage value includes a first initial voltage value and a second initial voltage value, wherein the first initial voltage value obtains an equal offset of U millivolts (mV) to the offset voltage value, and the second initial voltage value obtains an equal offset of U mV to the offset voltage value, or any possible value other than U mV.

[0043] S702: Perform a read operation based on the initial voltage value and the offset voltage value in the at least one set of read voltages, and obtain the number of storage units whose read results for each voltage value meet the set conditions.

[0044] In some embodiments, performing a read operation based on the initial voltage value and the offset voltage value in the at least one set of read voltages to obtain the number of memory cells whose read results for each voltage value satisfy a set condition may include: Each of the at least one set of read voltages contains an initial voltage value and an offset voltage value, which are used to read a storage surface of the memory respectively; Count the number of memory cells whose read results meet the set conditions in the memory surface for each voltage value read.

[0045] It should be noted that a memory can include multiple storage planes. In practical applications, before programming each storage cell of the memory to store data, the data to be stored is scrambled to reduce the occurrence of consecutive 0s or consecutive 1s, thereby ensuring that the probability of 0s or 1s appearing is close to 50%. This results in the number of storage cells in each storage plane of the memory being basically equal for the same storage state. Therefore, a set of read voltage values ​​can be used to read one storage plane of the memory to count the number of storage cells in that storage state in each storage plane.

[0046] Here, "meeting the set condition" can mean that the read result is a set number, where the set number can be 1 or 0. In one optional embodiment, if the read result of a memory cell with a threshold voltage lower than the read voltage is a set number (set number is 1), then the read result of a memory cell with a threshold voltage higher than the read voltage is 0. In another optional embodiment, if the read result of a memory cell with a threshold voltage higher than the read voltage is a set number (set number is 0), then the read result of a memory cell with a threshold voltage lower than the read voltage is 1.

[0047] The reading process described here is as follows: Each initial voltage value and offset voltage value from each of the at least one set of reading voltages is used to read one storage surface in the memory; then, the number of storage cells in each storage surface whose read results satisfy a set condition is counted. In other words, each voltage value from each of the at least one set of reading voltages is applied to one storage surface in the memory to perform a read operation, and then the number of storage cells in each storage surface whose read results are a set number is counted.

[0048] For example, such as Figure 10As shown, when the at least one set of read voltages includes a set of read voltages, if the set of read voltages includes: Vrdn, Vrdn_1, Vrdn_2, Vrdn_3, Vrdn_4, and the set number is 1, the above-mentioned reading process is to use Vrdn, Vrdn_1, Vrdn_2, Vrdn_3, Vrdn_4 to read a storage surface in the memory respectively, such as reading the storage surfaces Plane0, Plane1, Plane2, Plane3, and Plane4 of the memory respectively. Then, count the number of memory cells with a read result of 1 in each memory plane. For example, Plane0 contains the following number of memory cells with a read result of 1: C1_Vrdn; Plane1 contains the following number of memory cells with a read result of 1: C2_Vrdn; Plane2 contains the following number of memory cells with a read result of 1: C3_Vrdn; Plane3 contains the following number of memory cells with a read result of 1: C4_Vrdn; and Plane4 contains the following number of memory cells with a read result of 1: C5_Vrdn.

[0049] S703: Determine the difference between the two quantities corresponding to every two adjacent voltage values ​​belonging to the same group of read voltages.

[0050] Here, each pair of adjacent voltage values ​​belonging to the same group of read voltages can refer to: a certain initial voltage value and each pair of adjacent voltage values ​​in its corresponding offset voltage. For example, each pair of adjacent voltage values ​​in the initial voltage value Vrdn and its corresponding offset voltage values ​​Vrdn_1, Vrdn_2, Vrdn_3, and Vrdn_4 are respectively: (Vrdn, Vrdn_1); (Vrdn_1, Vrdn_2); (Vrdn_2, Vrdn_3); (Vrdn_3, Vrdn_4). Based on the above statistics of the number of storage units in the storage surface corresponding to each voltage value in this group of read voltages where the read result is a set number, the difference between the quantities corresponding to each pair of adjacent voltage values ​​can be obtained as follows: e1_Vrdn = C1_Vrdn - C2_Vrdn; e2_Vrdn=C2_Vrdn-C3_Vrdn; e3_Vrdn=C3_Vrdn-C4_Vrdn; e4_Vrdn=C4_Vrdn-C5_Vrdn.

[0051] The difference between the two quantities corresponding to every two adjacent voltage values ​​belonging to the same group of read voltages can be intuitively seen from [the following text is missing from the original]: Figure 11 A schematic diagram showing the differences.

[0052] S704: Determine the optimal read voltage for distinguishing the two adjacent memory states based on the difference.

[0053] In some embodiments, the at least one set of read voltages includes a first set of read voltages, and determining the optimal read voltage for distinguishing the two adjacent memory states based on the difference may include: When the trend of the difference is consistent with the trend of the voltage value in the first group of reading voltages, the offset direction of the optimal reading voltage relative to the initial voltage value of the first group of reading voltages is determined. The optimal reading voltage is determined based on the offset direction and the preset reading voltage offset table.

[0054] It should be noted that this description refers to the fact that the at least one set of read voltages only includes the first set of read voltages, that is, only an initial voltage value and an offset voltage value relative to that initial voltage value. In this case, determining the optimal read voltage based on the difference can be further divided into two situations: one is how to determine the optimal read voltage when the trend of the difference is consistent with the trend of the voltage values ​​in the first set of read voltages; the other is how to determine the optimal read voltage when the trend of the difference is inconsistent with the trend of the voltage values ​​in the first set of read voltages.

[0055] In the former case, when the trend of the difference is consistent with the trend of the voltage value in the first set of reading voltages, the offset direction of the optimal reading voltage relative to the initial voltage value in the first set of reading voltages is first determined; then, the optimal reading voltage is determined according to the offset direction and the preset reading voltage offset table. The preset reading voltage offset table may include multiple sets of preset voltage bias values ​​obtained through extensive experience or experimentation. In use, each preset voltage offset value in the preset reading voltage offset table is loaded onto the default initial reading voltage (e.g., Vinitial or Vrdn, or its value), obtaining the reading voltage for each reading. This process is repeated until a set of preset offset voltage values ​​that can correctly read data is found, thus obtaining the optimal set of reading voltages and increasing the probability of correctly reading data. The specific preset reading voltage offset table is shown in Table 1.

[0056] It should be noted that Rd1 to Rd7 in Table 1 represent different initial read voltages. Since different types of memory cells contain different numbers of memory states, the default initial read voltage used for every two adjacent memory states is different. In other words, the preset read voltage offset table contains a set of preset offset voltages corresponding to the default initial read voltages of every two adjacent memory states. Each set of preset offset voltages includes a positive offset that increases in the direction greater than the default initial read voltage and a negative offset that decreases in the direction less than the default initial read voltage. For example, for the default initial read voltage Rd7, +V1, +V2, +V3, and +V4 are positive offsets, where the values ​​of V1, V2, V3, and V4 increase sequentially; -V5 to -V11 are negative offsets, where the values ​​of V5 to V11 decrease sequentially.

[0057] Table 1 Preset Reading Voltage Offset Table 1

[0058] In some embodiments, determining the offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages may include: When the voltage value in the first group of read voltages decreases sequentially relative to the initial voltage value in the first group of read voltages, the offset direction of the optimal read voltage relative to the initial voltage value in the first group of read voltages is determined to be to the left. When the voltage value in the first set of read voltages increases sequentially relative to the initial voltage value in the first set of read voltages, the offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages is determined to be a rightward offset.

[0059] Specifically, when the bias voltage value of the first group of read voltages is to the left of the initial voltage value of the first group of read voltages, and the trend of change is decreasing sequentially relative to the initial voltage value of the first group of read voltages, the offset direction of the optimal read voltage relative to the initial voltage value of the first group of read voltages is determined to be to the left, that is, the optimal read voltage is to the left of the first initial voltage value; when the offset voltage value of the first group of read voltages is to the right of the initial voltage value of the first group of read voltages, and the trend of change is increasing sequentially relative to the initial voltage value of the first group of read voltages, the offset direction of the optimal read voltage relative to the initial voltage value of the first group of read voltages is determined to be to the right, that is, the optimal read voltage is to the right of the initial voltage value of the first group of read voltages.

[0060] After obtaining the offset direction of the optimal read voltage, in some embodiments, determining the optimal read voltage based on the offset direction and a preset read voltage offset table may include: Based on the offset direction, a first optimal offset amount is selected from the preset read voltage offset table; The optimal read voltage is determined based on the first optimal offset and the initial voltage value in the first set of read voltages.

[0061] It should be noted that after determining the offset direction of the optimal read voltage, a first optimal offset can be selected from the preset read voltage offset table; then, the optimal read voltage is determined based on the first optimal offset and the initial voltage value in the first group of read voltages. Here, the first optimal offset may include at least one preset offset voltage. When the first optimal offset includes multiple preset offset voltages, determining the optimal read voltage based on the first optimal offset and the initial voltage value in the first group of read voltages may mean loading each preset offset voltage included in the first optimal offset onto the corresponding default initial read voltage, conducting multiple experiments to find the preset offset voltage that can correctly read the stored data in the memory cell, and thus obtaining the optimal read voltage. In this way, after determining the offset direction of the optimal read voltage, a group of first optimal offsets that approach the optimal read voltage can be found in the preset read voltage offset table. Subsequently, one or more preset offset voltages from these first optimal offsets are loaded onto the corresponding default initial read voltage to obtain multiple read voltages, narrowing the range of preset offset voltages required to repeatedly try to obtain data that can be read correctly, and reducing the reread rate.

[0062] For example, see Table 2. If the initial voltage value Vrdn1 included in the first set of read voltages is -V5, and the optimal read voltage is offset to the left relative to this initial voltage value -V5, that is, offset to a direction smaller than this initial voltage value. Based on this, combined with the preset read voltage offset table shown in Table 1, the preset offset voltage amounts included in the first optimal offset amount are -V5 to -V11. Then, these preset offset voltage amounts are applied to the default initial read voltage Rd7 to attempt to obtain the optimal read voltage. This avoids trying positive values ​​from +V1 to +V4, narrowing the range of preset offset voltage amounts required to obtain data that can be read correctly through repeated attempts, and reducing the reread rate.

[0063] Table 2 Preset Reading Voltage Offset Table 2

[0064] In the latter case, in some embodiments, the method may further include: When the change trend of the difference is inconsistent with the change trend of the voltage values in the first set of read voltages, determine the minimum difference in the difference; Determine the optimal read voltage based on the minimum difference.

[0065] It should be noted that according to the characteristics of the threshold voltage distribution of the memory cells of the memory, when the change trend of the difference is inconsistent with the change trend of the voltage values in the first set of read voltages, that is, the change trend of the difference is not a monotonic change, and there is an inflection point (minimum difference) in the middle. This indicates that when reading the memory cells in one of the two adjacent storage states with the voltage values in the first set of read voltages, the number of memory cells whose read results meet the set conditions corresponding to each voltage value is not a monotonic change, which also means that there is an intersection point between these two adjacent storage states. According to the foregoing Figure 9 As shown, when there is an intersection point M in the threshold voltage distribution corresponding to two adjacent storage states, the read voltage V_intersection corresponding to the intersection point M is the optimal read voltage. Therefore, the range between two adjacent voltage values in the first set of read voltages corresponding to the inflection point of the difference contains the read voltage V_intersection corresponding to the intersection point M, that is, the optimal read voltage.

[0066] For example, as shown in the schematic diagrams of the differences Figure 11 before. When e2_Vrdn < e3_Vrdn < e1_Vrdn / e4_Vrdn (as shown Figure 12 before), e2_Vrdn can be determined as the minimum difference, and the optimal read voltage is included in the middle of the two adjacent voltage values corresponding to this minimum difference.

[0067] In some embodiments, the determining the optimal read voltage based on the minimum difference may include: Determine two adjacent voltage values corresponding to the minimum difference from the offset voltage values in the first set of read voltages; Determine the average voltage value of the two adjacent voltage values as the optimal read voltage.

[0068] It should be noted that the optimal read voltage here is the average voltage value of the two adjacent voltage values corresponding to the minimum difference.

[0069] In the actual application process, after obtaining the two adjacent voltage values corresponding to the minimum difference, determine one or more preset offset voltage amounts between the two adjacent voltage values from a preset read voltage offset table; then, in the same way as obtaining the optimal read voltage from the preset offset voltage amounts included in the first optimal offset amount, obtain the optimal read voltage from the one or more preset offset voltage amounts between the two adjacent voltage values.

[0070] The previously described scheme is a method for determining the optimal read voltage when the at least one set of read voltages contains only the first set of read voltages. In some embodiments, the at least one set of read voltages further includes a second set of read voltages, wherein there is a certain voltage difference between the initial voltage value in the second set of read voltages and the initial voltage value in the first set of read voltages; the offset voltage value in the second set of read voltages and the offset voltage value in the first set of read voltages are located between the initial voltage value in the second set of read voltages and the initial voltage value in the first set of read voltages; the difference includes a first sub-difference value corresponding to the first set of read voltages and a second sub-difference value corresponding to the second set of read voltages; The step of determining the optimal read voltage for distinguishing the two adjacent memory states based on the difference includes: The optimal reading voltage is determined based on the first trend of change of the first sub-difference and / or the second trend of change of the second sub-difference; Wherein, the initial voltage value in the second group of read voltages is greater than or less than the initial voltage value in the first group of read voltages.

[0071] It should be noted that the scheme described here involves at least one set of read voltages, including a first set of read voltages and a second set of read voltages. There is a certain voltage difference between the initial voltage values ​​contained in the first set of read voltages and the initial voltage values ​​contained in the second set of read voltages. The initial voltage value contained in the first set of read voltages is greater than or less than the initial voltage value contained in the second set of read voltages. The offset voltage values ​​contained in the first set of read voltages and the offset voltage values ​​contained in the second set of read voltages are between the initial voltage values ​​of the first set of read voltages and the initial voltage values ​​of the second set of read voltages. It should be noted that only when this offset voltage value is between the two initial voltage values ​​can the optimal read voltage be determined using the aforementioned two sets of read voltages. See the detailed reference below. Figure 13 As shown; the aforementioned difference includes a first sub-difference corresponding to the first group of read voltages and a second sub-difference corresponding to the second group of read voltages. In this case, determining the optimal read voltage may include: determining it based on a first trend of change of the first sub-difference and / or a second trend of change of the second sub-difference. It should be noted that... Since the method for determining the optimal reading voltage is the same regardless of whether the initial voltage value contained in the first set of reading voltages is greater than or less than the initial voltage value contained in the second set of reading voltages.

[0072] Therefore, in some embodiments, when the initial voltage value in the first set of read voltages is greater than the initial voltage value in the second set of read voltages, determining the optimal read voltage based on the first trend of change of the first sub-difference and / or the second trend of change of the second sub-difference includes: When the first trend of change is inconsistent with the trend of change of voltage values ​​in the first group of read voltages, and the second trend of change is consistent with the trend of change of voltage values ​​in the second group of read voltages, the optimal read voltage is determined based on the minimum value of the first sub-difference.

[0073] It should be noted that in this case, the first sub-differences contain inflection points, and the voltage values ​​in the first set of read voltages corresponding to these inflection points contain the optimal read voltage. The specific method for obtaining this has already been clearly described above and will not be repeated here.

[0074] In other embodiments, the operation method further includes: When the first trend of change is inconsistent with the trend of change of voltage values ​​in the first group of read voltages and when the second trend of change is inconsistent with the trend of change of voltage values ​​in the second group of read voltages, the optimal read voltage is determined based on the minimum value of the first sub-difference and / or the minimum value of the second sub-difference.

[0075] It should be noted that, in this case, if the inflection point corresponding to the first sub-difference value and the second sub-difference value is the same, then the optimal reading voltage is determined based on two adjacent voltage values ​​in the first group of reading voltages corresponding to the minimum value in the first sub-difference value, or based on two adjacent voltage values ​​in the second group of reading voltages corresponding to the minimum value in the second sub-difference value. The specific determination method has been described in detail above when only the first group of reading voltages is included, and will not be repeated here. If the inflection points corresponding to the first sub-difference value and the second sub-difference value are different, then the optimal reading voltage is determined based on two adjacent voltage values ​​in the first group of reading voltages corresponding to the minimum value in the first sub-difference value and two adjacent voltage values ​​in the second group of reading voltages corresponding to the minimum value in the second sub-difference value.

[0076] Specifically, assuming that the two adjacent voltage values ​​in the first group of read voltages corresponding to the minimum value in the first sub-difference are the first voltage value and the second voltage value; and the two adjacent voltage values ​​in the second group of read voltages corresponding to the minimum value in the second sub-difference are the third voltage value and the fourth voltage value, the optimal read voltage can be determined based on the first voltage value, the second voltage value, the third voltage value, and the fourth voltage value in the following ways: The first method uses the average voltage value of the first voltage value, the second voltage value, the third voltage value, and the fourth voltage value as the optimal reading voltage.

[0077] The second method involves obtaining one or more preset offset voltage values ​​within the voltage range consisting of the first, second, third, and fourth voltage values ​​based on a preset reading voltage offset table, and then obtaining the optimal reading voltage using the aforementioned trial method.

[0078] The third method involves obtaining a first average voltage value between a first voltage value and a second voltage value; and obtaining a second average voltage value between a third voltage value and a fourth voltage value; then, based on a preset reading voltage offset table, obtaining one or more preset offset voltage values ​​within the voltage range formed by the first average voltage value and the second average voltage value, and then obtaining the optimal reading voltage according to the aforementioned trial method.

[0079] It should be noted that the three methods for determining the optimal reading voltage based on the first voltage value, the second voltage value, the third voltage value, and the fourth voltage value are only three examples. In actual applications, there are other possible implementation methods, and their specific implementation processes still do not deviate from the technical solutions described in this application, which will not be elaborated here.

[0080] In other embodiments, the operation method further includes: When the first trend of change is consistent with the trend of change of voltage values ​​in the first group of read voltages, and the second trend of change is inconsistent with the trend of change of voltage values ​​in the second group of read voltages, the optimal read voltage is determined based on the minimum value of the second sub-difference.

[0081] It should be noted that in this case, the second sub-difference contains an inflection point, and the voltage values ​​in the second set of read voltages corresponding to the inflection point contain the optimal read voltage. How this is obtained has already been clearly described above and will not be repeated here.

[0082] In some other embodiments, the operation method further includes: When the first trend of change is consistent with the trend of change of voltage values ​​in the first group of read voltages and the second trend of change is consistent with the trend of change of voltage values ​​in the second group of read voltages, a first offset direction of the optimal read voltage relative to the initial voltage value in the first group of read voltages is determined; and a second offset direction of the optimal read voltage relative to the initial voltage value in the second group of read voltages is determined. A second optimal offset is determined from the preset voltage offset table based on the first offset direction and the second offset direction; The optimal reading voltage is determined based on the initial voltage value in the first set of reading voltages, the initial voltage value in the second set of reading voltages, and the second optimal offset.

[0083] It should be noted that, as previously defined, the initial voltage value in the first set of read voltages is greater than the initial voltage value in the second set of read voltages. Therefore, the offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages is determined to be to the left; that is, the first offset direction is the offset direction of the optimal read voltage relative to the initial voltage value in the first set of read voltages to the left. Similarly, the offset direction of the optimal read voltage relative to the initial voltage value in the second set of read voltages is determined to be to the right; that is, the second offset direction is the offset direction of the optimal read voltage relative to the initial voltage value in the second set of read voltages to the right. Based on this, based on the first and second offset directions, one or more preset offset voltage values ​​included in the second optimal offset are obtained from a preset read voltage offset table. Based on these preset offset voltage values, the optimal read voltage is obtained according to the trial method described above; the specific method will not be repeated here.

[0084] For example, see Table 3. If the initial voltage value Vrdn1 of the first set of read voltages is -V8, and the initial voltage value Vrdn2 of the second set of read voltages is -V6, since the values ​​of V5 to V11 decrease sequentially, the negative offset of -V5 to -V11 is smaller. Therefore, Vrdn1 is greater than Vrdn2. In this case, the second optimal offset includes one or more preset offset voltage values ​​from -V6 to -V8. Then, the optimal read voltage is obtained based on these preset offset voltage values. The method for determining the optimal read voltage based on the preset offset voltage values ​​has already been described above and will not be repeated here.

[0085] Table 3 Preset Reading Voltage Offset Table 3

[0086] In some embodiments, the operating method may be used when the memory is idle or during user operation.

[0087] It should be noted that the operation method provided in this application embodiment can be used when the memory is idle or during user operation. Idle refers to a time when the memory is not undergoing read or program operations, during which all steps of the operation method provided in this application embodiment can be completed at once to obtain the optimal read voltage set. User operation refers to a period when the user performs read or write operations on the memory, or other operations. During this period, all steps of the operation method provided in this application embodiment can be executed step-by-step interspersed throughout the user operation to ultimately obtain the optimal read voltage set.

[0088] In some embodiments, the memory includes a register for storing the optimal read voltage.

[0089] Regarding the operation method provided in the embodiments of this application described above, there are two methods in actual implementation. An alternative implementation, such as Figure 14 As shown, multiple different memory planes (Plane) are contained within a DIE. Typically, the number of Planes within a DIE is even. For two adjacent memory states, multiple offset voltage values ​​are set based on the initial voltage value Vrdn, sequentially as Vrdn_1, Vrdn_2, Vrdn_3, and Vrdn_4, forming a set of read voltages. Each voltage value in this set is used to simultaneously perform read operations on five Planes within a DIE. That is, the memory controller causes the control logic unit within the memory to simultaneously send read commands containing different read voltages to the five Planes (e.g., Plane0, Plane1, Plane2, Plane3, and Plane4), causing Plane0 to be read using Vrdn; Plane1 to be read using Vrdn_1; Plane2 to be read using Vrdn_2; Plane3 to be read using Vrdn_3; and Plane4 to be read using Vrdn_4. Then, the main control digital signal processing (DSP) included in the memory controller is used... The Processing DSP receives the read results of each memory cell in each Plane and counts the number of memory cells in each Plane whose read results meet the set conditions. Then, the DSP determines the optimal read voltage based on these numbers to guide the next read operation.

[0090] Another alternative implementation, such as Figure 15 As shown. When the memory array is NAND flash memory, if the NAND flash memory has statistical functions, Figure 15 and Figure 14 The only difference lies in the step of counting the number of memory cells with the set value. In this step, the NAND flash memory uses its built-in peripheral circuitry's control logic unit to count the number of memory cells in each plane whose read results meet the set conditions, and then sends this count to the DSP within the memory controller. The remaining steps are the same. Figure 14 The steps shown are the same, and have been explained in detail above, so they will not be repeated here.

[0091] The memory operation method provided in this application embodiment sets at least one set of read voltages containing multiple voltage values. Each voltage value is used to perform a read operation on a memory cell, obtaining the number of read results that satisfy a set condition. Then, based on the difference between the number corresponding to every two adjacent voltage values ​​in the same set of read voltages, an optimal read voltage is determined for distinguishing the memory cells from the corresponding adjacent memory states of that set of read voltages. Using the obtained optimal read voltage to read the corresponding memory cell greatly increases the probability of correctly reading the data stored in that memory cell. The operation method provided in this application embodiment is an online method for obtaining the optimal read voltage of a memory. In other words, this method uses real data generated during actual memory operation to determine the optimal read voltage, rather than using simulated data from the memory manufacturing process. It can obtain the optimal read voltage set online, improving the decoding success rate; or it can obtain the threshold offset method of the optimal read voltage online, allowing for more targeted selection of repeat voltages and reducing the number of repeat reads, thereby saving time.

[0092] Based on the same inventive concept, embodiments of this application also provide a memory, a memory array, the memory array including memory cells; and peripheral circuitry coupled to the memory array and configured to control the memory array; The peripheral circuit is configured to implement any step of the aforementioned operation method.

[0093] In some embodiments, the peripheral circuitry includes a register for storing the optimal read voltage.

[0094] It should be noted that the technical solution described in the memory and the technical solution of the aforementioned operation method belong to the same inventive concept and have the same technical features. The terms appearing in the technical solution of the operation method provided in the embodiments of this application have been described in detail above. Therefore, the terms appearing here can be understood according to the meanings described above, and will not be repeated here.

[0095] This application embodiment also provides a storage system, including: one or more of the memories described in any of the preceding claims; and a memory controller coupled to the memory; the memory controller is configured to: send a first command to the memory; The memory is configured to execute the aforementioned operation method in response to the first command.

[0096] The first command is used to initiate the execution of the aforementioned operation method. The first command includes commands such as instructing the memory to acquire at least one set of read voltages and commands to read a memory surface using the voltage values ​​in the at least one set of read voltages.

[0097] In other embodiments, the present invention also provides a storage system, comprising: one or more memories; and a memory controller coupled to the memories; wherein, The memory controller is configured to: obtain at least one set of read voltages; each set of read voltages includes an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of the memory cell; and send corresponding read commands to a storage surface contained in the memory based on the initial voltage value and the offset voltage value in the at least one set of read voltages. The memory is configured to: read the corresponding storage surface in response to the corresponding read command; and send the read result of each storage cell in the storage surface to the memory controller; The memory controller is further configured to: receive the read result; count the number of memory cells whose read result for each voltage value satisfies a set condition; determine the difference between the two quantities corresponding to each pair of adjacent voltage values ​​belonging to the same group of read voltages; and determine the optimal read voltage for distinguishing the two adjacent memory states based on the difference.

[0098] It should be noted that this storage system can achieve the aforementioned Figure 14 The implementation method.

[0099] In other embodiments, the present invention also provides another storage system, comprising: one or more memories; and a memory controller coupled to the memories; wherein, The memory controller is configured to: obtain at least one set of read voltages; each set of read voltages includes an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value; the initial voltage value in each set of read voltages is a preset read voltage used to distinguish two adjacent storage states of the memory cell; and send corresponding read commands to a storage surface contained in the memory based on the initial voltage value and the offset voltage value in the at least one set of read voltages. The memory is configured to: read the corresponding memory surface in response to the corresponding read command; count the number of memory cells whose read results for each voltage value meet the set conditions; and send the count to the memory controller. The memory controller is further configured to: receive the quantity; determine the difference between the two quantities corresponding to every two adjacent voltage values ​​belonging to the same group of read voltages; and determine, based on the difference, an optimal read voltage for distinguishing the two adjacent memory states of the memory cell.

[0100] It should be noted that the storage system here can achieve the aforementioned Figure 15 The implementation method shown.

[0101] In some embodiments, any of the aforementioned storage systems is a solid-state drive (SSD) or a memory card.

[0102] It should be noted that the storage system mentioned here includes the aforementioned memory, and the two have the same technical features. The structure of the memory and the terms appearing in the technical solution of this application have been described in detail above. Therefore, the terms appearing here can be understood according to the meanings described above, and will not be repeated here.

[0103] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

Claims

1. A storage system, comprising: The memory controller is configured to send the first command; and The memory, coupled to the memory controller, is configured to: In response to the first command, a first read operation is performed based on a first set of read voltages including a plurality of first read voltages to obtain a plurality of first quantities corresponding to a plurality of first read results based on the plurality of first read voltages, wherein any two adjacent first read voltages among the plurality of first read voltages have the same first offset value, each first read result is obtained based on a corresponding first read voltage, and each first quantity is the number of memory cells that satisfy a set condition in the first read results based on the corresponding first read voltage; and First information related to the plurality of first quantities is sent to the memory controller; The memory controller is also configured to: Based on the first information received from the memory, a plurality of first differences are obtained, wherein the first difference is the difference between two first quantities corresponding to the first read results of two adjacent first read voltages; Based on the multiple first differences, the optimal reading voltage is determined; and Send one or more second commands to the memory, the one or more second commands instructing the memory to read data stored in the memory cells based on the optimal read voltage.

2. The storage system according to claim 1, wherein, The plurality of first read voltages include a first initial voltage and at least two first offset voltages, and each of the at least two first offset voltages is an offset voltage value having a certain offset relative to the first initial voltage.

3. The storage system according to claim 2, wherein, To determine the optimal read voltage, the memory controller is configured to: The relationship between the first changing trend of the plurality of first differences and the second changing trend of the plurality of first read voltages is obtained; and The optimal reading voltage is determined based on the relationship between the first changing trend of the plurality of first differences and the second changing trend of the plurality of first reading voltages.

4. The storage system according to claim 3, wherein, To determine the optimal read voltage based on the relationship between a first trend of change of the plurality of first differences and a second trend of change of the plurality of first read voltages, the memory controller is configured to: In response to the first changing trend of the plurality of first differences being consistent with the second changing trend of the plurality of first read voltages, a first offset direction of the optimal read voltage relative to the first initial voltage is obtained; Based on the first offset direction, obtain the first optimal offset; and The optimal read voltage is determined based on the first optimal offset and the first initial voltage.

5. The storage system according to claim 4, wherein, The at least two first offset voltages decrease sequentially relative to the first initial voltage, and the first offset direction of the optimal read voltage relative to the first initial voltage is to the left; and The at least two first offset voltages increase sequentially relative to the first initial voltage, and the first offset direction of the optimal read voltage relative to the first initial voltage is to the right.

6. The storage system according to claim 3, wherein, To determine the optimal read voltage based on the relationship between a first trend of change of the plurality of first differences and a second trend of change of the plurality of first read voltages, the memory controller is configured to: In response to the inconsistency between the first changing trend of the plurality of first differences and the second changing trend of the plurality of first read voltages, the minimum value among the plurality of first differences is obtained; Obtain the two first read voltages corresponding to the minimum value among the plurality of first differences; and The optimal reading voltage is determined from the two first reading voltages corresponding to the minimum value among the plurality of first differences.

7. The storage system according to claim 1, wherein, The memory includes a memory array with memory cells and peripheral circuitry coupled to the memory array, through which the plurality of first quantities are obtained.

8. The storage system according to claim 7, wherein, The storage array includes a storage surface, and the peripheral circuitry is configured as follows: Based on the plurality of first read voltages, the first read operation is performed on the storage surface; and Obtain the plurality of first quantities.

9. The storage system according to claim 1, wherein: The memory is configured to: obtain the plurality of first differences based on the plurality of first quantities; and send the first information including the plurality of first differences to the memory controller; or The memory is configured to send the first information, including the plurality of first quantities, to the memory controller; The memory control is configured to: receive the first information including the plurality of first quantities; and obtain the plurality of first differences based on the plurality of first quantities.

10. The storage system according to claim 1, wherein, The memory is further configured as follows: In response to the first command, a second read operation is performed based on a second set of read voltages including a plurality of second read voltages to obtain a plurality of second quantities corresponding to a plurality of second read results based on the plurality of second read voltages, wherein any two adjacent second read voltages among the plurality of second read voltages have the same second offset value, each second read result is obtained based on a corresponding second read voltage, and each second quantity is the number of memory cells satisfying the set condition in the second read results based on the corresponding second read voltage; and Send second information related to the plurality of second quantities to the memory controller; The memory controller is further configured to: Based on the second information received from the memory, a plurality of second differences are obtained, wherein the second difference is the difference between two second quantities corresponding to the second read results of two adjacent second read voltages; and The optimal read voltage is determined based on the plurality of first differences and / or the plurality of second differences.

11. The storage system according to claim 10, wherein, The plurality of first read voltages include a first initial voltage and at least two first offset voltages, and the plurality of second read voltages include a second initial voltage and at least two second offset voltages; to determine the optimal read voltage based on the plurality of first differences and / or the plurality of second differences, the memory controller is configured to: In response to the inconsistency between the first trend of the plurality of first differences and the second trend of the plurality of first read voltages, and the consistency between the third trend of the plurality of second differences and the fourth trend of the plurality of second read voltages, the optimal read voltage is determined based on the minimum value among the plurality of first differences; In response to the fact that a first trend of change of the plurality of first differences is consistent with a second trend of change of the plurality of first read voltages, and that a third trend of change of the plurality of second differences is inconsistent with a fourth trend of change of the plurality of second read voltages, the optimal read voltage is determined based on the minimum value among the plurality of second differences; In response to the inconsistency between the first trend of the plurality of first differences and the second trend of the plurality of first read voltages, and the inconsistency between the third trend of the plurality of second differences and the fourth trend of the plurality of second read voltages, the optimal read voltage is determined based on the minimum value among the plurality of first differences and / or the minimum value among the plurality of second differences; and In response to the first changing trend of the plurality of first differences being consistent with the second changing trend of the plurality of first read voltages, and the third changing trend of the plurality of second differences being consistent with the fourth changing trend of the plurality of second read voltages: Obtain the first offset direction of the optimal read voltage relative to the first initial voltage and the second offset direction of the optimal read voltage relative to the second initial voltage; A second optimal offset is obtained based on the first offset direction and the second offset direction; and The optimal read voltage is determined based on the second optimal offset, the first initial voltage, and the second initial voltage.

12. A storage system, comprising: The memory controller is configured to send the first command; and The memory, coupled to the memory controller, is configured to: In response to the first command, a first read operation is performed based on a first set of read voltages including a plurality of first read voltages to obtain a plurality of first read results corresponding to the plurality of first read voltages, wherein any two adjacent first read voltages among the plurality of first read voltages have the same first offset value; and The plurality of first read results are sent to the memory controller; The memory controller is further configured to: Based on the received multiple first read results, multiple first quantities are obtained, wherein each first quantity is the number of storage units that meet the set conditions in the first read results based on the corresponding first read voltage; Based on the plurality of first quantities, a plurality of first differences are obtained, wherein the first difference is the difference between two first quantities corresponding to the first reading results of two adjacent first reading voltages respectively; Based on the multiple first differences, the optimal reading voltage is determined; and Send one or more second commands to the memory, the one or more second commands instructing the memory to read data stored in the memory cells based on the optimal read voltage.

13. The storage system according to claim 12, wherein, The plurality of first read voltages include a first initial voltage and at least two first offset voltages, and each of the at least two first offset voltages is an offset voltage value having a certain offset relative to the first initial voltage.

14. The storage system according to claim 13, wherein, To determine the optimal read voltage, the memory controller is configured to: The relationship between the first changing trend of the plurality of first differences and the second changing trend of the plurality of first read voltages is obtained; and The optimal reading voltage is determined based on the relationship between the first changing trend of the plurality of first differences and the second changing trend of the plurality of first reading voltages.

15. The storage system according to claim 14, wherein, To determine the optimal read voltage based on the relationship between a first trend of change of the plurality of first differences and a second trend of change of the plurality of first read voltages, the memory controller is configured to: In response to the first changing trend of the plurality of first differences being consistent with the second changing trend of the plurality of first read voltages, a first offset direction of the optimal read voltage relative to the first initial voltage is obtained; Based on the first offset direction, obtain the first optimal offset; and The optimal read voltage is determined based on the first optimal offset and the first initial voltage.

16. The storage system according to claim 15, wherein, The at least two first offset voltages decrease sequentially relative to the first initial voltage, and the first offset direction of the optimal read voltage relative to the first initial voltage is to the left; and The at least two first offset voltages increase sequentially relative to the first initial voltage, and the first offset direction of the optimal read voltage relative to the first initial voltage is to the right.

17. The storage system according to claim 13, wherein, To determine the optimal read voltage based on the relationship between a first trend of change of the plurality of first differences and a second trend of change of the plurality of first read voltages, the memory controller is configured to: In response to the inconsistency between the first changing trend of the plurality of first differences and the second changing trend of the plurality of first read voltages, the minimum value among the plurality of first differences is obtained; Obtain the two first read voltages corresponding to the minimum value among the plurality of first differences; and The optimal reading voltage is determined from the two first reading voltages corresponding to the minimum value among the plurality of first differences.

18. The storage system according to claim 13, wherein: The memory is further configured as follows: In response to the first command, a second read operation is performed based on a second set of read voltages including a plurality of second read voltages to obtain a plurality of second read results corresponding to the plurality of second read voltages, wherein any two adjacent second read voltages among the plurality of second read voltages have the same second offset value; and The plurality of second read results are sent to the memory controller; The memory controller is further configured to: Based on the received multiple second read results, multiple second quantities are obtained, wherein each second quantity is the number of storage cells that satisfy the set condition in the second read results based on the corresponding second read voltage; Based on the plurality of second quantities, a plurality of second differences are obtained, wherein the second difference is the difference between two second quantities corresponding to the second reading results of two adjacent second reading voltages; and The optimal read voltage is determined based on the plurality of first differences and / or the plurality of second differences.

19. The storage system according to claim 18, wherein, The plurality of first read voltages include a first initial voltage and at least two first offset voltages, and the plurality of second read voltages include a second initial voltage and at least two second offset voltages; to determine the optimal read voltage based on the plurality of first differences and / or the plurality of second differences, the memory controller is configured to: In response to the inconsistency between the first trend of the plurality of first differences and the second trend of the plurality of first read voltages, and the consistency between the third trend of the plurality of second differences and the fourth trend of the plurality of second read voltages, the optimal read voltage is determined based on the minimum value among the plurality of first differences; In response to the fact that a first trend of change of the plurality of first differences is consistent with a second trend of change of the plurality of first read voltages, and that a third trend of change of the plurality of second differences is inconsistent with a fourth trend of change of the plurality of second read voltages, the optimal read voltage is determined based on the minimum value among the plurality of second differences; In response to the inconsistency between the first trend of the plurality of first differences and the second trend of the plurality of first read voltages, and the inconsistency between the third trend of the plurality of second differences and the fourth trend of the plurality of second read voltages, the optimal read voltage is determined based on the minimum value among the plurality of first differences and / or the minimum value among the plurality of second differences; and In response to the first changing trend of the plurality of first differences being consistent with the second changing trend of the plurality of first read voltages, and the third changing trend of the plurality of second differences being consistent with the fourth changing trend of the plurality of second read voltages: Obtain the first offset direction of the optimal read voltage relative to the first initial voltage and the second offset direction of the optimal read voltage relative to the second initial voltage; A second optimal offset is obtained based on the first offset direction and the second offset direction; and The optimal read voltage is determined based on the second optimal offset, the first initial voltage, and the second initial voltage.

20. A storage system, comprising: The memory controller is configured to send multiple first commands; and The memory, coupled to the memory controller, is configured to: In response to the plurality of first commands, a plurality of read operations are performed based on a plurality of read voltages to obtain a plurality of read results corresponding to the plurality of read voltages respectively, wherein any two adjacent read voltages among the plurality of read voltages have the same offset value, and each of the read operations is performed based on one of the plurality of read voltages; and The multiple read results are sent to the memory controller; The memory controller is also configured to: Based on the received multiple read results, the number of multiple storage cells that meet the set conditions is obtained, and the number of each storage cell that meets the set conditions is the number of storage cells that meet the set conditions in the read results based on the corresponding read voltage; Based on the number of multiple storage cells that meet the set conditions, multiple differences are obtained. The difference is the difference between two quantities corresponding to the reading results of two adjacent reading voltages. Based on the aforementioned differences, the optimal reading voltage is determined; and Send one or more second commands to the memory, the one or more second commands instructing the memory to read data stored in the memory cells based on the optimal read voltage.

21. The storage system according to claim 20, wherein, To determine the optimal read voltage based on the plurality of differences, the memory controller is configured to: Obtain the relationship between the changing trends of the multiple differences and the changing trends of the multiple read voltages; and The optimal reading voltage is determined based on the relationship between the changing trends of the multiple differences and the changing trends of the multiple reading voltages.

22. The storage system according to claim 21, wherein, The memory control is configured as follows: In response to the fact that the changing trends of the plurality of differences are consistent with the changing trends of the plurality of reading voltages, the offset direction of the optimal reading voltage is obtained; Based on the offset direction, obtain the optimal offset amount; and Based on the optimal offset, the optimal read voltage is determined.

23. The storage system according to claim 21, wherein, The memory controller is configured to: In response to the inconsistency between the changing trends of the plurality of differences and the changing trends of the plurality of read voltages, the minimum value among the plurality of differences is obtained; Obtain the two reading voltages corresponding to the minimum value among the plurality of differences; and The optimal reading voltage is determined from the two reading voltages corresponding to the minimum value among the plurality of differences.

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