Memory device and operating method of memory device

Abstract

The present disclosure relates to a memory device and an operating method of the memory device, the memory device may include: a voltage generation circuit configured to sequentially generate a plurality of data determination voltages of different levels based on a voltage control signal; a line driving circuit configured to sequentially drive the selected word lines to a plurality of data determination voltages; a page buffer configured to generate a sensing detection signal when a memory cell connected to a selected word line is turned on; and a data counting circuit configured to perform a counting operation based on the voltage control signal, stop the counting operation based on the sensing detection signal, and provide a count value according to the counting operation to the page buffer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0148434, filed on October 28, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure relate to an integrated circuit technology, and more specifically, to a memory device and a method of operating the same. Background Technology

[0004] Recently, with the miniaturization, low power consumption, high performance, and diversification of electronic devices, there is a need for semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices. Semiconductor devices can be broadly divided into volatile memory devices and non-volatile memory devices. Volatile memory devices have a faster data processing speed, but their disadvantage is that they require a continuous power supply to retain the stored data. Non-volatile memory devices, on the other hand, can retain the stored data without a continuous power supply, but their disadvantage is that they have a slower data processing speed.

[0005] Therefore, research is being conducted to improve the data processing speed, i.e., the operating speed, of non-volatile memory devices. Summary of the Invention

[0006] In embodiments of this disclosure, a memory device may include: a voltage generation circuit configured to sequentially generate a plurality of data determination voltages of different levels based on a voltage control signal; a line driving circuit configured to sequentially drive selected word lines to the plurality of data determination voltages; a page buffer configured to generate a sensing detection signal when a memory cell connected to the selected word line is turned on; and a data counting circuit configured to perform a counting operation based on the voltage control signal, stop the counting operation based on the sensing detection signal, and provide a count value according to the counting operation to the page buffer.

[0007] In another embodiment of this disclosure, a memory device may include: a line driving circuit configured to provide a plurality of data-determining voltages of different levels to a selected word line to drive the selected word line; at least one sense latch configured to generate a sense detection signal when a memory cell connected to the selected word line is turned on; a data counting circuit configured to perform a counting operation whenever the voltage level used to drive the selected word line changes, stop the counting operation based on the sense detection signal, and generate a count value according to the counting operation; and at least one data latch circuit configured to store the count value and output the stored count value as data.

[0008] In another embodiment of this disclosure, an operation method of a memory device may include: during a read operation, sequentially providing data determination voltages of different levels to selected word lines; performing a counting operation whenever the level of the data determination voltage changes; detecting the voltage level of a bit line connected to a memory cell of the selected word line; stopping the counting operation when the detected voltage level of the bit line is lower than a set level; and outputting a count value corresponding to the stopped counting operation as data. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating the configuration of a memory device according to embodiments of the present disclosure.

[0010] Figure 2 This is a diagram illustrating the configuration of a memory bank in a memory device according to embodiments of the present disclosure.

[0011] Figure 3 This is a diagram illustrating a page buffer of a memory device according to embodiments of the present disclosure.

[0012] Figure 4 This is a diagram illustrating the operation of determining data stored in a memory cell of a memory device according to embodiments of the present disclosure.

[0013] Figure 5 This is a diagram illustrating the operation of a memory device according to embodiments of the present disclosure.

[0014] Figure 6 This is a diagram illustrating the operation of a code translation circuit of a memory device according to an embodiment of the present disclosure.

[0015] Figure 7 This is a diagram illustrating the effects of a memory device according to embodiments of the present disclosure.

[0016] Figure 8 This is a diagram illustrating the configuration of a memory device according to another embodiment of the present disclosure. Detailed Implementation

[0017] Various embodiments of this disclosure are intended to provide a memory device and a method of operating the same that can improve read operation speed.

[0018] The speed of a memory device can be increased by improving the speed of read operations.

[0019] In the following description, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0020] Figure 1 This is a diagram illustrating the configuration of a memory device 100 according to an embodiment of the present disclosure.

[0021] Reference Figure 1 The memory device 100 may include a control circuit 110, a page buffer group 120, a voltage generation circuit 130, a line drive circuit 140, a memory cell array 150, and a data counting circuit 160. The memory device 100 may additionally include a code conversion circuit 170.

[0022] In an embodiment, the control circuit 110 can control the page buffer group 120, voltage generation circuit 130, line drive circuit 140 and data counting circuit 160 to program data into the memory cell array 150 or erase data programmed into the memory cell array 150.

[0023] In an embodiment, the control circuit 110 may generate a page buffer control signal PB_ctrl based on the command signal CMD and the address signal ADD received from an external device (e.g., a host), and provide the page buffer control signal PB_ctrl to the page buffer group 120.

[0024] In this embodiment, the control circuit 110 can generate a voltage control signal V_ctrl based on the command signal CMD and provide the voltage control signal V_ctrl to the voltage generation circuit 130.

[0025] In this embodiment, the control circuit 110 can generate a drive address signal ADD_d based on the command signal CMD and the address signal ADD, and provide the drive address signal ADD_d to the line drive circuit 140.

[0026] In this embodiment, the page buffer group 120 may include multiple page buffers PB1, PB2, ..., and PBm. The multiple page buffers PB1, PB2, ..., and PBm may be connected to multiple bit lines BL1, BL2, ..., and BLm, respectively, where m is a natural number. Each of the multiple page buffers PB1, PB2, ..., and PBm can sense the data value stored in the memory cell through the bit lines and provide the sensed value as a sensing detection signal SD to the data counting circuit 160. Additionally, each of the multiple page buffers PB1, PB2, ..., and PBm can store the count value C<0:2> of the data counting circuit 160 and output the stored value as data in a first format, Data_c.

[0027] In an embodiment, the voltage generation circuit 130 can generate internal voltages V_int at various voltage levels based on the voltage control signal V_ctrl, and provide the internal voltages V_int to the line drive circuit 140. For example, during a read operation, the voltage generation circuit 130 can sequentially provide the line drive circuit 140 with multiple data determination voltages RV1 to RV8 at different levels (e.g., ...). Figure 4 and Figure 5 (As shown) is the internal voltage V_int.

[0028] In this embodiment, the line driver circuit 140 can drive the drain select line DSL, word line WL, and source select line SSL to the voltage level of the internal voltage V_int based on the drive address signal ADD_d. For example, the line driver circuit 140 can selectively drive the drain select line DSL, word line WL, and source select line SSL to the voltage level of the internal voltage V_int based on the drive address signal ADD_d. Specifically, during a read operation, the line driver circuit 140 can sequentially drive the word line WL selected according to the drive address ADD_d to the voltage levels of multiple data determination voltages RV1 to RV8.

[0029] In an embodiment, the memory cell array 150 may include a plurality of memory blocks BK1, BK2, ..., and BKn, where n is a natural number. Each of the plurality of memory blocks BK1, BK2, ..., and BKn may be selected by driving a drain select line DSL, a word line WL, and a source select line SSL, and the memory string of the selected memory block may be connected to a plurality of page buffers PB1, PB2, ..., and PBm via bit lines BL1, BL2, ..., and BLm. Additionally, each of the plurality of memory blocks BK1, BK2, ..., and BKn may include a plurality of memory strings in which a plurality of memory cells are connected in series. Besides including a plurality of memory cells connected in series, each of the plurality of memory strings may also include a first select transistor (e.g., a drain select transistor), a second select transistor (e.g., a source select transistor), and a dummy cell. The first select transistor may be turned on or off according to the voltage level of the drain select line DSL, and the second select transistor may be turned on or off according to the voltage level of the source select line SSL.

[0030] In this embodiment, the data counting circuit 160 can perform a counting operation based on the voltage control signal V_ctrl, and stop performing the counting operation when the page buffer connected to the selection line in the page buffer group 120 detects that a memory cell is turned on. Additionally, the data counting circuit 160 can send a count value C<0:2> to the page buffer when the counting operation stops. For example, the data counting circuit 160 can perform a counting operation based on the voltage control signal V_ctrl, stop the counting operation based on the sensing detection signal SD, and provide the count value C<0:2> to the page buffer that provided the sensing detection signal SD.

[0031] In this embodiment, the code conversion circuit 170 can convert the first format data Data_c output from the page buffer group 120 into a second format data Data_g, and then output the data Data_g. For example, the first format data Data_c output by the page buffer group 120 can have a data format with sequentially increasing count values. The second format data Data_g can be Gray code format data.

[0032] Figure 2 This is a diagram illustrating the configuration of a memory bank in a memory device according to embodiments of the present disclosure. In embodiments, the memory bank may include at least one string of cells. Figure 2 The text describes multiple strings of cells within a memory bank, but a memory bank can also be divided into groups of strings, each group containing multiple strings, and the memory bank includes at least one group of strings. Figure 2 middle, Figure 1 One of the plurality of memory banks BK1 to BKn shown is described as an example only, and it should be noted that the embodiments are not limited thereto. Furthermore, although a memory bank comprising a plurality of cell strings is described as an example in the memory device according to embodiments of the present disclosure, in addition to the cell string structure, the memory device may also be used for a memory bank structure comprising memory cells connected between bit lines and word lines.

[0033] In this embodiment, the memory bank BK1 may include multiple cell strings St_1 to St_m. The multiple cell strings St_1 to St_m may be connected between bit lines BL1 to BLm and the source line CSL. Each of the multiple cell strings St_1 to St_m may include a drain selection transistor DST, multiple cell transistors MC0 to MCn-1, and a source selection transistor SST connected in series between each of the bit lines BL1 to BLm and the source line CSL. In this case, since the configuration of the multiple cell strings St_1 to St_m is identical except for the names of the input signals or connection lines, the configuration of cell string St_1 among the multiple cell strings St_1 to St_m-1 is described representatively.

[0034] In an embodiment, the cell string St_1 may include a drain selection transistor DST, a plurality of cell transistors MC0 to MCn-1, and a source selection transistor SST connected in series between bit line BL1 and source line CSL.

[0035] In an embodiment, the drain selection transistor DST may have a gate connected to the drain selection line DSL, a drain connected to the bit line BL1, and a source connected to the unit transistor MCn-1.

[0036] In this embodiment, multiple unit transistors MC0 to MCn-1 can be connected in series between the drain select transistor DST and the source select transistor SST, and each of the multiple word lines WL0 to WLn-1 can be connected to a corresponding gate. Each of the multiple unit transistors MC0 to MCn-1 can be used as a memory cell for programming and erasing data.

[0037] In the following text, each of the multiple unit transistors MC0 to MC_n-1 can be referred to as a memory cell.

[0038] In an embodiment, the source selection transistor SST may have a gate connected to the source selection line SSL, a drain connected to the unit transistor MC0, and a source connected to the source line CSL.

[0039] As described above, the page buffer group 120 may include multiple page buffers PB1 to PBm. The multiple page buffers PB1 to PBm may be connected to multiple bit lines BL1 to BLm respectively. The multiple page buffers PB1 to PBm may each sense the threshold voltage of memory cells MC0 to MCn-1 through the connected bit lines BL1 to BLm. The page buffer group 120 may provide the data counting circuit 160 with the threshold voltage sensing result of at least one of the multiple page buffers PB1 to PBm, i.e., a sensing detection signal SD.

[0040] Figure 3 This is a diagram illustrating a page buffer of a memory device according to embodiments of the present disclosure. Figure 3 by Figure 1 Take page buffer PB1 as an example among the multiple page buffers PB1 to PBm shown, and the description of each of the multiple page buffers PB1 to PBm can be replaced by the description of page buffer PB1.

[0041] Reference Figure 3 Page buffer PB1 may include multiple latches Latch1 to Latch5 and a connection switch SW. For example, page buffer PB1 may include first latches Latch1 to fourth latches Latch4. Among the first latches Latch1 to fourth latches Latch4, one latch may sense the threshold voltage of the memory cell connected to the bit line BL. In addition, among the first latches Latch1 to fourth latches Latch4, the remaining latches may store the count value C<0:2> sent from the data counting circuit 160.

[0042] In this embodiment, the first latch (Latch 1) to the fourth latch (Latch 4) can be connected together to the sensing node (SO). The connection switch (SW) can electrically connect the bit line (BL) to the sensing node (SO) or disconnect the bit line (BL) from the sensing node (SO).

[0043] In an embodiment, the connection switch SW can electrically connect the bit line BL to the sensing node SO or disconnect the bit line BL from the sensing node SO based on the page buffer select signal PB_sel. For example, the connection switch SW can electrically connect the bit line BL to the sensing node SO based on a first-level page buffer select signal PB_sel. The connection switch SW can disconnect the bit line from the sensing node SO based on a second-level page buffer select signal PB_sel, which is different from the first level. The first level can represent a high level, and the second level can represent a low level. In the following description, the first level is a high level, and the second level is a low level; however, the first level of the page buffer select signal PB_sel can represent the level at which the connection switch SW is turned on, and the second level can represent the level at which the connection switch SW is turned off. The page buffer select signal PB_sel can be included in the page buffer control signal PB_ctrl.

[0044] In this embodiment, the first latch (Latch1) through the fourth latch (Latch4) can be connected together to the sensing node (SO). The first latch (Latch1) can be the latch closest to the bit line (BL).

[0045] In this embodiment, when the bit line BL is electrically connected to the sensing node SO, the first latch 1 can sense the voltage level of the sensing node SO, and the voltage level of the sensing node SO changes according to the voltage level of the bit line BL. That is, the first latch 1 can detect the voltage level of the bit line BL by sensing the voltage level of the sensing node SO.

[0046] In this embodiment, the first latch Latch1 can detect the voltage level of the bit line BL and store and output information about whether the memory cell is on. For example, when the memory cell is on and the voltage level of the bit line drops to a set voltage level or lower, that is, when the voltage level of the sensing node SO drops to a voltage level corresponding to the set voltage level or lower, the first latch Latch1 can store a second level. On the other hand, when the memory cell is not on and the voltage level of the bit line does not drop, that is, when the voltage level of the sensing node SO does not change, the first latch Latch1 can store a first level. Therefore, since the first latch Latch1 performs the function of sensing whether the memory cell is on, it can be called a sensing latch. In addition, the first latch Latch1 can send the stored level as a sensing detection signal SD to the data counting circuit 160.

[0047] In this embodiment, the second latch (Latch 2) through the fourth latch (Latch 4) can store the count value C<0:2>. For example, the second latch (Latch 2) can store the count value C<0:2>. <2> The third latch, Latch 3, can store the count value C. <1> The fourth latch, Latch 4, can store the count value C. <0> As data, latches 2 through 4 are latches that output the count value C<0:2> as data for the read operation, and therefore can be called data latches. The count value C<0:2> can be a value sent from the counting data circuit 160.

[0048] Figure 4 This is a diagram illustrating the operation of determining data stored in a memory cell of a memory device according to embodiments of the present disclosure. A memory cell is a memory cell that stores at least one bit of data. Figure 4 In the illustration, a memory cell storing 3 bits of data is shown as an example of a memory cell; however, the embodiments are not limited thereto.

[0049] Reference Figure 4 A memory cell can store data represented by the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB). Therefore, the threshold voltage of a memory cell can include eight different threshold voltage levels.

[0050] In an embodiment, a memory cell with a lowest threshold voltage can store data where the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB) are all at a low level (0). In this case, the threshold voltage level of the memory cell with the lowest threshold voltage can be lower than the level of the first data determination voltage RV1, which is at the lowest level. The lowest threshold voltage among the threshold voltages of the memory cells can be referred to as the first threshold voltage, and the first data determination voltage RV1, which has the lowest voltage level, can be referred to as the first data determination voltage.

[0051] In an embodiment, a memory cell with a second threshold voltage may have a threshold voltage higher than a first threshold voltage. The level of the second threshold voltage may be higher than the level of the first data determination voltage RV1 and lower than the level of the second data determination voltage RV2. A memory cell with a second threshold voltage may store data in which the least significant bit (LSB) is high (1) and the middle significant bit (CSB) and the most significant bit (MSB) are low (0).

[0052] In an embodiment, a memory cell with a third threshold voltage may have a threshold voltage higher than the second threshold voltage. The level of the third threshold voltage may be higher than the level of the second data determination voltage RV2 and lower than the level of the third data determination voltage RV3. A memory cell with a third threshold voltage may store data in which the least significant bit (LSB) is low (0), the middle significant bit (CSB) is high (1), and the most significant bit (MSB) is low (0).

[0053] In an embodiment, a memory cell with a fourth threshold voltage may have a threshold voltage higher than a third threshold voltage. The level of the fourth threshold voltage may be higher than the level of the third data determination voltage RV3 and lower than the level of the fourth data determination voltage RV4. A memory cell with a fourth threshold voltage may store data in which the least significant bit (LSB) is high (1), the middle significant bit (CSB) is high (1), and the most significant bit (MSB) is low (0).

[0054] In an embodiment, a memory cell having a fifth threshold voltage may have a threshold voltage higher than a fourth threshold voltage. The level of the fifth threshold voltage may be higher than the level of the fourth data determination voltage RV4 and lower than the level of the fifth data determination voltage RV5. A memory cell having a fifth threshold voltage may store data in which the least significant bit (LSB) is low (0), the middle significant bit (CSB) is low (0), and the most significant bit (MSB) is high (1).

[0055] In an embodiment, a memory cell having a sixth threshold voltage may have a threshold voltage higher than a fifth threshold voltage. The level of the sixth threshold voltage may be higher than the level of the fifth data determination voltage RV5 and lower than the level of the sixth data determination voltage RV6. A memory cell having a sixth threshold voltage may store data where the least significant bit (LSB) is high (1), the middle significant bit (CSB) is low (0), and the most significant bit (MSB) is high (1).

[0056] In an embodiment, a memory cell with a seventh threshold voltage may have a threshold voltage higher than the sixth threshold voltage. The level of the seventh threshold voltage may be higher than the level of the sixth data determination voltage RV6 and lower than the level of the seventh data determination voltage RV7. A memory cell with a seventh threshold voltage may store data in which the least significant bit (LSB) is low (0), the middle significant bit (CSB) is high (1), and the most significant bit (MSB) is high (1).

[0057] In an embodiment, a memory cell with an eighth threshold voltage may have a threshold voltage higher than the seventh threshold voltage. The level of the eighth threshold voltage may be higher than the level of the seventh data determination voltage RV7 and lower than the level of the eighth data determination voltage RV8. A memory cell with an eighth threshold voltage may store data in which the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB) are all at a high level (1).

[0058] In the embodiments, the operation of the memory device according to the embodiments of the present disclosure is as follows.

[0059] In this embodiment, during a read operation, the memory cell to be read can be selected based on the drive address signal ADD_d of the address signal ADD.

[0060] In an embodiment, the word line connected to the selected memory cell, i.e., the selected word line, can sequentially receive the first data determination voltage RV1 to the eighth data determination voltage RV8. For example... Figure 4 As shown, the first data determination voltage RV1 to the eighth data determination voltage RV8 can be voltages that increase sequentially in voltage level. In this case, the data counting circuit 160 can receive a voltage control signal V_ctrl, which is used to control the provision of the first data determination voltage RV1 to the eighth data determination voltage RV8. Whenever the level of the data determination voltage provided to the word line changes, the data counting circuit 160 can perform an upward counting operation by increasing the count value C<0:2> based on the voltage control signal V_ctrl.

[0061] In an embodiment, a memory cell can be turned on when the voltage level supplied to the word line that sequentially receives the first data determination voltage RV1 to the eighth data determination voltage RV8 is higher than the threshold voltage level of the memory cell connected to that word line. When the memory cell is turned on, the level of the bit line connected to the memory cell can be lower than a set voltage level. In this case, the level stored in the first latch Latch1 of the page buffer connected to the bit line can be changed. For example, the level stored in the first latch Latch1 can be initialized to a first level and can be changed to a second level when the voltage level of the bit line is lower than the set voltage level. In this case, the first latch Latch1 can send a sensing detection signal SD of the second level to the data counting circuit 160.

[0062] In an embodiment, the data counting circuit 160 that receives the second-level sensing detection signal SD can stop the counting operation and send the count value C<0:2> of the stopped counting operation to the second latch Latch2 to the fourth latch Latch4 of the page buffer.

[0063] In this embodiment, the count value C<0:2> stored in the second latch (Latch 2) to the fourth latch (Latch 4) of the page buffer can be data stored in a memory cell and can be output to an external device (e.g., a memory controller (not shown)) or provided to the code conversion circuit 170. In this case, the data output from the page buffer can be data in a first format, and the first format data can be converted to second format data by the code conversion circuit 170 and output to an external device. The first format data can be data based on an upward-counting count value, and the second format data can be data based on Gray code.

[0064] The following will refer to Figure 5 The operation of a memory device operating in this manner according to embodiments of the present disclosure will be described in more detail.

[0065] Figure 5 This is a diagram illustrating the operation of a memory device according to embodiments of the present disclosure. In this case, a memory cell may be a memory cell having one of a first threshold voltage to an eighth threshold voltage at different levels. A memory cell may also be a memory cell storing data corresponding to a sixth threshold voltage among the first to eighth threshold voltages.

[0066] Reference Figure 5 In order to determine the data stored in the selected memory cell during a read operation, the first data determination voltage RV1 to the eighth data determination voltage RV8 can be provided sequentially to the word line connected to the selected memory cell, i.e., the selected word line.

[0067] In an embodiment, whenever the first data determination voltage RV1 to the eighth data determination voltage RV8 are sequentially supplied to the selected word line, the data counting circuit 160 may sequentially increment the count value C<0:2>.

[0068] For example, when control circuit 110 provides voltage control signal V_ctrl to data counting circuit 160 to instruct voltage generation circuit 130 to generate a first data determination voltage RV1, data counting circuit 160 can generate a count value C<0:2> of (0, 0, 0). The count value C<0:2> can be expressed as C <2> C <1> C <0> The sequence is described as follows: When the control circuit 110 provides the data counting circuit 160 with a voltage control signal V_ctrl to instruct the voltage generation circuit 130 to generate the second data determination voltage RV2, the data counting circuit 160 can generate a count value C<0:2> of (0, 0, 1). When the control circuit 110 provides the data counting circuit 160 with a voltage control signal V_ctrl to instruct the voltage generation circuit 130 to generate the third data determination voltage RV3, the data counting circuit 160 can generate a count value C<0:2> of (0, 1, 0). When the control circuit 110 provides the data counting circuit 160 with a voltage control signal V_ctrl to instruct the voltage generation circuit 130 to generate the fourth data determination voltage RV4, the data counting circuit 160 can generate a count value C<0:2> of (0, 1, 1). When control circuit 110 provides voltage control signal V_ctrl to data counting circuit 160 to instruct voltage generation circuit 130 to generate fifth data determination voltage RV5, data counting circuit 160 can generate a count value C<0:2> of (1, 0, 0). When control circuit 110 provides voltage control signal V_ctrl to data counting circuit 160 to instruct voltage generation circuit 130 to generate sixth data determination voltage RV6, data counting circuit 160 can generate a count value C<0:2> of (1, 0, 1). When control circuit 110 provides voltage control signal V_ctrl to data counting circuit 160 to instruct voltage generation circuit 130 to generate seventh data determination voltage RV7, data counting circuit 160 can generate a count value C<0:2> of (1, 1, 0). When the control circuit 110 provides the data counting circuit 160 with a voltage control signal V_ctrl to instruct the voltage generation circuit 130 to generate the eighth data determination voltage RV8, the data counting circuit 160 can generate a count value C<0:2> of (1, 1, 1).

[0069] As described above, since the memory cell stores data corresponding to the sixth threshold voltage, it can be turned on when the sixth data determination voltage RV6 is provided to the selected word line. The turned-on memory cell can reduce the voltage level of the bit line to a set voltage level or lower, so the voltage level of the sensing detection signal SD can change from the first level to the second level.

[0070] In this embodiment, the sensing signal SD indicating a change in voltage level can stop the counting operation of the data counting circuit 160. Therefore, the data counting circuit 160 can send the count value C<0:2> of (1, 0, 1) to the second latch Latch 2 to the fourth latch Latch 4 of the page buffer when the sixth data determination voltage RV6 is provided. The second latch Latch 2 can store the level corresponding to the least significant bit (LSB), i.e., a high level; the third latch Latch 3 can store the level corresponding to the middle significant bit (CSB), i.e., a low level; and the fourth latch Latch 4 can store the level corresponding to the most significant bit (MSB), i.e., a high level.

[0071] In this way, data in a first format, based on the least significant bit (LSB), middle significant bit (CSB), and most significant bit (MSB) stored in the second latch (Latch 2) to the fourth latch (Latch 4), can be provided to an external device or code conversion circuit 170.

[0072] Figure 6 This is a diagram illustrating the operation of a code translation circuit of a memory device according to an embodiment of the present disclosure.

[0073] In an embodiment, Figure 6 The code conversion operation of the code conversion circuit 170 shown can be an operation to convert data in a first format with code values ​​MSB, CSB, LSB that are sequentially incremented by a count value C<0:2> into Gray code.

[0074] In this embodiment, the code conversion circuit 170 can convert data in a first format (0, 0, 0) to data in a second format (1, 1, 1). (This is repeated four times in the original text.)

[0075] Figure 7 This is a diagram illustrating the effects of a memory device according to embodiments of the present disclosure.

[0076] exist Figure 7 In (A), to determine the least significant bit (LSB) stored in the memory cell, a seventh data determination voltage RV7 and a third data determination voltage RV3 can be provided to the selected word line sequence, and then the selected word line can be precharged. A sixth data determination voltage RV6, a fourth data determination voltage RV4, and a second data determination voltage RV2 can be provided to the precharged word line sequence. Subsequently, the word line can be precharged again. A fifth data determination voltage RV5 and a first data determination voltage RV1 can be provided to the precharged word line.

[0077] In this way, Figure 7 The data determination method shown in (A) can provide a data determination voltage corresponding to the word line in order to sequentially determine the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB), and can include precharging the word line before providing the data determination voltage to determine the time period of the next bit.

[0078] exist Figure 7 In (B), the count value C<0:2> can be incremented whenever the level of the data determination voltage provided to the selected word line changes, and the count value C<0:2> can be provided as the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB) stored in the memory cell when the memory cell is turned on according to the voltage level of the selected word line.

[0079] Therefore, with Figure 7 (A) is different, in Figure 7 In (B), the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB) stored in the memory cell can be determined simultaneously. Furthermore, because the LSB, CSB, and MSB are determined simultaneously, a precharge period for determining the next bit is not required after determining the previous bit.

[0080] Therefore, the speed of the read operation for determining data in the memory device according to embodiments of this disclosure can be higher than [the speed of read operations]. Figure 7 The speed in method (A).

[0081] Figure 8 This is a diagram illustrating the configuration of a memory device according to another embodiment of the present disclosure.

[0082] Reference Figure 8 The memory device may include a control circuit 110, a sensing latch group 121, a data latch group 122, a voltage generation circuit 130, a line drive circuit 140, a memory cell array 150, and a data counting circuit 160.

[0083] In an embodiment, the control circuit 110 can control the sensing latch group 121, the data latch group 122, the voltage generation circuit 130, the line drive circuit 140, and the data counting circuit 160 to program and store data in the memory cell array 150, or output the data stored in the memory cell array 150.

[0084] In an embodiment, the control circuit 110 may generate a page buffer control signal PB_ctrl based on the command signal CMD and the address signal ADD received from an external device (e.g., a host), and provide the page buffer control signal PB_ctrl to the page buffer group 120.

[0085] In this embodiment, the control circuit 110 can generate a voltage control signal V_ctrl based on the command signal CMD and provide the voltage control signal V_ctrl to the voltage generation circuit 130.

[0086] In this embodiment, the control circuit 110 can generate a drive address signal ADD_d based on the command signal CMD and the address signal ADD, and provide the drive address signal ADD_d to the line drive circuit 140.

[0087] In this embodiment, the sensing latch group 121 may include multiple sensing latches SL1, SL2, ..., and SLm. The multiple sensing latches SL1, SL2, ..., and SLm may be connected to multiple bit lines BL1, BL2, ..., and BLm, respectively, where m is a natural number. Each of the multiple sensing latches SL1, SL2, ..., and SLm can sense the data value stored in the memory cell through the bit lines, store the sensed value as a sensing detection signal SD, and output the sensing detection signal SD. The sensing detection signal SD may be provided to the data counting circuit 160.

[0088] In an embodiment, the data latch group 122 may include multiple data latch circuits DS1, DS2, ..., DSm for storing the count value C<0:2> provided by the data counting circuit 160. The multiple data latch circuits DS1, DS2, ..., DSm may each include bits C that store the count value C<0:2>. <0> C <1> and C <2> The data latches. The count value C<0:2> stored in the data latch group 122 can be used as data output based on the read operation.

[0089] In an embodiment, the voltage generation circuit 130 can generate internal voltages V_int at various voltage levels based on the voltage control signal V_ctrl, and provide the internal voltages V_int to the line drive circuit 140. For example, during a read operation, the voltage generation circuit 130 can sequentially provide the line drive circuit 140 with multiple data determination voltages RV1 to RV8 at different levels (e.g., ...). Figure 4 and Figure 5 (As shown) is the internal voltage V_int.

[0090] In this embodiment, the line driver circuit 140 can drive the drain select line DSL, word line WL, and source select line SSL to the voltage level of the internal voltage V_int based on the drive address signal ADD_d. For example, the line driver circuit 140 can selectively drive the drain select line DSL, word line WL, and source select line SSL to the voltage level of the internal voltage V_int based on the drive address signal ADD_d. Specifically, during a read operation, the line driver circuit 140 can sequentially drive the word line WL selected according to the drive address ADD_d to the voltage levels of multiple data determination voltages RV1 to RV8.

[0091] In an embodiment, the memory cell array 150 may include a plurality of memory blocks BK1, BK2, ..., and BKn, where n is a natural number. Each of the plurality of memory blocks BK1, BK2, ..., and BKn may be selected by driving a drain select line DSL, a word line WL, and a source select line SSL, and the memory string of the selected memory block may be connected to a plurality of page buffers PB1, PB2, ..., and PBm via bit lines BL1, BL2, ..., and BLm. Additionally, each of the plurality of memory blocks BK1, BK2, ..., and BKn may include a plurality of memory strings in which a plurality of memory cells are connected in series. Besides including a plurality of memory cells connected in series, each of the plurality of memory strings may also include a first select transistor (e.g., a drain select transistor), a second select transistor (e.g., a source select transistor), and a dummy cell. The first select transistor may be turned on or off according to the voltage level of the drain select line DSL, and the second select transistor may be turned on or off according to the voltage level of the source select line SSL.

[0092] In this embodiment, the data counting circuit 160 can perform a counting operation based on the voltage control signal V_ctrl, and stop performing the counting operation when the sense latch connected to the selection line in the sense latch group 121 detects that the memory cell is turned on. Additionally, the data counting circuit 160 can send a count value C<0:2> to the data latch group 122 when the counting operation stops. For example, the data counting circuit 160 can perform a counting operation based on the voltage control signal V_ctrl, stop the counting operation based on the sense detection signal SD, which is the output of the sense latch connected to the selection line, and provide the count value C<0:2> of the stopped counting operation to the data latch group 122.

[0093] In an embodiment, Figure 8 The sense latch group 121 and data latch group 122 of the memory device shown can be as follows: Figure 1 The page buffers in each of the page buffer groups 120 included in the memory device shown are distinguished by the sense latch Latch1 and the data latches Latch2 to Latch4, and the group including sense latches SL1, SL2, ... and SLm can be referred to as group 121, and the group including data latch circuits DS1, DS2, ... and DSm with data latches Latch2 to Latch4 can be referred to as group 122.

[0094] While embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is merely for describing embodiments according to the concept of this disclosure, and this disclosure is not limited to the above embodiments. Those skilled in the art to which this disclosure pertains will recognize that various types of substitutions, modifications, and variations can be made to the embodiments without departing from the technical concept defined by the appended claims, and it should be understood that such substitutions, modifications, and variations fall within the scope of this disclosure. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A memory device, comprising: The voltage generation circuit determines the voltage by sequentially generating multiple data points of different levels based on the voltage control signal. The line driving circuit sequentially drives the selected word lines to the plurality of data determination voltages; A page buffer generates a sensing detection signal when a memory cell connected to the selected word line is turned on. as well as The data counting circuit performs a counting operation based on the voltage control signal, stops the counting operation based on the sensing detection signal, and provides the page buffer with a count value based on the counting operation.

2. The memory device according to claim 1, wherein, The voltage generation circuit generates the plurality of data-determined voltages based on the voltage control signal, in order from the lowest data-determined voltage to the highest data-determined voltage.

3. The memory device according to claim 2, wherein, The line driving circuit sequentially drives the selected word lines in order from the lowest data-determined voltage to the highest data-determined voltage.

4. The memory device according to claim 3, wherein, The page buffer includes multiple latches, and One of the plurality of latches generates the sensing detection signal when the bit line is connected to the sensing node and the level of the bit line drops to a set level or lower.

5. The memory device according to claim 4, wherein, The remaining latches among the plurality of latches store the count value.

6. The memory device according to claim 5, wherein, Whenever the level of the multiple data determination voltages provided to the selected word line changes, the data counting circuit counts the count value upwards based on the voltage control signal.

7. The memory device according to claim 6, wherein, When the data counting circuit receives the sensing detection signal, it stops counting the count value upwards and provides the count value corresponding to the stopped upward counting to the remaining latch in the page buffer.

8. The memory device of claim 7, further comprising a code conversion circuit that converts the data stored in the remaining latch into Gray code-based data to output the converted data.

9. A memory device, comprising: A line driving circuit provides multiple data-determining voltages of different levels to a selected word line to drive the selected word line; At least one sensing latch generates a sensing detection signal when a memory cell connected to the selected word line is turned on; A data counting circuit performs a counting operation whenever the level of multiple data determination voltages used to drive the selected word line changes, stops the counting operation based on the sensing detection signal, and generates a count value based on the counting operation. as well as At least one data latch circuit stores the count value and outputs the stored count value as data.

10. The memory device according to claim 9, wherein, The line driving circuit provides the plurality of data determination voltages to the selected word line in order from the lowest data determination voltage to the highest data determination voltage, so as to drive the selected word line.

11. The memory device according to claim 10, wherein, The sensing latch determines that the memory cell is turned on when the voltage level of the bit line connected to the memory cell drops to a set level or lower.

12. The memory device according to claim 11, wherein, Whenever the level of the multiple data determination voltages provided to the selected word line changes, the data counting circuit counts the count value upwards.

13. The memory device according to claim 11, wherein, When the data counting circuit receives the sensing detection signal, it stops counting the count value upwards and provides the count value corresponding to the stopped upward counting to the data latch circuit in the at least one data latch circuit.

14. The memory device according to claim 13, wherein, The at least one data latch circuit stores the count value.

15. A method of operating a memory device, comprising: During a read operation, different levels of data-determining voltage are sequentially supplied to the selected word lines; A counting operation is performed whenever the data determines a change in voltage level. Detect the voltage level of the bit line of the memory cell connected to the selected word line; The counting operation is stopped when the detected voltage level of the bit line is lower than the set level. as well as Output the count value corresponding to the stopped counting operation as data.

16. The method of operating a memory device according to claim 15, wherein, Providing data determination voltages at different levels sequentially includes providing the data determination voltages in order from the lowest data determination voltage to the highest data determination voltage.

17. The method of operating a memory device according to claim 16, wherein, Performing the counting operation includes counting up the count value.

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