Circuit and method for modulating PLL loop bandwidth based on VCO adjustable capacitor and circuit board
By modulating the PLL loop circuit with a VCO adjustable capacitor and dynamically adjusting the capacitor value to regulate the gain coefficient, the noise-power consumption problem in the traditional PLL loop bandwidth control is solved, realizing flexible bandwidth adjustment and low power consumption design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU AOSHIXIN TECH CO LTD
- Filing Date
- 2023-12-21
- Publication Date
- 2026-04-28
AI Technical Summary
Traditional PLL loop bandwidth control is constrained by noise and power consumption. High bandwidth leads to low lockout time and increased clock jitter, and existing noise handling methods contradict low-power design.
A PLL loop circuit based on VCO adjustable capacitor modulation is adopted. Through the direct connection of the charge-sharing filter and the phase-locked loop proportional path charge pump to the capacitor adjustable voltage-controlled oscillator, the capacitor value is dynamically adjusted to adjust the gain coefficient, thereby achieving flexible bandwidth modulation.
It achieves low power consumption and flexible PLL loop bandwidth adjustment, reduces hardware design complexity and circuit board area, and improves noise suppression capability.
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Figure CN121939976A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of phase-locked loop sources, specifically to circuits, methods, and circuit boards for modulating the loop bandwidth of a PLL based on a VCO adjustable capacitor. Background Technology
[0002] See Figure 1 , Figure 2 A PLL (Phase Locked Loop) is a phase-locked loop used to unify and integrate clock signals, ensuring the normal operation of high-frequency devices. The PLL loop bandwidth is equal to the integral of its closed-loop frequency response, reflecting the loop's noise suppression capability. A smaller noise bandwidth indicates a narrower loop and stronger noise suppression. Furthermore, the noise bandwidth is also related to the loop gain K, damping coefficient, and undamped oscillation frequency. For example, adjusting the PLL loop bandwidth (Kp, proportional path gain) means modifying the gain coefficient of the proportional path in the phase-locked loop to adjust the loop bandwidth.
[0003] As can be seen from the above, traditional PLL loop bandwidth control is constrained by "noise-power consumption". Higher PLL loop bandwidth means lower lockout time. At the same time, increasing the PLL bandwidth will reduce the loop system's ability to suppress in-band noise, thereby introducing more clock jitter into the output clock signal.
[0004] Typically, in order to improve loop bandwidth without affecting noise performance, additional noise reduction measures are required, such as increasing the reference clock frequency, introducing auxiliary loops, and increasing the charge pump current. However, these methods are all contrary to low-power design, making it difficult to solve the "noise-power" constraint. Summary of the Invention
[0005] In view of this, it is necessary to provide a circuit, method and circuit board for modulating the loop bandwidth of a PLL based on a VCO adjustable capacitor, which is highly flexible and has low power consumption.
[0006] This invention provides a circuit based on VCO adjustable capacitor modulation of PLL loop bandwidth, including: a frequency and phase detector, a charge-sharing filter, a phase-locked loop proportional path charge pump, and a capacitor-adjustable voltage-controlled oscillator;
[0007] The input terminal of the frequency and phase detector is connected to the reference signal;
[0008] The first output terminal of the frequency and phase detector is connected to the first input terminal of the capacitor-adjustable voltage-controlled oscillator through a charge-sharing filter.
[0009] The second output terminal of the frequency and phase detector is connected to the second input terminal of the capacitor-adjustable voltage-controlled oscillator via a phase-locked loop proportional path charge pump.
[0010] The capacitor-adjustable voltage-controlled oscillator includes: a capacitor bank and a VCO circuit module connected in parallel; the parallel connection point of the capacitor bank and the VCO circuit module is connected to the positive and negative output terminals VOUT+ and VOUT- of the capacitor-adjustable voltage-controlled oscillator.
[0011] The VCO circuit module is also connected to the output control voltage signal of the charge-sharing filter and the phase-locked loop proportional path charge pump.
[0012] Optionally, the charge-sharing filter includes: an integral path charge pump and a low-pass filter module;
[0013] The first output terminal of the frequency and phase detector is connected to the first input terminal of the capacitor-adjustable voltage-controlled oscillator via an integral path charge pump and a low-pass filter module.
[0014] Optionally, the VCO circuit module includes:
[0015] The system consists of a first variable capacitor C1, a second variable capacitor C2, a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, and an inductor L1.
[0016] The first MOSFET Q1 and the second MOSFET Q2 form a first cross-coupled negative resistor, and the third MOSFET Q3 and the fourth MOSFET Q4 form a second cross-coupled negative resistor.
[0017] The first terminal of the first cross-coupled negative resistor is connected in parallel to the second terminal of the first cross-coupled negative resistor and then connected to the voltage terminal VDD.
[0018] The third terminal of the first cross-coupled negative resistor is connected to the first terminal of inductor L1, the first terminal of the first variable capacitor C1, and the first terminal of the second cross-coupled negative resistor, respectively.
[0019] The fourth terminal of the first cross-coupled negative resistor is connected to the second terminal of inductor L1, the first terminal of the second variable capacitor C2, and the second terminal of the second cross-coupled negative resistor, respectively. The third terminal of the second cross-coupled negative resistor is connected in parallel to the fourth terminal of the first cross-coupled negative resistor and then grounded.
[0020] The second terminal of the first variable capacitor C1 is connected to the second terminal of the second variable capacitor C2.
[0021] Optionally, the third terminal and the fourth terminal of the first cross-coupled negative resistor are the parallel connection points of the capacitor bank and the VCO circuit module.
[0022] Optionally, the first MOSFET Q1, the second MOSFET Q2, the third MOSFET Q3, and the fourth MOSFET Q4 are all P-MOSFETs.
[0023] Optionally, the feedback signal terminal of the capacitor-adjustable voltage-controlled oscillator is connected to the feedback signal input terminal of the frequency and phase detector via a frequency divider.
[0024] The present invention also provides a method for modulating the bandwidth of a PLL loop, wherein the PLL loop employs the circuit described above based on the VCO adjustable capacitor for modulating the PLL loop bandwidth; the modulation method includes:
[0025] By changing the capacitance value of the capacitor-adjustable voltage-controlled oscillator, the proportional path gain value in the phase-locked loop proportional path charge pump is adjusted, thereby modulating the PLL loop bandwidth.
[0026] The present invention also provides a circuit board for a PLL loop bandwidth adjustment circuit, comprising: a circuit for modulating the PLL loop bandwidth based on a VCO adjustable capacitor as described above, and a substrate carrying the circuit for modulating the PLL loop bandwidth based on a VCO adjustable capacitor.
[0027] The advantages of the technical solution provided in this application are:
[0028] 1. In this application, a charge-sharing filter is used to achieve low-pass filtering and integration path functions, and the phase-locked loop proportional path charge pump is directly connected to a capacitor-adjustable voltage-controlled oscillator. In use, the gain coefficient of the phase-locked loop proportional path charge pump is changed by changing the output frequency of the capacitor-adjustable voltage-controlled oscillator, thereby realizing bandwidth modulation of the PLL loop. By dynamically adjusting the gain coefficient of the phase-locked loop proportional path, the modulation of the PLL loop bandwidth has the characteristics of flexibility and low power consumption.
[0029] 2. This application does not introduce additional hardware structures, which can reduce the complexity of hardware design and circuit board area. Attached Figure Description
[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of the structure of a PLL loop in the prior art;
[0032] Figure 2 This is a schematic diagram of the mathematical model of a PLL loop in the prior art;
[0033] Figure 3 This is a schematic diagram of the circuit structure of a PLL loop bandwidth adjustment circuit provided by the present invention;
[0034] Figure 4 This is a circuit diagram of the capacitor-adjustable voltage-controlled oscillator provided by the present invention;
[0035] In the picture:
[0036] 10 is a frequency and phase detector, 20 is a charge-sharing filter, 30 is a phase-locked loop proportional path charge pump, 40 is a capacitor-adjustable voltage-controlled oscillator, and 50 is a frequency divider.
[0037] 201 is an integral path charge pump, and 202 is a low-pass filter module;
[0038] 401 is a capacitor bank, and 402 is a VCO circuit module;
[0039] C1 is the first variable capacitor, and C2 is the second variable capacitor;
[0040] L1 is an inductor;
[0041] Q1 is the first MOSFET, Q2 is the second MOSFET, Q3 is the third MOSFET, and Q4 is the fourth MOSFET;
[0042] VDD is the voltage terminal. Detailed Implementation
[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0044] In this invention, the use of terms such as "first," "second," etc., is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0045] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.
[0046] The following section will further introduce the specific implementation method, as well as the technical difficulties and inventive points of this invention, using this design example as an example.
[0047] Example 1
[0048] See Figure 3 A circuit based on VCO adjustable capacitor modulation of PLL loop bandwidth is characterized by comprising: a frequency and phase detector 10, a charge sharing filter 20, a phase-locked loop proportional path charge pump 30, and a capacitor adjustable voltage-controlled oscillator 40.
[0049] The input terminal of the frequency and phase detector 10 is connected to the reference signal;
[0050] The first output terminal of the frequency and phase detector 10 is connected to the first input terminal of the capacitor-adjustable voltage-controlled oscillator 40 through the charge-sharing filter 20.
[0051] The second output terminal of the frequency and phase detector 10 is connected to the second input terminal of the capacitor-adjustable voltage-controlled oscillator 40 through the phase-locked loop proportional path charge pump 30.
[0052] The capacitor-adjustable voltage-controlled oscillator 40 includes: a capacitor bank 401 and a VCO circuit module 402 connected in parallel; the parallel connection point of the capacitor bank 401 and the VCO circuit module 402 is connected to the positive and negative output terminals VOUT+ and VOUT- of the capacitor-adjustable voltage-controlled oscillator 40.
[0053] The VCO circuit module 402 is also connected to the output control voltage signal of the charge-sharing filter 20 and the phase-locked loop proportional path charge pump 30.
[0054] This embodiment proposes a circuit for modulating the PLL loop bandwidth based on a VCO with adjustable capacitors. It achieves low-pass filtering and integration path functions through a charge-sharing filter, and directly connects the PLL proportional path charge pump to a capacitor-adjustable voltage-controlled oscillator. In use, by changing the capacitance value of the capacitor-adjustable voltage-controlled oscillator, the gain coefficient of the PLL proportional path charge pump is changed, thus achieving PLL loop bandwidth modulation. In this embodiment, by dynamically adjusting the PLL proportional path gain coefficient, the modulation of the PLL loop bandwidth exhibits flexibility and low power consumption.
[0055] In this embodiment, the charge-sharing filter 20 includes an integral path charge pump 201 and a low-pass filter module 202; the first output terminal of the frequency and phase detector 10 is connected to the first output terminal of the capacitor-adjustable voltage-controlled oscillator 40 through the integral path charge pump 201 and the low-pass filter module 202.
[0056] It should be noted that in this embodiment, the loop filter in the traditional PLL loop structure is replaced by a charge-sharing filter and a phase-locked loop proportional path charge pump. This allows for parameter settings of the integral path charge pump and the phase-locked loop proportional path charge pump separately during the adjustment of the PLL loop bandwidth, thereby improving the flexibility of bandwidth adjustment.
[0057] In this embodiment, the VCO circuit module 402 includes:
[0058] The system consists of a first variable capacitor C1, a second variable capacitor C2, a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, and an inductor L1.
[0059] The first MOSFET Q1 and the second MOSFET Q2 form a first cross-coupled negative resistor, and the third MOSFET Q3 and the fourth MOSFET Q4 form a second cross-coupled negative resistor.
[0060] The first terminal of the first cross-coupled negative resistor is connected in parallel to the second terminal of the first cross-coupled negative resistor and then connected to the voltage terminal VDD.
[0061] The third terminal of the first cross-coupled negative resistor is connected to the first terminal of inductor L1, the first terminal of the first variable capacitor C1, and the first terminal of the second cross-coupled negative resistor, respectively.
[0062] The fourth terminal of the first cross-coupled negative resistor is connected to the second terminal of inductor L1, the first terminal of the second variable capacitor C2, and the second terminal of the second cross-coupled negative resistor, respectively. The third terminal of the second cross-coupled negative resistor is connected in parallel to the fourth terminal of the first cross-coupled negative resistor and then grounded.
[0063] The second terminal of the first variable capacitor C1 is connected to the second terminal of the second variable capacitor C2.
[0064] In this embodiment, the third end of the first cross-coupled negative resistor and the fourth end of the first cross-coupled negative resistor are the parallel connection points of the capacitor bank 401 and the VCO circuit module 402.
[0065] In this embodiment, the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4 are all P-MOS transistors.
[0066] It should be noted that in this embodiment, the phase-locked loop proportional path charge pump is directly connected to the capacitor-adjustable voltage-controlled oscillator. By changing the array access scale, the path gain coefficient is changed to achieve loop bandwidth modulation. This embodiment can reduce the complexity of hardware design and the circuit board area without introducing additional hardware structures.
[0067] In this embodiment, the feedback signal terminal of the capacitor-adjustable voltage-controlled oscillator 40 is connected to the feedback signal input terminal of the frequency and phase detector 10 through the frequency divider 50.
[0068] This application embodiment also provides a method for modulating the bandwidth of a PLL loop, wherein the PLL loop employs the circuit described above that modulates the PLL loop bandwidth based on a VCO adjustable capacitor; the modulation method includes:
[0069] By changing the capacitance value of the capacitor-adjustable voltage-controlled oscillator, the proportional path gain value in the phase-locked loop proportional path charge pump is adjusted, thereby modulating the PLL loop bandwidth.
[0070] This application embodiment also provides a circuit board for a PLL loop bandwidth adjustment circuit, including: the circuit for modulating the PLL loop bandwidth based on the VCO adjustable capacitor as described above, and a substrate carrying the circuit for modulating the PLL loop bandwidth based on the VCO adjustable capacitor.
[0071] It should be noted that in this embodiment, the phase-locked loop proportional path charge pump is directly connected to the capacitor-adjustable voltage-controlled oscillator, which can save circuit board area.
[0072] In this application, a phase-locked loop proportional path charge pump ( Adjusting the PLL loop bandwidth has advantages such as high flexibility, high energy efficiency, low chip area occupation, and wide adjustment range. It has broad application prospects and development space in wired transmission, wireless transmission, 5G communication and audio processing.
[0073] In summary, this application achieves bandwidth modulation of the PLL loop by changing the output frequency of the capacitor-adjustable voltage-controlled oscillator and altering the gain coefficient of the proportional path charge pump in the phase-locked loop. This method features low power consumption, flexible adjustment, and high practicality.
[0074] Although one embodiment of the invention has been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to that embodiment. Therefore, the appended claims are intended to be interpreted as including the described embodiment as well as all changes and modifications falling within the scope of the invention.
[0075] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A circuit based on VCO adjustable capacitor modulation of PLL loop bandwidth, characterized in that, include: Frequency and phase detector (10), charge-sharing filter (20), phase-locked loop proportional path charge pump (30) and capacitor-adjustable voltage-controlled oscillator (40); The input terminal of the frequency and phase detector (10) is connected to the reference signal; The first output terminal of the frequency and phase detector (10) is connected to the first input terminal of the capacitor-adjustable voltage-controlled oscillator (40) through a charge-sharing filter (20); The second output terminal of the frequency and phase detector (10) is connected to the second input terminal of the capacitor-adjustable voltage-controlled oscillator (40) through a phase-locked loop proportional path charge pump (30). The capacitor-adjustable voltage-controlled oscillator (40) includes: a capacitor bank (401) and a VCO circuit module (402) connected in parallel; the parallel connection point of the capacitor bank (401) and the VCO circuit module (402) is connected to the positive and negative output terminals VOUT+ and VOUT- of the capacitor-adjustable voltage-controlled oscillator (40); The VCO circuit module (402) is also connected to the output control voltage signal of the charge-sharing filter (20) and the phase-locked loop proportional path charge pump (30).
2. The circuit based on VCO adjustable capacitor modulation of PLL loop bandwidth according to claim 1, characterized in that, The charge-sharing filter (20) includes: an integral path charge pump (201) and a low-pass filter module (202); The first output terminal of the frequency and phase detector (10) is connected to the first input terminal of the capacitor-adjustable voltage-controlled oscillator (40) through an integral path charge pump (201) and a low-pass filter module (202).
3. The circuit based on VCO adjustable capacitor modulation of PLL loop bandwidth according to claim 1, characterized in that, The VCO circuit module (402) includes: The system consists of a first variable capacitor C1, a second variable capacitor C2, a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, and an inductor L1. The first MOSFET Q1 and the second MOSFET Q2 form a first cross-coupled negative resistor, and the third MOSFET Q3 and the fourth MOSFET Q4 form a second cross-coupled negative resistor. The first terminal of the first cross-coupled negative resistor is connected in parallel to the second terminal of the first cross-coupled negative resistor and then connected to the voltage terminal VDD. The third terminal of the first cross-coupled negative resistor is connected to the first terminal of inductor L1, the first terminal of the first variable capacitor C1, and the first terminal of the second cross-coupled negative resistor, respectively. The fourth terminal of the first cross-coupled negative resistor is connected to the second terminal of inductor L1, the first terminal of the second variable capacitor C2, and the second terminal of the second cross-coupled negative resistor, respectively. The third terminal of the second cross-coupled negative resistor is connected in parallel to the fourth terminal of the first cross-coupled negative resistor and then grounded. The second terminal of the first variable capacitor C1 is connected to the second terminal of the second variable capacitor C2.
4. The circuit based on VCO adjustable capacitor modulation of PLL loop bandwidth according to claim 3, characterized in that, The third end of the first cross-coupled negative resistor and the fourth end of the first cross-coupled negative resistor are the parallel connection points of the capacitor bank (401) and the VCO circuit module (402).
5. The PLL loop bandwidth adjustment and control circuit according to claim 3, characterized in that, The first MOSFET Q1, the second MOSFET Q2, the third MOSFET Q3, and the fourth MOSFET Q4 are all P-MOSFETs.
6. The circuit based on VCO adjustable capacitor modulation of PLL loop bandwidth according to claim 1, characterized in that, The feedback signal terminal of the capacitor-adjustable voltage-controlled oscillator (40) is connected to the feedback signal input terminal of the frequency and phase detector (10) through a frequency divider (50).
7. A method for modulating the loop bandwidth of a PLL, characterized in that, The PLL loop employs the circuit described in any one of claims 1 to 6, which modulates the PLL loop bandwidth based on a VCO adjustable capacitor; the modulation method includes: By changing the capacitance value of the capacitor-adjustable voltage-controlled oscillator, the proportional path gain value in the phase-locked loop proportional path charge pump is adjusted, thereby modulating the PLL loop bandwidth.
8. A circuit board for a PLL loop bandwidth adjustment circuit, characterized in that, include: The circuit based on VCO adjustable capacitor modulation of PLL loop bandwidth as described in any one of claims 1 to 6, and the substrate carrying the circuit based on VCO adjustable capacitor modulation of PLL loop bandwidth.