SARADC based on segmented redundant structure and data conversion method thereof

Abstract

The invention provides an SARADC based on a segmented redundant structure and a data conversion method thereof, and relates to the technical field of integrated circuit design. The SARADC adopts a core architecture of'segmented redundancy capacitor array + VCM differential switching + upper-level board sampling + digital error correction ', a capacitor array is divided into an MSB section and an LSB section, the highest-bit capacitor C6 of the LSB section is accurately set to be 33Cu through a non-binary redundancy weight distribution strategy, dynamic redundancy adjustment logic is combined, the total weight and M + L = 2n-1 are met, and n is the ADC bit number. The data conversion method comprises three core processes of sampling, successive approximation and digital correction, charge injection is eliminated through upper-level board sampling, power consumption is reduced through VCM differential switching, and non-binary codes are converted into standard binary codes to be output through the digital error correction circuit. Compared with a traditional SARADC, the number of capacitors is reduced by more than 80%, dynamic power consumption is reduced by 90%, the effective bit ENOB reaches 11.8 bits, gain errors and non-linear deviation are eliminated, and the SARADC is suitable for low-power-consumption and high-precision scenes such as the Internet of Things, wearable equipment and 5G communication.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, specifically to a SARADC based on a segmented redundancy structure and its data conversion method, which is particularly suitable for low-power, high-precision scenarios with strict requirements on power consumption, area, and accuracy, such as IoT terminals, wearable devices, 5G communication modules, and medical monitoring instruments. Background Technology

[0002] SARADCs have become the mainstream solution for medium-to-high precision analog-to-digital conversion due to their simple structure and controllable power consumption. However, existing SARADC technology has many drawbacks: Contradiction in capacitor array redundancy design: Traditional binary weighted capacitor arrays require 2 n The large number of capacitors results in high chip area and power consumption; although redundant capacitor arrays can improve error tolerance, too much redundancy can increase the area, while too little redundancy cannot compensate for process deviations. Conversion accuracy is limited: unreasonable weight allocation can easily introduce gain error and nonlinear deviation, especially at the junction of MSB and LSB, where capacitor matching error has a significant impact on accuracy; Sampling interference issues: Top plate sampling is prone to charge injection and clock feedthrough, while bottom plate sampling suffers from signal attenuation, affecting sampling accuracy; Imbalance between power consumption and speed: Under the requirement of high precision, the increase in the number of capacitors leads to an increase in dynamic power consumption, making it difficult to balance the requirements of high-speed conversion and low power consumption.

[0003] While existing technologies have attempted to improve the situation through dynamic weight allocation and redundant capacitor optimization, they have failed to simultaneously address the issue of coordinating the optimization of capacitor quantity, power consumption, and accuracy, and lack an integrated solution that combines flexibility and efficiency.

[0004] Therefore, those skilled in the art have provided SARADCs based on segmented redundancy structures and their data conversion methods to solve the problems mentioned in the background art. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a SARADC based on a segmented redundancy structure and its data conversion method. This solves the problem that while existing technologies have attempted to improve the situation through dynamic weight allocation and redundant capacitor optimization, they have failed to simultaneously address the coordinated optimization of capacitor quantity, power consumption, and accuracy.

[0006] To achieve the above objectives, the present invention provides the following technical solution: The SARADC based on a segmented redundancy structure and its data conversion method include a CDAC segmented capacitor array, a switching network, a comparator, a SAR logic unit, and a digital error correction (DEC) circuit. The data conversion method includes the following steps: Step 1: Sampling Phase Through the upper-level board sampling technology, the differential input signal is connected to the top plate of the CDAC capacitor array, and the bottom plate switch is uniformly connected to the common-mode voltage VCM. The gate voltage bootstrap switch is turned on to complete the signal sampling. Step Two: Successive Approximation Phase Based on the VCM architecture, the differential switching logic SAR logic unit controls the bottom plate switch of the CDAC capacitor array to switch to the reference voltage VREF or VCM in the order from MSB to LSB. The comparator compares the DAC output voltage in real time and outputs the comparison result. Step 3: Digital Calibration Stage The DEC circuit receives the non-binary code of the SAR logic output and converts it into a standard binary output code through a preset mapping logic. The CDAC capacitor array is divided into MSB and LSB segments, and non-binary redundancy weight allocation is used, with the total weights satisfying M+L=2. n -1, n is the target number of bits for the ADC, and the highest bit capacitor of the LSB segment is C6=33Cu, which optimizes the balance between redundancy and the number of capacitors.

[0007] Furthermore, the MSB segment of the CDAC capacitor array includes capacitors C7-C12, with weights assigned as 1Cu, 2Cu, 3Cu, 5Cu, 9Cu, and 18Cu, and the sum of the weights M = 52 + 104 + 156 + 260 + 468 + 936 = 1976. The LSB segment includes capacitors C0-C6, with weights assigned as 1Cu, 2Cu, 3Cu, 5Cu, 9Cu, 18Cu, and 33Cu. The sum of the weights L = 1 + 2 + 3 + 5 + 9 + 18 + 33 = 71, and the total weight M + L = 2047 = 2. 12 -1, n=12.

[0008] Furthermore, the CDAC capacitor array adopts a differential structure design, with each weighted capacitor configured with positive and negative C+ and C- channels. The capacitor type is a high-precision matched MIM or MOM capacitor to suppress common-mode noise and the influence of process deviation.

[0009] Furthermore, the upper-level board sampling technology connects the input signal to the top plate of the CDAC and the bottom plate switches synchronously. Combined with the gate voltage bootstrap switching circuit, it reduces the nonlinearity of the on-resistance and eliminates the effects of charge injection and clock feedthrough.

[0010] Furthermore, the specific process of the differential switching logic in the VCM architecture is as follows: During the sampling phase, the bottom plate is connected to VCM. During the conversion phase, it is switched to VREF or VCM according to weight priority, and the MSB segment capacitor is switched first to reduce the total amount of capacitor switching and dynamic power consumption.

[0011] Furthermore, the DEC circuit is a combinational logic circuit that pre-stores the mapping relationship between non-binary weights and standard binary, receives the switch state codes of C0-C12, and outputs an n-bit standard binary code to ensure the monotonicity and linearity of the encoding.

[0012] Furthermore, the ADC has an effective number of bits ENOB ≥ 11.8 bits, the total number of capacitors is reduced by more than 80% compared to the traditional binary weighted capacitor array, dynamic power consumption is reduced by 90%, and it supports high-speed conversion at the Nyquist frequency.

[0013] Furthermore, the non-binary redundancy weight allocation can be adapted to ADCs with different bit widths. By adjusting the MSB / LSB segmentation point, capacitor weight ratio, and the value of C6 within the range of 30-40Cu, the condition M+L=2 can be satisfied. n The redundancy design objective is -1.

[0014] This invention provides a SARADC based on a segmented redundancy structure and its data conversion method. It has the following beneficial effects: 1. This invention provides a SARADC based on a segmented redundancy structure and its data conversion method. The number of capacitors is reduced by more than 80% compared with the traditional binary architecture, the chip area is significantly reduced, the dynamic power consumption is reduced by 90%, it is suitable for low power consumption scenarios, the ENOB reaches 11.8 bits, which is more than 1 bit higher than the traditional SARADC, the weight optimization eliminates gain error, and the nonlinear deviation is significantly reduced.

[0015] 2. This invention provides a SARADC based on a segmented redundancy structure and its data conversion method. The differential structure and VCM switching logic suppress common-mode noise. The upper-level board sampling + gate voltage bootstrapping eliminates charge injection, resulting in high sampling accuracy. It supports ADC adaptation with different bit lengths of n=8-16. The application can be expanded by adjusting the segment points and capacitor weights. Moreover, the structure is simple and easy to integrate, requiring no complex calibration algorithm, reducing mass production costs, and is suitable for high-precision and low-power requirements in multiple fields. Attached Figure Description

[0016] Figure 1 This is a diagram of the overall architecture of the segmented redundant SARADC of the present invention; Figure 2 This is a schematic diagram of the gate voltage bootstrap switch structure of the present invention; Figure 3 This is a schematic diagram of the segmented capacitor array structure of the present invention; Figure 4 This is a schematic diagram of the capacitance weight conversion of the present invention. Detailed Implementation

[0017] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0018] In the description of this invention, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0019] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0020] In the description of this embodiment, the terms "upper," "lower," "right," etc., refer to the orientation or positional relationship shown in the accompanying drawings. They are used only for ease of description and simplification of operation, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first" and "second" are used only for distinction in description and have no special meaning.

[0021] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0022] like Figure 1-4 As shown, this embodiment of the invention provides a SARADC based on a segmented redundancy structure, including a CDAC segmented capacitor array, a switching network, a comparator, a SAR logic unit, and a digital error correction (DEC) circuit. CDAC segmented capacitor array: The core conversion component, divided into MSB segment C7-C12 and LSB segment C0-C6, using non-binary redundancy weight allocation. MSB segment: The weight ratio is 1:2:3:5:9:18, corresponding to capacitor values ​​of 1Cu, 2Cu, 3Cu, 5Cu, 9Cu, and 18Cu. The weight sum M=1976, which is responsible for the conversion of the high 6 bits of the signal. LSB segment: The weight ratio is 1:2:3:5:9:18:33, corresponding to capacitance values ​​of 1Cu, 2Cu, 3Cu, 5Cu, 9Cu, 18Cu, and 33Cu, with a weight sum of L=71, responsible for the conversion of the lower 7 bits of the signal; The total weights satisfy M+L=2047=2 12 -1, n=12, redundant capacitors Cs and Cd2 are dynamically adjusted to ensure error tolerance; Switching network: includes gate voltage bootstrap switch and bottom plate switching switch. The gate voltage bootstrap switch connects the CDAC top plate to the input signal. The bottom plate switch switches to VCM or VREF according to VCM differential timing. Comparator: High-gain, low-offset dynamic latch comparator, receives CDAC differential outputs DAC+ and DAC-, and outputs the high / low level comparison result to the SAR logic unit; SAR logic unit: Successive approximation control core, in order from MSB to LSB, controls the switching state of the capacitor array according to the comparison result, and generates non-binary raw code; DEC circuit: a combinational logic circuit with a pre-stored weight mapping table, which converts non-binary codes into 12-bit standard binary output codes to ensure the monotonicity of the encoding.

[0023] The weight allocation process is as follows: 1) Determine target parameters: Set the ADC bit depth n=12, and the target total weight Target=2. 12 -1 = 2047; 2) Segmentation strategy: Divide the MSB segment (high 6 bits) and LSB segment (low 7 bits). The weight of the MSB segment is M=1+2+3+5+9+18=38, which is proportionally magnified to 1976, a magnification of 52 times. 3) Calculate the sum of LSB segment weights: L = Target - M = 2047 - 1976 = 71; 4) Optimize LSB segment weights: Set C6 as a redundant core capacitor. The initial value of 38Cu was too large, which caused the area to increase. It was adjusted to 33Cu. The remaining weights were distributed to C0-C5 in the ratio of 1:2:3:5:9:18. The total weight is 1+2+3+5+9+18+33=71, which meets the L requirement. 5) Verify the redundancy effect: C6=33Cu can tolerate the matching error at the junction of MSB and LSB, ensuring the linearity of the conversion.

[0024] This data transformation method includes the following steps: Step 1: Sampling Phase When the gate voltage bootstrap switch is turned on, the gate voltage of the switching transistor is raised to above the power supply voltage to ensure deep linear conduction; The top plate of the CDAC is connected to the differential input signals VIN+ and VIN-, and all switches on the bottom plate are connected to VCM. The capacitor array completes charging and signal sampling; the amount of stored charge is proportional to the input signal.

[0025] Step Two: Successive Approximation Phase SAR logic unit initialization, starting from MSB bit C12; Control the bottom plate switch of C12 to switch from VCM to VREF+, while keeping the other capacitors connected to VCM; The comparator compares the DAC+ and DAC- voltages and outputs the comparison result. The SAR logic unit records the state of this bit as 1 or 0. Process C11 to C0 sequentially, repeating the switch switching and comparison process to generate non-binary raw code.

[0026] Step 3: Digital Calibration Stage The DEC circuit receives non-binary codes and converts them using pre-stored mapping logic, such as 33Cu corresponding to specific bits of binary weights; Output 12-bit standard binary code to ensure encoding linearity and monotonicity; Complete one analog-to-digital conversion and wait for the next round of sampling to be triggered.

[0027] Implementation Case: ① Hardware parameter configuration CDAC capacitor array: MSB segment C7-C12 capacitor values ​​1Cu, 2Cu, 3Cu, 5Cu, 9Cu, 18Cu; LSB segment C0-C6 capacitor values ​​1Cu, 2Cu, 3Cu, 5Cu, 9Cu, 18Cu, 33Cu; Cu=10fF; capacitor type is MIM capacitor. Switching network: Gate voltage bootstrap switch threshold voltage 0.3V, on-resistance ≤50Ω, bottom plate switch adopts CMOS process, switching delay ≤1ns; Comparator: Gain ≥ 80dB, offset voltage ≤ 100μV, response time ≤ 5ns; SAR logic unit: clock frequency 100MHz, switching period 12 clock cycles; DEC circuit: combinational logic delay ≤2ns, supports 12-bit binary output.

[0028] ② Data Conversion Method Implementation Process Step 1: After the system is powered on, the SARADC is initialized, the DEC circuit loads the weight mapping table, and the switching network is reset to standby state; Step 2: When the sampling trigger signal arrives, the gate voltage bootstrap switch is turned on, the top plate is connected to VIN+ (2.5V) and VIN- (0.5V), and the bottom plate is connected to VCM (1.5V). The sampling time is 10ns. Step 3: Successive approximation begins. The SAR logic controls the bottom plate of C12 to switch to VREF+ (3V). CDAC outputs DAC+ and DAC- voltages, the comparator outputs a high level, and the C12 bit is recorded as 1. Step 4: Process C11 to C0 sequentially. During the switching of C6, due to the redundant design of weight 33Cu, the error in the comparison result between C7 and C6 is tolerated, and the comparison result is stable. Step 5: The SAR logic outputs a non-binary raw code, such as C6=1, C5=0, C4=1..., which is then converted into standard binary code by the DEC circuit, such as 011111010101; Step 6: Output binary code, complete the conversion, and wait for the next sampling trigger.

[0029] ③Performance test results Static performance: ENOB = 11.8 bits, integral nonlinearity INL ≤ ±0.5 LSB, differential nonlinearity DNL ≤ ±0.3 LSB; Dynamic performance: Signal-to-noise ratio (SNR) = 72dB, spurious-free dynamic range (SFDR) = 85dB; Power consumption and area: At a conversion rate of 1 MSps, the power consumption is only 1.2 μW, and the capacitor array area is reduced by 82% compared to the traditional structure; Environmental adaptability: Operating temperature -40℃~85℃, power supply voltage 1.8V~3.3V, stable performance.

[0030] The following points should be noted in this article: 1. The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments disclosed herein; other structures can be referred to in a general design.

[0031] 2. Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0032] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A SARADC based on a segmented redundancy structure, characterized in that, The data conversion method, which includes a CDAC segmented capacitor array, a switching network, a comparator, a SAR logic unit, and a digital error correction (DEC) circuit, comprises the following steps: Step 1: Sampling Phase Through upper-level board sampling technology, the differential input signal is connected to the top plate of the CDAC capacitor array, and the bottom plate switch is uniformly connected to the common-mode voltage VCM. The gate voltage bootstrap switch is turned on to complete signal sampling. Step Two: Successive Approximation Stage Based on the VCM architecture, the differential switching logic SAR logic unit controls the bottom plate switch of the CDAC capacitor array to switch to the reference voltage VREF or VCM in the order from MSB to LSB. The comparator compares the DAC output voltage in real time and outputs the comparison result. Step 3: Digital Calibration Stage The DEC circuit receives the non-binary code of the SAR logic output and converts it into a standard binary output code through a preset mapping logic. The CDAC capacitor array is divided into MSB and LSB segments, and non-binary redundancy weight allocation is used, with the total weights satisfying M+L=2. n -1, n is the target number of bits for the ADC, and the highest bit capacitor of the LSB segment is C6=33Cu, which optimizes the redundancy effect and balances the number of capacitors.

2. The SARADC based on a segmented redundancy structure according to claim 1, characterized in that, The MSB segment of the CDAC capacitor array includes capacitors C7-C12, with weights assigned as 1Cu, 2Cu, 3Cu, 5Cu, 9Cu, and 18Cu, and the sum of the weights M = 52 + 104 + 156 + 260 + 468 + 936 = 1976. The LSB segment includes capacitors C0-C6, with weights assigned as 1Cu, 2Cu, 3Cu, 5Cu, 9Cu, 18Cu, and 33Cu. The sum of the weights L = 1 + 2 + 3 + 5 + 9 + 18 + 33 = 71, and the total weight M + L = 2047 = 2. 12 -1, n=12.

3. The SARADC based on a segmented redundancy structure according to claim 1, characterized in that, The CDAC capacitor array adopts a differential structure design, with each weighted capacitor configured with positive and negative C+ and C- channels. The capacitor type is a high-precision matched MIM or MOM capacitor to suppress common-mode noise and the influence of process deviation.

4. The SARADC based on a segmented redundancy structure according to claim 1, characterized in that, The upper-level board sampling technology connects the input signal to the top plate of the CDAC, and the bottom plate switches synchronously. Combined with the gate voltage bootstrap switching circuit, it reduces the nonlinearity of the on-resistance and eliminates the effects of charge injection and clock feedthrough.

5. The SARADC based on a segmented redundancy structure according to claim 1, characterized in that, The specific process of the differential switching logic in the VCM architecture is as follows: During the sampling phase, the bottom plate is connected to VCM. During the conversion phase, it is switched to VREF or VCM according to weight priority, and the MSB segment capacitor is switched first to reduce the total amount of capacitor switching and dynamic power consumption.

6. The SARADC based on a segmented redundancy structure according to claim 1, characterized in that, The DEC circuit is a combinational logic circuit that pre-stores the mapping relationship between non-binary weights and standard binary, receives the switch state codes of C0-C12, and outputs an n-bit standard binary code to ensure the monotonicity and linearity of the encoding.

7. The SARADC based on a segmented redundancy structure according to claim 1, characterized in that, The ADC has an effective number of bits ENOB ≥ 11.8 bits, the total number of capacitors is reduced by more than 80% compared with the traditional binary weighted capacitor array, the dynamic power consumption is reduced by 90%, and it supports high-speed conversion at the Nyquist frequency.

8. The SARADC based on a segmented redundancy structure according to claim 1, characterized in that, The non-binary redundancy weight allocation can be adapted to ADCs with different bit widths. By adjusting the MSB / LSB segmentation point, capacitor weight ratio, and the value of C6 within the range of 30-40Cu, the condition M+L=2 can be satisfied. n The redundancy design objective is -1.

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