Communication device and method with frequency offset tracking mechanism

Abstract

The invention discloses a communication device and method with a frequency offset tracking mechanism. The method comprises the following steps: a phase compensation circuit receives a current symbol section of a data part of a packet and performs phase compensation according to a frequency offset to generate a phase compensation symbol section; the symbol processing circuit descrambles and balances the phase compensation symbol section according to the scrambling information, and further calculates and generates a phase difference and a data time difference between the symbol section and a previous symbol section according to a balancing result, and then the residual frequency offset estimation circuit performs specific value calculation to generate an instantaneous frequency offset estimation value. The frequency offset smoothing calculation circuit calculates the data time difference according to a function in positive correlation with the data time difference to generate a correction coefficient, multiplies the instantaneous frequency offset estimation value and the smoothing coefficient to generate a smoothing frequency offset estimation value, and then superposes the smoothing frequency offset estimation value with a previous frequency offset estimation value to generate a current frequency offset estimation value to update the frequency offset quantity.

Description

Technical Field

[0001] This invention relates to frequency offset tracking technology, and more particularly to a communication device and method with a frequency offset tracking mechanism. Background Technology

[0002] Ultra-wideband (UWB) technology, based on the IEEE 802.15.4a / f / z standard, is a wireless communication technology that uses nanosecond-level narrow pulses for data transmission. According to the UWB standard, its data modulation incorporates burst position modulation (BPM) to avoid long-term, continuous mutual interference when different devices transmit data simultaneously.

[0003] During communication, frequency offsets can occur due to crystal oscillator deviations or the Doppler effect. After frequency offset estimation in the preamble, residual frequency offsets often remain, requiring continued frequency offset tracking in the data segment to avoid significant phase deviations. To reduce errors during frequency offset tracking, the tracking results of multiple symbols are often smoothed. Previous frequency offset tracking techniques typically used fixed smoothing parameters based solely on the signal-to-noise ratio. However, with burst position modulation (BPM) techniques, the time intervals between adjacent data points vary, resulting in differences in frequency offset tracking accuracy. Using fixed parameters cannot achieve optimal frequency offset tracking. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a communication device and method with a frequency offset tracking mechanism to improve the prior art.

[0005] This invention includes a communication device with a frequency offset tracking mechanism, comprising: a phase compensation circuit, a symbol processing circuit, a residual frequency offset estimation circuit, and a frequency offset smoothing calculation circuit. The phase compensation circuit is configured to receive the current symbol segment of the data portion of a packet and perform phase compensation based on the frequency offset to generate a phase-compensated symbol segment, wherein the current symbol segment has a symbol time length. The symbol processing circuit is configured to descramble and equalize the phase-compensated symbol segment according to scrambling information to generate an equalization result, and further calculate the phase difference and data time difference between the current symbol segment and the previous symbol segment based on the equalization result. The residual frequency offset estimation circuit is configured to calculate the ratio between the phase difference and the data time difference to generate an instantaneous frequency offset estimate. The frequency offset smoothing calculation circuit is configured to calculate a correction coefficient for the data time difference based on a function positively correlated with the data time difference, multiply the instantaneous frequency offset estimate by the smoothing coefficient and the correction coefficient to generate a smoothed frequency offset estimate, and further superimpose the previous frequency offset estimate and the smoothed frequency offset estimate to generate a current frequency offset estimate to update the frequency offset.

[0006] The present invention also includes a communication method with a frequency offset tracking mechanism, comprising: enabling a phase compensation circuit to receive the current symbol segment of the data portion of a packet and perform phase compensation according to the frequency offset to generate a phase-compensated symbol segment, wherein the current symbol segment has a symbol time length; enabling a symbol processing circuit to descramble and equalize the phase-compensated symbol segment according to scrambling information to generate an equalization result, and further calculating the phase difference and data time difference with the previous symbol segment according to the equalization result; enabling a residual frequency offset estimation circuit to calculate the ratio between the phase difference and the data time difference to generate an instantaneous frequency offset estimate; and enabling a frequency offset smoothing calculation circuit to calculate a correction coefficient for the data time difference according to a function positively correlated with the data time difference, multiplying the instantaneous frequency offset estimate with the smoothing coefficient and the correction coefficient to generate a smoothed frequency offset estimate, and further superimposing the previous frequency offset estimate with the smoothed frequency offset estimate to generate a current frequency offset estimate to update the frequency offset.

[0007] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, showing preferred embodiments. Attached Figure Description

[0008] Figure 1 A block diagram showing a communication device with a frequency offset tracking mechanism in one embodiment of the present invention is shown. Figure 2A This diagram illustrates a packet received by a communication device in one embodiment of the present invention. Figure 2B This diagram illustrates a symbol segment in one embodiment of the present invention. Figure 3 This diagram shows a block diagram of a symbol processing circuit according to an embodiment of the present invention; and Figure 4 This diagram shows a flowchart of a communication method with a frequency offset tracking mechanism according to an embodiment of the present invention. Detailed Implementation

[0009] One objective of this invention is to provide a communication device and method with a frequency offset tracking mechanism. The method sets a correction coefficient based on the data time difference, so that when the difference in the actual data position between different symbol segments is greater and the data time difference is greater, the weight of the instantaneous frequency offset estimate is increased to update the frequency offset amount, thereby improving the accuracy of the frequency offset estimate.

[0010] Please refer to Figure 1 . Figure 1 This diagram shows a block diagram of a communication device 100 with a frequency offset tracking mechanism according to an embodiment of the present invention. The communication device 100 can be any device used for wireless communication transmission to receive signals.

[0011] In one embodiment, the communication device 100 may be a system using Burst Position Modulation (BPM), such as an Ultra Wide Band (UWB) system with the 802.15.4 protocol, to receive packets PK during signal reception.

[0012] Please refer to Figure 2A . Figure 2A This diagram illustrates a packet PK received by the communication device 100 in one embodiment of the present invention.

[0013] Taking an ultra-wideband system as an example, the packet PK sequentially includes a synchronization header (SHR) and a data portion (DAT). The synchronization header includes the synchronization segment SYNC and the start of frame delimiter (SFD) segment. The data portion (DAT) includes the physical layer header (PHR) and the payload segment PAD. Both the physical layer header (PHR) and the payload segment PAD use burst position modulation and contain one or more symbol segments.

[0014] Please refer to the following at the same time Figure 2B . Figure 2B This diagram illustrates a symbol segment SYB according to one embodiment of the present invention.

[0015] The symbol segment SYB has a symbol duration TSY. In one numerical example, the symbol duration TSY is 8 microseconds (μs). The symbol segment SYB comprises a first half segment BP1 and a second half segment BP2, each with multiple possible burst locations B1 to B8. In one embodiment, the first half segment BP1 and the second half segment BP2 may each include a guard interval GI after the burst locations B1 to B8. It should be noted that... Figure 2B The ratio between the total length of the sudden locations B1 to B8 and the length of the protection interval GI shown is for reference only. In reality, the ratio between the total length of the sudden locations B1 to B8 and the length of the protection interval GI can be 1:1, or it can be set differently depending on the requirements.

[0016] According to burst position modulation, a symbol segment SYB contains actual data only at one of the aforementioned burst positions, based on the random scrambling code at the transmitting end of the packet PK. Therefore, for the actual data of a symbol segment SYB, its actual data position includes both the actual segment and the actual burst position. For example, when the actual data is located at... Figure 2BWhen the sudden location is drawn in gray, the actual data location segment is the first half segment BP1, and the actual sudden location is the fifth sudden location B5.

[0017] Due to burst position modulation, the actual data positions between different symbol segments (SYBs) will differ, thus reducing communication interference between different devices. When the ratio of the total length of burst positions B1~B8 to the length of the guard interval GI is 1:1, the maximum positional difference between the actual data positions of two adjacent symbol segments (SYBs) can reach 7 / 4 symbol time length (TSY) (when the actual data position of the preceding symbol segment (SYB) corresponds to the first burst position B1 of the first half of segment BP1, and the actual data position of the following symbol segment (SYB) corresponds to the eighth burst position B8 of the second half of segment BP2). The minimum positional difference between the actual data positions of two adjacent symbol segments (SYBs) is 1 / 4 symbol time length (TSY) (when the actual data position of the preceding symbol segment (SYB) corresponds to the eighth burst position B8 of the second half of segment BP2, and the actual data position of the following symbol segment (SYB) corresponds to the first burst position B1 of the first half of segment BP1).

[0018] Figure 1 The communication device 100 includes a preprocessing circuit 110, a phase compensation circuit 120, a symbol processing circuit 130, a residual frequency offset estimation circuit 140, and a frequency offset smoothing calculation circuit 150. Through the structure and operation of the above circuits, the communication device 100 can process packet PK to achieve the purpose of frequency offset tracking and improve the accuracy of data reception.

[0019] The following will be based on Figure 2A as well as Figure 2B Taking the packet PK structure shown as an example, the structure and operation mechanism of the communication device 100 are explained.

[0020] The preprocessing circuit 110 processes the synchronization header section SHR before the data section DAT to generate the initial value ΔFI of the frequency offset ΔF and the initial channel information ICI.

[0021] Phase compensation circuit 120 is configured to receive the current symbol segment of packet PK (e.g., Figure 2B The symbol segment SYB is shown, and phase compensation is performed based on the frequency offset ΔF to generate the phase-compensated symbol segment SYP, where the current symbol segment has a symbol time length (e.g., Figure 2B The symbol time length shown is TSY.

[0022] Symbol processing circuit 130 is configured to descramble and equalize the phase-compensated symbol segment SYP according to the scrambling information SCI to generate an equalization result, and further calculate the phase difference ΔP and data time difference ΔT between the SYP and the previous symbol segment based on the equalization result. In one embodiment, the scrambling information SCI can be calculated from the symbol index of the preamble sequence of the packet PK. Detailed calculation methods can be found in the relevant protocol content and will not be repeated here.

[0023] Please refer to Figure 3 . Figure 3 This diagram shows a block diagram of a symbol processing circuit 130 according to one embodiment of the present invention. The symbol processing circuit 130 includes an actual data position calculation circuit 310, a descrambling circuit 320, an equalization circuit 330, a segment judgment circuit 340, a time difference calculation circuit 350, a hard decision circuit 360, a channel re-estimation circuit 370, and a phase difference calculation circuit 380.

[0024] The actual data location calculation circuit 310 is configured to calculate the current symbol segment based on the scrambling code information SCI and to locate the burst position accordingly (e.g., Figure 2B The method involves determining the actual burst location contained in the current actual data location AP(K) within the burst locations B1~B8 in the first half of the segment BP1 and the second half of the segment BP2, in order to generate burst location information BPI. Here, K in the current actual data location AP(K) represents the current time point.

[0025] More specifically, based on the scrambling code information SCI, the actual data position calculation circuit 310 can only determine the actual burst position of the current actual data position AP(K), but cannot determine the actual segment of the current actual data position AP(K).

[0026] The descrambling circuit 320 is configured to descramble the compensation symbol segment SYP according to the scrambling code information SCI and the burst position information BPI, so as to generate the first descrambling data DS1 corresponding to the first half segment BP1 and the second descrambling data DS2 corresponding to the second half segment BP2.

[0027] The equalization circuit 330 is configured to equalize the first descrambled data DS1 and the second descrambled data DS2 according to the initial channel information ICI, so as to generate the first equalized data DE1 and the second equalized data DE2 as the equalization result.

[0028] The segment judgment circuit 340 is configured to select the one with greater energy from the first equalization data DE1 and the second equalization data DE2 as the selected equalization data DL, and further determine the actual segment contained in the current actual data position AP(K) in the first half segment BP1 and the second half segment BP2 based on the selected equalization data DL.

[0029] In one embodiment, the first equalization data DE1 and the second equalization data DE2 are both complex numbers. The segment determination circuit 340 is configured to perform energy calculations on the first equalization data DE1 and the second equalization data DE2 respectively, to determine which of the first equalization data DE1 and the second equalization data DE2 has greater energy. For example, when the first equalization data DE1 is represented as a+bi in complex number form, the segment determination circuit 340 will add the square of the real part of a and the square of the imaginary part of b, and determine the energy magnitude accordingly.

[0030] More specifically, the descrambling circuit 320 first assumes that the actual segment is located in the first half segment BP1 and the second half segment BP2 based on the burst location information BPI, and then descrambles them respectively. After equalization by the equalization circuit 330, the segment judgment circuit 340 judges the larger energy of the first equalization data DE1 and the second equalization data DE2, and then judges that the larger energy corresponds to the actual segment with data.

[0031] In one embodiment, the segment determination circuit 340 can receive burst location information BPI from the actual data location calculation circuit 310 to obtain the actual burst location contained in the current actual data location AP(K), and then obtain the actual segment contained in the current actual data location AP(K) by selecting the equalization data DL.

[0032] In one embodiment, the segment determination circuit 340 can represent the current actual data position AP(K) as the current time length relative to the start position of the current symbol segment. The current actual data position AP(K) corresponds to... Figure 2B Taking the burst position (first half segment BP1 and fifth burst position B5) shown in gray as an example, the current actual data position AP(K) will be represented as the current time length TL(K) between the first burst position B1 and the fifth burst position B5 of the first half segment BP1. The segment determination circuit 340 further transmits the current actual data position AP(K) to the time difference calculation circuit 350 for calculation.

[0033] The time difference calculation circuit 350 is configured to calculate the data time difference ΔT based on the current actual data position AP(K) and the previous actual data position AP(K-1) corresponding to a previous symbol segment. Here, K-1 in the previous actual data position AP(K-1) represents the previous time point.

[0034] Similar to the current actual data position AP(K), the previous actual data position AP(K-1) can be represented as the previous time length TL(K-1) relative to the starting position of the previous symbol segment. The time difference calculation circuit 350 is configured to calculate the data time difference ΔT by subtracting the current time length TL(K) from the previous time length TL(K-1) and adding the symbol time length TSY, which can be expressed as ΔT=TL(K)-TL(K-1)+TSY.

[0035] The hard-decision circuit 360 is configured to perform hard decision on the selected equalization data DL to generate the real part positive / negative parameter SP. Hard decision infers the original transmitted data from the equalization data to eliminate the influence of differences in the original transmitted data when calculating the phase difference between symbols. Since the burst position modulation signal pulses in the 802.15.4 series UWB protocol are transmitted in binary phase-shift keying (BPSK) form, the hard decision result has only two possibilities: 1 / -1. More specifically, when the selected equalization data DL is expressed as a+bi in the complex form described above, the hard-decision circuit 360 uses the sign of a as the real part positive / negative parameter SP. In a numerical example, the real part positive / negative parameter SP is 1 when a is positive and -1 when a is negative.

[0036] The channel re-estimation circuit 370 is configured to divide the selected equalization data DL by the real part positive and negative parameter SP to produce the current channel re-estimation result CR(K). More specifically, the current channel re-estimation result CR(K) can be expressed as CR(K) = DL / SP.

[0037] The phase difference calculation circuit 380 is configured to calculate the phase difference ΔP based on the current channel re-estimation result CR(K) and the previous channel re-estimation result CR(K-1) of the corresponding previous symbol segment.

[0038] In one embodiment, the phase difference calculation circuit 380 performs conjugate calculation on the previous channel re-estimation result CR(K-1) and multiplies it with the current channel re-estimation result CR(K) to generate a multiplication result. The angle of the multiplication result is then taken as the phase difference ΔP. Therefore, the phase difference ΔP can be expressed as ΔP=angle(CR(K)×conj(CR(K-1))).

[0039] Please refer to this again. Figure 1 . Figure 1 The residual frequency offset estimation circuit 140 is configured to calculate the ratio between the phase difference ΔP generated by the symbol processing circuit 130 and the data time difference ΔT to generate an instantaneous frequency offset estimate ΔFE. Therefore, the instantaneous frequency offset estimate ΔFE can be expressed as ΔFE = ΔP / ΔT.

[0040] The frequency offset smoothing calculation circuit 150 is configured to calculate a correction coefficient MP for the data time difference based on a function positively correlated with the data time difference, and to multiply the instantaneous frequency offset estimate ΔFE with the smoothing coefficient α and the correction coefficient MP to produce a smoothed frequency offset estimate ΔFS. In one embodiment, this function may be, for example, the ratio between the data time difference ΔT and the symbol time length TSY.

[0041] The frequency offset ΔF at time point K has already been used by the phase compensation circuit 120 for phase compensation. Therefore, the previous frequency offset estimate can be expressed as ΔF(K). The frequency offset smoothing calculation circuit 150 superimposes the previous frequency offset estimate ΔF(K) with the smoothed frequency offset estimate ΔFS to generate the current frequency offset estimate ΔF(K+1) and update the frequency offset ΔF. Therefore, the frequency offset ΔF can be expressed as ΔF=ΔF(K+1)=ΔF(K)+ΔFS=ΔF(K)+ΔFE×α×MP. In one embodiment, MP=(ΔT / TSY), then ΔF =ΔF(K)+ΔFE×α×(ΔT / TSY).

[0042] Among the parameters mentioned above, the smoothing coefficient α is the optimal coefficient obtained under a fixed symbol time length TSY and a specific signal-to-noise ratio, and it remains unchanged once selected. Furthermore, some parameters are merely terms generated during the calculation process and therefore are not included in the calculation. Figure 1 Shown in the middle.

[0043] After the frequency offset ΔF is updated, the phase compensation circuit 120 performs phase compensation on the current symbol segment at the next time point (K+1) based on the frequency offset ΔF. The time difference calculation circuit 350 sets the current actual data position AP(K) to the previous actual data position and calculates it with the current actual data position corresponding to the symbol segment SYB at the next time point (e.g., represented as AP(K+1)). The phase difference calculation circuit 380 sets the current channel re-estimation result CR(K) to the previous actual data position and calculates it with the current channel re-estimation result corresponding to the symbol segment SYB at the next time point (e.g., represented as CR(K+1)). Therefore, as different symbol segments SYB are fed in, the communication device 100 can continuously track the frequency offset.

[0044] In some techniques, the frequency offset ΔF(K) is updated solely based on a smoothing coefficient α that is selected and remains unchanged. However, this approach suffers from limitations because burst position modulation continuously alters the actual data positions between different symbol segments, resulting in varying frequency offset estimation accuracy across different symbols. Therefore, using a fixed-coefficient smoothing method cannot achieve optimal frequency offset estimation.

[0045] The communication device 100 of the present invention sets a correction coefficient MP based on a function positively correlated with the data time difference ΔT. This increases the weight of the instantaneous frequency offset estimate ΔFE to update the frequency offset amount ΔF(K) when the difference in the actual data positions between different symbol segments is greater, resulting in a larger data time difference ΔT, thereby improving the accuracy of the frequency offset estimation. This setting is based on the principle that the larger the time interval, the higher the corresponding frequency offset estimation accuracy.

[0046] In a numerical example, with an average pulse repetition frequency (PRF) of 15.6 MHz and a data rate of 110 kbps, dynamically adjusting the smoothing coefficient by setting a correction factor (e.g., based on the ratio between the data time difference and the symbol time length) results in a signal-to-noise ratio that is approximately 1 dB lower than that of setting only a fixed smoothing coefficient, compared to setting only a fixed smoothing coefficient.

[0047] It should be noted that, for ease of explanation, in Figure 1 Only the circuitry for signal reception is shown in the diagram. In other embodiments, the communication device 100 may also include circuitry for signal transmission. The invention is not limited thereto.

[0048] Please refer to Figure 4 . Figure 4 This diagram shows a flowchart of a communication method 400 with a frequency offset tracking mechanism according to an embodiment of the present invention.

[0049] In addition to the aforementioned device, the present invention also discloses a communication method 400 with a frequency offset tracking mechanism, applicable to, for example, but not limited to, [other applications]. Figure 1 In the communication device 100. An embodiment of the communication method 400, for example... Figure 4 As shown, it includes the following steps.

[0050] In step S410, the phase compensation circuit 120 is configured to receive the current symbol segment (e.g., the data portion DAT of the packet PK) Figure 2B The symbol segment SYB is generated and phase compensation is performed based on the frequency offset ΔF(K) to produce the phase-compensated symbol segment SYP.

[0051] In step S420, the symbol processing circuit 130 descrambles and equalizes the phase compensation symbol segment SYP according to the scrambling code information SCI to generate an equalization result, and further calculates the phase difference ΔP and data time difference ΔT between the symbol segment and the previous symbol segment based on the equalization result.

[0052] In step S430, the residual frequency offset estimation circuit 140 calculates the ratio between the phase difference ΔP and the data time difference ΔT to generate an instantaneous frequency offset estimate ΔFE.

[0053] In step S440, the frequency offset smoothing calculation circuit 150 calculates a correction coefficient MP for the data time difference ΔT based on a function that is positively correlated with the data time difference ΔT. The instantaneous frequency offset estimate ΔFE is multiplied by the smoothing coefficient α and the correction coefficient MP to generate a smoothed frequency offset estimate ΔFS. The previous frequency offset estimate ΔF(K-1) is then superimposed with the smoothed frequency offset estimate ΔFS to generate the current frequency offset estimate and update the frequency offset amount ΔF(K).

[0054] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention. For example, the method for generating the phase difference and data time difference described above is only an example. In other embodiments, the symbol processing circuit can generate the phase difference and data time difference using other circuit structures and operating mechanisms. Furthermore, the communication device implemented using the 802.15.4 protocol in an ultra-wideband system is only an example. In other embodiments, the communication device can also be implemented using various technologies employing non-equidistant data transmission. The invention is not limited thereto.

[0055] In summary, the communication device and method with frequency offset tracking mechanism in this invention sets a correction coefficient based on the data time difference. When the positional difference of the actual data position between different symbol segments is greater, resulting in a larger data time difference, the weight of the instantaneous frequency offset estimate is increased to update the frequency offset amount, thereby improving the accuracy of the frequency offset estimate.

[0056] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make changes to the technical features of this application based on the express or implied content of this application. All such changes may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the claims of this specification.

[0057] Symbol Explanation 100:Communication device 110: Pre-processing circuit 120: Phase Compensation Circuit 130: Symbol Processing Circuit 140: Residual Frequency Offset Estimation Circuit 150: Frequency Deviation Smoothing Calculation Circuit 310: Actual data location calculation circuit 320: Descrambling circuit 330: Equalization Circuit 340: Section Judgment Circuit 350: Time Difference Calculation Circuit 360: Hard decision circuit 370: Channel Re-estimation Circuit 380: Phase Difference Calculation Circuit 400: Communication method S410~S440: Steps ΔF: Frequency offset ΔFE: Estimated instantaneous frequency offset ΔFI: Initial value ΔFS: Smoothed frequency offset estimate ΔP: Phase difference ΔT: Data time difference AP(K): Current actual data position AP(K-1): Previous actual data position B1~B8: Sudden Locations BP1: First half section BP2: Second Half Section BPI: Burst Location Information CR(K): Current channel re-estimation result CR(K-1): Previous channel re-estimation results DAT: Data Section DE1: First Equilibrium Data DE2: Second Equilibrium Data DL: Select balanced data DS1: First descrambled data DS2: Second Descrambled Data ICI: Initial Channel Information GI: Guard Interval PAD: Load Section PHR: Physical Layer Header Section PK: Packet SCI: Scrambling information SFD: Start Position Delimiter Segment for Message Frames SHR: Synchronization Header Section SP: Positive and negative parameter of the real part SYB: Symbolic segment SYNC: Synchronization segment TL(K): Current time length TSY: Symbol Time Length

Claims

1. A communication device with a frequency offset tracking mechanism, characterized in that, Include: A phase compensation circuit is configured to receive a current symbol segment of a data portion of a packet and perform phase compensation based on a frequency offset to generate a phase-compensated symbol segment. A symbol processing circuit is configured to descramble and equalize the phase-compensated symbol segment according to a scrambling code information to generate an equalization result, and further calculate a phase difference and a data time difference with a previous symbol segment based on the equalization result. A residual frequency offset estimation circuit is configured to calculate a ratio between the phase difference and the data time difference to generate an instantaneous frequency offset estimate. as well as A frequency offset smoothing calculation circuit is configured to calculate a correction coefficient for the data time difference based on a function that is positively correlated with the data time difference, to multiply the instantaneous frequency offset estimate by a smoothing coefficient and the correction coefficient to generate a smoothed frequency offset estimate, and further to superimpose a previous frequency offset estimate with the smoothed frequency offset estimate to generate a current frequency offset estimate to update the frequency offset amount.

2. The communication device as claimed in claim 1, characterized in that, The current symbol segment comprises a first half segment and a second half segment, and each of the first half segment and the second half segment has multiple possible burst positions. The symbol processing circuit includes: A real data location calculation circuit is configured to calculate the current symbol segment based on the scrambling information and determine the current real data location contained in the multiple burst locations to generate burst location information. A descrambling circuit is configured to descramble the compensation symbol segment according to the scrambling code information and the burst location information to generate a first descrambling data corresponding to the first half segment and a second descrambling data corresponding to the second half segment. An equalization circuit is configured to equalize the first descrambled data and the second descrambled data according to an initial channel information, so as to generate a first equalized data and a second equalized data as the equalization result; as well as A segment determination circuit is configured to select the one with greater energy from the first equalization data and the second equalization data as a selected equalization data, and further determine the actual segment contained in the current actual data position in the first half segment and the second half segment based on the selected equalization data. as well as A time difference calculation circuit is configured to calculate the data time difference based on the current actual data position and a previous actual data position corresponding to the previous symbol segment.

3. The communication device as described in claim 2, characterized in that, It also includes a preprocessing circuit configured to process a synchronization header portion preceding the data portion to generate an initial value for the frequency offset and the initial channel information.

4. The communication device as claimed in claim 2, characterized in that, The first equalization data and the second equalization data are both complex numbers. The segment judgment circuit is configured to perform an energy calculation on the first equalization data and the second equalization data respectively, so as to determine that the first equalization data and the second equalization data have a larger energy.

5. The communication device as described in claim 2, characterized in that, The current symbol segment has a symbol time length, the current actual data position is a current time length relative to the start position of a current symbol segment of the current symbol segment, and the previous actual data position is a previous time length relative to the start position of a previous symbol segment of the previous symbol segment. The time difference calculation circuit is configured to calculate the data time difference by subtracting the current time length from the previous time length and adding the symbol time length.

6. The communication device as described in claim 2, characterized in that, The symbol processing circuit also includes: A hard decision circuit is configured to make a hard decision on the selected equalization data to produce a real part positive or negative parameter. A channel re-estimation circuit is configured to divide the selected equalization data by the real part positive or negative parameter to produce a current channel re-estimation result. A phase difference calculation circuit is configured to calculate the phase difference based on the current channel re-estimation result and a previous channel re-estimation result corresponding to the previous symbol segment.

7. The communication device as claimed in claim 6, characterized in that, The phase difference calculation circuit performs a conjugate calculation on the previous channel re-estimation result and multiplies it with the current channel re-estimation result to produce a multiplication result. The angle of the multiplication result is then taken as the phase difference.

8. The communication device as claimed in claim 1, characterized in that, The current symbol segment has a symbol time length, and the function is a ratio between the data time difference and the symbol time length.

9. A communication method with a frequency offset tracking mechanism, characterized in that, Include: A phase compensation circuit is configured to receive a current symbol segment of a data portion of a packet and perform phase compensation based on a frequency offset to generate a phase-compensated symbol segment. A symbol processing circuit descrambles and equalizes the phase-compensated symbol segment according to a scrambling code information to generate an equalization result. Further, a phase difference and a data time difference between the equalization result and a previous symbol segment are calculated based on the equalization result. A residual frequency offset estimation circuit calculates the ratio between the phase difference and the data time difference to generate an instantaneous frequency offset estimate. as well as A frequency offset smoothing calculation circuit calculates a correction coefficient for the data time difference based on a function that is positively correlated with the data time difference. The instantaneous frequency offset estimate is multiplied by a smoothing coefficient and the correction coefficient to generate a smoothed frequency offset estimate. A previous frequency offset estimate is then superimposed with the smoothed frequency offset estimate to generate a current frequency offset estimate to update the frequency offset.

10. The communication method as described in claim 9, characterized in that, The current symbol segment comprises a first half segment and a second half segment, and each of the first half segment and the second half segment has multiple possible burst locations. The communication method includes: The symbol processing circuit includes an actual data position calculation circuit that calculates the current symbol segment based on the scrambling information and determines the actual burst position contained in the current actual data position among the multiple burst positions, so as to generate a burst position information. The symbol processing circuit includes a descrambling circuit that descrambles the compensation symbol segment according to the scrambling code information and the burst position information, so as to generate a first descrambling data corresponding to the first half segment and a second descrambling data corresponding to the second half segment. The symbol processing circuit includes an equalization circuit that equalizes the first descrambled data and the second descrambled data according to an initial channel information, so as to generate a first equalized data and a second equalized data as the equalization result. as well as The symbol processing circuit includes a segment determination circuit that selects the one with a larger energy from the first equalization data and the second equalization data as a selected equalization data, and further determines the actual segment contained in the current actual data position in the first half segment and the second half segment based on the selected equalization data. as well as The symbol processing circuit includes a time difference calculation circuit that calculates the data time difference based on the current actual data position and a previous actual data position corresponding to the previous symbol segment.

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