Manufacturing method for improving via hole corrosion, array substrate and display device

Abstract

The invention discloses a manufacturing method for improving via hole corrosion, an array substrate and a display device. The manufacturing method comprises the following steps: forming a metal layer above a substrate; forming a first insulating layer above the metal layer, etching the first insulating layer and forming a contact hole; a first transparent conductive layer is formed on the first insulating layer, a second insulating layer is formed on the first transparent conductive layer, the second insulating layer is used as a protection structure for first baking process treatment, and the oxidation corrosion effect on the metal layer at the high temperature is isolated; when the second transparent conductive layer is manufactured, due to the fact that the baked first transparent conductive layer is compact enough, the first transparent conductive layer serves as a protection structure to conduct second baking process treatment, and the oxidation corrosion effect on the metal layer at the high temperature is isolated again. The first transparent conducting layer and the second transparent conducting layer are in bridge connection with each other and form a thick transparent conducting layer, impedance can be reduced, and the protection effect on the metal layer can be improved in the follow-up using process.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a method for improving via corrosion, an array substrate, and a display device. Background Technology

[0002] With the development of display technology, thin and light display panels are increasingly favored by consumers, especially thin and light display panels (liquid crystal display, LCD). An existing display device includes a thin film transistor array substrate (TFT array substrate), a color filter substrate (CF substrate), and liquid crystal molecules filled between the TFT array substrate and the color filter substrate. When the display device is in operation, driving voltages are applied to the pixel electrodes of the TFT array substrate and the common electrode of the color filter substrate, or to the common electrode and pixel electrodes of the TFT array substrate, respectively. This controls the rotation direction of the liquid crystal molecules between the two substrates, refracting the backlight provided by the backlight module of the display device to display an image.

[0003] When conductive connections are needed between two different conductive layers in a thin-film transistor array substrate, contact holes are typically placed between the two conductive layers. For example, connecting pixel electrodes to drain electrodes, guiding gate drive circuits to top pads in the bonding area, and guiding source drive circuits to top pads in the bonding area are all achieved through contact holes. These conductive layers typically include a metal layer and a transparent conductive layer. Copper is a commonly used and highly conductive metal, while the transparent conductive layer is usually made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, when a hole is made in the upper insulating layer of a Cu (copper) conductive layer, Cu is prone to oxidation and corrosion, which can easily lead to product defects. Furthermore, high-temperature processes after the hole is made can exacerbate Cu oxidation.

[0004] Figure 1 This is a schematic diagram of a structure in the prior art where two conductive layers are electrically connected. Figures 2a-2c For the corresponding Figure 1 A schematic diagram illustrating the fabrication method of electrically connecting two conductive layers. (See diagram below.) Figures 1 to 2cAs shown, the existing manufacturing method includes: fabricating a copper film 2 on a substrate 1 and covering it with an insulating layer 3; then making openings in the insulating layer 3 to expose the copper film 2; then covering it with a transparent conductive layer 4; the transparent conductive layer 4 contacts the copper film 2 through contact holes TH; and finally, the transparent conductive layer 4 is subjected to high-temperature treatment. The transparent conductive layer is typically made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the high-temperature treatment of the transparent conductive layer 4 causes oxidation and corrosion of the copper film 2. Figure 3 These are electron microscope images of the contact hole after corrosion, including planar and cross-sectional images, such as... Figure 3 As shown, pits appear at the edge of the contact hole after corrosion, which can easily lead to poor contact between the two conductive layers.

[0005] To address the problem of copper's susceptibility to oxidation and corrosion, the following methods are employed in existing technologies: 1. Enhance cleaning capabilities after opening the insulation layer 3, for example: ① Increase the STR (stripping photoresist process) water washing time, flow rate, AK pressure, and AK time; ② Use high pressure in the STR water washing section to improve cleaning capabilities; ③ Add an MJ (jetting) process before cleaning in the STR AK section to improve cleaning capabilities.

[0006] 2. Improvements in transparent conductive layer film formation, for example: ① Increasing the ITO film thickness to improve protection and reduce the risk of copper oxidation after opening the PV (insulating layer 3) – PVD (rotating target modification evaluation); ② Improving the ITO film quality to enhance protection and reduce the risk of copper oxidation after opening the PV (insulating layer 3) – PVD (rotating target modification evaluation). Note: A planar target is conventionally used.

[0007] 3. PV DET (wet etching) conditions: Turning etching increases the selectivity ratio of MoNb (molybdenum niobium) and SiNx (silicon nitride), reduces MoNb loss in the DET process, and lowers the risk of copper oxidation corrosion.

[0008] Based on the shortcomings of the above three technical methods: ① The process surface cannot completely improve the copper corrosion situation, but only provides slight improvement; ② At present, the quality of planar target ITO film is worse than that of ITO rotating target. Rotating target ITO can effectively protect Cu from corrosion, but the cost is too high, requiring the purchase of new machines.

[0009] Figure 4 This is a schematic diagram of another existing structure for conductive connection of two conductive layers. (Example) Figure 4 As shown, in Figure 1Based on this, an aluminum film 5 is added to the insulating layer 3 and the transparent conductive layer 4. The aluminum film 5 is more corrosion resistant than the copper film 2. In terms of design, an additional aluminum process can be added. The aluminum film 5 covers the copper film 2 exposed at the contact hole TH, and a PV (insulating layer 3) is covered on the aluminum film 5. This can effectively improve the problem of copper corrosion. However, it requires an additional aluminum manufacturing process and an insulating layer opening process, which is complex, costly, and aluminum has poor conductivity. Summary of the Invention

[0010] In order to overcome the shortcomings and deficiencies of the prior art, the present invention aims to provide a manufacturing method for improving the corrosion of vias, as well as an array substrate and a display device, to solve the problems of complex processes, high costs and poor results in improving the corrosion of metal at openings in the prior art.

[0011] The objective of this invention is achieved through the following technical solution: This invention provides a method for improving through-hole corrosion, comprising: Provide substrate; A metal layer is formed over the substrate; A first insulating layer is formed over the metal layer, and the first insulating layer is etched to form a contact hole, through which the metal layer is exposed. A first transparent conductive layer is formed above the first insulating layer; A second insulating layer is formed above the first transparent conductive layer. The second insulating layer is used as a protective structure for the first baking process. Then, at least the second insulating layer at the contact hole is removed. A second transparent conductive layer is formed on top of the first transparent conductive layer, and a second baking process is performed with the first transparent conductive layer as a protective structure.

[0012] Furthermore, the thickness of the first transparent conductive layer is greater than or equal to the thickness of the second transparent conductive layer.

[0013] Furthermore, after the first baking process, the manufacturing method includes: Remove the second insulating layer at the contact hole, and the areas between the first transparent conductive layer and the second transparent conductive layer other than at the contact hole are separated from each other by the second insulating layer.

[0014] Furthermore, after the first baking process, the manufacturing method includes: Remove all of the second insulating layer, and make conductive contact between the first transparent conductive layer and the second transparent conductive layer in all areas.

[0015] Furthermore, the metal layer comprises copper, and the first transparent conductive layer and the second transparent conductive layer comprise indium tin oxide or indium zinc oxide.

[0016] Furthermore, before forming the first insulating layer over the metal layer, the fabrication method includes: The metal layer is etched to form a patterned first electrode.

[0017] Furthermore, before forming the second insulating layer over the first transparent conductive layer, the fabrication method includes: The first transparent conductive layer is etched to form a patterned second electrode.

[0018] Furthermore, prior to the second baking process, the manufacturing method includes: The second transparent conductive layer is etched to form a patterned third electrode.

[0019] This application also provides an array substrate, wherein the array substrate has contact holes at both the bonding area and the drain, and is manufactured using the method described above for improving via corrosion.

[0020] This application also provides a display device, including the array substrate described above.

[0021] The beneficial effects of this invention are as follows: By forming a second insulating layer above the first transparent conductive layer, and using the second insulating layer as a protective structure during the first baking process, the oxidation and corrosion of the metal layer under high temperature is isolated; during the fabrication of the second transparent conductive layer, since the first transparent conductive layer is sufficiently dense after baking, a second baking process is performed using the first transparent conductive layer as a protective structure, again isolating the metal layer from oxidation and corrosion under high temperature. The first and second transparent conductive layers bridge each other to form a thicker transparent conductive layer, which not only reduces impedance but also increases the protection of the metal layer during subsequent use. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a structure in the prior art where two conductive layers are electrically connected.

[0023] Figures 2a-2c For the corresponding Figure 1 A schematic diagram illustrating the fabrication method of electrically connecting two conductive layers.

[0024] Figure 3 These are electron microscope images of the contact hole after corrosion, including planar and cross-sectional images.

[0025] Figure 4 This is a schematic diagram of another existing structure for conductive connection of two conductive layers.

[0026] Figure 5 This is a schematic diagram of the structure of the via conductive connection in Embodiment 1 of the present invention.

[0027] Figures 6a-6e This is a schematic diagram of the manufacturing method for improving through-hole corrosion in Embodiment 1 of the present invention.

[0028] Figure 7 This is an electron microscope planar image of the normal contact hole in Embodiment 1 of the present invention.

[0029] Figure 8 This is a schematic diagram of the structure of the conductive connection point of the via in Embodiment 2 of the present invention.

[0030] Figures 9a-9e This is a schematic diagram of the manufacturing method for improving through-hole corrosion in Embodiment 2 of the present invention.

[0031] Figure 10 This is a schematic diagram of the array substrate in this invention.

[0032] Figure 11 This is a schematic diagram of the display device in the dark state according to the present invention.

[0033] Figure 12 This is a schematic diagram of the display device in the bright state in this invention. Detailed Implementation

[0034] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the improved via corrosion fabrication method, array substrate, and display device proposed according to the present invention: [Example 1] Figure 5 This is a schematic diagram of the structure of the via conductive connection in Embodiment 1 of the present invention. Figures 6a-6e This is a schematic diagram of the manufacturing method for improving through-hole corrosion in Embodiment 1 of the present invention.

[0035] like Figures 5 to 6e As shown, Embodiment 1 of the present invention provides a method for improving through-hole corrosion, comprising: like Figure 6aAs shown, a substrate 10 is provided, which may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0036] A metal layer 11 is formed above the substrate 10. The metal layer 11 can be made of copper (Cu), or other metals that are easily corroded by high-temperature baking in an oxygen environment. The metal layer 11 can be etched as needed to form patterned first electrodes, such as scan lines, gates, data lines, sources, drains, and peripheral metal traces.

[0037] like Figure 6b As shown, a first insulating layer 12 is formed above the metal layer 11. The first insulating layer 12 is etched to form a contact hole TH, through which the metal layer 11 is exposed. The contact hole TH can be a via at the pad in the bonding area of ​​the peripheral metal trace, a via at the connection between the drain and pixel electrode in the display area, or a bridging via in other areas. The material of the first insulating layer 12 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0038] like Figure 6c As shown, a first transparent conductive layer 13 is formed above the first insulating layer 12. The material of the first transparent conductive layer 13 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first transparent conductive layer 13 can be etched according to actual needs to form a patterned second electrode, such as a common electrode, pixel electrode, or bridging electrode.

[0039] Next, a second insulating layer 15 is formed above the first transparent conductive layer 13, and a first baking process (conditions: baking temperature of about 250°C, oxygen content of 5%) is performed with the second insulating layer 15 as the protective structure. The material of the second insulating layer 15 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0040] In other words, when the first transparent conductive layer 13 is formed, because the film of the transparent conductive layer is not dense enough at this time, it does not provide sufficient protection for the metal layer 11. Therefore, the first transparent conductive layer 13 is not annealed first. If a baking process is performed directly, the metal layer 11 will be accelerated to oxidize and corrode in a high-temperature and oxygen environment, making it easy for poor contact to occur between the first transparent conductive layer 13 and the metal layer 11. Therefore, in this application, after the second insulating layer 15 is formed above the first transparent conductive layer 13, the first baking process is performed with the second insulating layer 15 as a protective structure. This allows the first transparent conductive layer 13 to undergo annealing under the protection of the second insulating layer 15, avoiding the oxidation and corrosion of the metal layer 11 under high-temperature and oxygen conditions.

[0041] like Figure 6d As shown, after the first baking process, at least the second insulating layer 15 at the contact hole TH is removed, so that the first transparent conductive layer 13 is exposed from the contact hole TH, which facilitates subsequent conductive connection.

[0042] like Figure 6e As shown, a second transparent conductive layer 14 is formed above the first transparent conductive layer 13, and the second baking process is performed with the first transparent conductive layer 13 as a protective structure. Since the first transparent conductive layer 13 has already undergone annealing treatment during the first baking process, the first transparent conductive layer 13 is dense enough to provide good protection for the underlying metal layer 11. Therefore, the second baking process can use the first transparent conductive layer 13 as a protective structure to further avoid oxidation and corrosion of the metal layer 11 under high temperature and oxygen conditions. Moreover, the first transparent conductive layer 13 and the second transparent conductive layer 14 are bridged together to form a thicker transparent conductive layer, which not only reduces impedance but also increases the protection of the metal layer 11 during subsequent use. The material of the first transparent conductive layer 13 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Optionally, before the second baking process, the second transparent conductive layer 15 can be etched as needed to form a patterned third electrode, such as a common electrode, pixel electrode, or bridging electrode.

[0043] Furthermore, the thickness of the first transparent conductive layer 13 is greater than or equal to the thickness of the second transparent conductive layer 14. For example, in the prior art, the thickness of a single transparent conductive layer is 600 Å, which can be divided into a 400 Å first transparent conductive layer 13 superimposed with a 200 Å second transparent conductive layer 14, or a 300 Å first transparent conductive layer 13 superimposed with a 300 Å second transparent conductive layer 14. By dividing it into a first transparent conductive layer 13 and a second transparent conductive layer 14, a two-stage baking process can be used, reducing the time of each baking process and thus reducing the oxidative corrosion of the metal layer 11 under high temperature and oxygen conditions. Preferably, the thickness of the first transparent conductive layer 13 is equal to the thickness of the second transparent conductive layer 14, thereby minimizing the maximum time of the two baking processes and further reducing the oxidative corrosion of the metal layer 11 under high temperature and oxygen conditions.

[0044] In this embodiment, after the first baking process, the second insulating layer 15 at the contact hole TH is removed, and the areas between the first transparent conductive layer 13 and the second transparent conductive layer 14, except for the contact hole TH, are separated from each other by the second insulating layer 15. That is, after the first baking process, only the second insulating layer 15 at the contact hole TH is removed, while the second insulating layer 15 in other areas is retained. This allows the areas between the first transparent conductive layer 13 and the second transparent conductive layer 14, except for the contact hole TH, to be separated from each other by the second insulating layer 15. This facilitates the fabrication of different electrodes in the first transparent conductive layer 13 and the second transparent conductive layer 14. For example, the first transparent conductive layer 13 can be used to fabricate a common electrode, and the second transparent conductive layer 14 can be used to fabricate a pixel electrode; or, the first transparent conductive layer 13 can be used to fabricate a pixel electrode, and the second transparent conductive layer 14 can be used to fabricate a common electrode, thereby forming a fringe field switching (FFS) mode.

[0045] The etching process mentioned above includes photoresist application, exposure, development, etching (dry etching or wet etching), and photoresist removal. For specific etching process flow, please refer to existing technologies.

[0046] Figure 7 This is an electron microscope planar image of the normal contact hole in Embodiment 1 of the present invention. (See image below.) Figure 7 As shown, the edge of the contact hole TH in this application is relatively smooth and there are no traces of corrosion. That is, the manufacturing method in this application can avoid the oxidation and corrosion of the metal layer 11 under high temperature and oxygen conditions.

[0047] [Example 2] Figure 8 This is a schematic diagram of the structure of the conductive connection point of the via in Embodiment 2 of the present invention. Figures 9a-9e This is a schematic diagram of the manufacturing method for improving via corrosion in Embodiment 2 of the present invention. Figures 8 to 9e As shown, the method for improving through-hole corrosion provided in Embodiment 2 of the present invention is similar to that in Embodiment 1. Figures 5 to 6e The methods for improving via corrosion are basically the same as those in other articles, except that: In this embodiment, after the first baking process, all of the second insulating layer 15 is removed, and the first transparent conductive layer 13 and the second transparent conductive layer 14 in all areas are in conductive contact with each other. By directly removing the entire second insulating layer 15, not only can one masking process be reduced, but the connection effect of the first transparent conductive layer 13 and the second transparent conductive layer 14 can also be increased. When the first transparent conductive layer 13 and the second transparent conductive layer 14 are used together to form an electrode, the impedance of the electrode can be reduced. For example, the first transparent conductive layer 13 and the second transparent conductive layer 14 can be used together to form a pixel electrode or a common electrode. Of course, pixel electrodes and common electrodes can also be formed simultaneously (In-Plane Switching (IPS)).

[0048] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0049] Figure 10 This is a schematic diagram of the array substrate structure in this invention. (See diagram below.) Figure 10 As shown, this application also provides an array substrate 20, which is manufactured using the improved via corrosion method described above.

[0050] The array substrate 20 includes: A first metal layer is disposed above the array substrate 20. The first metal layer includes scan lines (not shown) and a gate 211, which is electrically connected to the scan lines. The first metal layer can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo.

[0051] A gate insulating layer 201 covers the scan line and the gate 211. The gate insulating layer 201 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0052] A semiconductor layer is disposed above the gate insulating layer 201, and the semiconductor layer includes an active layer 221 corresponding to the gate 211. The semiconductor layer can be made of polysilicon or a metal oxide (e.g., indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0053] A second metal layer is disposed above the gate insulating layer 201 and the semiconductor layer. The second metal layer includes a data line 231, a source 232, and a drain 233. Multiple scan lines and multiple data lines 231 are mutually insulated and intersected to form multiple pixel units. The data line 231 is electrically connected to the source 232, and the source 232 and the drain 233 are electrically connected through the active layer 221. That is, the gate 211, the active layer 221, the source 232, and the drain 233 together constitute a thin-film transistor (TFT) on the array substrate.

[0054] A planarization layer 202 is disposed above the second metal layer and covers the data line 231, the source electrode 232, and the drain electrode 233. The planarization layer 202 has a first via in the region corresponding to the drain electrode 233, and the drain electrode 233 is exposed through the first via. The material of the planarization layer 202 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0055] A third transparent conductive layer is disposed above the planarization layer 202, and the third transparent conductive layer includes a common electrode 241. The material of the third transparent conductive layer can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0056] An insulating spacer layer 203 is disposed above the third transparent conductive layer. The insulating spacer layer 203 has a second via in the region corresponding to the drain electrode 233. The first via and the second via together form a contact hole TH. The insulating spacer layer 203 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0057] A fourth transparent conductive layer is disposed above the insulating spacer layer 203. This fourth transparent conductive layer includes a pixel electrode 251 corresponding to a pixel unit. The pixel electrode 251 is a block electrode corresponding to the pixel unit and has a slit. The pixel electrode 251 is electrically connected to the corresponding drain electrode 233 through a contact hole TH. The pixel electrode 251 cooperates with the common electrode 241 to form a driving electric field. The material of the fourth transparent conductive layer can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0058] In this embodiment, the second metal layer, planarization layer 202, third transparent conductive layer, insulating spacer layer 203, and fourth transparent conductive layer are fabricated using the above-described method for improving via corrosion. The second metal layer is equivalent to metal layer 11 and is made of copper. The planarization layer 202 is equivalent to the first insulating layer 12. The third transparent conductive layer is equivalent to the first transparent conductive layer 13. The insulating spacer layer 203 is equivalent to the second insulating layer 15. The fourth transparent conductive layer is equivalent to the second transparent conductive layer 14.

[0059] Of course, in another embodiment, the array substrate 20 also has contact holes TH in the bonding area, and the first metal layer and the second metal layer both have peripheral connection circuits (e.g., gate drive circuit and source drive circuit) in the non-display area. The pads on the top of the bonding area of ​​the array substrate 20 are connected to the peripheral connection circuits through the contact holes TH. Therefore, the contact holes TH in the bonding area of ​​the array substrate 20 can also be fabricated using the improved via etching method described above, wherein the first metal layer and the second metal layer are both equivalent to metal layer 11 and are made of copper. The planarization layer 202 in the display area is equivalent to the first insulating layer 12. The gate insulating layer 201 and the planarization layer 202 in the non-display area are both equivalent to the first insulating layer 12. The third transparent conductive layer is equivalent to the first transparent conductive layer 13. The insulating spacer layer 203 is equivalent to the second insulating layer 15. The fourth transparent conductive layer is equivalent to the second transparent conductive layer 14.

[0060] Figure 11 This is a schematic diagram of the display device in the dark state according to the present invention. Figure 12 This is a schematic diagram of the display device in the present invention in the illuminated state. (See attached diagram.) Figure 11 and Figure 12 As shown, this application also provides a display panel, including an array substrate 20, a color filter substrate 30 disposed opposite to the array substrate 20, and a liquid crystal layer 40 located between the array substrate 20 and the color filter substrate 30. The array substrate 20 is the array substrate 20 described above.

[0061] The liquid crystal layer 40 uses positive liquid crystal molecules, that is, liquid crystal molecules with positive dielectric anisotropy, such as... Figure 11 As shown, in the initial state, the positive liquid crystal molecules in the liquid crystal layer 40 are aligned parallel to the color filter substrate 30 and the array substrate, and the alignment direction of the positive liquid crystal molecules near the color filter substrate 30 is opposite to that of the positive liquid crystal molecules near the array substrate. Of course, in other embodiments, the liquid crystal layer 40 can also use negative liquid crystal molecules, and the negative liquid crystal molecules in the liquid crystal layer 40 can be aligned perpendicular to the color filter substrate 30 and the array substrate, that is, similar to the alignment method of VA display mode.

[0062] On the side of the color filter substrate 30 facing the liquid crystal layer 40, there are multiple color resist layers 32 corresponding to pixel units and black matrices (BM) 31 that space the multiple color resist layers 32 apart from each other. A black matrix 31 is provided between any two adjacent columns and two adjacent rows of pixel units. The color resist layers 32 include red (R), green (G), and blue (B) color resist materials, which respectively form red, green, and blue pixel units. The black matrices 31 are located between the red, green, and blue pixel units, so that adjacent pixel units are spaced apart by the black matrices 31.

[0063] Furthermore, an upper polarizer 51 is provided on the side of the color filter substrate 30 away from the liquid crystal layer 40, and a lower polarizer 52 is provided on the side of the array substrate away from the liquid crystal layer 40. The light transmission axis of the upper polarizer 51 and the light transmission axis of the lower polarizer 52 are perpendicular to each other.

[0064] The color filter substrate 30 and the array substrate can be made of transparent substrates such as glass, acrylic, and polycarbonate. The common electrode block 241 and the pixel electrode 251 can be made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0065] The present invention also provides a display device, including a display panel and a backlight module 60, wherein the backlight module 60 is located below the display panel and is used to provide a backlight source for the display panel.

[0066] The backlight module 60 can be an edge-lit backlight module or a direct-lit backlight module. Preferably, the backlight module 60 adopts a collimated backlight (CBL) mode, which can collect light and ensure display effect.

[0067] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for improving through-hole corrosion, characterized in that, include: Provide substrate (10); A metal layer (11) is formed over the substrate (10); A first insulating layer (12) is formed over the metal layer (11), and the first insulating layer (12) is etched to form a contact hole (TH), through which the metal layer (11) is exposed; A first transparent conductive layer (13) is formed above the first insulating layer (12); A second insulating layer (15) is formed above the first transparent conductive layer (13), and a first baking process is performed with the second insulating layer (15) as a protective structure. Then, at least the second insulating layer (15) at the contact hole (TH) is removed. A second transparent conductive layer (14) is formed above the first transparent conductive layer (13), and a second baking process is performed with the first transparent conductive layer (13) as a protective structure.

2. The method for improving through-hole corrosion according to claim 1, characterized in that, The thickness of the first transparent conductive layer (13) is greater than or equal to the thickness of the second transparent conductive layer (14).

3. The method for improving through-hole corrosion according to claim 1, characterized in that, After the first baking process, the manufacturing method includes: Remove the second insulating layer (15) at the contact hole (TH), and the areas between the first transparent conductive layer (13) and the second transparent conductive layer (14), except at the contact hole (TH), are separated from each other by the second insulating layer (15).

4. The method for improving through-hole corrosion according to claim 1, characterized in that, After the first baking process, the manufacturing method includes: Remove all of the second insulating layer (15), and the first transparent conductive layer (13) and the second transparent conductive layer (14) in all regions are in conductive contact with each other.

5. The method for improving through-hole corrosion according to claim 1, characterized in that, The metal layer (11) comprises copper, and the first transparent conductive layer (13) and the second transparent conductive layer (14) comprise indium tin oxide or indium zinc oxide.

6. The method for improving via corrosion according to any one of claims 1-5, characterized in that, Before forming the first insulating layer (12) over the metal layer (11), the fabrication method includes: The metal layer (11) is etched to form a patterned first electrode.

7. The method for improving via corrosion according to any one of claims 1-5, characterized in that, Before forming the second insulating layer (15) above the first transparent conductive layer (13), the fabrication method includes: The first transparent conductive layer (13) is etched to form a patterned second electrode.

8. The method for improving through-hole corrosion according to any one of claims 1-5, characterized in that, Before the second baking process, the manufacturing method includes: The second transparent conductive layer (15) is etched to form a patterned third electrode.

9. An array substrate, characterized in that, The array substrate has contact holes (TH) at both the bonding area and the drain (233), and is manufactured using the method for improving via corrosion as described in any one of claims 1-8.

10. A display device, characterized in that, Includes the array substrate (20) as described in claim 9.

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