Instruction execution method and device, equipment, storage medium and program product
By constructing and executing functions corresponding to GPU instructions in the CPU environment, the problem of GPU instruction execution without GPU support is solved, thereby improving the performance and verification efficiency of graphics processing tasks.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
- Filing Date
- 2024-10-31
- Publication Date
- 2026-05-01
Smart Images
Figure CN121957597A_ABST
Abstract
Description
Instruction execution methods, apparatus, devices, storage media, and program products Technical Field
[0001] This application relates to the field of chip technology, and in particular to an instruction execution method, apparatus, device, storage medium, and program product. Background Technology
[0002] GPUs (Graphics Processing Units) are used in electronic devices to perform image rendering tasks by executing pre-designed functional code. For example, current GPUs primarily use SPIRV instructions to implement functions, meaning task code is written using SPIRV instructions. SPIRV (Standard Portable Intermediate Representation Version V) is an intermediate language that allows developers to write shaders and computation programs that can run across different platforms and devices.
[0003] However, in environments lacking GPUs (such as before GPU tape-out), the functional code for each task cannot be executed effectively, thus failing to meet the requirements for GPU functional verification before tape-out. Therefore, the problem of how to achieve effective interpretation and execution of GPU instructions in environments lacking GPU support urgently needs to be solved. Summary of the Invention
[0004] Therefore, it is necessary to provide an instruction execution method, apparatus, device, storage medium, and program product that can effectively interpret and execute GPU instructions in an environment lacking GPU support, addressing the aforementioned technical problems.
[0005] Firstly, this application provides an instruction execution method. The method includes:
[0006] Obtain the first function code information to be executed by the GPU; if the first function code information is verified to be valid, construct the first function corresponding to the first instruction in the first function code information; wherein, when the first instruction is executed in the GPU environment, it is used to implement the target function, and when the first function is executed in the non-GPU environment, it implements the target function; execute the first function to obtain the execution result of the target function.
[0007] In one embodiment, constructing the first function corresponding to the first instruction in the first functional code information includes: determining the bit field of the first instruction; parsing the bit field to obtain multiple sub-bit fields; determining the functional function corresponding to each sub-bit field; and using each functional function as the first function corresponding to the first instruction.
[0008] In one embodiment, before determining the bit field of the first instruction, the method further includes: querying whether a first association relationship corresponding to the first instruction exists in the function cache library according to the first instruction; the first association relationship is the correspondence between the first instruction and a preset function; if the first association relationship exists, the preset function is used as the first function.
[0009] In one embodiment, the method further includes: if the first association does not exist, determining the bit field of the first instruction, and determining the first function corresponding to the first instruction based on the bit field of the first instruction.
[0010] In one embodiment, there are multiple first functions; executing the first function includes: determining the amount of resources required to execute each first function; the amount of resources represents the number of first execution units of the target type required to execute each first function; determining the first execution units of the target type available in the GPU; dividing the available first execution units of the target type according to the amount of resources to obtain a division result; the division result is used to indicate the first function to be executed by the available first execution units of the target type; and executing the first function in the CPU environment if the division result satisfies the GPU resource allocation conditions.
[0011] In one embodiment, the method further includes: if it is determined that the partitioning result does not meet the GPU resource allocation conditions, re-partitioning the available first execution units of the target type according to the resource amount, obtaining the partitioning result again, and determining again whether the partitioning result meets the GPU resource allocation conditions; wherein, if the number of partitioning times reaches a preset partitioning threshold, the step of partitioning the available first execution units of the target type according to the resource amount is exited.
[0012] In one embodiment, obtaining the first functional code information to be executed from the GPU includes: submitting the first basic functional code to be executed to a task queue; the first basic functional code includes the first instruction; determining the first execution condition corresponding to the first basic functional code; generating a first task package in the task queue based on the first execution condition and the first basic functional code, and using the first task package as the first functional code information.
[0013] In one embodiment, the method further includes: submitting the execution result to the task queue; generating a status data packet of the execution result in the task queue and outputting the status data packet; the status data packet includes at least the time of executing the first function, the execution unit called, and the utilization rate of the called execution unit.
[0014] In one embodiment, the method further includes: performing code format verification on the first function code information; if the code format verification passes, performing instruction format verification on the first instruction in the first function code information; wherein the instruction format verification is used to verify whether the function executed by the first instruction is the target function; if the instruction format verification passes, it is determined that the first function code information has passed verification.
[0015] Secondly, this application also provides an instruction execution device. The device includes:
[0016] The acquisition module is used to acquire information about the first function code to be executed by the GPU;
[0017] A construction module is used to construct a first function corresponding to the first instruction in the first function code information when the first function code information is verified to be valid; wherein, when the first instruction is executed in a GPU environment, it is used to implement the target function, and when the first function is executed in a non-GPU environment, it implements the target function.
[0018] The execution module is used to execute the first function and obtain the execution result of the target function.
[0019] In one embodiment, the construction module is specifically used for: determining the bit field of the first instruction; parsing the bit field to obtain multiple sub-bit fields; determining the function corresponding to each sub-bit field; and using each function as the first function corresponding to the first instruction.
[0020] In one embodiment, the device further includes a function determination module, configured to: before determining the bit field of the first instruction, query whether there is a first association relationship in the function cache library corresponding to the first instruction; the first association relationship is the correspondence between the first instruction and a preset function; if the first association relationship exists, then the preset function is used as the first function.
[0021] In one embodiment, the apparatus further includes an association module, configured to: if the first association relationship does not exist, determine the bit field of the first instruction, and determine the first function corresponding to the first instruction based on the bit field of the first instruction.
[0022] In one embodiment, there are multiple first functions; the execution module is specifically configured to: determine the amount of resources required to execute each first function; the amount of resources represents the number of first execution units of the target type required to execute each first function; determine the first execution units of the target type available in the GPU; divide the available first execution units of the target type according to the amount of resources to obtain a division result; the division result is used to indicate the first function to be executed by the available first execution units of the target type; and execute the first function in the CPU environment if the division result satisfies the GPU resource allocation conditions.
[0023] In one embodiment, the device further includes a partitioning module, configured to: if it is determined that the partitioning result does not meet the GPU resource allocation conditions, re-partition the available first execution units of the target type according to the resource quantity, obtain the partitioning result again, and determine again whether the partitioning result meets the GPU resource allocation conditions; wherein, if the number of partitioning times reaches a preset partitioning threshold, the step of partitioning the available first execution units of the target type according to the resource quantity is exited.
[0024] In one embodiment, the acquisition module is specifically configured to: submit a first basic function code to be executed to a task queue; the first basic function code includes the first instruction; determine a first execution condition corresponding to the first basic function code; generate a first task package in the task queue based on the first execution condition and the first basic function code, and use the first task package as the information of the first function code.
[0025] In one embodiment, the device further includes an output module for: submitting the execution result to the task queue; generating a status data packet of the execution result in the task queue and outputting the status data packet; the status data packet includes at least the time of executing the first function, the execution unit called, and the utilization rate of the called execution unit.
[0026] In one embodiment, the device further includes a verification module, configured to: perform code format verification on the first function code information; if the code format verification passes, perform instruction format verification on the first instruction in the first function code information; wherein the instruction format verification is used to verify whether the function executed by the first instruction is the target function; if the instruction format verification passes, it is determined that the first function code information has passed verification.
[0027] Thirdly, this application also provides a computer device, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described in any of the first aspects above.
[0028] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of the first aspects above.
[0029] Fifthly, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects above.
[0030] The aforementioned instruction execution method, apparatus, device, storage medium, and program product can obtain the first function code information to be executed by the GPU; if the first function code information is verified to be valid, a first function corresponding to the first instruction in the first function code information is constructed; wherein, when the first instruction is executed in the GPU environment, it is used to implement the target function, and when the first function is executed in a non-GPU environment, it implements the target function; the first function is executed to obtain the execution result of the target function. Thus, by converting the first instruction in the GPU environment, the corresponding first function can be executed in a non-GPU environment to achieve the target function of the first instruction. This is equivalent to executing the first instruction in a non-GPU environment, that is, achieving effective interpretation and execution of GPU instructions in environments lacking GPU support, thereby improving the performance of processing systems lacking GPUs in graphics processing tasks. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 is a flowchart illustrating an instruction execution method in one embodiment;
[0033] Figure 2 is a flowchart illustrating the process of obtaining first function code information in one embodiment;
[0034] Figure 3 is a schematic diagram of the information verification process in one embodiment;
[0035] Figure 4 is a flowchart illustrating the determination of the first function in one embodiment;
[0036] Figure 5 is a flowchart illustrating another method for determining the first function in one embodiment;
[0037] Figure 6 is a flowchart illustrating the execution of the first function in one embodiment;
[0038] Figure 7 is a schematic diagram of the interpreter's processing procedure in one embodiment;
[0039] Figure 8 is a structural block diagram of an instruction execution device in one embodiment;
[0040] Figure 9 is an internal structure diagram of a computer device in one embodiment. Detailed Implementation
[0041] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description in order to provide a full understanding of this application, but this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0043] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
[0044] It is understandable that "at least one" refers to one or more, while "multiple" refers to two or more.
[0045] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0046] SPIRV (Standard Portable Intermediate Representation Version V) is an intermediate language (IL) designed specifically for graphics and computation shaders. It is used to describe graphics and computation shaders and is standardized as part of the Vulkan graphics API. SPIR-V is commonly used with APIs such as Vulkan, OpenGL, and OpenCL, allowing developers to write shaders and computation programs that can run across different platforms and devices.
[0047] In existing technologies, the main reliance is on the hardware-level support of the SPIRV instruction by the graphics processing unit (GPU). That is, the SPIRV instruction is generally compiled and executed directly on the GPU, providing efficient graphics processing capabilities.
[0048] Currently, instructions such as SPIRV, which are used in GPU compilation, can only run in a GPU environment. In an environment without a GPU, the execution of these instructions cannot be supported. For example, during GPU design, code for various functions is compiled based on SPIRV instructions. After design but before GPU tape-out, the code for these functions needs to be verified. However, since the GPU has not yet been tape-out, there is no GPU environment, making verification impossible and lacking effective support for the execution of SPIRV instructions.
[0049] Therefore, related technologies limit the flexibility and compatibility of processing systems lacking GPU environments when performing graphics tasks. For GPU designers, the lack of simulated execution of code for instructions such as SPIR-V makes it difficult to correctly verify the correctness of GPU functionality.
[0050] In view of this, embodiments of this application provide an instruction execution method for effectively interpreting and executing the instruction set used in GPU design in environments lacking GPU support (especially in scenarios such as before GPU tape-out or functional verification of software stack design).
[0051] It should be noted that the instruction execution method provided in this application can be executed by an instruction execution device, which can be implemented as part or all of an electronic device through software, hardware, or a combination of software and hardware. The electronic device can be a personal computer, laptop, smartphone, or tablet computer, etc., and is not exhaustively exemplified here.
[0052] In one embodiment, as shown in Figure 1, an instruction execution method is provided, including the following steps:
[0053] Step 101: Obtain the first function code information to be executed by the GPU.
[0054] The first function code information corresponds to the target function; that is, the first function code information, after being executed in the GPU, can achieve the target function. The first function code information includes the basic code for implementing the target function, which may contain a first instruction. Based on this, the first instruction is used to implement the target function. Since the GPU is a graphics processing unit, primarily used for drawing graphics on screens in electronic devices, the target function can be a function for drawing a target image, such as a function for drawing grass.
[0055] Among them, the electronic device obtains the first function code information in an environment where there is no actual GPU (non-GPU environment).
[0056] For example, an electronic device can use software to create a virtual GPU environment in which the GPU's design files are run to obtain first functional code information.
[0057] Optionally, a single first function code or multiple first function code information can be obtained simultaneously. If multiple first function code information is obtained, each first function code information can correspond to a different target function, and based on this, the function implemented by the first instruction in each first function code information can also be different.
[0058] Optionally, the first function code information may contain one or more first instructions. When multiple first instructions are included, each first instruction may correspond to the same target function or different target functions.
[0059] Optionally, the first instruction can be a SPIRV instruction from the SPIRV instruction set.
[0060] For example, the first instruction can belong to one of the following types of instructions: sampling instruction, memory access instruction, and computation instruction. Optionally, when multiple first instructions are included, the types of the first instructions can be the same or different.
[0061] Optionally, a CPU (Central Processing Unit) environment may be deployed in the electronic device, and a virtual GPU environment may be created in the CPU environment to obtain the first functional code information in the CPU environment.
[0062] Step 102: If the first function code information is verified to be valid, construct the first function corresponding to the first instruction in the first function code information.
[0063] If the first function code information passes verification, it means the format of the first function code information is correct, and instruction conversion can continue. Conversely, if the first function code information fails verification, it means the format is incorrect, instruction conversion cannot be performed, and subsequent steps are stopped, ending the simulation execution process of the first function code information.
[0064] As mentioned above, the first instruction can be single or multiple. It is understandable that if there are multiple first instructions, then for each first instruction, a single or multiple first functions corresponding to that first instruction can be constructed.
[0065] Optionally, the first function may be a sampling function, a structure caching function, or a general computation function, etc., which are not fully exemplified here.
[0066] In one implementation, for each first instruction, the bit field describing the first instruction is parsed, and the first function corresponding to the first instruction is determined based on the bit field.
[0067] In another implementation, for each first instruction, a preset function corresponding to that first instruction can be queried from the function cache library, and the queried preset function is used as the first function corresponding to that first instruction. The function cache library pre-stores multiple sets of correspondences between first instructions and preset functions.
[0068] In this embodiment, the first instruction is executed in a GPU environment to implement the target function, and the first function is executed in a non-GPU environment to implement the target function. In this way, by determining the first function, the first function is executed in a non-GPU environment (e.g., CPU environment) of the electronic device, thereby implementing the execution of the instruction, that is, implementing the execution of the first function code information, thereby running the target function. The execution result can be used to verify whether the target function can be correctly implemented, so as to determine whether the design of the target function of the GPU is correct.
[0069] Step 103: Execute the first function to obtain the execution result of the target function.
[0070] Optionally, the execution results may include whether the target function is running correctly and the running information during the process.
[0071] Optionally, when the electronic device acquires multiple first function code information, it constructs and runs a first function for each first function code information in the order of acquisition. For example, after the first function corresponding to each first instruction in the previous first function code information is constructed and run to obtain the execution result of the previous first function code information, the first function corresponding to each first instruction in the next first function code information is constructed and run to obtain the execution result of the next first function code information.
[0072] In the above instruction execution method, the first function code information to be executed by the GPU can be obtained; if the first function code information is verified, a first function corresponding to the first instruction in the first function code information is constructed; wherein, when the first instruction is executed in the GPU environment, it is used to implement the target function, and when the first function is executed in a non-GPU environment, it implements the target function; the first function is executed to obtain the execution result of the target function. In this way, by converting the first instruction in the GPU environment, the corresponding first function can be executed in a non-GPU environment to implement the target function of the first instruction. This is equivalent to executing the first instruction in a non-GPU environment, that is, realizing the effective interpretation and execution of GPU instructions in an environment lacking GPU support, thereby improving the performance of processing systems lacking GPUs in graphics processing tasks.
[0073] In one embodiment, Figure 2 illustrates a flowchart for obtaining first functional code information. Obtaining the first functional code information to be executed by the GPU includes:
[0074] Step 201: Submit the first basic function code to be executed to the task queue. The first basic function code includes the first instruction.
[0075] Step 202: Determine the first execution condition corresponding to the first basic function code.
[0076] Step 203: In the task queue, generate a first task package based on the first execution condition and the first basic function code, and use the first task package as the first function code information.
[0077] Since task submission in a GPU environment requires submission through a task queue, i.e., the first function code information needs to be submitted to the task queue, this application embodiment simulates a task queue and a task package that simulates the GPU state.
[0078] In this system, a task packet receiver can be constructed within the electronic device as a task queue. The task queue receives first function code information to enable task queue monitoring. For example, a single thread can be constructed to monitor the task queue.
[0079] As mentioned above, the first function code information includes the basic code for implementing the target function, namely the first basic function code. Taking the target function as drawing grass as an example, the function of the first basic function code is to draw grass. However, when the GPU is actually used by electronic devices from different manufacturers, some additional drawing conditions will be provided for the target function, namely the first execution conditions. For example, the first execution condition is that the grass being drawn is floating, or the color of the grass being drawn is dark green, etc. In this way, additional drawing actions are superimposed on the basic drawing of the first basic function code to achieve personalized drawing.
[0080] Optionally, the first execution condition can be one or more.
[0081] In this embodiment of the application, a first task package is generated in the task queue according to the first execution condition and the first basic function code. The first task package is used as the first function code information to improve the first function code information. This ensures that the target function can be fully realized after the first function code information is executed, thus enriching the verification process.
[0082] In one embodiment, Figure 3 illustrates a flowchart of an information verification process. The method further includes:
[0083] Step 301: Verify the code format of the first function code information.
[0084] For example, GPUs typically run binary code, so code format verification here can refer to verifying whether the code in the first functional code information is in binary format.
[0085] If the code is not in binary format, the code format verification fails, and subsequent verification steps for that first function code information are stopped.
[0086] Understandably, if the GPU is running code in a different format, then code format verification for that format will be performed.
[0087] Step 302: If the code format verification passes, perform instruction format verification on the first instruction in the first function code information. The instruction format verification verifies whether the function executed by the first instruction is the target function.
[0088] In other words, since the first function code information corresponds to the target function, under normal circumstances, the first instruction in the first function code information will implement the target function after execution. However, in abnormal situations, if the instructions are used incorrectly during GPU design, the first function code information may contain instructions that do not correspond to the target function. If construction is performed directly without instruction format verification, the entire verification process will fail and the cause cannot be identified. Therefore, further instruction format verification is required to verify whether the function executed by all first instructions is the target function. If so, the instruction format verification is considered successful.
[0089] Optionally, if any one of the first instructions fails verification, the instruction format verification of the entire first function code information is determined to be unsuccessful, and subsequent verification steps for that first function code information can be stopped.
[0090] Step 303: If the instruction format verification passes, then the verification of the first function code information is confirmed to be successful.
[0091] In this embodiment, two-layer format verification ensures that the first functional code information before function construction is correct, thus ensuring the accuracy of the execution results obtained from subsequent verification.
[0092] In one embodiment, Figure 4 illustrates a flowchart for determining a first function. Constructing the first function corresponding to the first instruction in the first function code information includes:
[0093] Step 401: Determine the bit field of the first instruction.
[0094] That is, the first instruction can be described using bit values in the first function code information, and this string of bit values serves as the bit field of the first instruction.
[0095] Step 402: Parse the bit field to obtain multiple sub-bit fields.
[0096] In this system, a segment of bit fields performs the same function as a corresponding functional field. Therefore, the electronic device can parse the total bit field to determine how many sub-bit fields it contains, in order to identify the functional field corresponding to each sub-bit field.
[0097] Step 403: Determine the function corresponding to each sub-bit field.
[0098] Step 404: Each function is designated as the first function corresponding to the first instruction.
[0099] For example, the bit field has 20 bits in total. Bits 1 to 5 are the first sub-bit field, corresponding to the first function; bits 6 to 11 are the second sub-bit field, corresponding to the second function; and bits 12 to 20 are the third sub-bit field, corresponding to the third function. If each function is used as the first function, then in this example, the first instruction corresponds to three first functions.
[0100] It is understandable that there may be cases where a bit field corresponds to only one function. For example, if a bit field has 15 bits and these 15 bits cannot be split, they correspond to one function. In this case, the first instruction corresponds to one first function.
[0101] In this embodiment of the application, the corresponding first function is accurately constructed by parsing the fields of the first instruction.
[0102] In one embodiment, Figure 5 illustrates another flowchart for determining the first function. Prior to determining the bit field of the first instruction, the method further includes:
[0103] Step 501: According to the first instruction, query whether there is a first association relationship in the function cache library corresponding to the first instruction.
[0104] The first association relationship is the correspondence between the first instruction and the preset function.
[0105] As mentioned above, the function cache library pre-stores multiple sets of correspondences between first instructions and preset functions. Therefore, the first association can be determined directly by querying the function cache library. Then, the preset function in the first association is used as the first function.
[0106] Step 502: If a first association exists, then the preset function is used as the first function.
[0107] Step 503: If there is no first association relationship, determine the bit field of the first instruction, and determine the first function corresponding to the first instruction based on the bit field of the first instruction.
[0108] That is, if there is no first association relationship, the step is to determine the bit field of the first instruction, parse the bit field to obtain multiple sub-bit fields, and then determine the function corresponding to each sub-bit field, and use each function as the first function corresponding to the first instruction.
[0109] Optionally, if no first association relationship exists, after determining the first function corresponding to the first instruction based on the bit field of the first instruction, the constructed first function is used as a preset function to form a correspondence between the first instruction and the preset function. This correspondence relationship is stored in the function cache library. In this way, when parsing other first function code information next time, if the first instruction still exists, the corresponding first association relationship can be directly obtained from the function cache library to determine its corresponding first function, without having to parse the bit field to determine the first function.
[0110] In this embodiment, the first function can be determined either by parsing the bit field or by querying the function cache library, thus improving the flexibility and effectiveness of determining the first function. Furthermore, since determining the first function based on the bit field takes longer than querying the function cache library, after constructing the first function corresponding to each first instruction, the corresponding relationship is stored in the function cache library. Subsequent queries can then directly determine the first function corresponding to that first instruction, effectively reducing the time required to obtain the first function. Essentially, for a single instruction, only one process based on bit field parsing is needed to determine the first function; subsequent queries can then directly query the function cache library to determine the first function, saving computational resources for the electronic device.
[0111] In one embodiment, Figure 6 illustrates a flowchart of executing a first function. Executing the first function includes:
[0112] Step 601: Determine the amount of resources required to execute each first function.
[0113] There can be multiple first functions. The resource quantity represents the number of first execution units of the target type required to execute each first function.
[0114] Step 602: Determine the first execution unit of the target type available in the GPU.
[0115] In a GPU environment, the GPU may execute multiple functional tasks simultaneously. Similarly, this is also true in a virtual GPU environment. Therefore, in addition to verifying whether the first functional code can be executed correctly, it is also necessary to verify whether the GPU resources support the execution of the first functional code.
[0116] For example, GPUs typically have multiple types of execution units, with the execution unit of the target type being used as the first execution unit. For instance, if the target type is addition, there are 200 addition execution units in the GPU used as the first execution units, but 150 are currently in use, then there are 50 first execution units of the target type that are currently available.
[0117] Optionally, a GPU may have multiple cores, each core comprising multiple first execution units of target types. Each execution unit may be composed of circuit elements.
[0118] Step 603: Based on the amount of resources, divide the available target types into first execution units to obtain the division results. The division results are used to indicate the first function to be executed by the first execution units of each available target type;
[0119] For example, if the target type is addition calculation, and the resource quantity represents the number of addition execution units required to execute all the first functions corresponding to the first instruction, which is 20, that is, to perform 20 additions, and the CPU has two cores, each with 10 available addition units, then the partitioning result can be that the first 10 additions are allocated to the 10 addition execution units of the first core for execution, and the other 10 are allocated to the 10 addition execution units of the other core for execution.
[0120] Step 604: If the partitioning result meets the GPU resource allocation conditions, execute the first function in the CPU environment.
[0121] Among them, meeting the GPU resource allocation conditions indicates that the GPU resources can successfully execute each of the first functions.
[0122] For example, in the example of step 603 above, all additions can be successfully performed using two core addition units. That is, the partitioning result satisfies the GPU resource allocation conditions.
[0123] For example, a CPU has 3 cores. The first core has 10 addition units, all of which are available. The second core has 10 addition units, 8 of which are available. The third core is fully utilized, with 0 available. If the 10 addition units of the first core are used to perform the first 10 additions, and the 8 execution units of the second core are used to perform the remaining 8 additions, then the remaining two additions cannot be performed. This means that the partitioning fails, and the partitioning result does not meet the GPU resource allocation conditions.
[0124] In one embodiment, the method further includes: if it is determined that the partitioning result does not meet the GPU resource allocation conditions, re-partitioning the first execution units of the available target type according to the resource quantity, obtaining the partitioning result again, and determining again whether the partitioning result meets the GPU resource allocation conditions; wherein, if the number of partitioning times reaches a preset partitioning threshold, the step of partitioning the first execution units of the available target type according to the resource quantity is exited.
[0125] For example, in the case of the failed partitioning above, the first execution unit of the available target type can be repartitioned according to the amount of resources. For example, it can be repartitioned into 10 addition units of the first core to perform 10 additions first. After the execution is completed, the 10 addition units of the first core can be used to perform the next 10 additions.
[0126] If the partitioning result that satisfies the GPU resource allocation conditions cannot be obtained after multiple repetitions, the partitioning can be terminated and the verification process can be exited.
[0127] For example, if the preset segmentation threshold is 10, then if the segmentation fails 10 times in a row, the verification will be terminated and no further steps will be executed.
[0128] In this embodiment, multiple partitioning steps are used to ensure that the execution process matches the GPU resources, thereby enabling the verification of GPU performance and functionality.
[0129] In one embodiment, the method further includes: submitting the execution result to a task queue; generating a status data packet of the execution result in the task queue; and outputting the status data packet.
[0130] The status data packet includes at least the execution time of the first function, the execution unit called, and the utilization rate of the called execution unit. Of course, the status data packet may also include other information generated during the execution process, which is not fully illustrated here.
[0131] Optionally, the task queue can output status data packets to the aforementioned virtual GPU environment for result verification within the GPU environment.
[0132] In one embodiment, the execution result is the function output result. The execution results of all first functions corresponding to all first instructions in the first function code information are cached in the CPU cache module. After the execution of all first functions corresponding to all first instructions in the first function code information is completed, all results from the cache module are submitted to the memory hardware for storage.
[0133] Optionally, the cache module can be cleared after submission to the memory hardware.
[0134] For ease of understanding, the following provides a complete embodiment of an interpreter provided in this application that translates and executes SPIRV instructions in real time on a CPU, corresponding to the instruction execution method described above. This interpreter can be implemented using software algorithms and runs in a non-GPU environment, such as a CPU environment, to implement the steps of the instruction execution method.
[0135] Please refer to Figure 7 for a schematic diagram of the interpreter's processing procedure.
[0136] The interpreter comprises the following key components:
[0137] 1) Task queue: GPU task submission needs to be done through the task queue. Therefore, this application embodiment simulates the task queue and the task package that simulates the GPU state.
[0138] 2) Instruction decoder: Responsible for parsing SPIRV binary code and converting it into internal function representations.
[0139] 3) Execution Engine: Performs logical processing based on the decoded instructions, simulating the execution logic of the GPU.
[0140] 4) Function Library: When the execution engine encounters complex execution instructions, it will call functions in the function library to perform calculations. The functions in the function library mainly include sampling functions, structure caching functions, and general calculation functions.
[0141] 5) State Manager: Manages the state and variables during shader execution.
[0142] 6) Memory Manager: Handles memory access requests for instructions and data.
[0143] 7) Graphics GPU: A virtual GPU environment implemented in the CPU.
[0144] 8) SPIR-V simulation platform: used for constructing and executing functions.
[0145] The execution process is as follows:
[0146] 1. Implement GPU software task queue, (1) Construct a task packet receiver (2) Implement task queue monitoring, and construct a separate thread to monitor the task queue;
[0147] 2. Implement SPIRV instruction semantic parsing, and parse the fields of the SPIRV instruction into function parameter information received by the executor;
[0148] 3. Implement the executor and function library, implementing the sampling instructions, memory access instructions, and computation instructions in SPIRV through the function library, and calling them in the executor;
[0149] 4. Implement executor state management. The executor needs to record the execution status and result of each instruction, and the result will affect the executor's state.
[0150] 5. Implement executor memory management, which can use existing C++ memory pools and interfaces with the executor.
[0151] In this embodiment of the application, where a SPIRV emulator for the GPU software stack does not currently exist, this interpreter can decouple driver and compiler development. The compiler uses the results of the SPIRV simulation to verify the correctness of the compiler development. The driver can use the results of the simulation to develop new driver software.
[0152] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0153] Based on the same inventive concept, this application also provides an instruction execution apparatus for implementing the instruction execution method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more instruction execution apparatus embodiments provided below can be found in the limitations of the instruction execution method above, and will not be repeated here.
[0154] In one embodiment, as shown in FIG8, an instruction execution device 800 is provided, comprising: an acquisition module 801, a construction module 802, and an execution module 803, wherein:
[0155] The acquisition module 801 is used to acquire the first function code information to be executed by the GPU;
[0156] The construction module 802 is used to construct a first function corresponding to the first instruction in the first function code information when the first function code information is verified to be valid; wherein, when the first instruction is executed in the GPU environment, it is used to implement the target function, and when the first function is executed in the non-GPU environment, it implements the target function.
[0157] Execution module 803 is used to execute the first function and obtain the execution result of the target function.
[0158] In one embodiment, the construction module 802 is specifically used to: determine the bit field of the first instruction; parse the bit field to obtain multiple sub-bit fields; determine the function corresponding to each sub-bit field; and use each function as the first function corresponding to the first instruction.
[0159] In one embodiment, the apparatus further includes a function determination module, configured to: before determining the bit field of the first instruction, query whether there is a first association relationship in the function cache library corresponding to the first instruction; the first association relationship is the correspondence between the first instruction and a preset function; if the first association relationship exists, then the preset function is used as the first function.
[0160] In one embodiment, the apparatus further includes an association module, configured to: if no first association relationship exists, determine the bit field of the first instruction, and determine the first function corresponding to the first instruction based on the bit field of the first instruction.
[0161] In one embodiment, there are multiple first functions; the execution module 803 is specifically used to: determine the amount of resources required to execute each first function; the amount of resources represents the number of first execution units of target type required to execute each first function; determine the first execution units of target type available in the GPU; divide the available first execution units of target type according to the amount of resources to obtain a division result; the division result is used to indicate the first function to be executed by the available first execution units of target type; and execute the first function in the CPU environment if the division result satisfies the GPU resource allocation conditions.
[0162] In one embodiment, the apparatus further includes a partitioning module, configured to: if the partitioning result does not meet the GPU resource allocation conditions, re-partition the first execution units of the available target type according to the resource quantity, obtain the partitioning result again, and determine again whether the partitioning result meets the GPU resource allocation conditions; wherein, if the number of partitioning times reaches a preset partitioning threshold, the step of partitioning the first execution units of the available target type according to the resource quantity is exited.
[0163] In one embodiment, the acquisition module 801 is specifically used for: submitting a first basic function code to be executed to a task queue; the first basic function code includes a first instruction; determining a first execution condition corresponding to the first basic function code; generating a first task package in the task queue based on the first execution condition and the first basic function code, and using the first task package as the first function code information.
[0164] In one embodiment, the apparatus further includes an output module for: submitting the execution result to a task queue; generating a status data packet of the execution result in the task queue and outputting the status data packet; the status data packet includes at least the time of execution of the first function, the execution unit called, and the utilization rate of the called execution unit.
[0165] In one embodiment, the apparatus further includes a verification module, configured to: perform code format verification on the first function code information; if the code format verification passes, perform instruction format verification on the first instruction in the first function code information; wherein, the instruction format verification is used to verify whether the function executed by the first instruction is the target function; if the instruction format verification passes, it is determined that the first function code information has passed verification.
[0166] Each module in the aforementioned instruction execution device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.
[0167] In one embodiment, a computer device, which may be a server, is provided, and its internal structure can be as shown in Figure 9. The computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is connected to the system bus via the I / O interfaces. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes non-volatile storage media and internal memory. The non-volatile storage media stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device stores instruction execution data. The I / O interfaces of the computer device are used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements an instruction execution method.
[0168] Those skilled in the art will understand that the structure shown in Figure 9 is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or may combine certain components, or may have different component arrangements.
[0169] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.
[0170] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.
[0171] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.
[0172] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0173] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0174] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A method for executing instructions, characterized in that, The method includes: obtaining first function code information to be executed by the GPU; if the first function code information is verified to be valid, constructing a first function corresponding to a first instruction in the first function code information; wherein, when the first instruction is executed in the GPU environment, it is used to implement the target function, and when the first function is executed in a non-GPU environment, it implements the target function; executing the first function to obtain the execution result of the target function.
2. The method according to claim 1, characterized in that, The step of constructing the first function corresponding to the first instruction in the first functional code information includes: determining the bit field of the first instruction; parsing the bit field to obtain multiple sub-bit fields; determining the functional function corresponding to each sub-bit field; and using each functional function as the first function corresponding to the first instruction.
3. The method according to claim 2, characterized in that, Before determining the bit field of the first instruction, the method further includes: querying whether a first association relationship corresponding to the first instruction exists in the function cache library according to the first instruction; the first association relationship is the correspondence between the first instruction and a preset function; if the first association relationship exists, the preset function is used as the first function.
4. The method according to claim 3, characterized in that, The method further includes: if the first association relationship does not exist, determining the bit field of the first instruction, and determining the first function corresponding to the first instruction based on the bit field of the first instruction.
5. The method according to any one of claims 1 to 4, characterized in that, The first function may be multiple; executing the first function includes: determining the amount of resources required to execute each first function; the amount of resources represents the number of first execution units of the target type required to execute each first function; determining the first execution units of the target type available in the GPU; dividing the available first execution units of the target type according to the amount of resources to obtain a division result; the division result is used to indicate the first function to be executed by each available first execution unit of the target type; and executing the first function in the CPU environment if the division result satisfies the GPU resource allocation conditions.
6. The method according to claim 5, characterized in that, The method further includes: if it is determined that the partitioning result does not meet the GPU resource allocation conditions, re-partitioning the available first execution units of the target type according to the resource quantity, obtaining the partitioning result again, and determining again whether the partitioning result meets the GPU resource allocation conditions; wherein, if the number of partitioning times reaches a preset partitioning threshold, the step of partitioning the available first execution units of the target type according to the resource quantity is exited.
7. The method according to claim 1, characterized in that, The step of obtaining the first functional code information to be executed by the GPU includes: submitting the first basic functional code to be executed to the task queue; the first basic functional code includes the first instruction; determining the first execution condition corresponding to the first basic functional code; in the task queue, generating a first task package according to the first execution condition and the first basic functional code, and using the first task package as the first functional code information.
8. The method according to claim 7, characterized in that, The method further includes: submitting the execution result to the task queue; generating a status data packet of the execution result in the task queue, and outputting the status data packet; the status data packet includes at least the time of executing the first function, the execution unit called, and the utilization rate of the called execution unit.
9. The method according to claim 1, characterized in that, The method further includes: performing code format verification on the first function code information; if the code format verification passes, performing instruction format verification on the first instruction in the first function code information; wherein, the instruction format verification is used to verify whether the function executed by the first instruction is the target function; if the instruction format verification passes, it is determined that the first function code information has passed verification.
10. An instruction execution device, characterized in that, The apparatus includes: an acquisition module for acquiring first function code information to be executed by a GPU; a construction module for constructing a first function corresponding to a first instruction in the first function code information if the first function code information is verified to be valid; wherein the first instruction is used to implement a target function when executed in a GPU environment, and the first function implements the target function when executed in a non-GPU environment; and an execution module for executing the first function to obtain the execution result of the target function.
11. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 9.
12. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 9.
13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 9.