Debugging method and device, electronic equipment, storage medium and computer program product

Abstract

The embodiment of the invention provides a debugging method and device, electronic equipment, a storage medium and a computer program product, the debugging method is applied to a processor, the debugging method comprises the steps that an insertion enable signal is acquired, and the insertion enable signal is used for indicating an instruction fetching position of the processor; under the condition that the insertion enable signal is the first enable signal, taking out an original instruction from a target buffer area of the processor, and executing the original instruction; wherein the first enable signal represents that the processor fetches an instruction from a target buffer area, and the target buffer area is used for storing an original instruction at a target address where the breakpoint instruction is inserted.

Description

Debugging methods and apparatus, electronic equipment, storage media and computer program products Technical Field

[0001] This disclosure relates to, but is not limited to, the field of processor debugging technology, and particularly to a debugging method and apparatus, electronic equipment, storage medium, and computer program product. Background Technology

[0002] In related technologies, breakpoint debugging is a commonly used technique during development and maintenance. Breakpoints are generally divided into hardware breakpoints and software breakpoints (i.e., soft breakpoints). However, restoring soft breakpoints usually requires a series of operations in sequence, such as restoring the original instructions, refreshing the instruction cache, single-stepping, resetting the breakpoint, refreshing the instruction cache, and continuing to run. This results in a complex and cumbersome debugging process and increases interference with the behavior of the program under test. Summary of the Invention

[0003] This disclosure provides a debugging method and apparatus, an electronic device, a storage medium, and a computer program product.

[0004] The technical solution of this disclosure embodiment is implemented as follows: In a first aspect, this disclosure embodiment provides a debugging method applied to a processor. The debugging method includes: acquiring an insertion enable signal, the insertion enable signal being used to indicate the instruction fetch position of the processor; when the insertion enable signal is a first enable signal, retrieving the original instruction from the processor's target buffer and executing the original instruction; wherein, the first enable signal indicates that the processor fetches an instruction from the target buffer, and the target buffer is used to store the original instruction at the target address of the inserted breakpoint instruction.

[0005] Secondly, embodiments of this disclosure provide a debugging method, comprising: replacing the original instruction at the target address of a target program with a breakpoint instruction, so that when the target program runs to the target address, the processor generates an exception to suspend the execution of the target program; in response to receiving a breakpoint recovery command, writing the original instruction into the processor's target buffer and configuring an insertion enable signal as a first enable signal, wherein the insertion enable signal is used to indicate the processor's instruction fetch position, and the target buffer is used to store the original instruction at the target address of the inserted breakpoint instruction; sending an instruction fetch command to the processor, so that the processor obtains the insertion enable signal in response to the instruction fetch command, and when the insertion enable signal is the first enable signal, fetches and executes the original instruction from the target buffer; wherein the first enable signal indicates that the processor fetches an instruction from the target buffer.

[0006] Thirdly, embodiments of this disclosure provide a debugging apparatus applied in a processor. The debugging apparatus includes an execution unit and a target buffer, wherein: the target buffer is used to store the original instruction at the target address of the inserted breakpoint instruction; the execution unit is used to acquire an insertion enable signal, the insertion enable signal being used to indicate the instruction fetching position of the processor; when the insertion enable signal is a first enable signal, the original instruction is fetched from the target buffer and executed; wherein the first enable signal indicates that the processor fetches an instruction from the target buffer.

[0007] Fourthly, embodiments of this disclosure provide a debugging apparatus, comprising: a processing module, configured to replace the original instruction at a target address of a target program with a breakpoint instruction, so that when the target program runs to the target address, the processor generates an exception to suspend the execution of the target program; a configuration module, configured to, in response to receiving a breakpoint recovery command, write the original instruction into the processor's target buffer and configure an insertion enable signal as a first enable signal, wherein the insertion enable signal is used to indicate the processor's instruction fetch position, and the target buffer is used to store the original instruction at the target address of the inserted breakpoint instruction; and a sending module, configured to send an instruction fetch command to the processor, so that the processor, in response to the instruction fetch command, obtains the insertion enable signal, and, when the insertion enable signal is the first enable signal, fetches and executes the original instruction from the target buffer; wherein the first enable signal indicates that the processor fetches an instruction from the target buffer.

[0008] Fifthly, embodiments of this disclosure provide an electronic device, including a memory and a processor, wherein the processor includes the debugging apparatus provided in the third aspect above, or, when executing a computer program on the memory, implements the debugging method provided in the second aspect above.

[0009] In a sixth aspect, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the debugging method provided in the second aspect above.

[0010] In a seventh aspect, embodiments of this disclosure provide a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements the debugging method provided in the second aspect above.

[0011] In this embodiment, on the one hand, by adding a dedicated target buffer inside the processor to temporarily store the original instructions covered by breakpoint instructions, compared with the related technologies that frequently rewrite the instruction content in memory (such as changing from the original instruction to the breakpoint instruction, and vice versa), this solution eliminates the need for frequent rewriting of the instruction content in memory. Throughout the debugging process, the breakpoint instruction remains at its original address (i.e., it is not removed or rewritten), significantly reducing interference with the storage system and minimizing the impact of debugging on the program under test, thus providing a more realistic feedback on the program's execution behavior. On the other hand, when the insertion enable signal is the first enable signal, the original instruction is directly retrieved from the target buffer and executed, eliminating the need for frequent instruction rewriting and cache refresh. This not only saves multiple steps such as restoring the original instruction, cache invalidation, and resetting breakpoints, greatly simplifying the breakpoint recovery process and improving debugging efficiency, but also reduces manual operations that are strictly dependent on timing, significantly reducing the risk of debugging errors and making the entire debugging process more stable and reliable. Furthermore, it reduces performance overhead and operational anomalies caused by frequent intervention. On the other hand, since the buffer is located inside the processor, it improves instruction access speed and reduces latency. The processor reads instructions directly from the internal buffer without going through any level of cache, and does not affect the data stored in any level of cache.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0014] Figure 1 is a schematic diagram of the implementation process of a debugging method provided in an embodiment of the present disclosure; Figure 2 is a schematic diagram of the implementation process of a debugging method provided in an embodiment of the present disclosure; Figure 3 is a schematic diagram of the composition structure of a debugging device provided in an embodiment of the present disclosure; Figure 4 is a schematic diagram of the composition structure of a debugging device provided in an embodiment of the present disclosure; Figure 5 is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0016] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0017] In the following description, the terms “first, second, third” are used merely to distinguish similar objects and do not represent a specified order of objects. It is understood that the order or sequence of “first, second, third” may be interchanged where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0019] The technical solutions in the embodiments of this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0020] Figure 1 is a schematic diagram of the implementation process of a debugging method provided in this embodiment of the present disclosure. It is applied to a processor. The debugging method is illustrated by taking the triggering of a soft breakpoint and entering the debugging state as an example. As shown in Figure 1, the debugging method includes steps S11 and S12, wherein: step S11: obtain the insertion enable signal. The insertion enable signal is used to indicate the instruction fetch position of the processor.

[0021] Here, the processor can include, but is not limited to, any suitable hardware device capable of instruction processing, such as a central processing unit (CPU) or a graphics processing unit (GPU).

[0022] The insert enable signal is used to dynamically control whether the processor (i.e., during the instruction fetch phase) enables the internal target buffer. The fetch location can be, but is not limited to, the target buffer, memory, and other storage locations. It is understood that other storage locations differ from the target buffer and memory.

[0023] Different insertion enable signals can indicate different fetch locations. In some implementations, the insertion enable signal may include, but is not limited to, a first enable signal, a second enable signal, etc. The first enable signal indicates that the internal target buffer is enabled, that is, the processor fetches instructions from the target buffer. The second enable signal indicates that the internal target buffer is not enabled, that is, the processor fetches instructions from memory in a conventional manner. The representation of the first and second enable signals can be any suitable form, for example, using a high level or 1 as the first enable signal and a low level or 0 as the second enable signal. In implementation, those skilled in the art can set more enable signals according to actual needs, and the embodiments of this application are not limited thereto. For example, the insertion enable signal may include a first enable signal, a second enable signal, and a third enable signal, wherein the first enable signal indicates that the processor fetches instructions from the internal target buffer, the second enable signal indicates that the processor fetches instructions from memory, and the third enable signal indicates that the processor fetches instructions from other memory locations.

[0024] In some implementations, the insertion enable signal can be a control signal set by the debugging side (such as debugging software, debugger, debugging equipment, etc.) as needed to achieve flexible switching of the processor's instruction fetch path. For example, if the processor generates an exception after a soft breakpoint is triggered, the debugging side can configure the insertion enable signal as the first enable signal. As another example, after determining that the original instruction has been executed, the debugging side can configure the insertion enable signal as the second enable signal. In some implementations, the insertion enable signal can be configured through a dedicated debugging interface. For example, the processor provides a dedicated enable signal register, which is configured through the debugging interface and then received and processed by the enable signal register.

[0025] In some implementations, the insertion enable signal can also be dynamically configured by the processor. For example, when the processor receives an enable signal configuration command sent by the debug side, it sets the insertion enable signal to a first enable signal. This enable signal configuration command can be any suitable command for configuring the insertion enable signal to the first enable signal; it may or may not carry the first enable signal. As another example, when the processor receives a reset command sent by the debug side, it sets the insertion enable signal to a second enable signal. This reset command can be any suitable command for configuring the insertion enable signal to the second enable signal; it may or may not carry the second enable signal.

[0026] Memory is a hardware device used to store data and instructions. This memory can include external memory, internal cache (ICache), etc. External memory refers to storage media located outside the processor, such as SDRAM (Synchronous Dynamic Random Access Memory) and Flash memory. ICache, on the other hand, is an instruction cache used to speed up the processor's access to frequently used instructions. In implementation, external memory or ICache assists the processor in completing data and instruction fetching operations at different levels.

[0027] The target buffer is a dedicated storage area located within the processor, used to temporarily store the original instructions covered by breakpoint instructions. The target buffer can be an on-chip memory cell or a set of memory-mapped I / O registers (MMIO). The size (or capacity) of the target buffer can be any suitable size capable of holding at least one instruction. In some implementations, the size of the target buffer can be set based on the size of the longest instruction in the processor. In practice, the size of the target buffer can be fixed-length or variable-length (i.e., dynamically configured according to needs). The purpose of the target buffer is to provide a temporary space for storing original instructions without modifying the contents of external memory, allowing the processor to directly read and execute the original instructions in the target buffer. This avoids disturbance to memory and cache states, thereby reducing the impact of the debugging process on processor behavior.

[0028] A breakpoint instruction is a machine instruction used to trigger an exception when program execution reaches a specified location, thereby interrupting program execution and causing the processor to enter debug state (or debug mode). A breakpoint instruction can be a trap instruction, an interrupt instruction, a jump instruction, etc. In implementation, when the processor encounters a breakpoint instruction, it immediately jumps to the exception handler set on the debug side, allowing inspection of the current program state (such as register values, memory state, etc.) to avoid dependence on hardware resources. This is suitable for various soft breakpoint debugging scenarios. In this disclosure, the breakpoint instruction is written into the program code (i.e., at the target address) to implement debugging functionality, but it is not modified or deleted and remains at the original address during subsequent execution.

[0029] The original instruction is the instruction that originally existed at the target address. During debugging, the original instruction is replaced by breakpoint instructions.

[0030] In some implementations, the insertion enable signal can be acquired after receiving the instruction fetch command from the debug side, or it can be acquired before the processor's instruction fetch unit performs the instruction fetch. The instruction fetch command can be any suitable command used to allow the processor to single-step through the original instruction. In some implementations, the instruction fetch command can specify a target thread unit, which can be the thread unit that triggered the breakpoint; the thread unit can be a thread or a thread bundle. There can be at least one target thread unit. It is understood that when the target thread unit triggers the breakpoint, the target thread unit will enter a paused state (or debug state).

[0031] Step S12: When the insertion enable signal is the first enable signal, fetch the original instruction from the processor's target buffer and execute the original instruction; wherein, the first enable signal indicates that the processor fetches the instruction from the target buffer, and the target buffer is used to store the original instruction at the target address of the inserted breakpoint instruction.

[0032] Here, when the insert enable signal is active (i.e., the first enable signal), the processor can directly fetch instructions from the target buffer, or it can fetch instructions from the target buffer only if preset conditions are met (such as the thread selection signal specifying the target thread unit, or the thread selection signal matching the identifier of the target thread unit in the fetch command). It can be understood that the process of the processor fetching raw instructions is similar to the process of the processor fetching instructions from memory.

[0033] The process by which this processor executes raw instructions is the same as the normal execution process of other instructions: the raw instruction is fed into the instruction pipeline, undergoes decoding and execution stages, and finally completes the operation on the raw instruction. Since the execution of raw instructions is done directly within the processor, this process does not affect the breakpoint instruction in external memory, nor does it cause cache invalidation or program counter (PC) updates. This ensures that after executing the raw instructions, the program can continue execution from the instruction following the breakpoint instruction.

[0034] Understandably, when the insert enable signal is invalid (i.e., the second enable signal), the processor continues to fetch instructions from external memory or cache in the usual manner.

[0035] In this embodiment, on the one hand, by adding a dedicated target buffer inside the processor to temporarily store the original instructions covered by breakpoint instructions, compared with the related technologies that frequently rewrite the instruction content in memory (such as changing from the original instruction to the breakpoint instruction, and vice versa), this solution eliminates the need for frequent rewriting of the instruction content in memory. Throughout the debugging process, the breakpoint instruction remains at its original address (i.e., it is not removed or rewritten), significantly reducing interference with the storage system and minimizing the impact of debugging on the program under test, thus providing a more realistic reflection of the program's behavior. On the other hand, when the insertion enable signal is the first enable signal, the original instruction is directly retrieved from the target buffer and executed, eliminating the need for frequent instruction rewriting and cache refresh. This not only saves multiple steps such as restoring the original instruction, cache invalidation, and resetting breakpoints, greatly simplifying the breakpoint recovery process and improving debugging efficiency, but also reduces manual operations that are strictly dependent on timing, significantly reducing the risk of debugging errors and making the entire debugging process more stable and reliable. Furthermore, it reduces performance overhead and operational anomalies caused by frequent intervention. On the other hand, since the buffer is located inside the processor, it improves instruction access speed and reduces latency. The processor reads instructions directly from the internal buffer without going through any level of cache, and does not affect the data stored in any level of cache.

[0036] In some implementations, step S11 includes: acquiring an insertion enable signal in response to receiving an instruction fetch command.

[0037] Here, the instruction fetch command can be any suitable command used to instruct the processor to single-step through the original instructions. This instruction fetch command can be sent from the debug side. In implementation, when it is necessary to single-step through or continue executing the original instructions overridden at the breakpoint, the instruction fetch command can be sent to the processor first. In some implementations, the instruction fetch command may also carry an identifier of the target thread unit, indicating that the target thread unit should execute the subsequent original instructions.

[0038] The insert enable signal is a control signal used to indicate whether the processor enables its internal instruction insertion mechanism (i.e., whether insert mode is enabled). When the insert enable signal is active (i.e., the first enable signal), the processor enters an insert mode in which it reads instructions from the target buffer instead of fetching them from the ICache or external memory. When the insert enable signal is inactive (i.e., the second enable signal), the processor does not enter insert mode and fetches instructions in the normal manner.

[0039] In this embodiment of the disclosure, the insertion enable signal is obtained only after the instruction fetch command is received, thereby reducing interference with the normal instruction fetch process.

[0040] In some implementations, the step S12 of "fetching the raw instruction from the processor's target buffer" includes: obtaining a thread selection signal; and fetching the raw instruction from the target buffer if the thread selection signal matches the identifier of the target thread unit included in the fetch command.

[0041] Here, the thread selection signal can be a control signal that determines which thread units participate in the execution of the original instruction in insert mode. A thread unit is a hardware thread entity that supports concurrent execution; each thread unit has its own independent program counter (PC), register set, and other related resources. In a multi-core or multi-threaded architecture, multiple thread units can run different code paths simultaneously, improving the processor's parallel processing capabilities. A thread unit can include threads or thread bundles. In implementation, since the processor includes multiple thread units, the thread selection signal can include at least two bits. The number of bits in the thread selection signal is adapted to the total number N of thread units in the processor. In some implementations, the number of bits in the thread selection signal is the same as N, that is, each bit of the thread selection signal corresponds to one thread unit. In some implementations, it can be based on... (Right now: The number of bits in the thread selection signal is determined by rounding up. For example, the number of bits in the thread selection signal is not less than [a certain value]. For example, if the total number of thread units is 16, then the thread selection signal can be at least 4 bits, meaning that at least 4 bits are used to represent these 16 thread units. If the total number of thread units is 20, then the thread selection signal can be at least 5 bits, meaning that at least 5 bits are used to represent these 20 thread units.

[0042] In some implementations, the thread selection signal can be a control signal set by the debugging side as needed to achieve precise selection of thread units. For example, the processor provides a dedicated set of thread selection registers, which the debugging side configures and processes. For instance, each bit of the thread selection signal corresponds to a thread unit. When the bit corresponding to a thread unit is valid (e.g., 1), the thread unit specified in the thread selection signal can execute the original instruction, while thread units not selected in the thread selection signal will continue to execute instructions according to the normal process.

[0043] In some implementations, the thread selection signal can also be dynamically configured by the processor. For example, when the processor receives a thread selection command from the debug side, it sets the thread selection signal according to the command. The thread selection command can be any suitable command for configuring the thread selection signal, and it can carry an identifier for a specified thread unit; that is, the thread selection signal is set according to the identifier of the specified thread unit. For example, if each bit of the thread selection signal corresponds to a thread unit, then the position corresponding to the specified thread unit is valid. Another example is if the thread selection signal has 100 bits... If the thread selection signal is set to the value corresponding to the specified thread unit, then the thread selection signal can be 4 bits, and 0000~1111 can be used to represent the 16 thread units respectively. If the specified thread unit is the second thread unit, then the thread selection signal can be set to the value corresponding to the second thread unit, that is: 0001.

[0044] The target thread unit refers to the thread unit selected to execute the original instruction at the breakpoint during this debugging process. There can be at least one target thread unit. It is understood that the identifier of the target thread unit is its number. There is a clear logical matching relationship between the thread selection signal and the identifier of the target thread unit. In implementation, the identifier of the target thread unit is compared with the thread selection signal to determine whether the target thread unit is selected. That is, when the thread selection signal matches the identifier of the target thread unit, it indicates that the target thread unit is selected. If the insertion enable signal is also valid, the processor will read the original instruction from the target buffer; otherwise, the processor will continue with the normal instruction fetch operation.

[0045] In this embodiment, the mechanism of controlling the execution of original instructions by the target thread unit through thread selection signals and insertion enable signals achieves precise control of a specified thread in a multi-threaded environment. Compared to related solutions that typically require pausing all thread units for single-step recovery, this solution allows breakpoint recovery to be performed only on the target thread unit, while other thread units maintain their original state, ensuring that other thread units are not disturbed and improving the flexibility and targeting of debugging. It also ensures the controllability and safety of the instruction insertion process, avoiding unnecessary instruction execution or misoperation.

[0046] In some implementations, "execute the original instruction" in step S12 includes: switching the state of the target thread unit to the running state so that the target thread unit executes the original instruction step by step; wherein the program counter of the target thread unit continues to point to the instruction after the breakpoint instruction.

[0047] Here, the target thread unit can be the thread unit that currently triggers the soft breakpoint and needs to execute the insert instruction. In a multi-threaded environment, the debugger can precisely select one or more thread units as the target thread units, thereby ensuring that only these thread units will execute the inserted original instruction, while other thread units remain unaffected. This not only reduces interference with other thread units but also prevents erroneous execution, thus improving debugging efficiency and processor stability.

[0048] The states of a thread unit can include, but are not limited to, running, paused, and waiting states. The running state refers to the state in which the thread unit resumes executing code. During debugging, when a thread unit is paused (i.e., in a paused or waiting state), to execute the inserted original instructions step-by-step, the thread unit's state must first be switched back to the running state. It's understandable that the running state at this time differs from the regular continuous execution mode; it is restricted to a single-step operation. In implementation, by controlling the switching of thread unit states, fine-grained control of the execution flow can be achieved, improving the safety and controllability of debugging.

[0049] Single-step execution is an execution mode that executes only one instruction. In this mode, the target thread unit executes the inserted original instruction only once, without skipping the breakpoint instruction at the breakpoint address. This simulates the actual execution path of the program, while ensuring that the breakpoint instruction is not modified or removed.

[0050] The Program Counter (PC) is the address in the processor that indicates the next instruction to be executed. In this step, although the target thread unit is executing the inserted original instruction, the PC in the target thread unit still points to the instruction following the breakpoint instruction. This ensures that after single-step execution, the target thread unit can continue executing subsequent instructions from the correct address, thus maintaining the continuity and correctness of program execution. At the same time, keeping the breakpoint instruction at its original address location, without removing or overwriting it, avoids repeatedly rewriting the breakpoint instruction, thereby reducing the number of memory and cache operations.

[0051] In practice, there is a close relationship between the target thread unit, the running state, single-step execution, and the program counter. Once the target thread unit is selected, it first switches to the running state, and then enters single-step execution mode. During single-step execution mode, the program counter always points to the position after the breakpoint instruction, ensuring seamless transition to the original program logic after the original instruction is completed, without the need for additional intervention or relocation.

[0052] In this embodiment, by switching the target thread unit to a running state and executing the original instruction step-by-step, it is ensured that only the target thread unit executes the instruction during breakpoint recovery, thereby achieving the debugging purpose. Since the program counter does not advance, subsequent instruction fetches still point to the next instruction after the breakpoint, thus achieving a safer and more controllable debugging process.

[0053] In some implementations, after the target thread unit has executed the original instructions, the debugging method further includes switching the state of the target thread unit to a paused state.

[0054] Here, the target thread unit is the object to which the original instruction is executed during this insertion. Compared to unselected thread units, the target thread unit executes the original instruction in insertion mode, instead of other instructions. In implementation, the target thread unit is in a running state to execute the original instruction in the target buffer once (i.e., single-step execution), and stops immediately after completing this execution. The single-step execution mechanism ensures the controllability of program execution, allowing the program to avoid skipping critical code segments. It can be understood that the original instruction is stored in the target buffer and invoked during single-step execution. Since the original instruction is never written back to external memory, it does not interfere with the external memory state.

[0055] The paused state refers to a waiting state that the target thread unit enters after completing single-step execution. In the paused state, the target thread unit does not automatically execute subsequent instructions, but waits for the next instruction (such as continuing execution or single-stepping again). This not only ensures the integrity of single-step execution and prevents the target thread unit from continuing to run after executing instructions and skipping debugging logic, but also ensures precise control over the debugging process. At the same time, it also guarantees the normal execution of non-target thread units, so that these thread units are not disturbed by debugging behavior.

[0056] In this embodiment of the disclosure, the target thread unit is switched to a paused state immediately after the original instruction is executed. This can prevent uncontrollable behavior that may be caused by its continued execution, avoid the target thread unit executing subsequent instructions in advance and causing the loss of debugging information, and improve the safety and stability of debugging.

[0057] In some implementations, the debugging method further includes setting the insertion enable signal to a second enable signal after the original instruction has been executed or in response to receiving a reset command; wherein the second enable signal indicates that the processor fetches an instruction from memory.

[0058] Here, the second enable signal is a specified state of the insert enable signal, indicating that insert mode is off and the processor resumes the normal instruction fetch process. At this time, the processor will fetch instructions from the regular instruction cache or external memory based on the current PC value. The switching of the second enable signal ensures that the insert operation only affects the intended instruction, avoiding interference with the subsequent instruction stream.

[0059] In some implementations, after executing the original instructions, the processor can automatically set the insertion enable signal to the second enable signal. This reduces the burden on the debugging side and improves the level of automation. In some implementations, after the processor executes the original instructions fetching from the target buffer, it can change the insertion enable signal to the second enable signal according to a reset command sent by the debugging side, thus disabling the insertion mode. This reset command can be any suitable command for configuring the insertion enable signal to the second enable signal; the reset command may or may not carry the second enable signal.

[0060] In this embodiment of the disclosure, by automatically closing the insert mode after the original instruction execution is completed or a reset command is received, it can be ensured that the subsequent instruction fetching process resumes normally, avoid affecting the normal execution of the program due to the accidental opening of the insert mode, improve debugging efficiency and enhance the security of the debugging process.

[0061] In some implementations, the debugging method further includes: in response to receiving a run command, fetching the next instruction after the breakpoint instruction from memory based on the program counter of the target thread unit.

[0062] Here, after completing single-step execution of the target thread unit and resetting the instruction insertion enable signal, the debugger can issue a run command to the processor, indicating a desire to continue execution of subsequent code flow. This run command can be a standard continue command (such as the continue command, next command, etc.), used to notify the processor to resume the normal instruction fetch flow. The continue command continues program execution until the next breakpoint is encountered, the program terminates, or an exception occurs. The next command executes the next line of code; if a function call is encountered, all statements inside the function are executed at once.

[0063] Upon receiving the run command, the processor locates the address of the next instruction to be executed based on the PC of the target thread unit. Since the PC of the target thread unit always points to the instruction following the breakpoint instruction (i.e., the instruction after the original instruction) during single-step execution, after exiting insert mode, the processor will follow the normal instruction fetch process, reading the instruction at the address of the next instruction to be executed from memory and sending that instruction into the instruction pipeline for execution. This achieves a smooth transition from insert mode to normal execution mode. In this way, the processor can ensure that after completing single-step execution, it continues to execute subsequent instructions in the program without instruction fetching errors or skipping the correct instruction sequence due to the presence of insert mode. This ensures that the processor can quickly return to a stable operating state after the debugging process ends, reducing interference with the program execution environment and thus improving overall debugging efficiency and stability.

[0064] In this embodiment of the disclosure, by fetching instructions from memory based on the program counter of the target thread unit, it can be ensured that the program continues to execute in the expected order after single-step execution is completed, thereby improving the coherence and accuracy of the debugging process.

[0065] In some implementations, the debugging method further includes fetching instructions from memory when the insertion enable signal is a second enable signal.

[0066] Here, when the insert enable signal is in the second enable state, the processor follows the normal instruction fetch path. That is, the processor no longer reads instructions from the internal target buffer, but instead fetches instructions from memory (such as external memory or cache). This control mechanism ensures that after completing the single-step execution of the original instruction, the processor can resume the normal execution flow and continue executing subsequent instructions according to the original code flow of the program, without causing erroneous instruction execution due to still being in insert mode. Simultaneously, it allows the debugger to flexibly control when to execute the original instruction and when to resume the normal execution flow, thereby achieving precise control and execution of instructions at breakpoint addresses, enhancing the controllability and stability of the debugging process. Furthermore, without needing to modify the instruction content in external memory, no cache flush operation is triggered, thus minimizing interference to the processor during the entire instruction fetch process.

[0067] During implementation, before the processor fetches an instruction, it can first determine whether the insertion enable signal is the second enable signal. If the insertion enable signal is the second enable signal, then the instruction is fetched from memory according to the PC of each thread unit.

[0068] In this embodiment of the disclosure, by fetching instructions from memory when the insertion enable signal is the second enable signal, the normal execution flow in non-insertion mode is ensured to be undisturbed, thereby enhancing the stability and compatibility of the debugging mechanism.

[0069] Based on the above embodiments, this disclosure also provides a debugging method applied to the debugging side communicating with the processor. Figure 2 is a schematic diagram of the implementation process of a debugging method provided by this disclosure. As shown in Figure 2, the debugging method includes steps S21 to S23, wherein: step S21, the original instruction at the target address of the target program is replaced with a breakpoint instruction, so that when the target program runs to the target address, the processor generates an exception to suspend the execution of the target program.

[0070] Here, the target program can be the currently running program. The target address can be the address of the breakpoint set as needed. A breakpoint instruction is a type of instruction, such as a trap instruction, interrupt instruction, or jump instruction. During implementation, when the processor encounters a breakpoint instruction, it immediately jumps to the set exception handler. By inserting breakpoint instructions at the target address, the program execution flow can be precisely controlled without modifying other code, thus achieving efficient debugging operations. This is particularly suitable for debugging specific threads in multi-threaded or multi-core environments.

[0071] Step S22: In response to receiving the breakpoint recovery command, the original instruction is written to the processor's target buffer and the insertion enable signal is configured as the first enable signal. The insertion enable signal is used to indicate the processor's instruction fetch location, and the target buffer is used to store the original instruction at the target address of the inserted breakpoint instruction.

[0072] Here, the breakpoint recovery command can be user-sent, indicating that the user wishes to execute the original instruction that was overwritten at the soft breakpoint. The breakpoint recovery command can take any suitable form, such as text, voice, or gestures. Upon receiving the breakpoint recovery command, the debugger writes the original instruction corresponding to the breakpoint address into the target buffer and sets the insert enable signal to the first enable signal, thus enabling insert mode. This allows the processor to directly read and execute instructions from the target buffer during the next instruction fetch, instead of reading from regular memory.

[0073] The purpose of the target buffer is to provide a temporary space for storing raw instructions without modifying the contents of external memory, so that the processor can directly read and execute the raw instructions in the target buffer under certain conditions.

[0074] The insert enable signal is a control signal used to indicate whether the processor enables insert mode. Its function is to precisely control the activation and deactivation of insert mode, ensuring that insert mode is only enabled under specified conditions, thereby achieving flexible control over the debugging process.

[0075] For example, in a multithreaded environment, suppose a thread T triggers a soft breakpoint and enters debug mode. At this point, the debugger can respond to the breakpoint recovery command, write the original instruction at the breakpoint address into the target buffer, and set the insert enable signal to the first enable signal. Subsequently, the debugger issues a fetch command, and the processor retrieves the original instruction from the target buffer and executes it. The entire process does not require modification of the instruction content in external memory or cache flushing, thus significantly simplifying the debugging process.

[0076] Step S23: Send the instruction fetch command to the processor so that the processor responds to the instruction fetch command by acquiring the insertion enable signal, and if the insertion enable signal is the first enable signal, fetches and executes the original instruction from the target buffer; wherein, the first enable signal indicates that the processor fetches the instruction from the target buffer.

[0077] Here, the instruction fetch command can be any suitable command used to instruct the processor to single-step through the original instructions. In implementation, when it is necessary to single-step through or continue executing the original instructions covered at the breakpoint, the instruction fetch command can be sent to the processor first. In some implementations, the instruction fetch command may also carry an identifier of the target thread unit, indicating that the target thread unit should execute the subsequent original instructions.

[0078] The insert enable signal is a control signal that indicates whether the processor enables insert mode. When the insert enable signal is activated (i.e., the first enable signal), the processor reads and executes a pre-saved raw instruction from the internal target buffer, instead of fetching from regular external memory or cache. This mechanism allows the debugger to execute the raw instruction at the breakpoint without modifying the program's stored contents.

[0079] The target buffer is a high-speed storage area inside the processor, specifically used to temporarily store raw instructions that have been overwritten by breakpoint instructions. During debugging, by writing the raw instructions into the target buffer, they can be directly retrieved and executed in subsequent executions without modifying the instructions in external memory. This not only reduces interference with the external storage system but also improves debugging efficiency.

[0080] In implementation, the process of the processor executing the original instructions can be found in the specific implementation of step S12 above. Through this mechanism, the processor can bypass breakpoint instructions during single-step execution and directly execute the original instructions, ensuring the accuracy of debugging while avoiding the performance overhead and interference caused by frequent memory modifications and cache refreshes. Furthermore, since the debugging operation is mainly completed automatically by hardware, the burden on the debugging side is greatly reduced, and the debugging process is more stable and reliable.

[0081] In this embodiment, on the one hand, the debugger can execute the original instructions through the instruction fetch command alone, simplifying the debugger's logic, significantly reducing the possibility of errors, and making the debugging operation smoother and more reliable. Simultaneously, by automatically writing the original instructions into the target buffer and setting the insertion enable signal according to the breakpoint recovery command before sending the instruction fetch command, preparation is made for the processor to fetch instructions from the target buffer subsequently, improving the automation and consistency of the debugging process. On the other hand, by adding a dedicated target buffer inside the processor to temporarily store the original instructions covered by the breakpoint instructions, compared to the frequent rewriting of instructions in memory in related technologies, this solution eliminates the need for frequent rewriting of instructions in memory. The breakpoint instructions can remain at their original address throughout the debugging process, significantly reducing interference with the memory system and minimizing the impact of debugging on the program under test, thus helping to provide a more realistic feedback on the program's running behavior. On the other hand, when the insertion enable signal is the first enable signal, the original instruction is directly retrieved from the target buffer and executed, eliminating the need for frequent instruction rewriting and cache flushing. This not only saves multiple steps such as restoring the original instruction, cache invalidation, and resetting breakpoints, greatly simplifying the breakpoint recovery process and improving debugging efficiency, but also reduces manual operations that are strictly dependent on timing, significantly lowering the risk of debugging errors and making the entire debugging process more stable and reliable. It also reduces performance overhead and runtime anomalies caused by frequent interventions. Furthermore, because this buffer is located inside the processor, it improves instruction access speed and reduces latency. The processor reads instructions directly from the internal buffer without going through any level of cache, thus not affecting the data stored in any level of cache.

[0082] In some implementations, the debugging method further includes: determining a target thread unit based on interrupt information sent by the processor or the current state of each thread unit; and configuring a thread selection signal based on the target thread unit, the thread selection signal being used to instruct the target thread unit to execute the original instructions.

[0083] Here, the interrupt information can be an exception notification generated when the processor encounters a soft breakpoint. This interrupt information may contain key information such as the identifier of the thread unit that triggered the soft breakpoint and the trigger address. During implementation, the debugging side can obtain this interrupt information through debugging interfaces (such as JTAG) or by listening to other processes. This interrupt information is used to identify which thread unit triggered the breakpoint, enabling precise control during subsequent debugging operations. For example, in a multi-threaded environment, the interrupt information can quickly locate the specific thread unit T, avoiding interference with other thread units that have not triggered breakpoints. It is understandable that in a multi-core or multi-threaded architecture, multiple thread units can run different code paths simultaneously, improving the processor's parallel processing capabilities.

[0084] The states of a thread unit include running, paused, and waiting states. During implementation, the debugger can also iterate through the states of each thread unit to determine which thread units triggered the breakpoints.

[0085] The target thread unit refers to the thread unit selected to execute the original instruction at the breakpoint during this debugging process. This target thread unit can be the thread unit that triggered the breakpoint. Therefore, all thread units that triggered the breakpoint can be directly used as target thread units, or at least one thread unit can be selected from all thread units that triggered the breakpoint as the target thread unit. This ensures that only these thread units execute the inserted original instruction, while other thread units remain unaffected. This improves the accuracy and efficiency of the debugging process, especially in complex systems, avoiding erroneous operations by non-target thread units. Furthermore, it allows for single-step recovery operations only on the thread unit where the breakpoint occurred without interrupting the entire system, thereby reducing the impact on other thread units and improving debugging efficiency.

[0086] The thread selection signal is a control signal that determines which thread units participate in the execution of the original instruction in insert mode. The purpose of the thread selection signal is to achieve fine-grained control in a multi-threaded environment. By setting the thread selection signal, the debugger can specify the target thread unit to execute the inserted original instruction, while non-target thread units maintain their original execution behavior, thus overcoming the drawback of related technologies that require pausing all thread units.

[0087] In this embodiment, the target thread unit is determined by analyzing interrupt information or thread status, and a corresponding thread selection signal is configured, achieving precise control over the thread. This ensures that debugging operations only affect the specified thread unit and do not affect the normal operation of other thread units. Compared to related technologies that often require pausing all thread units for individual processing, this solution improves the efficiency and targeting of debugging in a multi-threaded environment, and better supports the fine-grained debugging needs in a multi-threaded environment.

[0088] In some implementations, the debugging method further includes: upon determining that the original instruction has been executed, sending a reset command to the processor so that the processor sets the insertion enable signal to a second enable signal based on the reset command.

[0089] Here, the debugging side can determine whether the processor has finished executing the original instruction through debugging interfaces, listening, etc. After determining that the processor has finished executing the original instruction, a reset command can be sent to the processor. This reset command is used to disable the insert mode. When the insert enable signal is set to invalid (i.e., the second enable signal), the processor resumes the normal instruction fetching flow, that is, it no longer reads instructions from the target buffer, but continues to fetch instructions from the ICache or external memory. In implementation, the process of the processor setting the insert enable signal to the second enable signal can be referred to the aforementioned embodiment. This ensures that the insert mode only affects the execution of one instruction of the target thread unit, without interfering with the subsequent program flow or the normal operation of other thread units.

[0090] For example, in a multithreaded system, thread T triggers a soft breakpoint and enters debug mode. The debugger wants thread T to single-step through the original instruction at the breakpoint. At this point, the debugger can write the original instruction to the target buffer, enable the insertion enable signal, and set the thread selection signal, i.e., set the bit corresponding to thread T to 1. Then, the debugger issues a fetch command. The processor detects that thread T meets the conditions and the insertion enable signal is valid, so it fetches the original instruction from the target buffer and executes it. After execution, the debugger immediately sends a reset command, disabling the insertion enable signal to ensure that subsequent fetch operations resume normal flow, thus preventing other threads from being affected.

[0091] In this embodiment of the disclosure, by sending a reset command after the original instruction is executed, the insertion mode is closed in a timely manner, so that the insertion mode only affects the execution of the target instruction, thereby preventing the insertion mode from interfering with the subsequent instruction stream and improving the controllability and security of the debugging process.

[0092] In some implementations, the debugging method further includes sending a run command to the processor, such that the processor, in response to the run command, fetches the next instruction after the breakpoint instruction from memory based on the program counter of the target thread unit.

[0093] Here, after the processor finishes executing the original instructions, the debugger can issue a run command to the processor, indicating a desire to continue executing subsequent code. This run command is used to notify the processor to resume the normal instruction fetch process. In implementation, the processor's response to this run command can be found in the aforementioned embodiments.

[0094] In this embodiment of the disclosure, the execution command can achieve a smooth transition of the processor from insertion mode to normal mode, so as to ensure that the processor can quickly recover to a stable operating state, thereby reducing the interference of debugging on the program execution environment and improving the overall debugging efficiency and stability.

[0095] Based on the above embodiments, this disclosure also provides a debugging device applied in a processor. Figure 3 is a schematic diagram of the composition structure of a debugging device provided in this disclosure. As shown in Figure 3, the debugging device 30 includes a target buffer 31 and an execution unit 32, wherein: the target buffer 31 is used to store the original instruction at the target address of the breakpoint instruction; the execution unit 32 is used to obtain an insertion enable signal, which is used to indicate the instruction fetching position of the processor 3; when the insertion enable signal is a first enable signal, the original instruction is fetched from the target buffer 31 and the original instruction is executed; wherein, the first enable signal indicates that the processor fetches an instruction from the target buffer 31.

[0096] Here, the target buffer can be any suitable storage area, such as GPU memory or registers. This target buffer is primarily used to store the original instructions covered by the breakpoint instruction. The instruction fetch location can include, but is not limited to, the target buffer, memory, or other storage locations. The memory is a hardware device used to store data and instructions. This memory can include external memory, internal cache (ICache), etc.

[0097] The insert enable signal is used to dynamically control whether the processor enables the internal target buffer.

[0098] The execution unit can be any suitable hardware unit or a combination of hardware and software located in the processor that can implement this function. The process of the execution unit processing instructions can be found in the specific implementation of steps S11 to S12 above.

[0099] In this embodiment, on the one hand, by adding a dedicated target buffer inside the processor to temporarily store the original instructions covered by breakpoint instructions, compared with the related technologies that frequently rewrite the instruction content in memory (such as changing from the original instruction to the breakpoint instruction, and vice versa), this solution eliminates the need for frequent rewriting of the instruction content in memory. Throughout the debugging process, the breakpoint instruction remains at its original address (i.e., it is not removed or rewritten), significantly reducing interference with the storage system and minimizing the impact of debugging on the program under test, thus providing a more realistic feedback on the program's behavior. On the other hand, when the execution unit inserts the first enable signal, it directly retrieves and executes the original instruction from the target buffer, eliminating the need for frequent instruction rewriting and cache refresh. This not only saves multiple steps such as restoring the original instruction, cache invalidation, and resetting breakpoints, greatly simplifying the breakpoint recovery process and improving debugging efficiency, but also reduces manual operations that are strictly dependent on timing, significantly reducing the risk of debugging errors and making the entire debugging process more stable and reliable. Furthermore, it reduces performance overhead and operational anomalies caused by frequent intervention. On the other hand, since the buffer is located inside the processor, it improves instruction access speed and reduces latency. The execution unit reads instructions directly from the internal buffer without going through any level of cache, and does not affect the data stored in any level of cache.

[0100] In some implementations, the execution unit 32 is further configured to, in response to receiving an instruction fetch command, acquire an insert enable signal; acquire a thread selection signal; and, if the thread selection signal matches the identifier of the target thread unit included in the instruction fetch command, fetch the original instruction from the target buffer.

[0101] In some implementations, the execution unit 32 is further configured to switch the state of the target thread unit to a running state, so that the target thread unit executes the original instruction step by step; wherein the program counter of the target thread unit continues to point to the instruction following the breakpoint instruction.

[0102] In some implementations, the execution unit 32 is also configured to switch the state of the target thread unit to a paused state after the target thread unit has finished executing the original instructions.

[0103] In some embodiments, the execution unit 32 is further configured to set the insertion enable signal to a second enable signal upon completion of the original instruction or in response to receiving a reset command; wherein the second enable signal is used to instruct the processor to fetch instructions from memory.

[0104] In some implementations, the execution unit 32 is also configured to, in response to receiving a run command, fetch the next instruction following the breakpoint instruction from memory based on the program counter of the target thread unit.

[0105] In some implementations, the execution unit 32 is also configured to fetch instructions from memory when the insertion enable signal is a second enable signal.

[0106] The description of the above apparatus embodiments is similar to that of the above method embodiments, and has similar beneficial effects. For technical details not disclosed in the apparatus embodiments of this disclosure, please refer to the description of the method embodiments of this disclosure for understanding.

[0107] The following uses the CPU as an example to illustrate the technical solution disclosed herein.

[0108] In processor debugging, breakpoint debugging is a commonly used technique. Breakpoints are generally divided into hardware breakpoints and software breakpoints (soft breakpoints). Soft breakpoints are implemented by modifying program code: replacing the instruction at the target address with an interrupt instruction (such as an instruction that triggers a trap). When the program reaches that address, the processor generates an exception and pauses program execution, entering debug mode, due to the execution of the interrupt instruction. Soft breakpoints are implemented by modifying instructions and are not limited by the number of hardware breakpoints, therefore they are widely used in software debugging.

[0109] In related technologies, the recovery of soft breakpoints is usually achieved through the following process: 1) Recover the original instruction: Modify the instruction content at the breakpoint address in external memory (such as DDR), and write the original instruction before the breakpoint was overwritten back to that address to recover the original instruction code at that address.

[0110] 2) Refresh instruction cache: Trigger the processor's instruction cache (ICache) invalidation operation, so that the original instructions written in step 1 are re-fetched from external memory, ensuring that the processor can fetch the updated instructions.

[0111] 3) Single-step execution: The single-step execution command (next) causes the processor to execute only one instruction, namely the instruction that was just updated at the breakpoint address.

[0112] 4) Reset breakpoint: Replace the original instruction at this address with the breakpoint instruction to reset the soft breakpoint and trigger the instruction cache invalidation operation again.

[0113] 5) Continue running the program: The program is resumed to run normally by continuing the program, which allows the processor to skip the breakpoint address and continue to execute the subsequent instruction stream.

[0114] During the aforementioned soft breakpoint recovery process, the debugging software (corresponding to the aforementioned debugging side) needs to rewrite the program code segment multiple times (writing back the original instructions and restoring the breakpoint instructions) and repeatedly manipulate the processor cache (such as invalidating the ICache) to ensure correct instruction execution. This series of operations is complex, involving multiple interventions in the processor's internal and external states. The debugging software needs to precisely control the timing and state; improper control at any step can lead to debugging failure or abnormal program execution. Especially in multi-threaded or multi-core processor environments, in order to execute the above breakpoint recovery steps on a single thread, it is usually necessary to pause other threads as well (i.e., ensure that other threads do not skip the breakpoint) and possibly perform a global cache invalidation operation. This not only makes the debugging process more cumbersome but also causes greater interference with the normal operation of the system.

[0115] This technical solution has the following drawbacks: 1) The debugging process is complex and the software control is difficult: it requires repeated modification of the instruction content in the program memory and manipulation of the processor cache. The debugging software must strictly follow the sequence of operations such as restoring the original instructions, cache invalidation, single-step execution, and resetting breakpoints, which is cumbersome and relies on precise software control. If the timing control is not proper, breakpoints may not be restored in time or instruction execution errors may occur, leading to errors in the debugging process.

[0116] 2) Significant interference with system behavior: Frequent rewriting of program code in external memory and invalidating the cache will disrupt the original state of the program and the cache, interfering with the normal behavior of the system being debugged. This intervention may introduce additional performance overhead, change the program's runtime sequence, and even lead to some unforeseen side effects (such as cache flushing causing unnecessary instruction re-fetching, affecting execution time).

[0117] 3) Insufficient support for multi-threaded debugging: In multi-threaded or multi-core processor environments, existing soft breakpoint recovery solutions typically require pausing all threads and then performing the aforementioned cumbersome process on the thread where the breakpoint occurred separately. The lack of a mechanism for fine-grained control over a specific thread makes debugging multi-threaded programs inefficient, and also unnecessarily blocks the execution of other non-target threads, affecting the parallel operation of the system.

[0118] To address the above issues, this disclosure provides a processor debugging optimization method based on a soft breakpoint recovery mechanism. This overcomes the shortcomings of related technologies, such as cumbersome soft breakpoint recovery processes, significant system impact, and difficulty in adapting to multi-threaded environments. Through a novel mechanism design, debugging software can execute the original instructions at the breakpoint without modifying the instruction or operation cache in external memory, simplifying the processor debugging process. Furthermore, this solution aims to achieve more precise and secure debugging control, enabling debugging software to perform single-step breakpoint recovery on a specified thread in a multi-threaded processor without interfering with the execution of other threads.

[0119] To achieve the above objectives, this solution provides a processor debugging optimization method based on a soft breakpoint recovery mechanism. The main idea is to introduce a dedicated instruction insertion buffer and control registers (i.e., all registers mentioned below) within the processor, using hardware cooperation to save and execute the original instructions overwritten by breakpoint instructions. The specific technical solution includes the following aspects: 1) Instruction Insertion Buffer (corresponding to the aforementioned target buffer): A storage space is added inside the processor to store the original instructions, i.e., the "instruction insertion buffer." This buffer can be a high-speed on-chip memory unit or composed of several memory-mapped registers, used to temporarily store the original instruction code overwritten by soft breakpoint instructions. The purpose of setting up this internal buffer is that when the replaced original instructions need to be executed, the instruction content can be directly obtained from inside the processor without modifying external memory.

[0120] 2) Thread Selection Mask Register (corresponding to the aforementioned thread selection signal): A "thread selection mask register" is set up to identify the target thread affected by this instruction insertion mechanism. For systems supporting multiple hardware threads or multiple processor cores, this register is usually in bitmask form, with each bit corresponding to a thread ID; by setting the corresponding bits, one or more specified threads can be selected to enable the instruction insertion function. Threads not selected by the mask will not be affected by the instruction insertion mechanism when fetching instructions. This design ensures that in a multi-threaded environment, debuggers can accurately specify which thread executes the original inserted instruction, while other threads maintain their original execution behavior.

[0121] 3) Instruction Insertion Enable Signal (corresponding to the aforementioned Insertion Enable Signal): An "Instruction Insertion Enable Signal" (or control flag) is set to control whether the processor's instruction fetch unit enables the instruction insertion buffer. This signal can be set by the debugging software through the debug control interface. When this signal is active (enabled), the processor's instruction fetch unit will enter insertion mode: if the currently executing thread ID matches the thread selection mask mentioned above, subsequent instruction fetch operations will retrieve instructions from the instruction insertion buffer; otherwise, no response will be made (i.e., subsequent instruction fetch operations will still fetch instructions from the ICache or external memory according to the normal process). Through this enable signal, the debugging software can precisely control when the insertion buffer participates in the instruction fetching process.

[0122] Based on the newly added buffer and control mechanism, this solution makes the following improvements to the soft breakpoint recovery process: 1) When the program encounters a breakpoint instruction that triggers an exception, the thread pauses execution and enters debug mode. At this time, the memory content at the breakpoint address is the breakpoint instruction, and the thread has not yet executed the original instruction. The address PC that the thread will fetch next is the instruction following the breakpoint instruction.

[0123] 2) When the debugger wants to step through or continue executing the original instruction that is overwritten at the breakpoint, the debug software is configured as follows: (1) The debug software writes the original instruction at this breakpoint address into the instruction insertion buffer.

[0124] (2) The debugging software is configured in the thread selection mask register as the target thread for which one or more breakpoints have occurred.

[0125] (3) The debugging software sets the instruction insertion enable signal to be valid through the debugging interface.

[0126] (4) The debugging software issues a single-step execution instruction (corresponding to the aforementioned instruction fetch command) so that the processor executes only one instruction of code.

[0127] 3) During single-step execution, the processor's instruction fetch unit detects that insertion mode is enabled and the currently executing thread matches the mask condition. Therefore, instead of fetching instructions from conventional external memory such as ICache or DDR, it directly reads the pre-saved original instruction code from the instruction insertion buffer. This original instruction is then sent to the processor's instruction pipeline for execution. Thus, the processor actually executes the original instruction that should have been executed at the breakpoint address, without needing to modify the instruction content at that address in memory beforehand. At this point, the breakpoint address in memory still contains the breakpoint instruction, but it is ignored by the hardware logic during the instruction fetch stage.

[0128] 4) When fetching instructions via insert mode, the scheme requires the hardware to keep / not update the target thread's PC. That is, before and after inserting the original instruction, the thread's PC keeps pointing to the instruction following the original instruction.

[0129] 5) After the original instruction has been executed (single-step execution complete), the processor pauses again to wait for the next debug instruction. At this time, the instruction insertion enable signal needs to be reset (disabling the instruction insertion function). This instruction insertion enable signal reset can be designed to be automatically executed by hardware, that is, automatically cleared after the processor successfully fetches and executes an instruction insertion buffer instruction once, to ensure that the insertion operation only affects the intended instruction; or it can be designed to be manually cleared by the debugging software after single-step execution. Regardless of the method, the processor will return to normal instruction fetching mode after single-step execution is completed.

[0130] 6) At this point, the debugging software can continue to issue the corresponding continue or next command according to the instructions given by the debugging personnel in 2). The processor will resume normal program execution from the next instruction after the breakpoint address.

[0131] 7) Since the breakpoint instruction remains at the breakpoint address, if the program continues to run and reaches that address again, a breakpoint exception will still be triggered for user debugging until the breakpoint is removed (replacing the original instruction). This solution does not involve breakpoint addition and removal operations.

[0132] In summary, this solution implements a soft breakpoint recovery mechanism that eliminates the need for frequent rewriting of external memory code and refreshing of caches by adding an instruction insertion buffer and related control registers within the processor and modifying the debugging process. The entire breakpoint recovery and single-step execution process is primarily completed automatically by the processor hardware, significantly reducing the intervention and operation of debugging software, thereby lowering the probability of errors. Furthermore, since the execution of the original instructions is completed within the processor, multiple disturbances to the system memory and cache state are avoided, ensuring a relatively stable operating environment for the program being debugged.

[0133] For example, suppose there is a multi-threaded processor on which the target program has set a soft breakpoint at a certain address A, overriding the original instruction X1. At the same time, thread T has triggered the breakpoint, and the PC of thread T points to the next instruction X2 after X1. Assuming that the debugging environment allows only the target thread T to resume running (other threads do not perform any processing and execute normally or remain in a suspended state), the specific process is as follows: 1) Prepare for single-step execution: The debugger prepares to perform single-step operation on thread T to run the original instruction X1, and performs the following settings: (1) Set the instruction insertion enable signal to the active state; (2) Configure the Tth bit of the thread selection mask register to 1, and configure the other bits to 0; (3) Write the code of the original instruction X1 corresponding to address A into the instruction insertion buffer (the external memory address A is still the breakpoint instruction).

[0134] 2) Single-step instruction fetch and execution: The debugger issues a command to thread T to execute one instruction at a time. The processor responds to this command and resumes the execution of thread T, but only executes one instruction at a time. During the fetch phase, the processor detects that the current thread ID meets the mask and instruction insertion mode is enabled. Therefore, it does not fetch instructions from the ICache or external memory, but directly reads the code of instruction X1 from the internal instruction insertion buffer as the instruction to be executed. Because it is in insertion mode, thread T's PC does not advance and still points to instruction X2. Subsequently, the processor decodes and executes instruction X1 according to the normal instruction execution flow.

[0135] 3) Single-step completion: The processor successfully executes all operations of the original instruction X1 (e.g., updating registers and memory accordingly). This process is equivalent to the program actually executing the original instruction X1 at address A once. After execution, since the debugger only requires single-step execution of one instruction, thread T automatically pauses again, enters debug mode, and notifies the debugging software.

[0136] 4) Disable Instruction Insertion Mode and Restore Breakpoints: The debugging software confirms that the processor is paused and the original instruction X1 has been executed. At this point, the debugging software resets the instruction insertion enable signal to an invalid state, disabling insertion mode; the thread selection mask register can remain unchanged or be reset as needed. Since the breakpoint instruction was never removed, the soft breakpoint at address A remains valid.

[0137] 5) Resuming Thread Execution: When the debugging software issues a continue command, since instruction insertion mode is disabled, thread T will fetch and execute instructions according to its PC, that is, continue fetching and executing instructions from instruction X2, thereby resuming normal operation of subsequent programs. For other suspended threads, the debugging software can also choose to resume their execution, unaffected by thread T.

[0138] Therefore, this solution has the following beneficial effects: 1) Simplified debugging process: By utilizing the processor's built-in instruction insertion buffer and control mechanism, it is unnecessary to repeatedly rewrite the program instruction code in external memory during breakpoint single-step execution, nor is it necessary to enable / disable the cache every time. Many steps that were originally performed by the debugging software (such as instruction recovery, cache clearing, and resetting breakpoints) are replaced or omitted by hardware mechanisms, greatly simplifying the debugging process. The debugging software logic is simpler, the possibility of errors is significantly reduced, and the debugging operation is smoother and more reliable. This solution directly inserts the original instructions inside the processor, eliminating multiple steps such as instruction recovery and cache invalidation, greatly simplifying the breakpoint recovery process. Due to the reduction of manual operation steps that are strictly dependent on timing, the risk of debugging errors is significantly reduced, and the entire debugging process is more stable and reliable. This simplification is very important in complex debugging scenarios, improving the reliability of debugging work.

[0139] 2) Reduced System Interference: This solution does not modify the program's stored content or cache state when resuming single-step execution from breakpoints, minimizing intrusion into the system being debugged. Original instructions are executed through an internal buffer, and breakpoint instructions remain in their original memory locations. This avoids frequent memory writes and cache flushes that could damage the system state, minimizing the impact of debugging on the program under test. The program's code segment and cache maintain their original consistency, minimizing disturbances to system performance and timing during debugging, and helping to more realistically reflect program behavior. Simultaneously, this debugging process does not repeatedly disrupt the original layout of program instructions and cached content, avoiding interference with normal system behavior (performance, timing, etc.). Technically, this ensures the consistency of the debugged program's environment, making the debugging results more reliable.

[0140] 3) Fine-grained multi-threading control: Through the thread selection mask register mechanism, this solution enables single-step recovery from breakpoints on a specified thread in a multi-threaded environment. The execution of non-target threads will not be interfered with by the target thread's soft breakpoint recovery operation, improving the targeting of debugging operations. In contrast, existing solutions often require pausing all threads (to prevent them from executing the replaced original instructions and missing breakpoints) and then resuming them one by one, lacking flexibility. This solution allows debugging software to selectively control a particular thread to execute the original instructions from the buffer without interfering with the execution or debugging of other threads. This fine-grained control improves the efficiency and accuracy of multi-threaded debugging, enhancing the efficiency and accuracy of concurrent program debugging, and is particularly suitable for complex debugging tasks on multi-core, multi-threaded processors.

[0141] 4) Improved Debugging Efficiency: By eliminating the multiple memory read / write and cache refresh operations found in existing solutions, this approach significantly reduces the time overhead associated with breakpoint recovery and single-stepping. The processor inserts and executes raw instructions internally, at a much faster speed than existing methods that modify instructions by traveling back and forth between memory and the bus. Therefore, each single-step operation takes less time. This means developers can switch between breakpoint single-stepping and continue-running states more quickly, accelerating the overall debugging pace and improving efficiency. For debugging scenarios requiring frequent breakpoint setting / restoration, the advantages of this approach are even more pronounced. On one hand, reduced memory and bus operations make single-stepping faster; on the other hand, the simplified debugging software logic also shortens the waiting time for debugging instructions. In summary, this approach significantly improves the efficiency of breakpoint debugging, allowing developers to locate and analyze problems more quickly.

[0142] 5) This solution can be widely applied to various processors and is not specific to any particular architecture. It can be used with different CPU architectures or different GPU architectures.

[0143] Based on the above embodiments, this disclosure also provides a debugging device applied to the debugging side communicating with the processor. Figure 4 is a schematic diagram of the composition structure of a debugging device provided in this disclosure. As shown in Figure 4, the debugging device 40 includes a processing module 41, a configuration module 42, and a sending module 43, wherein: the processing module 41 is used to replace the original instruction at the target address of the target program with a breakpoint instruction, so that when the target program runs to the target address, the processor generates an exception to suspend the execution of the target program; the configuration module 42 is used to, in response to receiving a breakpoint recovery command, write the original instruction into the processor's target buffer and configure the insertion enable signal as a first enable signal, the insertion enable signal being used to indicate the processor's instruction fetch position, and the target buffer being used to store the original instruction at the target address of the inserted breakpoint instruction; the sending module 43 is used to send an instruction fetch command to the processor, so that the processor, in response to the instruction fetch command, obtains the insertion enable signal, and when the insertion enable signal is the first enable signal, retrieves and executes the original instruction from the target buffer; wherein, the first enable signal indicates that the processor fetches an instruction from the target buffer.

[0144] In some implementations, the processing module 41 is further configured to determine a target thread unit based on interrupt information sent by the processor or the current state of each thread unit; and configure a thread selection signal based on the target thread unit, wherein the thread selection signal is used to instruct the target thread unit to execute the original instruction.

[0145] In some implementations, the sending module 43 is further configured to send a reset command to the processor when it is determined that the original instruction has been executed, so that the processor sets the insertion enable signal to a second enable signal based on the reset command.

[0146] In some implementations, the sending module 43 is further configured to send a run command to the processor, so that the processor, in response to the run command, fetches the next instruction after the breakpoint instruction from memory based on the program counter of the target thread unit.

[0147] The description of the above apparatus embodiments is similar to that of the above method embodiments, and has similar beneficial effects. For technical details not disclosed in the apparatus embodiments of this disclosure, please refer to the description of the method embodiments of this disclosure for understanding.

[0148] It should be noted that, in the embodiments of this disclosure, if the above methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this disclosure, or the parts that contribute to related technologies, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this disclosure are not limited to any specific hardware and software combination.

[0149] This disclosure provides an electronic device, including a memory and a processor. The processor includes the aforementioned debugging device, or, when executing a computer program on the memory, implements any of the aforementioned debugging methods. This electronic device can be various types of terminals such as laptops, tablets, desktop computers, set-top boxes, and mobile devices (e.g., mobile phones, portable music players, personal digital assistants, dedicated messaging devices, portable gaming devices), or it can be implemented as a server. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0150] This disclosure provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements any of the debugging methods described above. The computer-readable storage medium can be transient or non-transient.

[0151] This disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in any of the debugging methods described above. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0152] It should be noted that Figure 5 is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of this disclosure. As shown in Figure 5, the hardware entity of the electronic device 500 includes: a processor 501, a communication interface 502, and a memory 503, wherein: the processor 501 typically controls the overall operation of the electronic device 500.

[0153] Communication interface 502 enables electronic devices to communicate with other terminals or servers via a network.

[0154] The memory 503 is configured to store instructions and applications executable by the processor 501, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 501 and various modules in the electronic device 500. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 501, the communication interface 502, and the memory 503 can be performed via bus 504.

[0155] It should be noted that the descriptions of the storage medium and device embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0156] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specified feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specified features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0157] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0158] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0159] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0160] In addition, each functional unit in the embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0161] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0162] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0163] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A debugging method, characterized in that, The debugging method, applied to a processor, includes: acquiring an insertion enable signal, the insertion enable signal indicating the instruction fetch location of the processor; when the insertion enable signal is a first enable signal, retrieving the original instruction from the processor's target buffer and executing the original instruction; wherein the first enable signal indicates that the processor fetches an instruction from the target buffer, the target buffer being used to store the original instruction at the target address of the inserted breakpoint instruction.

2. The debugging method according to claim 1, characterized in that, The step of acquiring the insertion enable signal includes: acquiring the insertion enable signal in response to receiving an instruction fetch command; the step of retrieving the original instruction from the processor's target buffer includes: acquiring a thread selection signal, and retrieving the original instruction from the target buffer if the thread selection signal matches the identifier of the target thread unit included in the instruction fetch command.

3. The debugging method according to claim 2, characterized in that, Executing the original instruction includes: switching the state of the target thread unit to a running state, so that the target thread unit executes the original instruction step by step; wherein, the program counter of the target thread unit continues to point to the instruction following the breakpoint instruction.

4. The debugging method according to claim 3, characterized in that, After the target thread unit has executed the original instruction, the debugging method further includes: switching the state of the target thread unit to a paused state.

5. The debugging method according to any one of claims 1 to 4, characterized in that, The debugging method further includes: setting the insertion enable signal to a second enable signal after the original instruction has been executed or in response to receiving a reset command; wherein the second enable signal indicates that the processor fetches an instruction from memory.

6. The debugging method according to claim 5, characterized in that, The debugging method further includes: in response to receiving a run command, retrieving the next instruction after the breakpoint instruction from the memory based on the program counter of the target thread unit.

7. The debugging method according to any one of claims 1 to 6, characterized in that, The debugging method further includes: fetching instructions from memory when the insertion enable signal is the second enable signal.

8. A debugging method, characterized in that, include: The original instruction at the target address of the target program is replaced with a breakpoint instruction, so that when the target program runs to the target address, the processor generates an exception to suspend the execution of the target program; in response to receiving a breakpoint recovery command, the original instruction is written to the processor's target buffer and an insertion enable signal is configured as a first enable signal, the insertion enable signal indicating the processor's instruction fetch position, and the target buffer storing the original instruction at the target address where the breakpoint instruction is inserted; an instruction fetch command is sent to the processor, so that the processor receives the insertion enable signal in response to the instruction fetch command, and when the insertion enable signal is the first enable signal, fetches and executes the original instruction from the target buffer; wherein, the first enable signal indicates that the processor fetches an instruction from the target buffer.

9. The debugging method according to claim 8, characterized in that, The debugging method further includes: determining a target thread unit based on interrupt information sent by the processor or the current state of each thread unit; and configuring a thread selection signal based on the target thread unit, wherein the thread selection signal is used to instruct the target thread unit to execute the original instruction.

10. The debugging method according to claim 8 or 9, characterized in that, The debugging method further includes: when it is determined that the original instruction has been executed, sending a reset command to the processor, so that the processor sets the insertion enable signal to a second enable signal based on the reset command.

11. A debugging device, characterized in that, The debugging device, applied in a processor, includes an execution unit and a target buffer, wherein: the target buffer is used to store the original instruction at the target address where the breakpoint instruction is inserted; the execution unit is used to acquire an insertion enable signal, which indicates the instruction fetch position of the processor; when the insertion enable signal is a first enable signal, the original instruction is fetched from the target buffer and executed; wherein the first enable signal indicates that the processor fetches an instruction from the target buffer.

12. A debugging device, characterized in that, include: A processing module is used to replace the original instruction at the target address of the target program with a breakpoint instruction, so that when the target program runs to the target address, the processor generates an exception to suspend the execution of the target program; a configuration module is used to, in response to receiving a breakpoint recovery command, write the original instruction into the processor's target buffer and configure an insertion enable signal as a first enable signal, wherein the insertion enable signal is used to indicate the processor's instruction fetch position, and the target buffer is used to store the original instruction at the target address where the breakpoint instruction is inserted; A sending module is configured to send an instruction fetch command to the processor, such that the processor responds to the instruction fetch command by acquiring an insertion enable signal, and, if the insertion enable signal is a first enable signal, fetches and executes the original instruction from the target buffer; wherein the first enable signal indicates that the processor fetches an instruction from the target buffer.

13. An electronic device, characterized in that, It includes a memory and a processor, wherein: the processor includes the debugging apparatus of claim 12 above, or, when executing a computer program on the memory, implements the debugging method of any one of claims 8 to 10 above.

14. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the debugging method described in any one of claims 8 to 10.

15. A computer program product, the computer program product comprising a non-transitory computer-readable storage medium storing a computer program, characterized in that, When the computer program is read and executed by the computer, it implements the debugging method described in any one of claims 8 to 10.

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