Automatic addressing circuit, automatic addressing method and battery management system

Abstract

The invention belongs to the technical field of battery management, and provides an automatic addressing circuit, an automatic addressing method and a battery management system. The automatic addressing circuit comprises a master control module and n slave control modules, each of the master control module and the slave control modules comprises two input and output interfaces, and the two input and output interfaces of the master control module are respectively connected with any input and output interface of the first slave control module and any input and output interface of the nth slave control module. Any input and output interfaces of the adjacent slave control modules are connected, the communication interface of the master control module and the communication interfaces of the n slave control modules are mounted on the same communication bus, and n is a natural number greater than or equal to 2. According to the automatic addressing circuit, automatic addressing of all the slave control modules is achieved through bidirectional input and output control and the communication bus, and meanwhile the automatic addressing circuit can achieve automatic addressing when the number of the slave control modules is changed, a fault module is replaced or the installation sequence is changed.

Description

Technical Field

[0001] This application belongs to the field of battery management technology, and in particular relates to an automatic addressing circuit, an automatic addressing method and a battery management system. Background Technology

[0002] In commercial and industrial applications, a Battery Management System (BMS) typically consists of a master control board and multiple slave control boards. The master control board accesses these slave control boards via a communication bus to obtain information, but it needs to know the address information of each slave control board. Therefore, all slave control boards must be addressed beforehand to ensure that the desired slave control board is accurately located during access.

[0003] Current addressing schemes are typically implemented in hardware, such as using DIP switches. However, this approach requires pre-setting each slave control board via DIP switches and managing these preset values, impacting installation and debugging efficiency. Furthermore, changes in the number of slave control boards, replacement of faulty boards, or alteration of the installation order necessitate manual address resetting and corresponding software adaptations, increasing maintenance costs. These low installation and debugging efficiency and high maintenance costs result in poor maintainability for current addressing schemes. Summary of the Invention

[0004] This application provides an automatic addressing circuit, an automatic addressing method, and a battery management system, which can solve the problem of poor maintainability in current addressing schemes.

[0005] In a first aspect, embodiments of this application provide an automatic addressing circuit, including a master control module and n slave control modules. Each of the master control module and the slave control modules includes two input / output interfaces. The two input / output interfaces of the master control module are respectively connected to any input / output interface of the first slave control module and any input / output interface of the nth slave control module. The arbitrary input / output interfaces of adjacent slave control modules are connected. The communication interface of the master control module and the communication interfaces of the n slave control modules are mounted on the same communication bus, where n is a natural number greater than or equal to 2.

[0006] The master control module is used to change the level signal of any of its input / output interfaces and output a first detection command and address offset to each slave control module through the communication bus, so that each slave control module detects the level signals of its two input / output interfaces according to the first detection command; when a slave control module detects that the level signals of its two input / output interfaces are different, the slave control module is used to address according to the address offset and the initial address, then change the level signal of the input / output interface connected to the next level slave control module, and output a first feedback signal to the master control module; the master control module is also used to decrement the address offset by 1 each time it receives the first feedback signal, and output the first detection command and address offset to each slave control module again, until the address offset becomes 0; wherein, the initial value of the address offset is n; the initial address of each slave control module is the same.

[0007] In one possible implementation of the first aspect, the master control module is further configured to change the level signal of any of its input / output interfaces and output a second detection command to each slave control module via a communication bus, so that each slave control module detects the level signals of its two input / output interfaces according to the second detection command; when a slave control module detects that the level signals of its two input / output interfaces are different, the slave control module is configured to change the level signal of the input / output interface connected to the next-level slave control module and output a second feedback signal to the master control module; the master control module is further configured to increment a first variable by 1 each time it receives the second feedback signal and output the second detection command to each slave control module again until it no longer receives the second feedback signal within a preset time, and determine that the value stored in the first variable is the number of slave control modules.

[0008] In one possible implementation of the first aspect, the main control module includes a main control unit, a first signal conversion unit, and a second signal conversion unit. A first input / output interface of the main control unit is connected to a first terminal of the first signal conversion unit. A second input / output interface of the main control unit is connected to a second terminal of the first signal conversion unit. A third terminal of the first signal conversion unit serves as one input / output interface of the main control module. A third input / output interface of the main control unit is connected to a first terminal of the second signal conversion unit. A fourth input / output interface of the main control unit is connected to a second terminal of the second signal conversion unit. A third terminal of the second signal conversion unit serves as another input / output interface of the main control module. The communication interface of the main control unit is connected to the communication interfaces of n slave control modules via a communication bus.

[0009] The master control unit is configured to set its first and third input / output interfaces as output interfaces, and its second and fourth input / output interfaces as input interfaces. The master control unit is also configured to change the level signal of any of its output interfaces, thereby changing the level signal of any of the master control module's input / output interfaces. The master control unit is also configured to output a first detection command and an address offset to each slave control module via a communication bus. The master control unit is also configured to, upon receiving the first feedback signal each time, decrement the address offset by 1 and output the first detection command and address offset to each slave control module again, until the address offset becomes 0. The first signal conversion unit is configured to perform level signal conversion. The second signal conversion unit is configured to perform level signal conversion.

[0010] In one possible implementation of the first aspect, the master control unit includes a first microcontroller, a first input / output interface of the first microcontroller connected to a first end of the first signal conversion unit, a second input / output interface of the first microcontroller connected to a second end of the first signal conversion unit, a third input / output interface of the first microcontroller connected to a first end of the second signal conversion unit, a fourth input / output interface of the first microcontroller connected to a second end of the second signal conversion unit, and a communication interface of the first microcontroller connected to the communication interfaces of n slave control modules via a communication bus.

[0011] In one possible implementation of the first aspect, the slave control module includes a slave control unit, a third signal conversion unit, and a fourth signal conversion unit. The first input / output interface of the slave control unit is connected to the first end of the third signal conversion unit, the second input / output interface of the slave control unit is connected to the second end of the third signal conversion unit, the third end of the third signal conversion unit serves as one input / output interface of the slave control module, the third input / output interface of the slave control unit is connected to the first end of the fourth signal conversion unit, the fourth input / output interface of the slave control unit is connected to the second end of the fourth signal conversion unit, the third end of the fourth signal conversion unit serves as another input / output interface of the slave control module, and the communication interface of the slave control unit is connected to the communication interface of the master control module via a communication bus.

[0012] The slave control unit is configured to set its first and third input / output interfaces as output interfaces, and its second and fourth input / output interfaces as input interfaces. The slave control unit is also configured to detect the level signals of its two input interfaces according to the first detection instruction; when the level signals of its two input interfaces are detected to be different, it performs addressing according to the address offset and the initial address, then changes the level signal of its output interface, thereby changing the level signal of the input / output interface connected to the next-level slave control module, and outputs a first feedback signal to the master control module. The third signal conversion unit is configured to perform level signal conversion; the fourth signal conversion unit is configured to perform level signal conversion.

[0013] In one possible implementation of the first aspect, the slave control unit includes a second microcontroller, a first input / output interface of the second microcontroller connected to a first terminal of the third signal conversion unit, a second input / output interface of the second microcontroller connected to a second terminal of the third signal conversion unit, a third input / output interface of the second microcontroller connected to a first terminal of the fourth signal conversion unit, a fourth input / output interface of the second microcontroller connected to a second terminal of the fourth signal conversion unit, and a communication interface of the second microcontroller connected to the communication interface of the master control module via a communication bus.

[0014] Secondly, embodiments of this application provide an automatic addressing method, based on the automatic addressing circuit described in any one of the first aspects, comprising:

[0015] The master control module obtains the number of slave control modules;

[0016] The master control module changes the level signal of any of its input / output interfaces and outputs a first detection command and an address offset to each slave control module through the communication bus, so that each slave control module detects the level signals of its two input / output interfaces according to the first detection command; wherein, the initial value of the address offset is the number of slave control modules;

[0017] When the slave control module detects that the level signals of its two input / output interfaces are different, the slave control module performs addressing according to the address offset and the initial address, then changes the level signal of the input / output interface connected to the next level slave control module, and outputs a first feedback signal to the master control module; wherein, the initial address of each slave control module is the same;

[0018] The main control module also reduces the address offset by 1 each time it receives the first feedback signal, and outputs the first detection command and address offset to each slave control module again, until the address offset becomes 0.

[0019] The master control module also outputs latch instructions to each slave control module through the communication bus, so that each slave control module latches its address according to the latch instructions.

[0020] In one possible implementation of the second aspect, the master control module obtains the number of slave control modules, including:

[0021] The master control module changes the level signal of any of its input and output interfaces and outputs a second detection command to each slave control module through the communication bus, so that each slave control module detects the level signals of its two input and output interfaces according to the second detection command.

[0022] When the slave control module detects that the level signals of the two input / output interfaces are different, the slave control module changes the level signal of the input / output interface connected to the next-level slave control module and outputs a second feedback signal to the master control module;

[0023] The master control module also increments the first variable by 1 each time it receives the second feedback signal, and outputs the second detection command to each slave control module again, until it no longer receives the second feedback signal within a preset time, and determines that the value stored in the first variable is the number of slave control modules.

[0024] In one possible implementation of the second aspect, after the master control module obtains the number of slave control modules, the following is included:

[0025] The master control module resets the level signals of its two input / output interfaces and outputs a reset command to each slave control module via the communication bus, so that each slave control module resets the level signals of its two input / output interfaces according to the reset command.

[0026] Thirdly, embodiments of this application provide a battery management system, including the automatic addressing circuit described in any one of the first aspects.

[0027] The beneficial effects of the embodiments in this application compared with the prior art are:

[0028] This application provides an automatic addressing circuit, including a master control module and n slave control modules. Both the master control module and the slave control modules include two input / output interfaces. The two input / output interfaces of the master control module are respectively connected to any input / output interface of the first slave control module and any input / output interface of the nth slave control module. The arbitrary input / output interfaces of adjacent slave control modules are connected. The communication interface of the master control module and the communication interfaces of the n slave control modules are connected on the same communication bus, where n is a natural number greater than or equal to 2.

[0029] The master control module is used to change the level signals of any of its input / output interfaces and outputs a first detection command and address offset to each slave control module via the communication bus, enabling each slave control module to detect the level signals of its two input / output interfaces according to the first detection command. When a slave control module detects that the level signals of its two input / output interfaces are different, the slave control module performs addressing based on the address offset and the initial address, then changes the level signals of the input / output interfaces connected to the next-level slave control module, and outputs a first feedback signal to the master control module. The master control module also decrements the address offset by 1 each time it receives the first feedback signal, and outputs the first detection command and address offset to each slave control module again, until the address offset becomes 0. The initial value of the address offset is n; the initial address is the same for each slave control module.

[0030] The automatic addressing circuit provided in this application embodiment uses a bidirectional input / output control and communication bus to achieve automatic addressing of all slave control modules. Compared with the current addressing scheme, it eliminates the need for presetting each slave control board or managing preset values, thus improving installation and debugging efficiency. Furthermore, the automatic addressing circuit provided in this application embodiment can automatically address modules even when the number of slave control modules changes, faulty modules are replaced, or the installation order changes. Compared with the current addressing scheme, it eliminates the need for manual address resetting or software changes, reducing maintenance costs. Therefore, the automatic addressing circuit provided in this application embodiment has the advantages of high installation and debugging efficiency and low maintenance costs. Because of these advantages, the automatic addressing circuit provided in this application embodiment also has the advantage of good maintainability.

[0031] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic block diagram of an automatic addressing circuit provided in an embodiment of this application;

[0034] Figure 2 This is a schematic block diagram of an automatic addressing circuit provided in another embodiment of this application;

[0035] Figure 3This is a schematic block diagram of an automatic addressing circuit provided in another embodiment of this application;

[0036] Figure 4 This is a flowchart of an automatic addressing method provided in an embodiment of this application;

[0037] Figure 5 This is a flowchart of an automatic addressing method provided in another embodiment of this application.

[0038] In the diagram: 10, main control module; 11, main control unit; 111, first microcontroller; 12, first signal conversion unit; 13, second signal conversion unit; 20, slave control module; 21, slave control unit; 211, second microcontroller; 22, third signal conversion unit; 23, fourth signal conversion unit. Detailed Implementation

[0039] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0040] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0041] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0042] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0043] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0044] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0045] Current addressing schemes typically employ hardware implementation, such as using DIP switches. Each slave control board is assigned a different encoding combination to distinguish its address. A communication bus connects the master control board and each slave control board serially. The master control board receives data through this communication bus and manages the data of each slave control board using the address information contained within. However, this encoding scheme requires pre-setting each slave control board using DIP switches and managing the preset values, impacting installation and debugging efficiency. Furthermore, changes in the number of slave control boards, replacement of faulty boards, or changes in the installation order necessitate manual address resetting and corresponding software adaptation, increasing maintenance costs. These low installation and debugging efficiency and high maintenance costs result in poor maintainability for this addressing scheme.

[0046] Another current addressing scheme uses pulse width modulation (PWM) signals to transmit address information. The master control board, starting with the slave control boards connected to it, sequentially connects the PWM signal lines of other slave control boards in series, thus preseting the address. The master control board and all slave control boards are connected to a CAN communication bus. The master control board sends PWM signals with a preset duty cycle to the connected slave control boards. Each slave control board sets its own coded address based on the duty cycle contained in the received PWM signal. Furthermore, each slave control board increases the duty cycle in the received PWM signal by a preset step value and then sends the PWM signal with the preset step value to the slave control boards connected in series. However, this addressing scheme uses PWM signals to transmit address information, requiring encoding and decoding of the information, resulting in a large software processing workload; moreover, PWM signals are susceptible to electromagnetic interference, leading to information transmission errors.

[0047] To address the above problems, embodiments of this application provide an automatic addressing circuit, such as... Figure 1As shown, the system includes a master control module 10 and n slave control modules 20. Both the master control module 10 and the slave control modules 20 include two input / output interfaces (IO). The two input / output interfaces (IO) of the master control module 10 are connected to any input / output interface (IO) of the first slave control module 20 and any input / output interface (IO) of the nth slave control module 20, respectively. The arbitrary input / output interfaces (IO) of adjacent slave control modules 20 are connected. The communication interface of the master control module 10 and the communication interfaces of the n slave control modules 20 are mounted on the same CAN communication bus, where n is a natural number greater than or equal to 2.

[0048] Specifically, the master control module 10 is used to change the level signal of any of its input / output interfaces (IOs), and outputs a first detection command and address offset to each slave control module 20 via the CAN communication bus, so that each slave control module 20 detects the level signals of its two input / output interfaces (IOs) according to the first detection command. It should be noted that the master control module 10 can change the level signal of any of its input / output interfaces (IOs). When the master control module 10 changes the level signal of the input / output interface (IO) connected to the first slave control module, the addressing path starts from the first slave control module; when the master control module 10 changes the level signal of the input / output interface (IO) connected to the nth slave control module, the addressing path starts from the nth slave control module.

[0049] When the slave control module 20 detects that the level signals of its two input / output interfaces (IOs) are different, the slave control module 20 performs addressing based on the address offset and the initial address, then changes the level signal of the input / output interface (IO) connected to the next-level slave control module 20, and outputs a first feedback signal to the master control module 10. The master control module 10 further decrements the address offset by 1 each time it receives the first feedback signal, and outputs a first detection command and the address offset to each slave control module 20 again, until the address offset becomes 0. The initial value of the address offset is n; the initial address of each slave control module 20 is the same.

[0050] The automatic addressing circuit provided in this embodiment uses bidirectional I / O control and a CAN communication bus to automatically address all slave control modules 20. Compared to current addressing schemes, it eliminates the need for presetting each slave control board or managing preset values, thus improving installation and debugging efficiency. Furthermore, the automatic addressing circuit provided in this embodiment can automatically address modules even when the number of slave control modules 20 changes, faulty modules are replaced, or the installation order changes. Compared to current addressing schemes, it eliminates the need for manual address resetting and software changes, reducing maintenance costs. Therefore, the automatic addressing circuit provided in this embodiment has the advantages of high installation and debugging efficiency and low maintenance costs. Because of these advantages, the automatic addressing circuit provided in this embodiment also has the advantage of good maintainability.

[0051] Meanwhile, compared with the scheme of addressing using pulse width modulation signals, the automatic addressing circuit provided in this application directly uses level signals for addressing, without the need for decoding and encoding, which simplifies the software process; the level signals in this application have stronger anti-electromagnetic interference capabilities than pulse width modulation signals; and the automatic addressing circuit provided in this application supports addressing paths in two directions, so that if one addressing path fails, addressing can still be completed through the other addressing path.

[0052] In some embodiments, when performing automatic addressing, this application needs to first obtain the number of slave control modules 20, because the initial value of the address offset is the number of slave control modules 20. There are two methods to obtain the number of slave control modules 20: one method is to manually write the number of slave control modules 20 into the master control module 10 through a human-machine interface; the other method is for the master control module 10 to automatically detect the number of slave control modules 20. Specifically, the process of automatically obtaining the number of slave control modules 20 is as follows: the master control module 10 changes the level signal of any of its input / output interfaces (IOs) and outputs a second detection command to each slave control module 20 via the CAN communication bus, causing each slave control module 20 to detect the level signals of its two input / output interfaces (IOs) according to the second detection command. When a slave control module 20 detects that the level signals of its two input / output interfaces (IOs) are different, the slave control module 20 changes the level signal of the input / output interface (IO) connected to the next-level slave control module 20 and outputs a second feedback signal to the master control module 10. The main control module 10 is also used to increment the first variable by 1 each time a second feedback signal is received, and to output a second detection command to each slave control module 20 again, until no more second feedback signals are received within a preset time, and to determine that the value stored in the first variable is the number of slave control modules 20.

[0053] In some embodiments, the main control module 10 includes a main control unit 11, a first signal conversion unit 12, and a second signal conversion unit 13. The first input / output interface IO1 of the main control unit 11 is connected to the first end of the first signal conversion unit 12, the second input / output interface IO2 of the main control unit 11 is connected to the second end of the first signal conversion unit 12, the third end of the first signal conversion unit 12 serves as one input / output interface IO of the main control module 10, the third input / output interface IO3 of the main control unit 11 is connected to the first end of the second signal conversion unit 13, the fourth input / output interface IO4 of the main control unit 11 is connected to the second end of the second signal conversion unit 13, and the third end of the second signal conversion unit 13 serves as another input / output interface IO of the main control module 10. The communication interface of the main control unit 11 is connected to the communication interfaces of n slave control modules 20 via a CAN communication bus.

[0054] Specifically, the master control unit 11 is configured as output interfaces for its first input / output interface IO1 and third input / output interface IO3, and as input interfaces for its second input / output interface IO2 and fourth input / output interface IO4. The master control unit 11 is also configured to change the level signal of any of its output interfaces, thereby changing the level signal of any input / output interface IO of the master control module 10. The master control unit 11 is also configured to output a first detection command and address offset to each slave control module 20 via the CAN communication bus. The master control unit 11 is also configured to decrease the address offset by 1 each time it receives a first feedback signal, and then output the first detection command and address offset to each slave control module 20 again, until the address offset becomes 0. The first signal conversion unit 12 is used to implement level signal conversion. The second signal conversion unit 13 is used to implement level signal conversion.

[0055] More specifically, the first input / output interface IO1 and the third input / output interface IO3 of the main control unit 11 are configured as output interfaces. By default, both the first input / output interface IO1 and the third input / output interface IO3 of the main control unit 11 output low-level signals. These two low-level signals are converted into high-level signals by the first signal conversion unit 12 and the second signal conversion unit 13, respectively. That is, by default, both input / output interfaces IO of the main control module 10 output high-level signals. It should be noted that the high-level signals output by the two input / output interfaces IO of the main control module 10 can be 24V level signals, which ensures that the signal is not easily interfered with during transmission.

[0056] When the main control module 10 changes the level signal of any of its input / output interfaces (IO), the main control unit 11 only needs to change the level signal of any of its output interfaces. That is, the main control unit 11 changes the low-level signal of any output interface to a high-level signal, and the high-level signal is converted to a low-level signal after passing through the signal conversion unit. Therefore, when the main control module 10 changes the level signal of any of its input / output interfaces (IO), it essentially changes the high-level signal of any of its input / output interfaces (IO) to a low-level signal.

[0057] It should be noted that when both input / output interfaces (IO) of the main control module 10 receive low-level signals, the first signal conversion unit 12 and the second signal conversion unit 13 convert the low-level signals and output low-level signals to the two input interfaces of the main control unit 11 respectively. When both input / output interfaces (IO) of the main control module 10 receive high-level signals, the first signal conversion unit 12 and the second signal conversion unit 13 convert the high-level signals and output high-level signals (e.g., 3.3V) that conform to the main control unit 11 to the two input interfaces of the main control unit 11 respectively.

[0058] Both the first signal conversion unit 12 and the second signal conversion unit 13 have self-testing functions. They convert their output signals and feed them back to the main control unit 11. The main control unit 11 can determine whether the first signal conversion unit 12 and the second signal conversion unit 13 are functioning correctly based on the feedback signals. For example, in the default state, the first input / output interface IO1 of the main control unit 11 outputs a low-level signal. After conversion by the first signal conversion unit 12, it outputs a high-level signal. Since the first signal conversion unit 12 has a self-testing function, it will also convert this high-level signal and output a high-level signal (e.g., a 3.3V level signal) that conforms to the main control unit 11 to the second input / output interface IO2 of the main control unit 11.

[0059] This application does not limit the specific structure of the first signal conversion unit 12 and the second signal conversion unit 13, as long as they can achieve their functions in this application.

[0060] For example, such as Figure 3As shown, the main control unit 11 includes a first microcontroller 111. The first input / output interface IO1 of the first microcontroller 111 is connected to the first end of the first signal conversion unit 12. The second input / output interface IO2 of the first microcontroller 111 is connected to the second end of the first signal conversion unit 12. The third input / output interface IO3 of the first microcontroller 111 is connected to the first end of the second signal conversion unit 13. The fourth input / output interface IO4 of the first microcontroller 111 is connected to the second end of the second signal conversion unit 13. The communication interface of the first microcontroller 111 is connected to the communication interfaces of n slave control modules 20 through a CAN communication bus.

[0061] In some embodiments, such as Figure 2 As shown, the slave control module 20 includes a slave control unit 21, a third signal conversion unit 22, and a fourth signal conversion unit 23. The first input / output interface IO1 of the slave control unit 21 is connected to the first end of the third signal conversion unit 22, the second input / output interface IO2 of the slave control unit 21 is connected to the second end of the third signal conversion unit 22, the third end of the third signal conversion unit 22 serves as one input / output interface IO of the slave control module 20, the third input / output interface IO3 of the slave control unit 21 is connected to the first end of the fourth signal conversion unit 23, the fourth input / output interface IO4 of the slave control unit 21 is connected to the second end of the fourth signal conversion unit 23, the third end of the fourth signal conversion unit 23 serves as another input / output interface IO of the slave control module 20, and the communication interface of the slave control unit 21 is connected to the communication interface of the master control module 10 through a CAN communication bus.

[0062] Specifically, the slave control unit 21 is used to set its first input / output interface IO1 and third input / output interface IO3 as output interfaces, and its second input / output interface IO2 and fourth input / output interface IO4 as input interfaces. The slave control unit 21 is also used to detect the level signals of its two input interfaces according to a first detection instruction. When the level signals of its two input interfaces are detected to be different, it performs addressing based on the address offset and the initial address, then changes the level signal of its output interface, thereby changing the level signal of the input / output interface IO connected to the next-level slave control module 20, and outputs a first feedback signal to the master control module 10. The third signal conversion unit 22 is used to implement level signal conversion. The fourth signal conversion unit 23 is used to implement level signal conversion.

[0063] More specifically, the first input / output interface IO1 and the third input / output interface IO3 of the slave control unit 21 are set as output interfaces. By default, both the first input / output interface IO1 and the third input / output interface IO3 of the slave control unit 21 output low-level signals. After being converted by the third signal conversion unit 22 and the fourth signal conversion unit 23, these two low-level signals are converted into high-level signals. That is, by default, both input / output interfaces IO of the slave control module 20 output high-level signals.

[0064] Both the third signal conversion unit 22 and the fourth signal conversion unit 23 have self-test functions. They convert their output signals and feed them back to the slave control unit 11. The slave control unit 11 can determine whether the third signal conversion unit 22 and the fourth signal conversion unit 23 are functioning correctly based on the feedback signals. Since, by default, both input / output interfaces (IO) of the slave control module 20 output high-level signals, the third signal conversion unit 22 converts the high-level signals and outputs a high-level signal (e.g., a 3.3V level signal) conforming to the slave control unit 11 to one input interface (second input / output interface IO2). The fourth signal conversion unit 23 converts the high-level signals and outputs a high-level signal (e.g., a 3.3V level signal) conforming to the slave control unit 11 to the other input interface (fourth input / output interface IO4). Therefore, by default, the level signals of both input interfaces (i.e., second input / output interface IO2 and fourth input / output interface IO4) of the slave control unit 21 are high-level signals. As can be seen from the above, the level signals at the two input / output interfaces (IO) of the slave control module 20 before addressing begins are both high-level signals.

[0065] When the master control module 10 changes the level signal of an input / output interface IO, that is, the input / output interface IO of the master control module 10 outputs a low-level signal, the input / output interface IO of the slave control module 20 connected to the master control module 10 receives the low-level signal, the third signal conversion unit 22 inside the slave control module 20 will convert the low-level signal and output a low-level signal to an input interface (second input / output interface IO2) of the slave control unit 21.

[0066] When the slave control unit 21 detects that the level signals of the two input interfaces change to a high level signal and a low level signal (i.e., the level signal at the second input / output interface IO2 is a low level signal, and the level signal at the fourth input / output interface IO4 remains a high level signal), the slave control unit 21 can perform addressing according to the address offset and the initial address, and output a feedback signal to the master control module 10. At the same time, it changes the level state of another unchanged input / output interface IO (i.e., the input / output interface IO connected to the next-level slave control module 20). That is, the slave control unit 21 changes the level signal of the output interface (i.e., the third input / output interface IO3) to a high level signal. After being converted by the fourth signal conversion unit 23, the high level signal becomes a low level signal, that is, the input / output interface IO connected to the next-level slave control module 20 outputs a low level signal. As can be seen from the above, after the addressing is completed, the level signals at both input / output interface IOs of the slave control module 20 become low level signals.

[0067] When the input / output interface IO connected to the next-level slave control module 20 outputs a low-level signal, the fourth signal conversion unit 23 will convert the low-level signal and output a low-level signal to another input interface of the slave control unit 21 (i.e., the fourth input / output interface IO4). That is, after the addressing is completed, both input interfaces of the slave control unit 21 will also become low-level signals.

[0068] It should be noted that the specific structure of the third signal conversion unit 22 and the fourth signal conversion unit 23 is not limited in this application, as long as they can achieve their functions in this application.

[0069] For example, such as Figure 3 As shown, the slave control unit 21 includes a second microcontroller 211. The first input / output interface IO1 of the second microcontroller 211 is connected to the first end of the third signal conversion unit 22. The second input / output interface IO2 of the second microcontroller 211 is connected to the second end of the third signal conversion unit 22. The third input / output interface IO3 of the second microcontroller 211 is connected to the first end of the fourth signal conversion unit 23. The fourth input / output interface IO4 of the second microcontroller 211 is connected to the second end of the fourth signal conversion unit 23. The communication interface of the second microcontroller 211 is connected to the communication interface of the master control module 10 through a CAN communication bus.

[0070] In summary, the automatic addressing circuit provided in this application uses two bidirectional I / Os and a communication bus to complete the automatic addressing of all slave control modules 20. Not only is the hardware circuit simple, but the software control logic is also simple, saving development, debugging, and installation costs and shortening the development cycle. Furthermore, this application also supports addressing paths in two directions. If one addressing path fails, addressing can still be completed through the other addressing path.

[0071] This application also provides an automatic addressing method based on the automatic addressing circuit described above, such as... Figure 4 As shown, the automatic addressing method includes steps S401-S405.

[0072] S401, The master control module obtains the number of slave control modules.

[0073] Specifically, in this application, the master control module needs to know the number of slave control modules before addressing, so that the master control module can confirm the number of slave control module addresses. This number will be used in the automatic addressing process.

[0074] For example, the number of slave modules can be manually written into the master module through a human-computer interaction interface.

[0075] S402, the master control module changes the level signal of any of its input / output interfaces (IO), and outputs a first detection command and address offset to each slave control module through the communication bus, so that each slave control module detects the level signals of its two input / output interfaces (IO) according to the first detection command; wherein, the initial value of the address offset is the number of slave control modules.

[0076] Specifically, the master control module can change the level signal of one of its input / output interfaces (IO) by changing the level signal of one of its input / output interfaces (IO). Then, it outputs a first detection command and address offset to all slave control modules through the CAN communication bus, so that each slave control module can detect the level signals of its two input / output interfaces (IO) according to the first detection command.

[0077] S403. When the slave control module detects that the level signals of its two input / output interfaces (IO) are different, the slave control module performs addressing according to the address offset and the initial address, then changes the level signal of the input / output interface (IO) connected to the next-level slave control module, and outputs the first feedback signal to the master control module; wherein, the initial address of each slave control module is the same.

[0078] Specifically, by default, the input / output (IO) interface levels of the slave module are identical and both are high. When the slave module detects that the IO levels of its two IO interfaces are different, it adds an address offset to the initial address, then changes the IO level of the input / output interface connected to the next-level slave module, causing the next-level slave module to enter the addressing state. The next-level slave module then outputs a first feedback signal to the master module, informing it that the slave module has completed addressing.

[0079] S404. Each time the master control module receives the first feedback signal, it reduces the address offset by 1 and outputs the first detection command and address offset to each slave control module again until the address offset becomes 0.

[0080] Specifically, since addressing all slave modules involves a repetitive process, the master module, upon receiving the first feedback signal, decrements the address offset by 1 and outputs the first detection command and the updated address offset to each slave module again. This causes each slave module to re-detect the level signals of its two input / output interface (IO) ports according to the first detection command. When a slave module detects that the level signals of its two IO ports are different, it adds the updated address offset to its initial address, then changes the level signals of the IO ports connected to the next-level slave module, causing the next-level slave module to enter the addressing state and outputs the first feedback signal to the master module, informing it that the slave module has completed addressing. This entire addressing process is repeated multiple times until the address offset becomes 0.

[0081] S405 The master control module also outputs latch instructions to each slave control module through the communication bus, so that each slave control module latches its address according to the latch instructions.

[0082] Specifically, after all slave control modules have completed addressing, the master control module will also output latch instructions to each slave control module through the CAN communication bus, so that each slave control module latches its address according to the latch instructions, and the entire programming process is completed.

[0083] In some embodiments, such as Figure 5 As shown, step S401 includes steps S4011-S4013.

[0084] S4011 The main control module changes the level signal of any of its input / output interfaces (IO) and outputs a second detection command to each slave control module through the communication bus, so that each slave control module can detect the level signals of its two input / output interfaces (IO) according to the second detection command.

[0085] Specifically, the master control module can change the level signal of one of its input / output interfaces (IO) by changing the level signal of one of its input / output interfaces (IO). Then, it outputs a second detection command to all slave control modules through the CAN communication bus, so that each slave control module can detect the level signals of its two input / output interfaces (IO) according to the first detection command.

[0086] S4012. When the slave control module detects that the level signals of the two input / output interfaces are different, the slave control module changes the level signal of the input / output interface connected to the next-level slave control module and outputs a second feedback signal to the master control module.

[0087] Specifically, by default, the input / output interface (IO) levels of the slave module are identical and both are high. When the slave module detects that the levels of its two input / output interface (IO) levels are different, it changes the levels of the input / output interface (IO) levels of the next-level slave module, causing the levels of the two input / output interface (IO) levels of the next-level slave module to become different, and then outputs a second feedback signal to the master module.

[0088] S4013. Each time the main control module receives the second feedback signal, it increments the first variable by 1 and outputs the second detection command to each slave control module again until it no longer receives the second feedback signal within a preset time, thus determining that the value stored in the first variable is the number of slave control modules.

[0089] Specifically, since obtaining the number of slave control modules involves a repetitive process, the master control module increments the first variable by 1 each time it receives the second feedback signal, and then outputs a second detection command to each slave control module. This causes each slave control module to detect the level signals of its two input / output interface IOs according to the second detection command. When a slave control module detects that the level signals of its two input / output interface IOs are different, the slave control module changes the level signal of the input / output interface IO connected to the next-level slave control module, so that the level signals of the two input / output interface IOs of the next-level slave control module become different signals, and outputs a second feedback signal to the master control module. This continues until the master control module no longer receives the second feedback signal within a preset time. The master control module then determines that the value stored in the first variable is the number of slave control modules, and the detection of the number of slave control modules is completed.

[0090] In some embodiments, after the master control module obtains the number of slave control modules, the method further includes:

[0091] The master control module resets the level signals of its two input / output interfaces and outputs a reset command to each slave control module via the communication bus, so that each slave control module resets the level signals of its two input / output interfaces according to the reset command.

[0092] Specifically, after the master control module obtains the number of slave control modules, it enters the automatic addressing process. In order to ensure the accuracy of the automatic addressing process, it is necessary to reset the level signals at the two input / output interfaces (IO) of the master control module and the level signals at the two input / output interfaces (IO) of all slave control modules.

[0093] In summary, the automatic addressing method provided in this application uses two bidirectional I / O pins and a communication bus to automatically address all slave control modules. The software control logic is simple, shortening the development cycle. Furthermore, the automatic addressing method provided in this application can detect the number of slave control modules and automatically address them from two different directions. Even if a disconnection occurs, all the above operations can still be completed.

[0094] This application also provides a battery management system, including the automatic addressing circuit described above. Since the battery management system provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon further here.

[0095] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0096] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An automatic addressing circuit, characterized in that, It includes a master control module and n slave control modules. Each master control module and each slave control module includes two input / output interfaces. The two input / output interfaces of the master control module are respectively connected to any input / output interface of the first slave control module and any input / output interface of the nth slave control module. The input / output interfaces of adjacent slave control modules are connected. The communication interface of the master control module and the communication interfaces of the n slave control modules are connected on the same communication bus, where n is a natural number greater than or equal to 2. The master control module is used to change the level signal of any of its input / output interfaces and output a first detection command and address offset to each slave control module through the communication bus, so that each slave control module detects the level signals of its two input / output interfaces according to the first detection command; when a slave control module detects that the level signals of its two input / output interfaces are different, the slave control module is used to address according to the address offset and the initial address, then change the level signal of the input / output interface connected to the next level slave control module, and output a first feedback signal to the master control module; the master control module is also used to decrement the address offset by 1 each time it receives the first feedback signal, and output the first detection command and address offset to each slave control module again, until the address offset becomes 0; wherein, the initial value of the address offset is n; the initial address of each slave control module is the same.

2. The automatic addressing circuit according to claim 1, characterized in that, The master control module is also used to change the level signal of any of its input / output interfaces and output a second detection command to each slave control module through the communication bus, so that each slave control module detects the level signals of its two input / output interfaces according to the second detection command; when the slave control module detects that the level signals of its two input / output interfaces are different, the slave control module is used to change the level signal of the input / output interface connected to the next level slave control module and output a second feedback signal to the master control module; the master control module is also used to increment a first variable by 1 each time it receives the second feedback signal and output the second detection command to each slave control module again until it no longer receives the second feedback signal within a preset time, and determine that the value stored in the first variable is the number of slave control modules.

3. The automatic addressing circuit according to claim 1 or 2, characterized in that, The main control module includes a main control unit, a first signal conversion unit, and a second signal conversion unit. The first input / output interface of the main control unit is connected to the first end of the first signal conversion unit, the second input / output interface of the main control unit is connected to the second end of the first signal conversion unit, the third end of the first signal conversion unit serves as one input / output interface of the main control module, the third input / output interface of the main control unit is connected to the first end of the second signal conversion unit, the fourth input / output interface of the main control unit is connected to the second end of the second signal conversion unit, and the third end of the second signal conversion unit serves as another input / output interface of the main control module. The communication interface of the main control unit is connected to the communication interfaces of n slave control modules through a communication bus. The master control unit is configured to set its first and third input / output interfaces as output interfaces, and its second and fourth input / output interfaces as input interfaces. The master control unit is also configured to change the level signal of any of its output interfaces, thereby changing the level signal of any of the master control module's input / output interfaces. The master control unit is also configured to output a first detection command and an address offset to each slave control module via a communication bus. The master control unit is also configured to, upon receiving the first feedback signal each time, decrement the address offset by 1 and output the first detection command and address offset to each slave control module again, until the address offset becomes 0. The first signal conversion unit is configured to perform level signal conversion. The second signal conversion unit is configured to perform level signal conversion.

4. The automatic addressing circuit according to claim 3, characterized in that, The main control unit includes a first microcontroller, a first input / output interface of the first microcontroller connected to a first end of the first signal conversion unit, a second input / output interface of the first microcontroller connected to a second end of the first signal conversion unit, a third input / output interface of the first microcontroller connected to a first end of the second signal conversion unit, a fourth input / output interface of the first microcontroller connected to a second end of the second signal conversion unit, and a communication interface of the first microcontroller connected to the communication interfaces of n slave control modules via a communication bus.

5. The automatic addressing circuit according to claim 1 or 2, characterized in that, The slave control module includes a slave control unit, a third signal conversion unit, and a fourth signal conversion unit. The first input / output interface of the slave control unit is connected to the first end of the third signal conversion unit, the second input / output interface of the slave control unit is connected to the second end of the third signal conversion unit, the third end of the third signal conversion unit serves as one input / output interface of the slave control module, the third input / output interface of the slave control unit is connected to the first end of the fourth signal conversion unit, the fourth input / output interface of the slave control unit is connected to the second end of the fourth signal conversion unit, the third end of the fourth signal conversion unit serves as another input / output interface of the slave control module, and the communication interface of the slave control unit is connected to the communication interface of the master control module through a communication bus. The slave control unit is configured to set its first and third input / output interfaces as output interfaces, and its second and fourth input / output interfaces as input interfaces. The slave control unit is also configured to detect the level signals of its two input interfaces according to the first detection instruction; when the level signals of its two input interfaces are detected to be different, it performs addressing according to the address offset and the initial address, then changes the level signal of its output interface, thereby changing the level signal of the input / output interface connected to the next-level slave control module, and outputs a first feedback signal to the master control module. The third signal conversion unit is configured to perform level signal conversion; the fourth signal conversion unit is configured to perform level signal conversion.

6. The automatic addressing circuit according to claim 5, characterized in that, The slave control unit includes a second microcontroller. The first input / output interface of the second microcontroller is connected to the first end of the third signal conversion unit. The second input / output interface of the second microcontroller is connected to the second end of the third signal conversion unit. The third input / output interface of the second microcontroller is connected to the first end of the fourth signal conversion unit. The fourth input / output interface of the second microcontroller is connected to the second end of the fourth signal conversion unit. The communication interface of the second microcontroller is connected to the communication interface of the master control module through a communication bus.

7. An automatic addressing method, based on the automatic addressing circuit according to any one of claims 1-6, characterized in that, include: The master control module obtains the number of slave control modules; The master control module changes the level signal of any of its input / output interfaces and outputs a first detection command and an address offset to each slave control module through the communication bus, so that each slave control module detects the level signals of its two input / output interfaces according to the first detection command; wherein, the initial value of the address offset is the number of slave control modules; When the slave control module detects that the level signals of its two input / output interfaces are different, the slave control module performs addressing according to the address offset and the initial address, then changes the level signal of the input / output interface connected to the next level slave control module, and outputs a first feedback signal to the master control module; wherein, the initial address of each slave control module is the same; The main control module also reduces the address offset by 1 each time it receives the first feedback signal, and outputs the first detection command and address offset to each slave control module again, until the address offset becomes 0. The master control module also outputs latch instructions to each slave control module through the communication bus, so that each slave control module latches its address according to the latch instructions.

8. The automatic addressing method according to claim 7, characterized in that, The master control module obtains the number of slave control modules, including: The master control module changes the level signal of any of its input and output interfaces and outputs a second detection command to each slave control module through the communication bus, so that each slave control module detects the level signals of its two input and output interfaces according to the second detection command. When the slave control module detects that the level signals of the two input / output interfaces are different, the slave control module changes the level signal of the input / output interface connected to the next-level slave control module and outputs a second feedback signal to the master control module; The master control module also increments the first variable by 1 each time it receives the second feedback signal, and outputs the second detection command to each slave control module again, until it no longer receives the second feedback signal within a preset time, and determines that the value stored in the first variable is the number of slave control modules.

9. The automatic addressing method according to claim 7, characterized in that, After the master control module obtains the number of slave control modules, the process includes: The master control module resets the level signals of its two input / output interfaces and outputs a reset command to each slave control module via the communication bus, so that each slave control module resets the level signals of its two input / output interfaces according to the reset command.

10. A battery management system, characterized in that, Includes the automatic addressing circuit as described in any one of claims 1-6.

Images