Multi-to-one dma access system, access method, device, medium

Abstract

This invention discloses a many-to-one DMA access system, method, apparatus, and medium, belonging to the field of DMA access technology. The many-to-one DMA access method includes: receiving and buffering multiple DMA access requests sent by multiple DMA request initiators; arbitrating the buffered DMA access requests to obtain a target DMA access request; unpacking the arbitrated target DMA access request and performing boundary detection and segmentation on target DMA access requests crossing 4K address boundaries to generate multiple burst transfer requests; converting the multiple burst transfer requests into standard AXI4 interface requests and sending them to a shared target memory unit; receiving data returned by the shared target memory unit based on multiple AXI IDs and rearranging it, then returning the rearranged data to the corresponding DMA request initiator. This invention reduces the number of AXI interfaces mounted to the NOC and the arbitration overhead of the NOC.

Description

Technical Field

[0001] This invention belongs to the field of memory access technology, specifically relating to many-to-one DMA access systems, access methods, devices, and media. Background Technology

[0002] With the development of high-performance computing, artificial intelligence acceleration, 5G communication, and embedded systems, System-on-a-Chip (SoC) typically integrates multiple data processing units (such as CPU cores, GPUs, AI accelerators, image signal processors (ISPs), and network coprocessors). These processing units frequently exchange large blocks of data with external memory (such as DDR / HBM) or high-speed peripherals (PCIe) during operation. To reduce the processor load and improve system throughput, Direct Memory Access (DMA) technology is widely adopted.

[0003] In a typical multi-master SoC architecture, multiple DMA engines (or master devices with DMA capabilities) often need to concurrently access the same target resource (such as shared system memory, unified cache, or a single high-speed interface). While this "many-to-one" DMA access mode improves resource utilization, it also brings several key technical challenges:

[0004] First, bus contention and arbitration incur significant overhead. When multiple DMA requests arrive simultaneously at the interconnect structure (such as an AXI crossbar switch or a NoC router), an arbitrator is needed to determine the access order. Traditional round-robin or fixed-priority arbitration mechanisms struggle to balance fairness and Quality of Service (QoS). High-bandwidth demanding master devices may experience severe delays due to low priority, while low-frequency master devices may occupy the bus for extended periods, leading to a decrease in overall system throughput.

[0005] Secondly, there is a lack of dynamic bandwidth allocation capabilities. Existing DMA controllers typically use static configurations, making it impossible to adjust the access weights of each master device in real time based on application load. For example, in video processing scenarios, the AI ​​inference module may require bursts of high-bandwidth feature map readings at a certain stage, while the image acquisition module only needs low-bandwidth writing of raw frames. If the DMA scheduling strategy cannot dynamically adapt to such changes, it will result in resource waste or critical task timeouts.

[0006] Secondly, the risk of cache inconsistency and data conflicts increases. When multiple masters concurrently write to the same memory region, the lack of effective address isolation or transaction ordering mechanisms may lead to problems such as data overwriting and read / write conflicts, especially in bare-metal or RTOS environments without operating system management.

[0007] In addition, existing commercial DMA IPs (such as ARM PL330, Xilinx AXI DMA, etc.) are mostly designed for "one-to-one" or "simple multi-channel" scenarios. Their internal arbitration logic is closed and their scheduling strategies are not programmable, making it difficult to meet the advanced requirements of heterogeneous computing platforms for differentiated service levels, configurable bandwidth allocation, and low-latency response.

[0008] Therefore, there is an urgent need to improve the many-to-one DMA access technology solution, which can support on-demand bandwidth allocation, dynamic priority adjustment, conflict avoidance and efficient arbitration while ensuring system fairness, thereby improving the overall data transmission efficiency and real-time performance of multi-master SoC systems. Summary of the Invention

[0009] This invention provides a many-to-one DMA access system, method, apparatus, and medium, aiming to partially or completely solve the technical problems existing in the prior art when multiple master devices concurrently access a single target resource in many-to-one DMA access scenarios, such as severe bus contention, rigid bandwidth allocation, high risk of cache inconsistency and data conflicts, and closed arbitration logic and non-programmable scheduling strategies within commercial DMA IPs. This invention can reduce DMA access latency and improve overall throughput and real-time performance. To achieve the objectives of this invention, the following technical solutions are adopted:

[0010] In a first aspect, a many-to-one DMA access system is characterized by comprising a plurality of DMA request initiators, a shared target memory unit, and an interconnection structure disposed between the plurality of DMA request initiators and the shared target memory unit, the interconnection structure comprising:

[0011] The caching module is used to receive and cache the DMA access requests sent by the multiple DMA request initiators, wherein the DMA access requests include address information and data size information;

[0012] The arbitration control module is used to arbitrate cached DMA access requests in order to obtain the target DMA access request;

[0013] The packet processing module is used to unpack the target DMA access request obtained through arbitration, and to perform boundary detection and segmentation processing on the target DMA access request that crosses the 4K address boundary to generate multiple burst transmission requests. The burst transmission requests not only meet the limitation that the burst length is not greater than the preset unpacking length, but also meet the address boundary access requirements, reducing the complexity of user modules manually avoiding the 4K address boundary when initiating DMA access requests.

[0014] The interface conversion module is used to convert the multiple burst transmission requests into standard AXI4 interface requests and send them to the shared target storage unit;

[0015] The data rearrangement module is used to receive the data returned by the shared target storage unit based on multiple AXI IDs, rearrange the data, and return the rearranged data to the corresponding DMA request initiator.

[0016] Optionally, the many-to-one DMA access system further includes a configurable register group, which is used to configure the arbitration mode, the bandwidth weight value corresponding to each DMA request initiator, and the packet unpacking length of the packet processing module.

[0017] Optionally, the arbitration control module supports at least one of strict priority scheduling, cyclic scheduling, and weighted priority scheduling.

[0018] Optionally, the many-to-one DMA access system further includes a data control module, which generates multiple DMA access requests for the corresponding DMA request initiator to send based on the basic address information and data size information of the image data, combined with the image width information, image height information and image block size information configured by the configurable register group. The multiple DMA access requests are used to support image data reading by image block and / or by channel.

[0019] Secondly, a many-to-one DMA access method, employing the many-to-one DMA access system described in any one of the first aspects above, the method comprising:

[0020] Step S100: Receive and cache multiple DMA access requests sent by DMA request initiators, wherein the DMA access requests include address information and data size information;

[0021] Step S200: Arbitrate the cached DMA access request to obtain the target DMA access request;

[0022] Step S300: The target DMA access request obtained through arbitration is unpacked, and the target DMA access request that crosses the 4K address boundary is subjected to boundary detection and segmentation to generate multiple burst transmission requests.

[0023] Step S400: Convert the multiple burst transmission requests into standard AXI4 interface requests and send them to the shared target storage unit;

[0024] Step S500: Receive the data returned by the shared target storage unit based on multiple AXI IDs, rearrange the data, and return the rearranged data to the corresponding DMA request initiator.

[0025] Optionally, in step S200, arbitrating the cached DMA access request includes:

[0026] Weighted round-robin arbitration is performed on each DMA request initiator based on a preset weight value, and access opportunities proportional to its weight value are allocated to each DMA request initiator in each scheduling cycle; an independent credit counter is maintained for each DMA request initiator, and the number of consecutive transactions initiated by the corresponding DMA request initiator is controlled according to a preset initial credit value.

[0027] Optionally, in step S300, the unpacking process of the target DMA access request obtained through arbitration includes: determining the unpacking length according to the hardware access characteristics of the shared target storage unit, splitting the target DMA access request into several burst transmission requests, such that the burst length of each burst transmission request is not greater than the preset unpacking length; wherein, the preset unpacking length is set according to the prefetch value of the shared target storage unit.

[0028] Optionally, in step S500, rearranging the returned data includes: receiving data returned by the shared target storage unit according to multiple AXI IDs; sorting and reorganizing the returned data according to the AXI IDs corresponding to the returned data and the original request order; and returning the sorted and reorganized data to the DMA request initiator that initiated the corresponding DMA access request.

[0029] Thirdly, this application provides a many-to-one DMA access device, including a memory and a processor connected in communication, wherein the memory is used to store a computer program, and the processor is used to read the computer program and execute the many-to-one DMA access method as described in any of the second aspects.

[0030] Fourthly, this application provides a computer-readable storage medium storing instructions that, when executed on a computer, perform the many-to-one DMA access method as described in any of the second aspects.

[0031] (1) In this invention application, the many-to-one DMA access system can support dynamic bandwidth allocation and efficient transaction scheduling. The packet processing module’s unpacking and 4K boundary transparent processing greatly simplifies the design complexity of the upstream DMA request initiation module. The data rearrangement module makes full use of the multi-identifier concurrent pending transaction characteristics of the AXI bus, improves bandwidth utilization, has good QoS guarantee capability, programmability and system throughput capability, and is suitable for high-performance multi-core SoC scenarios such as 5G communication, AI acceleration and image processing, thereby improving data transmission real-time performance and resource utilization.

[0032] (2) In this invention application, the many-to-one DMA access system can realize on-demand bandwidth allocation. Through configurable weights and WRR arbitration mechanism, the DMA request initiators of different modules can obtain differentiated bandwidth guarantees according to actual business needs, thereby improving the real-time data access of critical tasks. At the same time, by setting independent credit tokens or credit counting control mechanisms for each DMA request initiator, the number of times a single initiator continuously occupies bus resources is limited, effectively avoiding the problems of bus starvation and long-term monopoly of the bus by individual initiators, thereby improving the overall fairness of the system. The key configurations such as weight parameters and packet unpacking length in the system can be dynamically adjusted by the software at runtime, which can adapt to the needs of business load changes over time in application scenarios such as artificial intelligence inference and video encoding and decoding, and enhance the flexibility and reconfigurability of the system. The hardware implementation overhead of the many-to-one DMA access system is low and has strong compatibility. It can be implemented on the standard AXI / CHI interconnect architecture without modifying the existing DMA interface, making it easy to integrate into various hardware platforms and having high engineering application value. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of a many-to-one DMA access system according to an embodiment of this invention.

[0035] Figure 2 This invention provides another embodiment of a data transfer scenario in the 5G uplink, illustrating the structure of a many-to-one DMA access system.

[0036] Figure 3 This is a schematic diagram illustrating the principle of strict priority scheduling SP according to this invention application;

[0037] Figure 4 This is a schematic diagram illustrating the principle of the cyclic scheduling (RR) method of this invention.

[0038] Figure 5 This is a schematic diagram illustrating the principle of Weighted Priority Rescheduling (WRR) according to this invention.

[0039] Figure 6 This is a schematic diagram of packet processing module according to an embodiment of the present invention in a scenario where packet unpacking does not cross 4K address boundaries;

[0040] Figure 7This is a schematic diagram of packet processing module according to an embodiment of the present invention in a scenario involving cross-4K address boundaries.

[0041] Figure 8 This is a schematic diagram of an image block from the present invention application;

[0042] Figure 9 This is a schematic diagram showing how the data control module of this invention generates a DMA access request when reading image blocks from image data.

[0043] Figure 10 This is a flowchart illustrating a many-to-one DMA access method according to an embodiment of this invention.

[0044] The accompanying drawings are provided to further understand the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation thereof. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0046] As shown in the present invention application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, and "a plurality of" includes one, two, or more steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0047] While this application makes various references to certain modules of the system according to embodiments of the present invention, any number of different modules can be used and run on user terminals and / or servers. The modules are merely illustrative, and different aspects of the system and method may use different modules.

[0048] This invention application uses flowcharts to illustrate the operations performed by the system according to embodiments of the invention. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0049] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein.

[0050] It is worth noting that in this invention application, all data acquisition actions are carried out in compliance with the relevant data protection laws and policies of the country where the location is located, and with the authorization granted by the owner of the relevant device.

[0051] Firstly, such as Figure 1 , Figure 2 As shown, a many-to-one DMA access system includes multiple DMA request initiators, a shared target memory unit, and an interconnection structure disposed between the multiple DMA request initiators and the shared target memory unit. The interconnection structure includes:

[0052] The caching module is used to receive and cache the DMA access requests sent by the multiple DMA request initiators, wherein the DMA access requests include address information and data size information;

[0053] The arbitration control module is used to arbitrate cached DMA access requests in order to obtain the target DMA access request;

[0054] The packet processing module is used to unpack the target DMA access request obtained through arbitration, and to perform boundary detection and segmentation processing on the target DMA access request that crosses the 4K address boundary in order to generate multiple burst transmission requests.

[0055] The interface conversion module is used to convert the multiple burst transmission requests into standard AXI4 interface requests and send them to the shared target storage unit;

[0056] The data rearrangement module is used to receive the data returned by the shared target storage unit based on multiple AXI IDs, rearrange the data, and return the rearranged data to the corresponding DMA request initiator.

[0057] In some embodiments, a many-to-one DMA (Direct Memory Access) system is deployed within the SoC chip to enable concurrent access to the same shared memory resource by multiple functional modules. An SoC chip can be understood at least as a system-on-a-chip that integrates a processor, dedicated functional modules, a memory controller, and bus interconnect resources on the same chip. As the number of heterogeneous computing units within the SoC increases, different functional modules often need to move data to the same off-chip memory or on-chip shared memory resource via DMA. Therefore, it is necessary to set up a dedicated interconnect structure between each functional module and the shared target memory unit to uniformly cache, arbitrate, unpack, convert protocols, and process returned data for multiple DMA access requests.

[0058] In some embodiments, the master device can act as the DMA request initiator. Multiple DMA request initiators can include multiple master devices, such as master device 0, master device 1, ..., master device N, where N is an integer. For example, multiple DMA request initiators include 3 DMA request initiators, which can correspondingly include 3 master devices, namely master device 0, master device 1, and master device 2, wherein master device 0 is the first DMA request initiator, master device 1 is the second DMA request initiator, and master device 2 is the third DMA request initiator.

[0059] For example, master device 0 can be an uplink encoding module, corresponding to services with medium bandwidth requirements; master device 1 can be a PRACH (Physical Random Access Channel) encoding module, corresponding to services with bursty low bandwidth requirements; and master device 2 can be a framing module, corresponding to services with high bandwidth requirements. This configuration simulates application scenarios in real-world SoC systems where multiple service units have different bandwidth requirements for shared storage resources. The framing module typically needs to continuously move large amounts of data, thus requiring high bandwidth; the uplink encoding module needs stable data read / write operations, with moderate bandwidth requirements; and the PRACH encoding module primarily exhibits bursty access, with lower average bandwidth requirements but instantaneous response requirements. By having these three types of master devices concurrently access the same interconnect structure, the applicability of a many-to-one DMA access system in heterogeneous service scenarios can be comprehensively demonstrated.

[0060] In some embodiments, the NOC bus (Network on Chip) is essentially an on-chip interconnect communication architecture for multiple master devices, slave devices, and storage resources within a SoC, providing a high-bandwidth, scalable data transfer channel between different modules within the chip. DDR4 (Double Data Rate 4 Synchronous Dynamic Random Access Memory) is a fourth-generation synchronous dynamic random access memory with high data transfer rates, large capacity, and low power consumption, making it a commonly used high-performance external storage medium in current SoC systems. AXI4 (Advanced eXtensible Interface 4) is a high-performance on-chip bus protocol standard that supports multiple ID (identifier) ​​concurrent pending transactions, burst transmission, and other advanced features, improving the bandwidth utilization of the memory controller. In this embodiment, the shared target storage unit is a DDR4 memory controller mounted on the NOC bus, which is connected to the interconnect structure via a standard AXI4 interface. Specifically, the NOC bus is an on-chip network interconnect structure used to provide data transmission paths between different master devices, slave devices, and storage resources within the SoC; the DDR4 memory controller controls the data read / write timing of the external DDR4 dynamic random access memory and converts access requests from the on-chip master device into control commands that the DDR4 memory can recognize; the AXI4 interface, as a high-performance bus interface protocol in the AMBA architecture, supports independent read / write channels, burst transfers, address and data separation transfers, and multi-transaction concurrent processing, making it suitable for high-throughput, low-latency storage access scenarios. By adopting a system architecture combining the NOC bus, DDR4 memory controller, and AXI4 interface, it facilitates interfacing with existing standard bus architectures, improving system compatibility and integrability.

[0061] In some embodiments, the interconnect structure is disposed between the plurality of DMA request initiators and the shared target memory unit. More specifically, the interconnect structure is disposed between the plurality of master devices and the DDR4 memory controller to shield the differences in DMA access protocols, access timings, and bandwidth requirements of different master devices, so that each master device only needs to submit the access address and access length according to a unified user-side DMA request format, while the interconnect structure internally handles request caching, access opportunity allocation, burst splitting, bus interface adaptation, and return data order restoration.

[0062] In some embodiments, the caching module is connected to master device 0, master device 1, and master device 2 respectively, and is used to cache the address information and data size information of DMA access requests issued by each master device. Specifically, the caching module may include multiple input cache queues or cache units, with each master device corresponding to at least one cache queue or cache unit for receiving DMA access requests sent by that master device.

[0063] For example, the caching module includes multiple independent caching units, such as caching unit 0, caching unit 1, ..., caching unit N, where N is an integer. In an implementation scenario with three master devices, it can include three caching units, namely caching unit 0, caching unit 1, and caching unit 2. Each caching unit corresponds to one master device and is used to temporarily store DMA requests sent by that master device, including key information such as the starting address and transmission length. Preferably, the instruction buffer unit and data buffer unit can be set in the interface conversion module and work in conjunction with the caching module to further buffer requests and data, thereby improving the system's resilience against backpressure.

[0064] In some embodiments, each DMA access request may include at least address information and data size information, and may further include request direction, initiator identifier, or other control fields if necessary. By caching requests submitted by the master device, the caching module can pre-cacherate the requests submitted by the master device, enabling the interconnect structure to maintain a certain queuing capability when multiple master devices initiate requests simultaneously, preventing front-end requests from directly impacting the subsequent arbitration and bus transmission paths. Simultaneously, the caching module can also act as a buffer when bandwidth fluctuations or bus backpressure occur in the shared target storage unit, thereby improving system stability.

[0065] In some embodiments, the arbitration control module is connected to the cache module and is used to select a target DMA access request from multiple cached DMA access requests. Specifically, when only one master device has a valid DMA access request in the cache module, the arbitration control module can directly grant access rights to that master device; when multiple valid DMA access requests from master device 0, master device 1, and master device 2 exist simultaneously in the cache module, the arbitration control module selects one of the multiple pending requests as the target DMA access request according to a preset arbitration rule and sends the target DMA access request to the packet processing module. The role of the arbitration control module is to resolve the problem of contention for access to shared storage resources by multiple master devices, enabling the orderly allocation of shared bus bandwidth among multiple master devices.

[0066] Preferably, the arbitration control module can support strict priority scheduling, round-robin scheduling, or weighted priority scheduling. In scenarios where bandwidth requirements differ, it can also combine weight information and credit counters to control the number of consecutive transactions initiated by each master device, so as to avoid a master device occupying bus resources for a long time.

[0067] In some embodiments, the packet processing module is connected to the arbitration control module and is used to perform packet unpacking processing on the target DMA access request that has obtained access rights. More specifically, the packet processing module splits a large DMA access request into several smaller burst transfer requests based on the memory hardware characteristics and bus burst transfer requirements. This is because DDR-class memories and AXI4 buses typically have requirements for single burst length. When a single request is too large, sending it directly is not conducive to improving transmission efficiency or subsequent bus scheduling. Therefore, the packet processing module can split a large request into multiple burst transfer requests according to a preset unpacking length to match the efficient access characteristics of the underlying bus and memory.

[0068] Furthermore, when a target DMA access request simultaneously crosses a 4K address boundary, the packet processing module, while performing packet splitting according to the preset splitting length, also performs 4K boundary detection and segmentation on the target DMA access request. In other words, the packet processing module not only splits the length based on the hardware access characteristics of the shared target memory unit, but also further segments the boundary-crossing request. This ensures that each split burst transmission request satisfies both the limitation that the burst length does not exceed the preset splitting length and the address boundary access requirements, thereby reducing the complexity of user modules manually avoiding 4K address boundaries when initiating DMA access requests. For example, when the starting address and access length of a target DMA access request cross a 4K address boundary, the packet processing module will split the request into two or more burst transmission requests at the 4K boundary, without requiring the master device to manually avoid the 4K boundary issue, thus reducing the design complexity of the master device and minimizing system anomalies caused by boundary processing oversights.

[0069] In some embodiments, the interface conversion module is connected to the packet processing module and is used to convert the multiple burst transmission requests into standard AXI4 interface requests and send them to the shared target memory unit. More specifically, the interface conversion module is used to convert the unpacked requests into standard AXI4 interface requests and send them to the DDR4 memory controller. Specifically, after receiving multiple burst transmission requests generated by the packet processing module, the interface conversion module generates corresponding address channel control information, burst length information, transmission type information, and identification information according to the AXI4 protocol requirements, and encapsulates them into standard AXI4 read requests or write requests before sending them to the shared target memory unit. Preferably, the interface conversion module may further include an instruction buffer unit and a data buffer unit, wherein the instruction buffer unit is used to cache the address and control information of the DMA request, and the data buffer unit is used to cache the data content to be written or returned. By setting a buffer unit (i.e., a buffer unit) in the interface conversion module, the module can have a certain degree of resistance to backpressure. When the DDR4 memory controller response is delayed or the NOC bus is momentarily congested, it buffers the previous requests, thereby offsetting the impact of memory bandwidth fluctuations on the entire DMA access link.

[0070] In some embodiments, the data reordering module is located on the data return path. It reorders the data returned by the DDR4 memory controller based on different AXI IDs (Advanced eXtensible Interface Identifiers) before returning them to Master 0, Master 1, and Master 2 respectively. When the interconnect structure sends multiple burst transfer requests to the shared target memory unit, it can assign multiple AXI IDs to different requests, allowing multiple transactions to flow concurrently on the bus. Since the completion times of transactions corresponding to different AXI IDs may differ, requests sent earlier may not return first, and requests sent later may return first, resulting in a discrepancy between the returned data order and the original request order. The data reordering module maintains the mapping relationship between AXI IDs and the original DMA requests, identifying, caching, reorganizing, and outputting the out-of-order data returned by the shared target memory unit. This ensures that each returned data item is accurately sent back to the corresponding master device. If necessary, it can further restore the expected order of data on the master device side, thereby guaranteeing data correctness under conditions of concurrent access by multiple IDs.

[0071] In one specific embodiment, such as Figure 6The diagram shows the packet processing module's unpacking process in scenarios not spanning 4K address boundaries. The clock can be used to indicate the temporal order of each request or data segment. With a system bus width of 32 bytes and a read size of 544 bytes, the target DMA access request enters the packet processing module after arbitration. The packet processing module splits the target DMA access request into 3 burst transfer requests according to a preset unpacking length. In the diagram, 7, 7, and 0 in the top row represent the burst length parameters corresponding to the 3 burst transfer requests, while 0x0, 0x20, and 0x40 in the middle row represent the starting addresses of the 3 burst transfer requests. The first two burst transfer requests have a burst length of 7, corresponding to 8 consecutive data cycles, while the last burst transfer request has a burst length of 0, corresponding to 1 consecutive data cycle. In the data segment below, D0, D7, D8, D15, and D16 represent the data boundaries corresponding to each burst transfer request after unpacking. That is, the first burst transfer request (corresponding to Burst 0 in the diagram) covers D0 to D7, the second burst transfer request covers D8 to D15 (corresponding to Burst 0 in the diagram), and so on. 1) The third burst transfer request (corresponding to Burst2 in the diagram) overwrites D16, thus splitting the 544-byte data into three burst transfer requests of "8 beats + 8 beats + 1 beat". Subsequently, the interface conversion module further converts these three burst transfer requests into read requests conforming to the AXI4 bus protocol and sends them to the DDR4 memory controller via the NOC bus for data reading. Since the interconnect structure can use multiple AXI IDs for concurrent access, the data returned by the DDR4 memory controller may not be returned strictly in the order of the requests. Therefore, after receiving the returned data, the data rearrangement module matches and reorders the data according to the AXI ID and master device identifier corresponding to the request, and then accurately sends the reordered data back to master device 2. With the above structure, master device 0, master device 1, and master device 2 do not need to directly handle the DDR controller protocol details, AXI4 transaction management details, and low-level issues such as crossing 4K boundaries, thereby significantly reducing the complexity of user module design and improving system integration efficiency.

[0072] In another specific embodiment, such as Figure 7The diagram illustrates the packet processing module's unpacking process in a scenario spanning 4K address boundaries. The clock can be used to represent the temporal order of each request or data segment. When the system bus width is 32 bytes, the read size is 544 bytes, and the starting address of the target DMA access request is near 0xFE0, the packet processing module performs 4K boundary detection and segmentation processing simultaneously with the unpacking process because the DMA access request crosses the 4K address boundary of 0x1000. The 0, 7, and 7 in the top row represent the burst length parameters corresponding to the three burst transmission requests, while the 0xFE0, 0x1000, and 0x1020 in the middle row represent the starting addresses of the three burst transmission requests. The first burst transmission request (corresponding to the one in the diagram)... The burst length of Burst0 is 0, corresponding to the continuous transmission of 1 data clock cycle, used to complete the data access before the 4K boundary. The burst length of the next two burst transmission requests (corresponding to Burst1 and Burst2 in the figure) is 7, corresponding to the continuous transmission of 8 data clock cycles. In the data segment below, D0, D1, D8, D9, and D16 represent the data boundaries covered by each burst transmission request after boundary segmentation. This allows the original DMA access request that crosses the 4K address boundary to be split into multiple burst transmission requests that meet the address boundary constraints, avoiding the need for the user-side module to manually handle cross-boundary access issues.

[0073] In some embodiments, multiple DMA request initiators send DMA access requests to a caching module for caching. The DMA access requests include address information and data size information; the address information may include a starting address. The arbitration control module schedules the cached requests according to a preset arbitration strategy, such as strict priority scheduling (SP), round-robin scheduling (RR), or weighted priority scheduling (WRR), selects the target DMA access request, and can maintain an independent credit counter for each initiator. The initial credit value controls the number of consecutive transactions initiated, preventing any single initiator from monopolizing the bus for an extended period. After the target request enters the packet processing module, larger DMA access requests are split according to the configured packet size value. For example, a 544-byte request is split into multiple bursts with a burst length of 8. Simultaneously, 4K address boundary detection and segmentation are performed, eliminating the need for user modules to manually split cross-boundary requests. The interface conversion module converts the split burst requests into standard AXI4 interface signals, using multiple AXI IDs to improve the ability to handle concurrent pending transactions with multiple IDs. After buffering by the instruction buffer unit and data buffer unit, the signals are sent to the shared target storage unit. Data returned from the target shared storage unit may arrive out of order due to different AXI IDs. The data rearrangement module is responsible for rearranging the data according to the original request correspondence and returning it to the corresponding DMA request initiator. The interface conversion module also provides anti-backpressure capability, thereby realizing caching, arbitration, unpacking, protocol conversion and return data organization for multiple DMA access requests, and completing concurrent access to the same target storage resource by multiple DMA request initiators.

[0074] In this invention, the many-to-one DMA access system can support dynamic bandwidth allocation and efficient transaction scheduling. The packet processing module's unpacking and 4K boundary transparency processing greatly simplifies the design complexity of the upstream DMA request initiation module. The data rearrangement module fully utilizes the multi-identifier concurrent pending transaction characteristics of the AXI bus, improving bandwidth utilization. It has good QoS guarantee capabilities, programmability, and system throughput capabilities, making it suitable for high-performance multi-core SoC scenarios such as 5G communication, AI acceleration, and image processing, thereby improving data transmission real-time performance and resource utilization.

[0075] Optionally, the many-to-one DMA access system further includes a configurable register group, which is used to configure the arbitration mode, the bandwidth weight value corresponding to each DMA request initiator, and the packet unpacking length of the packet processing module.

[0076] In some embodiments, the many-to-one DMA access system further includes a configurable register group, which is located in the arbitration layer of the interconnect structure. The configurable register group is connected to an external control terminal through a PCIE BAR (Peripheral Component Interconnect Express Base Address Register) register controller or REG I / F (Register Interface) to configure the arbitration mode, the bandwidth weight value of each DMA request initiator, and the packet unpacking length of the packet processing module. This enables unified configuration of the arbitration strategy, bandwidth allocation strategy, and packet processing strategy in the many-to-one DMA access system, thereby allowing the many-to-one DMA access system to adapt to the DMA access requirements under different business scenarios.

[0077] In some embodiments, the configurable register group may include an arbitration mode configuration register, a weight configuration register, and a packet splitting length configuration register; wherein, the arbitration mode configuration register is used to configure the currently adopted arbitration mode, the weight configuration register is used to allocate corresponding bandwidth weight values ​​to each DMA request initiator, and the packet splitting length configuration register is used to configure the packet splitting length used by the packet processing module when splitting DMA access requests.

[0078] In some embodiments, the arbitration mode may include at least one of Round Robin (RR), Strict Priority (SP), and Weighted Round Robin (WRR). Specifically, when the access opportunities of multiple DMA request initiators in the system need to be allocated as evenly as possible, the arbitration mode can be configured as Round Robin (RR) through the configurable register group; when a DMA request initiator in the system needs to obtain priority access to the shared target memory unit, the arbitration mode can be configured as Strict Priority (SP); when the bandwidth requirements of multiple DMA request initiators in the system for the shared target memory unit differ, the arbitration mode can be configured as Weighted Priority (WRR).

[0079] In some embodiments, when the arbitration mode is configured as Weighted Priority Rescheduling (WRR), the weight configuration register is used to configure bandwidth weight values ​​for each DMA request initiator. The arbitration control module performs weighted round-robin arbitration based on the bandwidth weight values ​​and allocates access opportunities to each DMA request initiator in each scheduling cycle in proportion to its weight. Furthermore, the arbitration control module can also maintain an independent credit counter for each DMA request initiator and control the number of consecutive transactions initiated by it based on a preset initial credit value to prevent any DMA request initiator from monopolizing bus resources for an extended period.

[0080] In some embodiments, the weight configuration register may include multiple weight configuration sub-registers, each corresponding to a different DMA request initiator, for storing the bandwidth weight value corresponding to each DMA request initiator. Specifically, when the multiple DMA request initiators include a first DMA request initiator, a second DMA request initiator, and a third DMA request initiator, the weight configuration register may include a first weight configuration sub-register, a second weight configuration sub-register, and a third weight configuration sub-register; wherein, the first weight configuration sub-register stores the bandwidth weight value corresponding to the first DMA request initiator, the second weight configuration sub-register stores the bandwidth weight value corresponding to the second DMA request initiator, and the third weight configuration sub-register stores the bandwidth weight value corresponding to the third DMA request initiator. After reading the weight parameters in each weight sub-register, the arbitration control module determines the access opportunity obtained by each DMA request initiator in the current scheduling period based on the weight value corresponding to each DMA request initiator. By using multiple weight configuration sub-registers to configure the bandwidth weight values ​​of different DMA request initiators, the targeting and flexibility of bandwidth allocation configuration can be improved.

[0081] In some embodiments, the packet splitting length configuration register is used to configure the packet splitting length of the packet processing module. The packet processing module splits the target DMA access request according to the splitting length to generate multiple burst transfer requests. For example, in a scenario where the system bus width is 32 bytes and the read size is 544 bytes, when the default splitting length is configured to 8 through the configurable register group, the packet processing module can split the DMA access request into 3 burst transfer requests and send them out. By setting the splitting length, the burst transfer requests output by the packet processing module can better match the characteristics of the underlying bus and memory access.

[0082] In some embodiments, the external control terminal can write configuration parameters to the configurable register group through the PCIE BAR register controller during system initialization, or dynamically adjust the arbitration mode, bandwidth weight value, and packet splitting length according to changes in service load during system operation. Through the above configuration methods, the many-to-one DMA access system can switch different resource allocation strategies at different service stages, thereby improving the system's flexibility and adaptability in complex service scenarios.

[0083] In some embodiments, after multiple DMA request initiators initiate DMA access requests, the caching module first caches each DMA access request; the arbitration control module reads the arbitration mode configured in the configurable register group and the bandwidth weight value corresponding to each DMA request initiator, and schedules the cached requests according to the current configuration result; the packet processing module reads the packet unpacking length configured in the configurable register group and unpacks the target DMA access request according to the packet unpacking length; the interface conversion module converts the unpacked burst transmission request into a standard AXI4 interface request and sends it to the shared target storage unit; the data returned by the shared target storage unit is processed by the data rearrangement module and returned to the corresponding DMA request initiator. Thus, programmable control over the arbitration strategy, bandwidth allocation, and unpacking granularity of multiple DMA access requests is achieved.

[0084] Taking a 5G uplink data transfer scenario as an example, during the system initialization phase, the configuration terminal writes the following parameters to the configurable register group via the PCIE BAR register controller: setting the weight of the framing module corresponding to master device 2 to 50%, the weight of the uplink encoding module corresponding to master device 0 to 30%, and the weight of the PRACH encoding module corresponding to master device 1 to 20%, while setting the packet splitting length to 8. After configuration, the arbitration control module controls the allocation of access opportunities for the DDR4 (Double Data Rate 4 Synchronous Dynamic Random Access Memory) memory controller among the three master devices according to the above weights, and the packet processing module splits large DMA access requests according to the rule of a packet splitting length of 8. In this way, when the framing module is in a high-throughput working state, it can obtain a higher proportion of bus bandwidth; when the PRACH encoding module only occasionally generates burst requests, it can complete the access with a smaller bandwidth ratio.

[0085] In this invention application, by adding the configurable register group, the arbitration mode can be flexibly selected according to different business scenarios, and the bandwidth weight value of each DMA request initiator and the packet unpacking length of the packet processing module can be configured. The same interconnection structure can be used for heterogeneous module combinations with large differences in bandwidth requirements, as well as for scenarios where multiple identical business modules are deployed in parallel. This makes the many-to-one DMA system more configurable and reusable, and improves the programmability, adaptability, and resource utilization of the many-to-one DMA access system. Especially in scenarios where the bandwidth requirements of multiple DMA request initiators are large differences, by configuring different bandwidth weight values ​​and packet unpacking lengths, the rationality of shared bus bandwidth allocation can be improved, and the matching degree between DMA access requests and underlying bus transmission characteristics can be improved, thereby improving the overall throughput of the system.

[0086] Optionally, the arbitration control module supports at least one of strict priority scheduling, cyclic scheduling, and weighted priority scheduling.

[0087] In some embodiments, when a service corresponding to a DMA request initiator in the system has high real-time requirements or needs priority access to a shared target storage unit, the arbitration control module can employ strict priority scheduling (SP). Specifically, the arbitration control module can pre-set different priority orders for multiple DMA request initiators. When multiple DMA request initiators simultaneously have valid DMA access requests, the arbitration control module prioritizes the DMA access request corresponding to the DMA request initiator with the higher priority as the target DMA access request. By employing strict priority scheduling (SP), the data access needs of high real-time services can be prioritized, reducing the access waiting time for critical services.

[0088] In some embodiments, when the access needs of multiple DMA request initiators in the system are relatively similar, and there is a greater focus on the balanced allocation of access opportunities among the DMA request initiators, the arbitration control module can employ round-robin scheduling (RR). Specifically, the arbitration control module allocates access opportunities to the shared target memory unit among the multiple DMA request initiators sequentially according to a preset round-robin order, ensuring that each DMA request initiator receives a relatively balanced access opportunity during the round-robin process. By employing round-robin scheduling (RR), the long-term occupation of shared bus resources by a single DMA request initiator can be avoided, thereby improving the fairness of system access.

[0089] In some embodiments, when multiple DMA request initiators in the system have different bandwidth requirements for a shared target storage unit, the arbitration control module can employ weighted priority scheduling (WRR). Specifically, the arbitration control module performs weighted round-robin arbitration based on the weight value corresponding to each DMA request initiator, and allocates access opportunities to each DMA request initiator in each scheduling cycle in proportion to its weight. By employing weighted priority scheduling (WRR), high-bandwidth demand services can obtain more bus resources while ensuring that each DMA request initiator can obtain access opportunities, thereby improving the rationality of bandwidth allocation.

[0090] In some embodiments, when the arbitration control module adopts weighted priority scheduling (WRR), it can also maintain an independent credit counter for each DMA request initiator and control the number of consecutive transactions initiated by each DMA request initiator based on a preset initial credit value, thereby preventing any DMA request initiator from monopolizing bus resources for an extended period. By combining the weight value with the credit counter, the throughput capacity of high-bandwidth services can be improved while also taking into account the basic access needs of other services, thus further improving the system's service quality.

[0091] In some embodiments, the arbitration control module supports at least one of strict priority scheduling (SP), round-robin scheduling (RR), and weighted priority scheduling (WRR). By setting the above multiple arbitration methods, the many-to-one DMA access system can flexibly select the appropriate scheduling strategy according to the bandwidth requirements, real-time requirements, and fairness requirements under different business scenarios, thereby improving the access efficiency of shared target storage units and the overall resource utilization of the system.

[0092] like Figures 3 to 5 As shown, Req represents a request. Req can be understood at least as a DMA access request. Taking master device 0, master device 1, and master device 2 as the initiators of the first, second, and third DMA requests, respectively, specifically:

[0093] When master device 0, master device 1, and master device 2 concurrently access the shared DDR4 memory controller, SP2, SP1, and SP0 represent the strict priorities corresponding to different DMA request initiators, with SP0 being the highest, SP1 the next highest, and SP2 the lowest. When the arbitration control module operates in strict priority scheduling mode, if multiple DMA access requests are valid at the same time, the DMA access request corresponding to SP0 is selected first. If master device 1 (the second DMA request initiator) corresponding to SP0 does not currently have a valid DMA access request, then the DMA access request corresponding to SP1 is selected. If master device 2 (the third DMA request initiator) corresponding to SP1 also does not currently have a valid DMA access request, then the DMA access request corresponding to SP2 is selected. That is, master device 0 sends a DMA access request, thereby strictly ensuring the real-time access of high-priority services.

[0094] When the business modules corresponding to Master Device 0, Master Device 1 and Master Device 2 in the system are multiple modules with the same function or basically the same access opportunity requirements, the arbitration control module can work in the round-robin scheduling mode. At this time, the arbitration control module selects the DMA access requests of Master Device 0, Master Device 1 and Master Device 2 in the preset round-robin order, so that the three master devices share the bus bandwidth equally.

[0095] When the bandwidth requirements of Master Device 0, Master Device 1, and Master Device 2 are significantly different, the arbitration control module can operate in a weighted priority scheduling mode. For example, in a 5G uplink scenario, Master Device 2 has the highest DMA bandwidth requirement for its framing module, Master Device 0 has the second highest DMA bandwidth requirement for its uplink coding module, and Master Device 1 has the lowest DMA bandwidth requirement for its PRACH coding module. In this case, the arbitration control module can adopt weighted priority scheduling (WRR) and set different bandwidth weight values ​​for Master Device 2, Master Device 0, and Master Device 1 respectively. For example, 50% of the bandwidth can be allocated to the framing module corresponding to Master Device 2, 30% to the uplink coding module corresponding to Master Device 0, and 20% to the PRACH coding module corresponding to Master Device 1. This ensures that the system bandwidth allocation matches the actual service requirements of each module. Within a scheduling cycle, the arbitration control module allocates access opportunities to the three master devices according to the above proportions and maintains an independent credit counter for each master device to limit the number of times a single master device can continuously occupy the bus and prevent any master device from monopolizing bus resources for a long time.

[0096] In some embodiments, when only one DMA request initiator has a valid DMA access request, the arbitration control module can directly grant access rights to that DMA request initiator without performing a complex arbitration process. When multiple valid DMA access requests exist simultaneously, the arbitration control module selects a target DMA access request from the multiple DMA access requests according to the currently configured arbitration mode and sends the target DMA access request to the packet processing module for further processing. Through this method, the arbitration control module can achieve orderly scheduling of multiple DMA access requests under different service load conditions.

[0097] In some embodiments, when SP mode is selected, only the currently active highest priority request receives all scheduling opportunities, suitable for scenarios dominated by a single module, and beneficial for ensuring low-latency access requirements of high real-time services; in RR mode, each DMA request initiator takes turns receiving equal access opportunities, suitable for expansion of multiple identical modules, and beneficial for improving access fairness among multiple DMA request initiators; in WRR mode, the arbitration control module allocates opportunities proportionally in each scheduling cycle based on weight values ​​and credit counters (e.g., the module with weight 2 receives more slots), and switches after the credit value decreases to 0, which is beneficial for achieving on-demand bandwidth allocation. The scheduling results are transmitted to the packet processing module. Different modes generate different request sending orders.

[0098] In this invention, the multi-mode support of the arbitration control module takes into account fairness, quality of service, and bandwidth utilization. The SP mode enables one-to-one exclusive and efficient access, the RR mode supports symmetrical resource expansion, and the WRR mode allocates resources according to actual needs (such as high bandwidth for framing and low bandwidth for PRACH), avoiding the delay or waste caused by fixed arbitration in the background technology. Combined with the credit counter, it effectively prevents bus monopoly and improves the overall real-time performance and stability of many-to-one DMA in 5G and AI SoC.

[0099] Optionally, the many-to-one DMA access system further includes a data control module, which generates multiple DMA access requests for the corresponding DMA request initiator to send based on the basic address information and data size information of the image data, combined with the image width information, image height information and image block size information configured by the configurable register group. The multiple DMA access requests are used to support image data reading by image block and / or by channel.

[0100] In some embodiments, the many-to-one DMA access system further includes a data control module integrated within the interconnect structure, which controls the image data reading process when the DMA access object is image data. Specifically, as... Figure 8As shown, image data can be stored in memory in a [C, H, W] format, where C represents the channel dimension, H represents the height dimension, and W represents the width dimension. The data control module is connected to a configurable register set, which provides the data control module with image width information, image height information, and image patch size information. Based on the image width information, image height information, and image patch size information, and in conjunction with the address information and data size information contained in the DMA access request, the data control module calculates the address distribution of the target image data in memory and generates a corresponding DMA access request. By providing image parameters to the data control module through the configurable register set, the data control module can adapt to the image data access requirements of different sizes and layouts.

[0101] In some embodiments, when a DMA access request corresponds to image data, the data control module receives the base address information and data size information of the image data, and combines this with image parameters configured in the registers, such as image width, image height, and image patch size parameters, to generate multiple DMA access requests by organizing the data into patches or channels. For example, the generated DMA access requests may include instruction fields or corresponding signal sequences such as command validity indication signals, read address burst length parameters, and read address parameters. For image patch reading scenarios, the data control module can calculate the access address and access length corresponding to each sub-request according to the batch and image patch index, such as image patch 0, image patch 1, image patch 2, image patch 3, etc., and generate corresponding DMA access requests, which are then sent after arbitration and packet processing. This allows for efficient reading of non-contiguous but highly localized image patch data from memory without requiring upstream modules to manually calculate the address corresponding to each image patch.

[0102] In some embodiments, the user only needs to send one DMA access request and configure register parameters such as image width, image height, and image patch size, and the data control module can generate multiple DMA access requests. Specifically:

[0103] Taking an image patch size of 16 and an image width W of 448 as an example, such as Figure 9As shown, this diagram illustrates the generation of DMA access requests by the data control module when reading image blocks. Taking patch0, patch1, patch2, and patch3 as examples, each image block is arranged sequentially along the image width direction, with positional offsets between adjacent image blocks. cmd0, cmd1, cmd2, and cmd3 represent the DMA access instructions generated by the data control module for patch0, patch1, patch2, and patch3, respectively. For example, the corresponding read address range for patch0 includes 0x0, 0x10, 0x20, and 0x30; for patch2, it includes 0x200, 0x210, 0x220, and 0x230; and for patch3, it includes 0x400, 0x410, 0x420, and 0x430. Subsequent image blocks may further correspond to address ranges such as 0x600, 0x610, 0x620, and 0x630. Based on this, after receiving the basic address information and data size information of the image data, the data control module, in conjunction with the image width information, image height information, and image block size information configured in the configurable register group, calculates the access address range and address step size relationship corresponding to patch0, patch1, patch2, and patch3, and generates multiple DMA access requests accordingly. The generated DMA access requests can correspond to the reading interval of each image block shown in the figure, and are then sent to the cache module for caching, then to the arbitration control module for arbitration, and finally sent to the shared target storage unit via the packet processing module and interface conversion module, thereby realizing the automatic reading of multiple image blocks in the image data. Thus, the data control module can generate DMA access requests not only for a single image, but also for reading four batches of image data, meeting the data access requirements in batch image processing services. This supports reading by image block and / or by channel in multi-batch scenarios, thereby reducing the control complexity of upstream user modules and improving the efficiency of image data access.

[0104] In some embodiments, the data control module supports reading image data by image patch. Specifically, the data control module determines the location range of the target image patch in the original image based on the image patch size information, image width information, and image height information, and generates a corresponding DMA access request accordingly. This allows the system to read only a specified local area in the image without having to transfer the entire image data. For example, taking the example that the master device needs to perform image patch reading on an image stored in [C, H, W] format, the data control module first calculates the starting address, row span, and total read length of the target image patch in DDR4 (Double Data Rate 4 Synchronous Dynamic Random Access Memory) memory based on the image width, image height, and image patch size configured in the register, and then generates a set of DMA access requests and sends them to the cache module. Thus, by adopting the image patch reading method, unnecessary data transfer can be reduced, shared bus bandwidth usage can be reduced, and access efficiency in image local processing scenarios can be improved.

[0105] In some embodiments, the data control module also supports reading image data by channel. Specifically, when image data is stored in [C, H, W] format, the data control module can generate DMA access requests for a single channel or multiple channels based on the storage location corresponding to the target channel, thereby achieving channel-by-channel reading. For example, if the main device needs to read only one or a few channels of data from a multi-channel image, the data control module generates a channel-by-channel DMA access request based on the arrangement of channel dimensions in the [C, H, W] storage format, without requiring the user module to perform complex address calculations. Therefore, by reading by channel, the application requirements of processing only a portion of channel data during image preprocessing, feature extraction, or neural network inference can be met, thereby improving the DMA access flexibility of image-related services and the accuracy and efficiency of multi-channel image data access.

[0106] In some embodiments, after the data control module generates a DMA access request, it sends the DMA access request to the caching module for caching. The caching module caches the address information and data size information corresponding to the DMA access request, and the arbitration control module arbitrates the cached DMA access request to obtain the target DMA access request. The packet processing module unpacks the target DMA access request and performs boundary detection and segmentation processing on target DMA access requests that cross 4K address boundaries to generate multiple burst transmission requests. The interface conversion module converts the multiple burst transmission requests into standard AXI4 (Advanced eXtensible Interface 4) interface requests and sends them to the shared target storage unit. The data returned by the shared target storage unit is processed by the data rearrangement module and returned to the corresponding DMA request initiator. Thus, a complete processing flow from image parameter configuration and DMA command generation to data reading and return is realized in image data scenarios.

[0107] In this invention, by adding the data control module, the many-to-one DMA access system can handle not only DMA access requests for general data blocks but also dedicated DMA access requests for image data. By combining image width information, image height information, and image patch size information to generate DMA access requests, it can support reading by image patch and reading by channel, thereby improving the targeting and flexibility of image data access. At the same time, it can also reduce the design burden of upstream image processing modules to complete address calculation and instruction organization, realize efficient reading of image data by image patch and / or by channel, and improve the data access efficiency of the system in scenarios such as image processing, video processing, and artificial intelligence acceleration.

[0108] Secondly, such as Figure 10 As shown, a many-to-one DMA access method employs the many-to-one DMA access system described in any one of the first aspects above, the method comprising:

[0109] Step S100: Receive and cache multiple DMA access requests sent by DMA request initiators, wherein the DMA access requests include address information and data size information;

[0110] Step S200: Arbitrate the cached DMA access request to obtain the target DMA access request;

[0111] Step S300: The target DMA access request obtained through arbitration is unpacked, and the target DMA access request that crosses the 4K address boundary is subjected to boundary detection and segmentation to generate multiple burst transmission requests.

[0112] Step S400: Convert the multiple burst transmission requests into standard AXI4 interface requests and send them to the shared target storage unit;

[0113] Step S500: Receive the data returned by the shared target storage unit based on multiple AXI IDs, rearrange the data, and return the rearranged data to the corresponding DMA request initiator.

[0114] In step S100, multiple DMA access requests sent by DMA request initiators are received and cached. The DMA access requests include address information and data size information. By caching the DMA access requests first, the system can have request queuing and front-end buffering capabilities when multiple DMA request initiators initiate access at the same time, providing a unified request input basis for subsequent arbitration scheduling. For details, please refer to the technical content of the caching module in the first aspect. This application will not elaborate further on this.

[0115] In step S200, the cached DMA access requests are arbitrated to obtain the target DMA access request. During arbitration, at least one of strict priority scheduling, round-robin scheduling, or weighted priority scheduling can be selected according to the business scenario. In the weighted priority scheduling mode, weighted round-robin can be performed according to the weight value corresponding to each DMA request initiator, and the number of times a single initiator continuously occupies the bus can be limited by combining a credit counter, thereby realizing the orderly allocation of shared bus resources. For details, please refer to the technical content of the arbitration module in the first aspect, which will not be repeated here in this application.

[0116] In step S300, the target DMA access request obtained through arbitration is unpacked, and the target DMA access request that crosses the 4K address boundary is subjected to boundary detection and segmentation to generate multiple burst transmission requests. According to the memory hardware characteristics and bus burst transmission requirements, a large DMA access request is split into several smaller burst requests for transmission, so that the burst length is more adapted to the underlying memory access characteristics. At the same time, when the target DMA access request crosses the 4K address boundary, the system segments the request at the 4K boundary, so that the user does not need to manually avoid the 4K boundary problem when initiating the DMA access request. For details, please refer to the technical content of the packet processing module in the first aspect, which will not be repeated here.

[0117] In step S400, the multiple burst transmission requests are converted into standard AXI4 interface requests and sent to the shared target memory unit. For details, please refer to the technical content of the interface conversion module in the first aspect; this application will not repeat it here. The interconnect structure converts the user-side DMA access request into an AXI4 interface request recognizable by the standard bus side and connects to the shared target memory unit via the standard bus to achieve standardized access to the shared target memory unit. Furthermore, the instruction buffer unit and data buffer unit in the interface conversion link can also buffer the address information and data information of the DMA request to offset memory bandwidth fluctuations and enhance the system's resistance to backpressure.

[0118] In step S500, the data returned by the shared target storage unit based on multiple AXI IDs is received and rearranged, and the rearranged data is returned to the corresponding DMA request initiator. When the system initiates access, it can use multiple AXI IDs to transmit concurrently. The completion time of transactions corresponding to different AXI IDs may be inconsistent, resulting in data requested earlier being returned later and data requested later being returned earlier. Therefore, it is necessary to rearrange the returned data to ensure that the correct data is returned to the corresponding DMA request initiator. For details, please refer to the technical content of the data rearrangement module in the first aspect. This application will not elaborate further on this.

[0119] In this invention application, the many-to-one DMA access method organizes concurrent accesses to the same shared target storage unit from multiple DMA request initiators into an ordered, controllable, and high-bandwidth-utilization data transmission process through a "caching-arbitration-unpacking / boundary handling-interface conversion-data rearrangement" process. This completes the many-to-one DMA access, enabling unified access and scheduling of multiple DMA request initiators to the same shared target storage unit. It improves system organization and access stability under multi-master concurrent access conditions, supports different arbitration modes such as strict priority scheduling, cyclic scheduling, and weighted priority scheduling, and can be tailored to the real-time requirements and fairness of different business scenarios. By flexibly allocating access opportunities to multiple DMA request initiators based on performance and bandwidth requirements, large DMA access requests can be converted into multiple burst transfer requests that are more adapted to memory and bus characteristics. At the same time, it avoids upstream user modules from manually avoiding 4K address boundary issues when initiating requests, thereby simplifying upstream module design and reducing the risk of system anomalies caused by boundary handling oversights. Combined with the rearrangement of returned data, the multi-identifier concurrent pending transaction capability of the AXI bus can be fully utilized to improve system transmission bandwidth and throughput while ensuring the correctness of data return. Overall, this improves the data transmission efficiency, real-time performance, resource utilization, and system reliability of multi-master SoC systems.

[0120] Optionally, in step S200, arbitrating the cached DMA access request includes:

[0121] Weighted round-robin arbitration is performed on each DMA request initiator based on a preset weight value, and access opportunities proportional to its weight value are allocated to each DMA request initiator in each scheduling cycle; an independent credit counter is maintained for each DMA request initiator, and the number of consecutive transactions initiated by the corresponding DMA request initiator is controlled according to a preset initial credit value.

[0122] In some embodiments, in step S200, the arbitration of cached DMA access requests can adopt a weighted round-robin (WRR) arbitration method. Specifically, the arbitration control module performs weighted round-robin arbitration on each DMA request initiator based on pre-configured weight values, and allocates access opportunities proportional to its weight value to each DMA request initiator in each scheduling cycle. This allows different DMA request initiators to share the bandwidth resources allocated to the corresponding AXI4 interface bus according to their respective service needs. The preset weight values ​​can be pre-configured by a configurable register set and correspond one-to-one with each DMA request initiator. When executing step S200, the arbitration control module reads the weight value corresponding to each DMA request initiator and determines the number of access opportunities that each DMA request initiator can obtain in the current scheduling cycle based on the weight value. When the weight value of a DMA request initiator is large, the DMA request initiator will have more access opportunities in the current scheduling period; when the weight value of a DMA request initiator is small, it will have fewer access opportunities. Thus, based on the actual bandwidth requirements of different business modules, differentiated bandwidth allocation can be performed on multiple DMA request initiators.

[0123] In some embodiments, an independent credit counter is maintained for each DMA request initiator, and the number of consecutive transactions initiated by the corresponding DMA request initiator is controlled according to a preset initial credit value. That is, when a DMA request initiator has already obtained multiple transaction initiation opportunities within the current scheduling period, the arbitration control module can limit its continued occupation of bus resources based on the remaining value of the credit counter corresponding to that DMA request initiator, thus preventing any DMA request initiator from monopolizing the bus for an extended period. By introducing a credit counter mechanism, it is possible to ensure that high-bandwidth services have priority access opportunities while also taking into account the basic access needs of other DMA request initiators.

[0124] In some embodiments, when DMA access requests from multiple DMA request initiators are simultaneously cached in the cache module, the arbitration control module first determines the allocation of access opportunities within the current scheduling period based on the preset weight value corresponding to each DMA request initiator. Then, considering the credit counter status of each DMA request initiator, it selects a target DMA access request from among the multiple pending DMA access requests. If a DMA request initiator, although corresponding to a large weight value, has its credit counter fallen below a preset threshold, the arbitration control module can temporarily suspend granting that DMA request initiator new transaction initiation opportunities and prioritize scheduling DMA access requests from other DMA request initiators. This avoids high-weight DMA request initiators continuously monopolizing the bus, improving the overall arbitration fairness of the system.

[0125] In some embodiments, by adopting the arbitration method combining weighted round-robin arbitration and credit counter in step S200, it is possible to achieve proportional bandwidth allocation based on the bandwidth requirements of different DMA request initiators, and to control the number of times a single DMA request initiator continuously occupies bus resources. This not only improves the utilization of the shared bus, but also effectively prevents any DMA request initiator from monopolizing bus resources for a long time, ensuring the system's response balance, service quality, and overall throughput to various service requests.

[0126] Optionally, in step S300, the unpacking process of the target DMA access request obtained through arbitration includes: determining a preset unpacking length based on the hardware access characteristics of the shared target storage unit, and splitting the target DMA access request into several burst transmission requests, such that the burst length of each burst transmission request is not greater than the preset unpacking length; wherein, the preset unpacking length is set according to the prefetch value of the shared target storage unit.

[0127] In some embodiments, in step S300, the unpacking length can be determined based on the hardware access characteristics of the shared target memory cell. Specifically, for the memory hardware characteristics of the shared target memory cell, the burst length can be understood at least as the number of data continuously transferred in a single memory access operation, and the prefetch value can be understood at least as the number of bits of data retrieved from the memory array at one time by the memory chip. Generally speaking, memory access performance is better when the maximum value of the burst length is equal to the prefetch value.

[0128] Based on the hardware access characteristics of the shared target storage unit, the packet processing module splits a large DMA access request into several smaller burst transmission requests and sends them, so that the burst length of each burst transmission request is not greater than the preset unpacking length, thereby making the unpacked access request better match the access characteristics of the shared target storage unit.

[0129] In some embodiments, the preset unpacking length is set based on the prefetch value of the shared target memory unit. That is, after determining the prefetch value of the shared target memory unit, the preset unpacking length can be set to a value no greater than the prefetch value. Preferably, the preset unpacking length can be set to the upper limit of the burst length corresponding to the prefetch value, so that the shared target memory unit achieves better access efficiency when performing burst access. Therefore, by setting the preset unpacking length according to the prefetch value, the matching degree between DMA access requests and the underlying memory access mechanism can be improved, thereby improving data transfer efficiency.

[0130] In some embodiments, when the data volume of the target DMA access request is large and not suitable for direct transmission in a single transaction, the packet processing module splits the target DMA access request according to the preset splitting length, so that the multiple burst transfer requests after splitting can be sent to the shared target memory unit in small granularity. Taking a scenario with a system bus width of 32 bytes and a read size of 544 bytes as an example, after the target DMA access request obtains access rights through arbitration, the packet processing module splits the target DMA access request according to the default splitting length configured in the system. When the default splitting length is set to 8, the target DMA access request can be split into 3 burst transfer requests and sent out, and finally sent to the corresponding NOC bus for data acquisition through the interface conversion module. It can be seen that by splitting a large DMA access request according to the preset splitting length, a large access request can be converted into multiple burst transfer requests that are more suitable for the underlying bus and memory processing. This avoids the adverse effects of excessively large single transfer length on bus scheduling and memory access efficiency, and is beneficial for the subsequent interface conversion module to convert each burst transfer request into a standard AXI4 interface request for transmission.

[0131] Optionally, in step S500, rearranging the returned data includes:

[0132] Receive data returned by the shared target storage unit based on multiple AXI IDs;

[0133] The returned data is sorted and reorganized according to the AXI ID corresponding to the returned data and the original request order;

[0134] The sorted and reorganized data is returned to the DMA request initiator that initiated the corresponding DMA access request.

[0135] In some embodiments, when sending the multiple burst transfer requests, multiple different AXI IDs can be assigned to different burst transfer requests. Since the processing latency of transactions corresponding to different AXI IDs in the shared target storage unit may differ, the arrival time of the returned data corresponding to different AXI IDs may also be inconsistent, resulting in situations where an earlier DMA access request returns later, and a later DMA access request returns earlier. In other words, the arrival order of the returned data may not be consistent with the original request order. Therefore, after receiving the returned data, it is necessary to sort and reorganize the returned data according to the AXI ID corresponding to the returned data and the original request order to restore the correspondence between the returned data and the original DMA access requests.

[0136] In some embodiments, the sorting and reorganization process can be performed by a data rearrangement module. Specifically, the data rearrangement module maintains the mapping relationship between each AXI ID and the original DMA access request. After receiving the data returned by the shared target storage unit, it identifies the original DMA access request to which the returned data belongs based on the AXI ID corresponding to the returned data. Then, it sorts, caches, and reorganizes the multiple returned data in combination with the original request order, thereby ensuring that the reorganized data is output in the expected order. The sorted and reorganized data is then returned to the DMA request initiator that initiated the corresponding DMA access request, so as to ensure that each DMA request initiator can receive the data content that matches its original DMA access request. This ensures the correctness of the data under the condition of concurrent access by multiple AXI IDs and realizes the orderly recovery of out-of-order returned data from multiple transactions.

[0137] In some embodiments, taking the concurrent access of multiple DMA request initiators to a shared target storage unit as an example, when the interface conversion module assigns multiple different AXI IDs to multiple burst transmission requests, the data return times corresponding to different AXI IDs may be inconsistent, resulting in data requested earlier being returned later. In this case, the data reordering module reassembles the returned data according to the AXI IDs corresponding to each returned data and the original request order, and returns the correct data to the corresponding master device module.

[0138] In this invention application, by adopting the processing method of "allocating multiple different AXI IDs - sorting and reorganizing according to the AXI IDs and the original request order - returning to the corresponding DMA request initiator", it is possible to fully utilize the multi-ID concurrent access capability of the AXI4 bus while avoiding data mismatch problems caused by out-of-order returns of different transactions. This balances high bandwidth access requirements with data return correctness and improves the access bandwidth and transaction throughput of the shared target storage unit.

[0139] Thirdly, this application provides a many-to-one DMA access device, including a memory and a processor connected in communication, wherein the memory is used to store a computer program, and the processor is used to read the computer program and execute the many-to-one DMA access method as described in any of the second aspects.

[0140] Those skilled in the art will understand that a many-to-one DMA access device includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the many-to-one DMA access method described in any of the second aspects above.

[0141] Fourthly, this application provides a computer-readable storage medium storing instructions that, when executed on a computer, perform the many-to-one DMA access method as described in any of the second aspects.

[0142] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device via various interfaces and lines.

[0143] The memory can be used to store the computer programs and / or modules. The processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory and by calling data stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0144] Wherein, if the modules / units integrated in the terminal device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0145] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0146] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A many-to-one DMA access system, characterized by, It includes multiple DMA request initiators, a shared target memory unit, and an interconnection structure disposed between the multiple DMA request initiators and the shared target memory unit, the interconnection structure including: A caching module is used to receive and cache DMA access requests sent by the multiple DMA request initiators, wherein the DMA access requests include address information and data size information; The arbitration control module is used to arbitrate cached DMA access requests in order to obtain the target DMA access request; The packet processing module is used to unpack the target DMA access request obtained through arbitration, and to perform boundary detection and segmentation processing on the target DMA access request that crosses the 4K address boundary to generate multiple burst transmission requests. The burst transmission requests not only meet the limitation that the burst length is not greater than the preset unpacking length, but also meet the address boundary access requirements, reducing the complexity of user modules manually avoiding the 4K address boundary when initiating DMA access requests. The interface conversion module is used to convert the multiple burst transmission requests into standard AXI4 interface requests and send them to the shared target storage unit; The data rearrangement module is used to receive the data returned by the shared target storage unit based on multiple AXI IDs, rearrange the data, and return the rearranged data to the corresponding DMA request initiator.

2. The many-to-one DMA access system of claim 1, wherein, The multiple-to-one DMA access system further includes a configurable register group, which is used to configure the arbitration mode, the bandwidth weight value corresponding to each DMA request initiator, and the packet unpacking length of the packet processing module.

3. The multiple-to-one DMA access system of claim 2, wherein, The arbitration control module supports at least one of strict priority scheduling, cyclic scheduling, and weighted priority scheduling.

4. The multiple-to-one DMA access system of claim 2, wherein, The multiple-to-one DMA access system further includes a data control module, which generates multiple DMA access requests for the corresponding DMA request initiator to send based on the basic address information and data size information of the image data, combined with the image width information, image height information and image block size information configured by the configurable register group. The multiple DMA access requests are used to support image data reading by image block and / or by channel.

5. A method of many-to-one DMA access, the method comprising: The method employing the many-to-one DMA access system according to any one of claims 1 to 4 includes: Step S100: Receive and cache multiple DMA access requests sent by DMA request initiators, wherein the DMA access requests include address information and data size information; Step S200: Arbitrate the cached DMA access request to obtain the target DMA access request; Step S300: The target DMA access request obtained through arbitration is unpacked, and the target DMA access request that crosses the 4K address boundary is subjected to boundary detection and segmentation to generate multiple burst transmission requests. Step S400: Convert the multiple burst transmission requests into standard AXI4 interface requests and send them to the shared target storage unit; Step S500: Receive the data returned by the shared target storage unit based on multiple AXI IDs, rearrange the data, and return the rearranged data to the corresponding DMA request initiator.

6. A many-to-one DMA access method according to claim 5, characterized in that, In step S200, arbitrating the cached DMA access request includes: Weighted round-robin arbitration is performed on each DMA request initiator based on a preset weight value, and access opportunities proportional to its weight value are allocated to each DMA request initiator in each scheduling cycle; an independent credit counter is maintained for each DMA request initiator, and the number of consecutive transactions initiated by the corresponding DMA request initiator is controlled according to a preset initial credit value.

7. The many-to-one DMA access method of claim 5, wherein, In step S300, the unpacking process of the target DMA access request obtained through arbitration includes: The packet length is determined based on the hardware access characteristics of the shared target storage unit. The target DMA access request is split into several burst transmission requests, such that the burst length of each burst transmission request is not greater than the preset packet length. The preset packet length is set according to the prefetch value of the shared target storage unit.

8. A many-to-one DMA access method according to claim 5, characterized in that, In step S500, rearranging the returned data includes: Receive data returned by the shared target storage unit based on multiple AXI IDs; The returned data is sorted and reorganized according to the AXI ID corresponding to the returned data and the original request order; The sorted and reorganized data is returned to the DMA request initiator that initiated the corresponding DMA access request.

9. A many-to-one DMA access device, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, it implements a many-to-one DMA access method as described in any one of claims 5 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements a many-to-one DMA access method as described in any one of claims 5 to 8.

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