Array substrate and display device

Abstract

The invention discloses an array substrate and a display device. The array substrate comprises a substrate body and at least one test unit. The substrate is provided with a display area and a non-display area located on one side of the display area. The test unit is located in the non-display area; the test unit comprises a test element, a test bonding pad and a wire; each port of the test element corresponds to the test bonding pad and the wire, and is connected with the corresponding test bonding pad through the corresponding wire; and the orthographic projection of the test bonding pad on the substrate is circular.

Description

Array substrate and display device Technical Field

[0001] This application belongs to the field of display technology, specifically relating to an array substrate and a display device. Background Technology

[0002] The array substrate is the main structure of a display and requires relevant testing to ensure product yield. Current testing of array substrates includes Electronic Performance Measurement (EPM) of the Thin Film Transistor (TFT). EPM involves setting up TFT test element groups (TEGs) on the array substrate, and using customized probes from the EPM equipment to penetrate the square pads of the TEGs for testing. If even one probe deviates from the square pad, the entire substrate risks being scrapped. Summary of the Invention

[0003] This application provides an array substrate and a display device, which aims to at least partially solve the problem of probes easily deviating from the pads.

[0004] In a first aspect of this application, an array substrate is provided, the array substrate comprising: a substrate having a display area and a non-display area located on one side of the display area; at least one test unit located in the non-display area; the test unit comprising a test element, a test pad, and a trace; each port of the test element corresponding to the test pad and the trace, and connected to the corresponding test pad through the corresponding trace; the orthographic projection of the test pad on the substrate is circular.

[0005] In some embodiments, the test element is a transistor with three ports, and the test unit includes three test pads and three traces, each of which corresponds to one of the three ports of the test element.

[0006] In some embodiments, the centers of the orthographic projections of the three test pads onto the substrate are not collinear.

[0007] In some embodiments, the orthographic projections of two of the test pads on the substrate are located on a first side of the orthographic projection of the test element on the substrate; the orthographic projection of the other test pad on the substrate is located on a second side of the orthographic projection of the test element on the substrate, the second side being opposite to the first side.

[0008] In some embodiments, the non-display area includes test areas corresponding one-to-one with the test units, and the test units are located within the corresponding test areas; the orthographic projection of the test area on the substrate is a triangle.

[0009] In some embodiments, the line connecting the centers of the two test pads located on the same side of the test element is parallel to one side of the triangle.

[0010] In some embodiments, the array substrate includes a plurality of test units, and the plurality of test areas are arranged in at least one row and multiple columns; the orthographic projection of two adjacent test areas in the same row onto the substrate is a point-symmetric pattern.

[0011] In some embodiments, the plurality of test areas are arranged in at least two rows; the orthographic projection of two adjacent test areas in the same column onto the substrate is an axisymmetric figure, and the axis of symmetry is parallel to the row direction.

[0012] In some embodiments, the orthographic projections of the three test pads onto the substrate are circles of equal size, and the distance between the centers of the orthographic projections of the three test pads onto the substrate is equal.

[0013] In some embodiments, the orthographic projections of the three test pads on the substrate are spaced apart along a first direction.

[0014] In some embodiments, the orthographic projections of the three test pads on the substrate are located on the same side of the orthographic projections of the test element on the substrate; the orthographic projections of the test pads and the test element on the substrate are spaced apart along a second direction, which intersects the first direction.

[0015] In some embodiments, the non-display area includes test areas corresponding one-to-one with the test units, and the test units are located within the corresponding test areas; the orthographic projection of the test area on the substrate is rectangular.

[0016] In some embodiments, the array substrate includes a plurality of the test units, and the plurality of test areas are arranged in an array.

[0017] In some embodiments, the orthographic projections of the three test pads onto the substrate are circles of equal size, and the centers of the orthographic projections of the three test pads onto the substrate are collinear.

[0018] In some embodiments, the orthographic projections of two adjacent test areas onto the substrate overlap by one side. 1. In some embodiments, the array substrate further includes: a pixel circuit located in the display area; the pixel circuit includes a plurality of thin-film transistors, and the test element has the same material, thickness, and aspect ratio as the thin-film transistors.

[0019] In a second aspect of this application, a display device is provided, the display device comprising an array substrate as provided in the first aspect.

[0020] An array substrate and display device according to one or more embodiments of this application include a substrate and at least one test unit. The substrate has a display area and a non-display area located on one side of the display area. The test unit is located in the non-display area and does not affect normal display. The test unit includes test elements, test pads, and traces. Each port of the test element corresponds to a test pad and a trace, and is connected to the corresponding test pad through the corresponding trace. Customized probes of the EPM device are inserted into each test pad of the test unit to test the test element. The orthographic projection of the test pad on the substrate is circular. Compared with a square pad of the same area, the probe's tolerance for offset is improved, thereby increasing the difficulty of the probe offsetting off the pad and reducing the risk of the probe being scrapped due to offset off the square pad. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 shows a top view of the test component group in the related technology.

[0023] Figure 2 shows a schematic diagram of the test unit in Figure 1.

[0024] Figure 3 shows a schematic diagram of the offset of the probe inserted into the pad in Figure 2.

[0025] Figure 4 shows a top view of an array substrate in one or more embodiments of this application.

[0026] Figure 5 shows a top view of the test unit in one embodiment of this application.

[0027] Figure 6 shows a schematic diagram of the offset of the probe inserted into the pad in Figure 5.

[0028] Figure 7 shows a schematic diagram of the distribution of the test units in Figure 5.

[0029] Figure 8 shows a schematic diagram of the process of the solder pad penetrating the probe as shown in Figure 7.

[0030] Figure 9 shows a top view of the test unit in another embodiment of this application.

[0031] Figure 10 shows a schematic diagram of the offset of the pad insertion probe in Figure 9.

[0032] Figure 11 shows a schematic diagram of the distribution of the test units in Figure 9.

[0033] Figure 12 shows a schematic diagram of the electrical characteristic testing process in one or more embodiments of this application.

[0034] Explanation of reference numerals in the attached figures: 10': Pad; 11': Source pad; 12': Drain pad; 13': Gate pad; 20': TFT under test; 30': Connection trace; 40': Test equipment; 41': Probe; 10: Substrate; 11: Display area; 12: Non-display area; 120: Test area; 20: Test unit; 21: Test element; 22: Test pad; 23: Trace. Detailed Implementation

[0035] To enable those skilled in the art to more clearly understand this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0036] Figure 1 is a top view of a TEG in the related technology. Referring to Figure 1, the TEG includes multiple test units, which are arranged in an array on the substrate. Each test unit includes a source pad 11', a drain pad 12', a gate pad 13', a TFT under test 20', and a connection trace 30'. The source pad 11', drain pad 12', gate pad 13', and TFT under test 20' are arranged sequentially at intervals along the row direction of the test unit array. The source pad 11', drain pad 12', and gate pad 13' are connected to the TFT under test 20' through the connection trace 30'. The connection trace 30' connected to the source pad 11' is located on the first side of the TFT under test 20', the connection trace 30' connected to the drain pad 12' is located on the second side of the TFT under test 20', and the connection trace 30' connected to the gate pad 13' is located on the side of the TFT under test 20' closest to the gate pad 13'. The first side and the second side of the TFT 20' to be tested are opposite each other and are adjacent to the side of the TFT 20' to be tested that is close to the gate pad 13'.

[0037] Figure 2 is a schematic diagram of the test unit in Figure 1. Referring to Figure 2, the orthographic projection of the test unit on the substrate is a rectangle with a length X0 = 450 μm and a width Y0 = 200 μm. The orthographic projections of the source pad 11', drain pad 12', and gate pad 13' on the substrate are squares with a side length X1 = 100 μm. The pad spacing X2 = 50 μm. The width W of the space for placing the TFT 20' to be tested is 50 μm, and the critical dimension CD of the connection trace 30' is 16 μm. At this time, the area of ​​the orthographic projection of the test unit on the substrate is X0*Y0 = 90000 μm. 2 The projected area of ​​the pads on the substrate is X1*X1=10000μm 2 The area ratio of the pad relative to the test unit's orthogonal projection on the substrate is 3*X1*X1 / (X0*Y0)=33.33%. Figure 3 is a schematic diagram of the offset of the probe inserted into the pad in Figure 2. Please refer to Figure 3. The maximum offset of the probe in the pad is X3=X1 / 2=50μm, that is, the probe's tolerance offset is 50μm.

[0038] Figure 4 is a top view of an array substrate according to one or more embodiments of this application. Referring to Figure 4, a first aspect embodiment of this application provides an array substrate, which includes a substrate 10 and at least one test unit 20. The substrate 10 has a display area 11 and a non-display area 12 located on one side of the display area 11. The test unit 20 is located within the non-display area 12.

[0039] Figure 5 is a top view of a test unit in one embodiment of this application. Referring to Figure 5, the test unit 20 includes a test element 21, a test pad 22, and a trace 23. Each port of the test element 21 corresponds to a test pad 22 and a trace 23, and is connected to the corresponding test pad 22 through the corresponding trace 23. The orthographic projection of the test pad 22 on the substrate 10 is circular.

[0040] Figure 6 is a schematic diagram of the offset of the probe inserted into the pad in Figure 5. Referring to Figure 6, taking the orthogonal projection of the test pad 22 on the substrate 10 as a circle with radius R = 60 μm as an example, the orthogonal projection area of ​​the test pad 22 on the substrate 10 is π*R*R = 11309.73 μm. 2 The maximum probe offset within the pad, X3, is 60 μm, meaning the probe's tolerance offset is 60 μm. Compared to Figure 3, the probe's tolerance offset increases from 50 μm to 60 μm. The probe's tolerance offset increases by (60 μm - 50 μm) / 50 μm = 20%, while the pad area only increases by 11309.73 μm. 2 -10000μm 2 ) / 10000μm 2=13.09%. As can be seen, the test pads projected onto the substrate in this application are circular. Compared with square pads of the same area, this can increase the probe's tolerance for offset, increase the difficulty of the probe offsetting off the pad, and reduce the risk of the probe being scrapped due to offset off the square pad.

[0041] In summary, the array substrate described above includes a substrate 10 and at least one test unit 20. The substrate 10 has a display area 11 and a non-display area 12 located on one side of the display area 11. The test unit 20 is located within the non-display area 12 and will not affect normal display. The test unit 20 includes a test element 21, test pads 22, and traces 23. Each port of the test element 21 corresponds to a test pad 22 and a trace 23, and is connected to the corresponding test pad 22 through the corresponding trace 23. Probes are inserted into each test pad 22 of the test unit 20 to test the test element 21. The orthographic projection of the test pad 22 on the substrate 10 is circular. Compared with a square pad of the same area, the probe's tolerance for offset is improved, thereby increasing the difficulty of the probe offsetting off the pad, reducing the risk of the probe being scrapped due to offset off the square pad, improving the probe's lifespan, and ensuring the test effect.

[0042] In some embodiments, referring to FIG5, the test element 21 can be a transistor with three ports, and the test unit 20 includes three test pads 22 and three traces 23, which correspond one-to-one with the three ports of the test element 21.

[0043] For example, the three ports of a transistor may include a source, a drain, and a gate, or they may include a collector, an emitter, and a base.

[0044] In one possible embodiment, referring to Figure 5, the centers of the orthographic projections of the three test pads 22 onto the substrate 10 may not be collinear. In this case, the line connecting the centers of the orthographic projections of the three test pads 22 onto the substrate 10 can form a triangle.

[0045] For example, referring to Figure 5, the orthographic projections of two test pads 22 on the substrate 10 can be located on the first side of the orthographic projection of the test element 21 on the substrate 10. The orthographic projection of the other test pad 22 on the substrate 10 can be located on the second side of the orthographic projection of the test element 21 on the substrate 10. The second side of the orthographic projection of the test element 21 on the substrate 10 is opposite to the first side of the orthographic projection of the test element 21 on the substrate 10. By placing the test element 21 in the middle of the three test pads 22, the blank area in the middle of the three test pads 22 can be fully utilized, saving the space occupied by the test unit 20.

[0046] For example, the three test pads 22 can be designated as a first test pad, a second test pad, and a third test pad, with the second test pad located between the first and third test pads. The orthographic projections of the first and third test pads onto the substrate 10 are located on the first side of the orthographic projection of the test element 21 onto the substrate 10. The orthographic projection of the second test pad onto the substrate 10 is located on the second side of the orthographic projection of the test element 21 onto the substrate 10.

[0047] For example, the triangle formed by the center line connecting the orthographic projections of the three test pads 22 onto the substrate 10 can be an acute triangle.

[0048] For example, referring to Figure 5, the orthographic projections of the three test pads 22 onto the substrate 10 can be circles of equal size. The distance between the centers of the orthographic projections of the three test pads 22 onto the substrate 10 is equal. In this case, the line connecting the centers of the orthographic projections of the three test pads 22 onto the substrate 10 can form an equilateral triangle. This provides a larger space in the blank area between the three test pads 22, facilitating the placement of test components.

[0049] In some embodiments, referring to FIG5, the non-display area 12 includes test areas 120 corresponding one-to-one with the test units 20, and the test units 20 are located within the corresponding test areas 120. The orthographic projection of the test area 120 on the substrate 10 can be triangular to match the setting of the test pads 22.

[0050] For example, the center line connecting two test pads 22 located on the same side of the test element 21 can be parallel to one side of the orthogonal projection of the test area 120 onto the substrate 10. Again, taking three test pads 22 as an example, namely the first test pad, the second test pad, and the third test pad, the second test pad is located between the first and third test pads, the first and third test pads are located on the same side of the test element 21, and the center line connecting the orthogonal projections of the first and third test pads onto the substrate 10 is parallel to one side of the orthogonal projection of the test area 120 onto the substrate 10.

[0051] For example, the orthographic projection of the test area 120 onto the substrate 10 can be an equilateral triangle.

[0052] Please refer to Figure 5. Taking the orthographic projection of the test pad 22 on the substrate 10 as a circle with radius R = 60 μm as an example, the orthographic projection of the test unit on the substrate (i.e., the test area 120) is an equilateral triangle with side length L = 380 μm. The spacing of the test pads 22 is D = 35 μm. The shortest distance S1 between the orthographic projection of the test pad 22 on the substrate 10 and the edge of the test area 120 is 5 μm. The distance S2 between the center of the orthographic projection of the test pad 22 on the substrate 10 and the vertex of the test area 120 is S2 = (R / 2 + S1) / sin(30° / 2) = 130 μm. The width W of the placement space of the test component 21 is W = (L / 2)*tan60°-(S2 + 2*2*R + S1) = 14 μm. The critical dimension CD of the trace 30 is 10 μm. At this point, the area of ​​the test unit's orthographic projection on the substrate is L*(L / 2)*tan60° / 2=62527.03μm 2 The area of ​​test pad 22 relative to the orthogonal projection of the test unit on the substrate is 3*π*R*R / (L*(L / 2)*tan60° / 2)=54.26%. Compared with Figure 3, the area of ​​the orthogonal projection of the test unit on the substrate has increased from 90000μm. 2 Reduced to 62527.03μm 2 The area ratio of the test pads relative to the test cells increased from 33.33% to 54.26%. Therefore, the arrangement of the test cells in this application can improve the space utilization within the test cells and reduce the area occupied by the test cells, which is beneficial for setting up a larger number of test cells and saving the effective area of ​​the array substrate. Furthermore, the radius R of the orthographic projection of the test pads 22 onto the substrate 10, the critical dimension CD of the traces 30, etc., can all be adjusted according to actual conditions.

[0053] Figure 7 is a schematic diagram of the distribution of the test units in Figure 5. Referring to Figure 7, exemplarily, the array substrate may include multiple test units 20, and multiple test areas 120 arranged in at least one row and multiple columns. The orthographic projection of two adjacent test areas 120 in the same row onto the substrate 10 is a point-symmetric pattern. This facilitates the neat arrangement of the test areas 120 and saves the space occupied by the non-display area 12.

[0054] For example, referring to Figure 7, multiple test areas 120 are arranged in at least two rows. The orthographic projection of two adjacent test areas 120 in the same column onto the substrate 10 is an axisymmetric figure, and the axis of symmetry is parallel to the row direction. This facilitates the neat arrangement of the test areas 120 and saves the space occupied by the non-display area 12.

[0055] For example, referring to Figure 7, the orthographic projections of two adjacent test areas 120 on the substrate 10 can overlap along one edge. This facilitates the neat arrangement of the test areas 120 and saves space occupied by the non-display area 12.

[0056] Figure 8 is a schematic diagram of the process of inserting the probe into the pad in Figure 7. Please refer to Figure 8. The twelve probes are double-sided crimped. First, the test element 21 in the test area 120 with one arrangement is tested. Then, the array substrate 10 is rotated 180° to test the test element 21 in the test area 120 with another arrangement.

[0057] Figure 9 is a top view of the test unit in another embodiment of this application. Referring to Figure 9, in another possible embodiment, the orthographic projections of the three test pads 22 on the substrate 10 can be arranged at intervals along a first direction. In this case, the orthographic projections of the three test pads 22 on the substrate 10 are located in the same row.

[0058] Taking the three test pads 22 as an example, which can be designated as the first test pad, the second test pad, and the third test pad, with the second test pad located between the first and third test pads, the orthographic projections of the first, second, and third test pads on the substrate 10 are arranged in a row.

[0059] For example, referring to Figure 9, the orthographic projections of the three test pads 22 on the substrate 10 can be located on the same side as the orthographic projection of the test element 21 on the substrate 10. The orthographic projections of the test pads 22 and the test element 21 on the substrate 10 are arranged at intervals along a second direction, which intersects with the first direction. In this way, the test element 21 and the traces 30 are all located on the same side of the three test pads 22, which facilitates the connection of the test element 21 to the three test pads 22 through the traces 30, and reduces the space occupied by the traces 30, thereby saving space occupied by the test unit 20.

[0060] For example, the second direction may be perpendicular to the first direction, and the orthographic projections of one of the three test pads 22 and the test element 21 on the substrate 10 are spaced apart along the second direction.

[0061] For example, referring to Figure 9, the orthographic projections of the three test pads 22 onto the substrate 10 can be circles of equal size. The centers of the orthographic projections of the three test pads 22 onto the substrate 10 are collinear. In this case, the centers of the orthographic projections of the three test pads 22 onto the substrate 10 are collinear and their areas are the same, so that the area occupied by each test pad 22 can be maximized, and the space occupied by the test unit is not wasted.

[0062] In some embodiments, referring to FIG9, the non-display area 12 includes test areas 120 corresponding one-to-one with the test units 20, and the test units 20 are located within the corresponding test areas 120. The orthographic projection of the test area 120 on the substrate 10 can be rectangular to match the setting of the test pads 22.

[0063] For example, the orthographic projection of the test area 120 onto the substrate 10 can be rectangular.

[0064] Referring to Figure 9, and still taking the orthographic projection of the test pad 22 onto the substrate 10 as a circle with radius R = 60 μm as an example, the orthographic projection of the test unit onto the substrate (i.e., the test area 120) is a rectangle with length X0 = 450 μm and width Y0 = 200 μm. The spacing between the test pads 22 is D = (X0 / 3 - R) = 30 μm, the width of the space for placing the test component 21 is W = 50 μm, and the critical dimension CD of the trace 30 is 10 μm. In this case, the area of ​​the orthographic projection of the test unit onto the substrate is X0 * Y0 = 90000 μm. 2 The area of ​​test pad 22 relative to the orthogonal projection of the test unit on the substrate is 3*π*R*R / (X0*Y0)=37.70%. Compared with Figure 3, the area of ​​the orthogonal projection of the test unit on the substrate remains unchanged, but the area ratio of the test pad relative to the test unit increases from 33.33% to 37.70%.

[0065] The radius R of the orthographic projection of the test pad 22 onto the substrate 10 and the critical dimension CD of the trace 30 can be adjusted according to actual conditions. For example, the orthographic projection of the test pad 22 onto the substrate 10 may be a circle with radius R = 70 μm, and the orthographic projection of the test unit on the substrate (i.e., the test area 120) may still be a rectangle with length X0 = 450 μm and width Y0 = 200 μm. The spacing between the test pads 22 may be D = (X0 / 3 - R) = 10 μm, the width W of the space for placing the test component 21 may be 50 μm, and the critical dimension CD of the trace 30 may be 3 μm. In this case, the area of ​​the orthographic projection of the test unit on the substrate is X0 * Y0 = 90000 μm. 2 The area of ​​the test pad 22 relative to the orthogonal projection of the test unit on the substrate is 3*π*R*R / (X0*Y0)=51.31%. Compared with Figure 3, the area of ​​the orthogonal projection of the test unit on the substrate remains unchanged, but the area ratio of the test pad relative to the test unit increases from 33.33% to 51.31%. Therefore, the arrangement of the test units in this application can improve the space utilization within the test units without changing the area occupied by the test units.

[0066] Furthermore, the probe's tolerance offset is further increased. Figure 10 is a schematic diagram of the probe offset when the pad is inserted into the substrate 10 as shown in Figure 9. Referring to Figure 10, when the orthogonal projection of the test pad 22 onto the substrate 10 is a circle with radius R = 70 μm, the maximum offset of the probe in the pad is X3 = 70 μm, that is, the probe's tolerance offset is 70 μm. Compared with Figure 6, the probe's tolerance offset increases from 60 μm to 70 μm. Compared with Figure 3, the probe's tolerance offset increases from 50 μm to 70 μm.

[0067] Figure 11 is a schematic diagram of the distribution of the test units in Figure 9. Referring to Figure 11, by way of example, the array substrate may include multiple test units 20 and multiple test areas 120 arranged in an array. This facilitates the neat arrangement of the test areas 120 and saves the space occupied by the non-display area 12.

[0068] For example, referring to Figure 11, the orthographic projections of two adjacent test areas 120 on the substrate 10 can overlap along one edge. This facilitates the neat arrangement of the test areas 120 and saves space occupied by the non-display area 12.

[0069] In some embodiments, the array substrate may further include pixel circuitry located in the display area 11. The pixel circuitry includes multiple thin-film transistors, and the test element 21 is identical to the thin-film transistors in material, thickness, and aspect ratio.

[0070] Semiconductor photolithography follows a sequence of cleaning, deposition, exposure, development, etching, and lift-off to form film layers with a pattern identical to the photomask, such as source / drain (SD) layers, gate (Gate) layers, semiconductor layers, and gate insulator (GI) layers. The source / drain, gate, semiconductor, and gate insulator layers work together to form a TFT. However, the characteristics of the TFTs in the active area (AA) cannot be directly obtained from the above process; currently, EPM (Engineering Processing) is performed by placing TFT TEGs in the non-display area.

[0071] In this application, the test unit 20 serves as a TFT TEG. The transistor serving as the test element 21 is fabricated at the same time and using the same process as the TFT within the AA, and its materials, film thickness, aspect ratio, etc., are all consistent with the TFT within the AA. Therefore, the test results of the transistor serving as the test element 21 can reflect the characteristics of the TFT within the AA. The three ports of the transistor serving as the test element 21 are each connected to the test pads 22 via traces 23. By simultaneously inserting the probes of the test equipment into the three test pads 22 connected to one transistor, the electrical characteristics of the transistor serving as the test element 21 can be tested. Thus, the electrical characteristics of the TFT within the AA can be determined from the test results of the transistor serving as the test element 21.

[0072] Figure 12 is a schematic diagram of the EPM process in one or more embodiments of this application. Referring to Figure 12, the probes 41' of the test device 40' are inserted into the three test pads 22 of the transistor, which serves as the test element 21, and connected by the traces 23. The pre-set test signal is input to the test element 21, and the feedback signal from the test element 21 is received and processed to perform various tests, such as threshold voltage Vth, mobility, dynamic range DR Range, subthreshold swing SS, on-current Ion, off-current Ioff, hysteresis Hys, contact resistance Rc, load resistance Rs, capacitance Cap, etc.

[0073] For example, the test apparatus may include twelve probes. Each probe inserts into one test pad 22, and the twelve probes can insert into twelve test pads 22 simultaneously (using single-sided or double-sided crimping). Since each test element 21 is connected to three test pads 22, the twelve probes can simultaneously insert into four pads connected to the test elements 21. The goal of each probe is to insert into the center point of the corresponding test pad 22.

[0074] However, probes undergo plastic deformation during long-term use, causing some probes to shift. Some probes may not be centered on their corresponding pads. Because probes are precision components and cannot be repaired, and given their high cost and long lead times, if even one probe shifts off-center from a pad, it risks being rendered unusable.

[0075] The test pad 22 of this application has a circular orthographic projection on the substrate 10. Compared with a square pad of the same area, the probe's tolerance for offset is improved, thereby increasing the difficulty of the probe offsetting off the pad, reducing the risk of the probe being scrapped due to offset off the square pad, improving the probe's service life, and ensuring the test effect.

[0076] A second aspect of this application provides a display device that includes an array substrate as provided in the first aspect embodiment.

[0077] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0078] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", and "counterclockwise" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0079] In this application, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0080] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0081] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, characterized in that, The array substrate includes: a substrate (10) having a display area (11) and a non-display area (12) located on one side of the display area (11); at least one test unit (20) located in the non-display area (12); the test unit (20) includes a test element (21), a test pad (22) and a trace (23); each port of the test element (21) corresponds to the test pad (22) and the trace (23), and is connected to the corresponding test pad (22) through the corresponding trace (23); the orthographic projection of the test pad (22) on the substrate (10) is circular.

2. The array substrate according to claim 1, characterized in that, The test element (21) is a transistor with three ports. The test unit (20) includes three test pads (22) and three traces (23). The three test pads (22) and the three traces (23) correspond one-to-one with the three ports of the test element (21).

3. The array substrate according to claim 2, characterized in that, The centers of the orthographic projections of the three test pads (22) onto the substrate (10) are not collinear.

4. The array substrate according to claim 3, characterized in that, The orthographic projections of two of the test pads (22) on the substrate (10) are located on the first side of the orthographic projection of the test element (21) on the substrate (10); the orthographic projection of the other test pad (22) on the substrate (10) is located on the second side of the orthographic projection of the test element (21) on the substrate (10), and the second side is opposite to the first side.

5. The array substrate according to claim 4, characterized in that, The non-display area (12) includes test areas (120) that correspond one-to-one with the test units (20), and the test units (20) are located within the corresponding test areas (120); the orthographic projection of the test areas (120) on the substrate (10) is a triangle.

6. The array substrate according to claim 5, characterized in that, The center line connecting the two test pads (22) located on the same side of the test element (21) is parallel to one side of the triangle.

7. The array substrate according to claim 5, characterized in that, The array substrate includes multiple test units (20), and multiple test areas (120) are arranged in at least one row and multiple columns; the orthographic projection of two adjacent test areas (120) in the same row onto the substrate (10) is a point-symmetric pattern.

8. The array substrate according to claim 6, characterized in that, The test areas (120) are arranged in at least two rows; the orthographic projection of two adjacent test areas (120) in the same column onto the substrate (10) is an axisymmetric figure, and the axis of symmetry is parallel to the row direction.

9. The array substrate according to any one of claims 3-8, characterized in that, The orthographic projections of the three test pads (22) onto the substrate (10) are circles of equal size, and the distance between the centers of the orthographic projections of the three test pads (22) onto the substrate (10) is equal.

10. The array substrate according to claim 2, characterized in that, The three test pads (22) are arranged at intervals along a first direction on the orthographic projection of the substrate (10).

11. The array substrate according to claim 10, characterized in that, The orthographic projections of the three test pads (22) on the substrate (10) are located on the same side as the orthographic projection of the test element (21) on the substrate (10); the orthographic projections of the test pads (22) and the test element (21) on the substrate (10) are spaced apart along a second direction, which intersects the first direction.

12. The array substrate according to claim 11, characterized in that, The non-display area (12) includes test areas (120) that correspond one-to-one with the test units (20), and the test units (20) are located within the corresponding test areas (120); the orthographic projection of the test areas (120) on the substrate (10) is rectangular.

13. The array substrate according to claim 12, characterized in that, The array substrate includes multiple test units (20) and multiple test areas (120) arranged in an array.

14. The array substrate according to any one of claims 10-13, characterized in that, The orthographic projections of the three test pads (22) onto the substrate (10) are circles of equal size, and the centers of the orthographic projections of the three test pads (22) onto the substrate (10) are collinear.

15. The array substrate according to any one of claims 7, 8, and 13, characterized in that, The two adjacent test areas (120) have one side of their orthographic projection on the substrate (10) overlapping.

16. The array substrate according to any one of claims 2-8 and 10-13, characterized in that, The array substrate further includes a pixel circuit located in the display area (11); the pixel circuit includes a plurality of thin-film transistors, and the test element (21) is identical to the thin-film transistors in terms of material, thickness and aspect ratio.

17. A display device, characterized in that, The display device includes the array substrate as described in claims 1-16.

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