Display device

Abstract

According to an embodiment of the present disclosure, a display device having improved moisture barrier characteristics is provided. The display device may include: a display panel including a display area and a non-display area; a power line disposed in the non-display area; a plurality of metal layers extending from a portion of the power line and including a groove portion having a partially recessed side surface; and a shielding layer corresponding to the groove portion of the metal layer.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an apparatus, and more specifically, for example, and not limitingly, to a display device. Background Technology

[0002] With the advent of the information age, the field of displays that visually present electrical information signals has developed rapidly. In response, various types of display devices have been developed that offer excellent performance in terms of thickness, light weight, and low power consumption.

[0003] Display devices used to provide images to users such as televisions, mobile phones, tablets, computers, navigation systems, and game consoles may include display panels that generate and display images.

[0004] A display panel may include multiple pixels, driving units for driving the pixels, and signal lines for sending electrical signals to the pixels. The pixels, driving units, and signal lines included in the display panel may be damaged or degraded by moisture or foreign matter introduced from the outside. Therefore, there is a need to research and develop methods to prevent damage and defects to the display panel caused by moisture or foreign matter. Summary of the Invention

[0005] Embodiments of this disclosure can provide a display device with excellent moisture barrier properties by including multiple metal layers formed on a portion of the power line to increase the moisture permeation path.

[0006] Embodiments of this disclosure may provide a display device that prevents or reduces the formation of cracks in an inorganic material disposed on the upper portion of a metal layer by including a shielding layer covering a recessed portion formed on the side of a metal layer.

[0007] Embodiments of this disclosure can provide a display device with improved moisture barrier properties by including multiple inorganic layers covering power lines and metal layers in non-display areas.

[0008] The objectives addressed by the embodiments of this disclosure are not limited to those described above, and other objectives not mentioned will be readily apparent to those skilled in the art from the following detailed description.

[0009] Embodiments of this disclosure may provide a display device comprising: a display panel including a display area and a non-display area; power lines disposed in the non-display area; a plurality of metal layers extending from a portion of the power lines and including recessed portions having partially recessed side surfaces; and a shielding layer corresponding to the recessed portions of the metal layers.

[0010] According to embodiments of this disclosure, a display device with excellent moisture barrier properties can be provided by including multiple metal layers formed on a portion of the power lines to increase the moisture penetration path.

[0011] According to embodiments of the present disclosure, a display device can be provided that prevents or reduces cracks in an inorganic material disposed on the upper portion of a metal layer by including a shielding layer covering a recessed portion formed on the side of a metal layer.

[0012] According to embodiments of this disclosure, a display device with improved moisture barrier performance can be provided by including multiple inorganic layers covering a metal layer and power lines in the non-display area.

[0013] According to embodiments of this disclosure, a display device capable of process optimization can be provided by using the same material as the embankment to form the shielding layer, thereby allowing the embankment and the shielding layer to be formed together.

[0014] The effects of the embodiments disclosed herein are not limited to those described above, and those skilled in the art will clearly understand from the claims additional effects not mentioned herein.

[0015] Other systems, methods, features, and advantages will be apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, within the scope of this disclosure, and protected by the appended claims. Nothing in this section should be construed as limiting those claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0016] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0017] This disclosure will be more fully understood from the following detailed description and accompanying drawings. The detailed description and accompanying drawings are provided for illustrative purposes only and are not intended to limit the scope of this specification.

[0018] Figure 1 This is a schematic diagram illustrating the configuration of a display device 100 according to an embodiment of the present disclosure.

[0019] Figure 2 This is a schematic diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure.

[0020] Figure 3 This is a plan view of a display panel according to an embodiment of the present disclosure.

[0021] Figure 4It is according to the embodiments of this disclosure along Figure 3 A cross-sectional view taken from line A-A'.

[0022] Figure 5 It is based on the embodiments of this disclosure. Figure 3 An enlarged plan view of region "S" in the image.

[0023] Figure 6 It is according to the embodiments of this disclosure along Figure 5 The cross-sectional view taken by line B-B'.

[0024] Figure 7 This is a cross-sectional view of a metal layer according to one embodiment of the present disclosure.

[0025] Figure 8 This is an example of an embodiment of the present disclosure. Figure 7 A schematic diagram of the shielding layer in the grooved portion of the metal layer shown.

[0026] Figure 9 This is a cross-sectional view of a display panel according to another embodiment of the present disclosure.

[0027] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals shall be construed as referring to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and depictions of these elements may be exaggerated. Detailed Implementation

[0028] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that may be implemented by way of example, and the same reference numerals and symbols may be used to designate the same or similar components even when shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components included herein may be omitted or may be discussed only briefly when it is determined that such detailed descriptions would make the subject matter of some embodiments of this disclosure less clear. Unless a term is used with the term “only,” terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional components. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0029] The advantages and features of this disclosure, and methods of implementing them, will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. These exemplary embodiments are provided, in contrast, to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0030] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative sizes and depictions of these elements may be enlarged. The described process steps and / or operation sequence is an example; however, the order of steps and / or operations is not limited to that described herein, and may be modified as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals refer to the same elements throughout the text. The names of the various elements used in the following description are chosen solely for ease of writing and may therefore differ from the names used in actual products.

[0031] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings to describe embodiments of this disclosure are merely examples. Therefore, this disclosure is not limited to the details shown. The same reference numerals always refer to the same elements. In the following description, a detailed description of a known function or configuration may be omitted when it is determined that such a description would unnecessarily obscure the focus of this disclosure. When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless "only" is used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context clearly indicates otherwise.

[0032] Any implementation described in this article as an "example" is not necessarily to be interpreted as preferred or advantageous over other implementations.

[0033] In the description of various embodiments of this disclosure, when describing positional relationships (e.g., when describing the positional relationship between two components as "above," "over," "below," "adjacent," etc.), one or more other components may be located between the two components unless more restrictive terms such as "exactly" or "directly" are used. For example, when one element or layer is disposed "above" another element or layer, a third layer or element may be interposed therebetween.

[0034] The terms “first element,” “second element,” and / or “third element” should be understood as one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0035] The term “at least one” should be understood to include any and all combinations of one or more associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0036] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0037] When referring to a first element being "connected or linked to" a second element, or "in contact with or overlapping" a second element, it should be interpreted as meaning that the first element can not only be "directly connected or linked to" the second element or "directly contact with or overlap" a second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or linked to" or "in contact with or overlap" each other through a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or linked" or "in contact with or overlap" each other.

[0038] When time-relative terms such as “after,” “following,” “next,” “before,” etc., are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations unless used together with the terms “direct” or “immediate.”

[0039] Furthermore, when referring to any size, relative size, etc., even without a specific description, it should be assumed that the numerical values ​​or corresponding information of the component or feature (e.g., level, range, etc.) include the range of tolerances or errors that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "may".

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions.

[0041] In contrast, these embodiments may be provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0042] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be partially or entirely linked or combined with each other, and may be interoperable and technically driven differently from each other. The embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0043] Various embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 This is a schematic diagram illustrating the configuration of a display device according to an embodiment of the present disclosure, and Figure 2 This is a diagram illustrating the configuration of a display panel according to an embodiment of the present disclosure.

[0045] Reference Figure 1 and Figure 2 The display device 100 may include a display panel 10 as a component for displaying images and a display driving circuit for driving the display panel 10.

[0046] The display panel 10 may include a display area AA for displaying images and a non-display area NA for not displaying images. The non-display area NA may be an outer area of ​​the display area AA and may correspond to a border area. All or part of the non-display area NA may be visible on the front surface of the display device 100, or may be curved and therefore not visible from the front surface of the display device 100.

[0047] The display panel 10 may include a plurality of sub-pixels SP. The display panel 10 may also include various types of signal lines to drive the plurality of sub-pixels SP. For example, the signal lines may include a plurality of data lines DL that transmit data signals (also known as data voltages or image signals) and a plurality of gating lines GL that transmit gating signals (also known as scan signals). However, embodiments of this disclosure are not limited thereto.

[0048] Multiple data lines (DL) and multiple gating lines (GL) can intersect each other. Each of the multiple data lines (DL) can extend in a first direction, and each of the gating lines (GL) can be configured to extend in a second direction. The first direction can correspond to the column direction and the second direction can correspond to the row direction, or vice versa.

[0049] The display device 100 according to embodiments of the present disclosure may be a liquid crystal display device or a self-emissive display device in which the display panel 10 emits its own light. In the case that the display device 100 is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting device ED and a pixel driving circuit SPC for driving the light-emitting device ED.

[0050] The pixel driving circuit SPC may include a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0051] The driving transistor DRT controls the current flowing through the light-emitting device ED to drive it. The scanning transistor SCT delivers the data voltage VDATA to the second node N2, which serves as the gate node of the driving transistor DRT. The storage capacitor Cst can be configured to maintain the voltage for a predetermined period of time.

[0052] The light-emitting device (ED) may include a first electrode AE, a second electrode CE, and a light-emitting layer EL disposed between the first electrode and the second electrode. The first electrode AE ​​may serve as a pixel electrode involved in the formation of the ED for each sub-pixel SP and may be electrically connected to a first node N1 of the driving transistor DRT. The second electrode CE may serve as a common electrode involved in the formation of the ED for all sub-pixels SP and may receive a base voltage EVSS.

[0053] For example, the light-emitting device ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), or a quantum dot light-emitting device that includes a self-emissive semiconductor crystal. However, the embodiments disclosed herein are not limited thereto.

[0054] The driving transistor DRT for driving the light-emitting device (ED) may include a first node N1, a second node N2, and a third node N3. The first node N1 may be a source node or a drain node and may be electrically connected to the first electrode AE ​​of the ED. The second node N2 may be a gate node and may be electrically connected to the source node or drain node of the scanning transistor SCT. The third node N3 may be a drain node or a source node and may be electrically connected to the driving voltage line DVL for providing the driving voltage EVDD. For ease of explanation, it is assumed that the first node N1 is a source node and the third node N3 is a drain node, but embodiments of this disclosure are not limited thereto.

[0055] The scanning transistor SCT can switch the connection between the data line DL and the second node N2 of the driving transistor DRT. The scanning transistor SCT can control the connection between the second node N2 of the driving transistor DRT and the corresponding data line DL among multiple data lines DL in response to the scan signal SCAN provided from the scan line SCL (which is a gating line GL). A storage capacitor Cst can be formed between the first node N1 and the second node N2 of the driving transistor DRT.

[0056] Figure 2 The structure of the sub-pixel SP illustrated herein is exemplary for illustrative purposes only and may include one or more additional transistors or one or more additional capacitors. However, embodiments of this disclosure are not limited thereto. Multiple sub-pixels may all have the same structure, or some may have different structures. Each of the driving transistor DRT and the scanning transistor SCT may be an n-type transistor or a p-type transistor. One of the driving transistor DRT and the scanning transistor SCT may include one of an oxide semiconductor layer, a polycrystalline silicon semiconductor layer, or a low-temperature polycrystalline silicon semiconductor layer, but embodiments of this disclosure are not limited thereto.

[0057] The display driving circuit may include a data driving circuit 11, a gating driving circuit 12, and a display controller 13.

[0058] The data driving circuit 11 can be a circuit for driving multiple data lines DL, and can output data signals to the multiple data lines DL. The gating driving circuit 12 can be a circuit for driving multiple gating lines GL, and can output gating signals to the multiple gating lines GL.

[0059] The display controller 13 can be a device for controlling the data drive circuit 11 and the gating drive circuit 12. The display controller 13 can control the driving timing of multiple data lines DL and the driving timing of multiple gating lines GL.

[0060] The display controller 13 can provide data drive control signals to the data drive circuit 11 to control the data drive circuit 11, and can provide gating drive control signals to the gating drive circuit 12 to control the gating drive circuit 12.

[0061] The data driving circuit 11 can provide data signals to multiple data lines DL based on the driving timing control of the display controller 13. The data driving circuit 11 can receive digital format image data from the display controller 13, convert the received image data into analog data signals, and output the analog data signals to multiple data lines DL.

[0062] The gating drive circuit 12 can provide gating signals to multiple gating lines GL according to the timing control of the display controller 13. The gating drive circuit 12 can receive various gating drive control signals (e.g., start signal, reset signal, etc.), and provide a first gating voltage corresponding to the on level and a second gating voltage corresponding to the off level to generate gating signals, and output the generated gating signals to multiple gating lines GL.

[0063] The gate drive circuit 12 can be connected to the display panel 10 using the tape auto-bonding (TAB) method, or to the bonding pads of the display panel 10 using the chip-on-glass (COG) method or the chip-on-panel (COP) method, or to the display panel 10 using the chip-on-film (COF) method. Alternatively, the gate drive circuit 12 can be formed as a gate-in-panel (GIP) type in the non-display area NA of the display panel 10.

[0064] The gate drive circuit 12 can be disposed on or connected to the substrate, but the embodiments disclosed herein are not limited thereto. For example, when the gate drive circuit 12 is of type GIP, it can be disposed in the non-display area NA of the substrate. When the gate drive circuit 12 is of type COG or COF, it can be connected to the substrate.

[0065] At least one of the data driving circuit 11 and the gating driving circuit 12 may be disposed in the display area AA of the display panel 10. For example, at least one of the data driving circuit 11 and the gating driving circuit 12 may be configured not to overlap with the sub-pixel SP, or may be configured to partially or completely overlap with the sub-pixel SP. However, embodiments of this disclosure are not limited thereto.

[0066] The data driving circuit 11 can be connected to one side of the display panel 10 (e.g., the top or bottom side). Depending on the driving method or panel design method, the data driving circuit 11 can be connected to both sides of the display panel 10 (e.g., the top and bottom sides), or it can be connected to two or more of the four sides of the display panel 10. However, the embodiments of this disclosure are not limited thereto.

[0067] The gating drive circuit 12 can be connected to one side of the display panel 10 (e.g., the left or right side). Depending on the driving method or panel design method, the gating drive circuit 12 can be connected to both sides of the display panel 10 (e.g., the left and right sides), or it can be connected to two or more of the four sides of the display panel 10. However, the embodiments of this disclosure are not limited thereto.

[0068] The display controller 13 can be implemented as a component separate from the data driving circuit 11, or it can be integrated with the data driving circuit 11 and implemented as an integrated circuit. However, the embodiments of this disclosure are not limited thereto.

[0069] The display controller 13 may be a timing controller used in conventional display technology, a controller that includes a timing controller and performs additional control functions, a controller different from a timing controller, or circuitry within a controller. The display controller 13 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors. However, embodiments of this disclosure are not limited thereto.

[0070] The display controller 13 can be mounted on a printed circuit board or flexible printed circuit and can be electrically connected to the data drive circuit 11 and the gating drive circuit 12 via the printed circuit board or flexible printed circuit.

[0071] The display controller 13 can send signals to and receive signals from the data drive circuit 11 based on one or more predefined interfaces. For example, the interface may include a low-voltage differential signaling (LVDS) interface, an EPI interface, or a serial peripheral interface (SPI), but embodiments of this disclosure are not limited thereto.

[0072] The display device 100 according to embodiments of the present disclosure may include a touch panel TP and a touch sensing circuit 14 to provide touch sensing functions in addition to image display functions. The touch sensing circuit 14 can sense the touch panel TP to detect whether a touch object (e.g., a finger or pen) has touched the device, or to detect the touch location. The touch panel TP may be a touch portion, but embodiments of the present disclosure are not limited thereto.

[0073] The touch panel TP can be a touch sensor and may include multiple touch electrodes TE. The touch panel TP can be disposed outside or inside the display panel 10. When the touch panel TP is disposed outside the display panel 10, it is referred to as an external type. In this case, the touch panel TP and the display panel 10 can be manufactured and combined separately during assembly. When the touch panel TP is disposed inside the display panel 10, it is referred to as an embedded type. In this case, the touch panel TP can be formed within the display panel 10 during the manufacturing process of the display panel 10. For example, the touch panel TP can be disposed on the encapsulation layer 170 within the display panel 10.

[0074] The touch sensing circuit 14 may include a touch driving circuit 15 that drives and senses the touch panel TP and generates and outputs touch sensing data, and a touch controller 17 that can use the touch sensing data to detect the occurrence or location of a touch.

[0075] The touch driving circuit 15 can provide a touch driving signal to at least one of the plurality of touch electrodes TE, and can sense at least one of the plurality of touch electrodes TE to generate touch sensing data.

[0076] The touch sensing circuit 14 can perform touch sensing using a self-capacitance sensing method or a mutual capacitance sensing method.

[0077] When the touch sensing circuit 14 performs touch sensing using the self-capacitance sensing method, the touch sensing circuit 14 can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger or a pen).

[0078] According to the self-capacitance sensing method, each of the plurality of touch electrodes can act as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 15 can drive all or some of the plurality of touch electrodes, and can also sense all or some of them.

[0079] When the touch sensing circuit 14 performs touch sensing using the mutual capacitance sensing method, the touch sensing circuit 14 can perform touch sensing based on the capacitance between the touch electrodes.

[0080] According to the mutual capacitance sensing method, multiple touch electrodes may include driving touch electrodes and sensing touch electrodes. The touch driving circuit 15 can drive the touch electrodes and sense the touch electrodes.

[0081] The touch driving circuit 15 and touch controller 17 included in the touch sensing circuit 14 can be implemented as separate devices or as a single device. Additionally, the touch driving circuit 15 and data driving circuit 11 can be implemented as separate devices or as a single device.

[0082] Figure 3This is a plan view of a display panel according to an embodiment of the present disclosure.

[0083] Reference Figure 3 The display panel 10 may include a display area AA and a non-display area NA.

[0084] The display area AA can display an image through multiple sub-pixels SP. The non-display area NA can be located around or surrounding the display area AA. The non-display area NA can include a curved area BA and a pad area PA. The curved area BA can be located on one side of the display area AA, and the pad area PA can be located on one side of the curved area BA. The curved area BA can be a flexible area of ​​the base substrate 110 and can be located between the pad area PA and the display area AA.

[0085] The gating drive circuit 12 can be disposed on both sides of the display area AA. The gating drive circuit 12 can be a gate in panel (GIP) type disposed inside the display panel 10. However, the embodiments of this disclosure are not limited thereto.

[0086] Figure 4 Is it along this Figure 3 A cross-sectional view taken from line A-A'.

[0087] Reference Figure 4 The display panel 10 may include a base substrate 110, a thin film transistor 120, a first planarization layer 130, a second planarization layer 140, a first electrode AE, a contact electrode 150, a dam layer 160, a light-emitting layer EL, a second electrode CE, an encapsulation layer 170, and a protective layer 180.

[0088] The base substrate 110 is used to support various components of the display device 100 and can be formed of an insulating material such as a glass substrate or a plastic substrate.

[0089] The base substrate 110 can be disposed in the display area AA and the non-display area NA, and can be composed of multiple layers. For example, the base substrate 110 may include a first base substrate 111, a second base substrate 112 and an insulating layer 113 disposed between the first base substrate 111 and the second base substrate 112.

[0090] The first base substrate 111 and the second base substrate 112 can be formed of polyimide (PI). Polyimide is a polymer with relatively low crystallinity or a mostly amorphous structure, which is easy to synthesize into thin films and has advantages in terms of transparency, heat resistance, and mechanical properties. However, since polyimide has poor moisture barrier properties, the moisture barrier properties of the base substrate 110 can be improved by providing an insulating layer 113 made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) between the first base substrate 111 and the second base substrate 112.

[0091] Multiple buffer layers for blocking moisture and oxygen from entering can be disposed on the second base substrate 112. For example, the buffer layers may include multiple buffer layers 114 and active buffer layers 115.

[0092] The multiple buffer layer 114 is used to block the entry of moisture and oxygen, and can be formed of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), or aluminum oxide (Al2O3). In this embodiment, the multiple buffer layer 114 is illustrated as comprising two layers, but it can comprise one, two, or more layers.

[0093] The active buffer layer 115 can be disposed on the multi-buffer layer 114 and can be formed of an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON) or aluminum oxide (Al2O3).

[0094] The thin-film transistor 120 can be disposed on the base substrate 110 and can include a first thin-film transistor 121 and a second thin-film transistor 122.

[0095] The first thin-film transistor 121 may include a first semiconductor layer 21, a first gate electrode 22, a first source electrode 23, and a first drain electrode 24.

[0096] The first semiconductor layer 21 can be formed on the active buffer layer 115. The first semiconductor layer 21 may include a channel region, a source region, and a drain region. The channel region can overlap with the first gate electrode 22 through the first interlayer insulating layer 116a, and can be formed between the first source electrode 23 and the first drain electrode 24. The source region can be electrically connected to the first source electrode 23, and the drain region can be electrically connected to the first drain electrode 24.

[0097] The first gate electrode 22 may be formed on the first interlayer insulating layer 116a. For example, the first gate electrode 22 may overlap with the channel region of the first semiconductor layer 21 through the first interlayer insulating layer 116a. The first gate electrode 22 may be formed of a single layer or multiple layers of any one or a combination of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0098] The first gate electrode 22 may be covered by a first gate insulating layer 117a, a second interlayer insulating layer 116b, a second gate insulating layer 117b, and a third interlayer insulating layer 116c.

[0099] The first source electrode 23 can penetrate the first interlayer insulating layer 116a, the first gate insulating layer 117a, the second interlayer insulating layer 116b, the second gate insulating layer 117b and the third interlayer insulating layer 116c, and can be connected to the source region of the first semiconductor layer 21.

[0100] The first drain electrode 24 can be configured to face the first source electrode 23 and can penetrate the first interlayer insulating layer 116a, the first gate insulating layer 117a, the second interlayer insulating layer 116b, the second gate insulating layer 117b and the third interlayer insulating layer 116c, and can be connected to the drain region of the first semiconductor layer 21.

[0101] The second thin-film transistor 122 may be configured to be spaced apart from the first thin-film transistor 121, and may include a second semiconductor layer 25, a second gate electrode 26, a second source electrode 27, and a second drain electrode 28.

[0102] The second semiconductor layer 25 can be formed on the second interlayer insulating layer 116b. The second semiconductor layer 25 may include a channel region, a source region, and a drain region. The channel region can overlap with the second gate electrode 26 through the second gate insulating layer 117b, and can be formed between the second source electrode 27 and the second drain electrode 28. The source region can be electrically connected to the second source electrode 27, and the drain region can be electrically connected to the second drain electrode 28.

[0103] The second gate electrode 26 may be formed on the second gate insulating layer 117b and may be covered by the third interlayer insulating layer 116c. For example, the second gate electrode 26 may overlap with the channel region of the second semiconductor layer 25, and the first interlayer insulating layer 116a may be inserted therebetween. The second gate electrode 26 may be formed of a single layer or multiple layers of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0104] The second source electrode 27 can penetrate the second gate insulating layer 117b and the third interlayer insulating layer 116c and be connected to the source region of the second semiconductor layer 25.

[0105] The second drain electrode 28 can be configured to face the second source electrode 27 and can penetrate the second gate insulating layer 117b and the third interlayer insulating layer 116c, and be connected to the drain region of the second semiconductor layer 25.

[0106] In this embodiment, the first thin-film transistor 121 can be used as a scanning transistor (SCT), and the second thin-film transistor 122 can be used as a driving transistor (DRT). However, this disclosure is not limited to the example shown.

[0107] Storage capacitor 133 (Cst) can be disposed between the first thin film transistor 121 and the second thin film transistor 122.

[0108] The storage capacitor 133 can be configured such that the first storage electrode 33a and the second storage electrode 33b overlap with the first gate insulating layer 117a interposed therebetween.

[0109] The first storage electrode 33a can be electrically connected to the second gate electrode 26 or the second source electrode 27 of the second thin-film transistor 122. For example, the first storage electrode 33a can be disposed on the first interlayer insulating layer 116a and can be formed in the same layer and the same material as the first gate electrode 22.

[0110] The second storage electrode 33b can be disposed on the first gate insulating layer 117a and can be electrically connected to the second gate electrode 26 or the second source electrode 27 of the second thin-film transistor 122 via the storage power line 33c. For example, the storage power line 33c can pass through the second interlayer insulating layer 116b, the second gate insulating layer 117b and the third interlayer insulating layer 116c to connect to the second storage electrode 33b.

[0111] The first planarization layer 130 may be disposed on the third interlayer insulating layer 116c formed on the base substrate 110, and may include a first contact hole 131 in the region overlapping with the second source electrode 27. For example, the first planarization layer 130 may be formed of an organic material such as photoacrylic acid (PAC), and may mitigate the step difference caused by the assembly of the first thin-film transistor 121, the second thin-film transistor 122, and the storage capacitor 133 disposed on the third interlayer insulating layer 116c.

[0112] The second planarization layer 140 may be disposed on the first planarization layer 130. For example, the second planarization layer 140 may be formed of an organic material such as photoacrylic acid (PAC) and may include a second contact hole 141 in the region between the second source electrode 27 and the second drain electrode 28.

[0113] The first electrode AE ​​can be disposed on the second planarization layer 140. In this embodiment, the first electrode AE ​​can be an anode electrode.

[0114] The contact electrode 150 can be inserted between the first planarization layer 130 and the second planarization layer 140, and can electrically connect the thin-film transistor 120 and the first electrode AE. For example, the contact electrode 150 can be disposed on the first planarization layer 130, and can be electrically connected to the second source electrode 27 of the second thin-film transistor 122 through the first contact hole 131.

[0115] The dam layer 160 can be disposed on the second planarization layer 140 to divide pixels. For example, the dam layer 160 disposed in the display area AA can have an opening 161 that exposes a portion of the first electrode AE ​​located below.

[0116] The barrier layer 160 can be formed of a material containing black pigment, or it can be composed of organic materials such as benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer. However, embodiments of the present disclosure are not limited thereto. When the barrier layer 160 is formed of a material containing black pigment or black dye, the barrier layer 160 can be referred to as a black barrier. Using a material containing black pigment or black dye to form the barrier layer 160 can block light from external sources or reflected light, thereby further improving the brightness of the display device.

[0117] The dam layer 160 may include spacers 162 for preventing or reducing damage caused by the mask used in forming the light-emitting layer EL.

[0118] The light-emitting layer EL can be disposed on the dam layer 160 and the first electrode AE. For example, the light-emitting layer EL can be in contact with the first electrode AE ​​exposed through the opening 161 of the dam layer 160. In this embodiment, the light-emitting layer EL can be an organic light-emitting layer including an organic compound layer (e.g., a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting material layer (EML), an electron transfer layer (ETL), and an electron injection layer (EIL)), but this disclosure is not limited thereto.

[0119] The second electrode CE can be disposed on the light-emitting layer EL. In this embodiment, the second electrode CE can be a cathode electrode.

[0120] The encapsulation layer 170 can be disposed on the second electrode CE. For example, the encapsulation layer 170 can cover the second electrode CE to protect the light-emitting device ED from external moisture, oxygen, impact, etc.

[0121] The encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 172, and a third encapsulation layer 173.

[0122] The first encapsulation layer 171 can be disposed on the second electrode CE and can be formed from an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), or aluminum oxide (Al2O3) that can be deposited at low temperatures. When the first encapsulation layer 171 is deposited at a low temperature atmosphere, it can prevent or reduce damage to the light-emitting layer EL containing organic materials (which may be susceptible to high-temperature conditions during the deposition process).

[0123] The second encapsulation layer 172 may be disposed on the first encapsulation layer 171. For example, the second encapsulation layer 172 may be formed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon carbide (SiOC). Since the second encapsulation layer 172 is formed of an organic material, it can simultaneously seal the underlying components and mitigate step differences.

[0124] The third encapsulation layer 173 may be disposed on the second encapsulation layer 172. For example, the third encapsulation layer 173 may be formed of an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), or aluminum oxide (Al2O3).

[0125] As described above, since the encapsulation layer 170 consists of multiple layers, it can effectively protect the light-emitting device ED by minimizing the penetration of moisture and oxygen from the outside.

[0126] According to this embodiment, the touch portion TS can be disposed on the encapsulation layer 170. For the insulation and manufacturing of the touch portion TS, both the touch buffer layer 118 and the touch insulating layer 119, which are formed of inorganic materials, can be disposed on the encapsulation layer 170.

[0127] A touch buffer layer 118 may be disposed on the encapsulation layer 170. A touch portion TS, including a touch metal TSM and a bridging metal BRG, may be disposed on the touch buffer layer 118. A touch insulating layer 119 may be disposed on the touch buffer layer 118, and the touch metal TSM and the bridging metal BRG may make contact through openings formed in the touch insulating layer 119.

[0128] The touch portion TS can be covered by a protective layer 180 disposed on the touch insulating layer 119. Therefore, the protective layer 180 can cover the underlying components and patterns, and can reduce height differences caused by the structure. For example, the protective layer 180 can be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. However, the material of the protective layer 180 is not limited to this, and the protective layer can also be formed of at least one inorganic material and at least one organic material. Embodiments of this disclosure are not limited thereto.

[0129] Figure 5 yes Figure 3 An enlarged plan view of region "S" in the diagram, and Figure 6 It is along Figure 5 The cross-sectional view taken by line B-B'.

[0130] Reference Figure 5 and Figure 6 The display device 100 may include a display panel 10, power lines 20, a metal layer 30, and a shielding layer 40.

[0131] The display panel 10 may include a display area AA and a non-display area NA. The display panel 10 may include a plurality of inorganic layers 610, 620, and 630 located on a base substrate 110. Here, the inorganic layers 610, 620, and 630 may be connected to… Figure 3 and Figure 4 This corresponds to all or some of layers 114 to 116c. Other configurations of the display panel 10 are the same as those described in the previous embodiments and will not be described in detail again.

[0132] The power line 20 can be located in the non-display area NA and can include a first power line 20A and a second power line 20B. For example, the first power line 20A can include one of a common power line (VSS) and a drive current line (VDD), and the second power line 20B can include the other of the common power line (VSS) and the drive current line (VDD).

[0133] In this embodiment, for ease of explanation, it is assumed that the first power line 20A includes a common power line VSS, and the second power line 20B includes a drive current line VDD.

[0134] The first electric field line 20A can be used to provide a low potential voltage to the second electrode CE, and a portion of it can be disposed in the non-display area NA formed below the display area AA.

[0135] The second power line 20B can be used to provide a high potential voltage higher than the low potential voltage to the drive voltage line DVL, and a portion of it can be disposed in the non-display area NA along the first power line 20A. That is, the first power line 20A and the second power line 20B can be arranged to face each other in a spaced-out manner.

[0136] Metal layer 30 can be disposed in the non-display area NA to extend the path that moisture can enter along the power line 20. For example, metal layer 30 can be disposed in the non-display area NA between the display area AA and the curved area BA. In this embodiment, three metal layers 30 are illustrated, but the number is not limited to this and can be greater. As the number of metal layers 30 increases, the moisture penetration path of the power line 20 can become longer.

[0137] The metal layer 30 can be formed of the same material as the contact electrode 150, and can be configured as multiple structures extending from a portion of the side surface of the electric field line 20. For example, multiple metal layers 30 extending from one side of the electric field line 20 can be spaced apart from each other at regular intervals. Therefore, by providing the metal layer 30 on the electric field line 20, the moisture permeation path of the electric field line 20 can be increased, thereby improving the moisture barrier properties.

[0138] The metal layer 30 may include a first metal layer 30a1 and a second metal layer 30a2.

[0139] The first metal layer 30a1 may extend from a portion of the first electric field line 20A, and the second metal layer 30a2 may extend from a portion of the second electric field line 20B. For example, the first electric field line 20A and the second electric field line 20B may be arranged to face each other in a spaced-out manner, and the first metal layer 30a1 may protrude from one side of the first electric field line 20A toward the second electric field line 20B, and the second metal layer 30a2 may protrude from one side of the second electric field line 20B toward the first electric field line 20A.

[0140] The metal layer 30 may include a protrusion 31A and a head portion 31B.

[0141] The protrusion 31A may extend from a portion of the power line 20, and multiple protrusions 31A may be configured to be spaced apart from each other.

[0142] The head portion 31B can extend from the end of each protrusion 31A and can be formed to have a width greater than the width of the protrusion 31A. This allows the two side surfaces of the metal layer 30 to be recessed, and the length of the metal layer 30 can be increased according to the recess length of the protrusion 31A. Therefore, the moisture penetration path can be extended, and the moisture barrier performance of the display device 100 can be improved.

[0143] The shielding layer 40 can be configured to correspond to the recessed portion 30a. That is, the shielding layer 40 can cover the recessed portion 30a formed on one side of the metal layer 30 to flatten the step 30b formed on one side of the metal layer 30. For example, the shielding layer 40 can be formed of the same material as the embankment layer 160 or the second planarization layer 140. Therefore, the shielding layer 40 can be formed together with the embankment layer 160 or the second planarization layer 140, thereby simplifying the manufacturing process.

[0144] Figure 7 This is a cross-sectional view of a metal layer according to an embodiment of the present disclosure, and Figure 8 Example Coverage Figure 7 The shielding layer of the grooved portion of the metal layer shown.

[0145] Reference Figure 7 and Figure 8 The metal layer 30 may include multiple layers. For example, the metal layer 30 may include a first layer 31, a second layer 32, and a third layer 33.

[0146] The first layer 31 can be formed of titanium (Ti). The second layer 32 can be disposed on the first layer 31 and can be formed of aluminum (Al). The third layer 33 can be disposed on the second layer 32 and can be formed of titanium (Ti). Since only the second layer 32 is formed of aluminum, the difference in etching rate between the titanium and aluminum layers may result in the width of the second layer 32 being smaller than the widths of the first and third layers. In other words, the sides of the second layer 32 may be undercut to form steps 30b.

[0147] When a step 30b is formed on one side of the metal layer 30 as described above, cracks may appear in the first encapsulation layer 171 of the metal layer 30 covering the non-display area NA. If cracks appear in the first encapsulation layer 171, moisture may penetrate along the power lines 20 and cause defects in the display panel 10. To solve this problem, this embodiment may include a shielding layer 40 that covers the recessed portion 30a of the metal layer 30 and flattens the step 30b formed on the side of the metal layer 30.

[0148] For example, the shielding layer 40 may cover the side surfaces of the first layer 31, the second layer 32, and the third layer 33, and partially cover the upper surface of the third layer 33. That is, the shielding layer 40 may be broken at the upper portion of the third layer 33. This is because if the shielding layer 40, made of organic material, is continuously connected as a single unit, it can become an additional moisture permeation path.

[0149] The recessed portion 30a of the metal layer 30 can be planarized by the shielding layer 40. Therefore, when the first encapsulation layer 171 is formed above the metal layer 30, the material of the first encapsulation layer 171 will not flow into the recessed portion 30a of the metal layer 30, and thus no cracks will appear in the first encapsulation layer 171. Therefore, the moisture barrier performance of the display panel 10 can be improved, and a display device 100 with excellent moisture resistance can be provided.

[0150] Furthermore, the width of the third layer 33 can be greater than the width of the second layer 32 and less than the width of the first layer 31. Due to this structure, a portion of the groove portion 30a formed on the side of the second layer 32 can be exposed, thereby allowing the shielding layer 40 to be more easily formed in the groove portion 30a.

[0151] According to this embodiment, the power lines 20 and the metal layer 30 can be covered by the first encapsulation layer 171, the third encapsulation layer 173, the touch buffer layer 118, and the touch insulating layer 119. That is, the first encapsulation layer 171, the third encapsulation layer 173, the touch buffer layer 118, and the touch insulating layer 119 can extend from the display area AA to the non-display area NA and cover the power lines 20 and the metal layer 30.

[0152] In this way, by covering the upper part of the power line 20 and the metal layer 30 with the inorganic first encapsulation layer 171, the third encapsulation layer 173, the touch buffer layer 118 and the touch insulation layer 119, moisture penetration through the power line 20 and the metal layer 30 can be prevented or reduced, thereby further improving the moisture resistance of the display device 100.

[0153] Figure 9 This is a cross-sectional view of a display panel according to another embodiment of the present disclosure. In this embodiment, the differences from the previous embodiment will be mainly described.

[0154] Reference Figure 9 The display device 100 may also include a first moisture barrier 50 and a second moisture barrier 60.

[0155] The first moisture barrier 50 can be configured to overlap with the metal layer 30 in the non-display area NA and can be interposed between the touch buffer layer 118 and the touch insulating layer 119. For example, the first moisture barrier 50 can be formed of the same material as the bridging metal BRG. By including the first moisture barrier 50 covering the power lines 20 and the metal layer 30 from above, moisture can be effectively blocked from penetrating into the metal layer 30, thereby improving the moisture barrier performance of the display device 100.

[0156] The second moisture barrier 60 can be configured to overlap with the metal layer 30 in the non-display area NA and can cover the touch insulating layer 119. For example, the second moisture barrier 60 can be formed of the same material as the touch metal TSM. By further including the second moisture barrier 60 covering the upper part of the metal layer 30, moisture can be effectively blocked from penetrating into the metal layer 30, thereby further improving the moisture barrier performance of the display device 100.

[0157] The embodiments of this disclosure described above can be summarized as follows.

[0158] According to embodiments of the present disclosure, a display device may be provided, comprising: a display panel including a display area and a non-display area; power lines disposed in the non-display area; a plurality of metal layers extending from a portion of the power lines and including recessed portions having partially recessed side surfaces; and a shielding layer corresponding to the recessed portions of the metal layers.

[0159] According to embodiments of this disclosure, the non-display area may include a curved area disposed on one side of the display area, and a metal layer may be disposed in the non-display area between the display area and the curved area.

[0160] According to embodiments of the present disclosure, the metal layer may include a plurality of protrusions and a head portion, the plurality of protrusions extending from a portion of the power line and spaced apart from each other, and the head portion extending from the end of a respective protrusion and having a width greater than the width of the protrusion.

[0161] According to embodiments of this disclosure, the metal layer may include a first layer, a second layer, and a third layer, wherein the first layer is formed of titanium (Ti), the second layer is disposed on the first layer and formed of aluminum (Al), the third layer is disposed on the second layer and formed of titanium (Ti), and the width of the second layer may be smaller than the widths of the first layer and the third layer.

[0162] According to an embodiment of this disclosure, the width of the third layer can be greater than the width of the second layer and less than the width of the first layer.

[0163] According to embodiments of this disclosure, the shielding layer may cover the side surfaces of the first, second, and third layers, as well as a portion of the upper surface of the third layer.

[0164] According to embodiments of the present disclosure, a display panel may include: a base substrate disposed in a display area and a non-display area; at least one thin-film transistor disposed on the base substrate; a first planarization layer covering the thin-film transistor; a second planarization layer disposed on the first planarization layer; a first electrode disposed on the second planarization layer; a contact electrode interposed between the first and second planarization layers and electrically connecting the thin-film transistor and the first electrode; a dam layer disposed on the second planarization layer and including an opening exposing a portion of the first electrode; a light-emitting layer disposed on the dam layer and the first electrode; a second electrode disposed on the light-emitting layer; and an encapsulation layer disposed on the second electrode.

[0165] According to embodiments of this disclosure, the encapsulation layer may include a first encapsulation layer disposed on the second electrode, a second encapsulation layer disposed on the first encapsulation layer, and a third encapsulation layer disposed on the second encapsulation layer.

[0166] According to embodiments of this disclosure, the first encapsulation layer and the third encapsulation layer can extend from the display area to the non-display area and can cover the power lines and the metal layer.

[0167] According to embodiments of this disclosure, the metal layer may be formed of the same material as the contact electrode.

[0168] According to embodiments of this disclosure, the shielding layer may be formed of the same material as the embankment layer or the second planarization layer.

[0169] According to embodiments of this disclosure, it may further include a touch buffer layer disposed on the encapsulation layer and a touch insulating layer disposed on the touch buffer layer.

[0170] According to embodiments of this disclosure, the touch buffer layer and the touch insulating layer can extend from the display area to the non-display area and can cover the power lines and the metal layer.

[0171] According to embodiments of the present disclosure, the display device may further include a touch sensor portion disposed on a touch buffer layer and including bridging metal and touch metal disposed on the bridging metal.

[0172] According to embodiments of this disclosure, the first moisture barrier can be configured to overlap with the metal layer in a non-display area and can be inserted between the touch buffer layer and the touch insulating layer.

[0173] According to embodiments of this disclosure, the first moisture barrier may be formed of the same material as the bridge metal.

[0174] According to embodiments of this disclosure, the second moisture barrier can be configured in a non-display area to overlap with the metal layer and can cover the touch insulation layer.

[0175] According to embodiments of this disclosure, the second moisture barrier may be formed of the same material as the touch metal.

[0176] According to embodiments of this disclosure, the power lines may include a first power line and a second power line, and the metal layer may include a first metal layer formed on a portion of the first power line and a second metal layer formed on a portion of the second power line. The first power line on which the first metal layer is formed and the second power line on which the second metal layer is formed may be configured to face each other in a spaced-apart manner.

[0177] According to embodiments of this disclosure, the first power line may include one of a common power line and a drive current line, and the second power line may include the other of a common power line and a drive current line.

[0178] The above description has been prepared to enable those skilled in the art to make and use the technical ideas of this disclosure, and has been provided in the context of the specific application and its claims. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and drawings provide examples of the technical ideas of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of this disclosure.

[0179] Cross-references to related applications

[0180] This application claims priority to Korean Patent Application No. 10-2024-0150570, filed on October 30, 2024, which is incorporated herein by reference for all purposes as if fully stated herein.

Claims

1. A display device, the display device comprising: The display panel includes a display area and a non-display area. Power lines, which are disposed in the non-display area; Multiple metal layers extend from a portion of the power line and the multiple metal layers include recessed portions having partially recessed side surfaces; as well as A shielding layer that corresponds to the grooved portion of the metal layer.

2. The display device according to claim 1, in, The non-display area includes a curved region located on one side of the display area, and The metal layer is disposed in the non-display area between the display area and the curved area.

3. The display device according to claim 1, in, Each of the metal layers includes: A plurality of protrusions extending from a portion of the power line and spaced apart from each other; and The head portion extends from the end of each of the protrusions and has a width greater than the width of the protrusion.

4. The display device according to claim 1, in, Each of the metal layers includes a first layer, a second layer, and a third layer. The first layer is formed of titanium (Ti). The second layer is disposed on the first layer and is formed of aluminum (Al), and The third layer is disposed on the second layer and is formed of titanium (Ti). The width of the second layer is smaller than the width of the first layer and the width of the third layer.

5. The display device according to claim 4, in, The width of the third layer is greater than the width of the second layer, and the width of the third layer is less than the width of the first layer.

6. The display device according to claim 4, in, The shielding layer covers the side surfaces of the first layer, the second layer, and the third layer, as well as the upper portion of the third layer.

7. The display device according to claim 1, in, The display panel includes: A base substrate, wherein the base substrate is disposed in the display area and the non-display area; At least one thin-film transistor, the at least one thin-film transistor being disposed on the base substrate; A first planarization layer covers the thin-film transistor; A second planarization layer is disposed on the first planarization layer; A first electrode is disposed on the second planarization layer; A contact electrode is disposed between the first planarization layer and the second planarization layer and is electrically connected to the thin-film transistor and the first electrode; A dam layer is disposed on the second planarization layer and the dam layer has an opening that exposes a portion of the first electrode; A light-emitting layer is disposed on the embankment and the first electrode; A second electrode, wherein the second electrode is disposed on the light-emitting layer; and An encapsulation layer is disposed on the second electrode.

8. The display device according to claim 7, in, The encapsulation layer includes a first encapsulation layer disposed on the second electrode, a second encapsulation layer disposed on the first encapsulation layer, and a third encapsulation layer disposed on the second encapsulation layer.

9. The display device according to claim 8, in, The first encapsulation layer and the third encapsulation layer extend from the display area to the non-display area and cover the power lines and the metal layer.

10. The display device according to claim 7, in, The metal layer is formed of the same material as the contact electrode.

11. The display device according to claim 7, in, The shielding layer is formed of the same material as the dike layer or the second planarization layer.

12. The display device according to claim 7, further comprising a touch buffer layer and a touch insulating layer, the touch buffer layer being disposed on the encapsulation layer, and the touch insulating layer being disposed on the touch buffer layer.

13. The display device according to claim 12, in, The touch buffer layer and the touch insulating layer extend from the display area to the non-display area and cover the power lines and the metal layer.

14. The display device according to claim 12, further comprising a touch sensor portion disposed on the touch buffer layer and the touch sensor portion comprising bridging metal and touch metal disposed on the bridging metal.

15. The display device of claim 14, the display device comprising a first moisture barrier, the first moisture barrier being configured to overlap the metal layer in the non-display area, and the first moisture barrier being interposed between the touch buffer layer and the touch insulating layer.

16. The display device according to claim 15, in, The first moisture barrier is formed of the same material as the bridging metal.

17. The display device of claim 14, the display device comprising a second moisture barrier, the second moisture barrier being configured to overlap the metal layer in the non-display area, and the second moisture barrier covering the touch insulating layer.

18. The display device according to claim 17, in, The second moisture barrier is formed of the same material as the touch metal.

19. The display device according to claim 1, in, The power lines include a first power line and a second power line. The metal layer includes a first metal layer formed on a portion of the first electric field line and a second metal layer formed on a portion of the second electric field line. The first electric field lines on which the first metal layer is formed and the second electric field lines on which the second metal layer is formed are arranged to face each other in a spaced-out manner.

20. The display device according to claim 19, in, The first power line includes one of a common power line and a drive current line, and the second power line includes the other of the common power line and the drive current line.

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