Low power write erase non-volatile memory

Abstract

The invention provides a low power supply write-in erase type non-volatile memory, which belongs to the field of memories and comprises a common source line, a word line, a bit line, a memory array, a first electronic switch, a second electronic switch, a decoding device, a first storage capacitor, a second storage capacitor and a booster circuit. Each memory array is coupled to a common source line, a word line and four bit lines. The decoding device is coupled with a common source line, a word line and a bit line, and is coupled with a high voltage, a medium voltage, a low voltage and a grounding voltage. One end of the first storage capacitor is coupled with reference voltage, and the other end is coupled with the decoding device through the first electronic switch. One end of the second storage capacitor is coupled with the reference voltage, and the other end is coupled with the decoding device through the second electronic switch. The boost circuit is coupled to the first storage capacitor. The boost circuit can charge the first storage capacitor to complete a programming action or an erasing action. The power consumption can be reduced, and the stability of stored data can be improved.

Description

Technical Field

[0001] This invention relates to the field of memory, specifically to a low-power write-erase non-volatile memory, and particularly to a low-power write-erase non-volatile memory that stores high-voltage charges with low power. Background Technology

[0002] Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common manufacturing method for application-specific integrated circuits (ASICs). In today's world of advanced computer information products, electrically erasable programmable read-only memory (EEPROM) is widely used in electronic products because it possesses the non-volatile memory function of electrically writing and erasing data, and the data is not lost after the power is turned off.

[0003] Non-volatile memory (NVMemory) is programmable, used to store charge to change the gate voltage of the memory's transistors, or to leave no charge, thus maintaining the original gate voltage of the memory's transistors. An erase operation removes all charge stored in the NVMemory, returning all NVMemory to the gate voltage of the original memory's transistors. In existing technologies, high-voltage DC charge is used for writing and erasing. However, high-voltage DC increases circuit power consumption during writing or erasing, especially when the circuit receives high voltage for extended periods. Furthermore, high-voltage charge can cause material degradation in the storage medium or induce memory effects. These problems reduce the stability of stored data and increase read and write errors.

[0004] Therefore, in order to address the above-mentioned problems, the present invention proposes a low-power write-erase non-volatile memory to solve the aforementioned issues. Summary of the Invention

[0005] This invention provides a low-power write-erase non-volatile memory that reduces power consumption and improves the stability of stored data.

[0006] In one embodiment of the present invention, a low-power write-erase non-volatile memory is provided, comprising multiple parallel common-source lines, multiple parallel word lines, multiple parallel bit lines, multiple memory arrays, a first electronic switch, a second electronic switch, a decoding device, at least one first storage capacitor, at least one second storage capacitor, and a boost circuit. The word lines and common-source lines are parallel to each other, and the bit lines and common-source lines are perpendicular to each other. Each memory array is coupled to one common-source line, one word line, and four bit lines. The decoding device is coupled to the common-source line, the word line, and the bit lines, and is coupled to a high voltage, a medium voltage, a low voltage, and a ground voltage, wherein the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. One end of the first storage capacitor is coupled to a reference voltage, and the other end is coupled to the decoding device through the first electronic switch. One end of the second storage capacitor is coupled to a supply voltage, and the other end is coupled to the decoding device through the second electronic switch. The boost circuit is coupled to the first storage capacitor. When the first and second electronic switches are off, the boost circuit receives an input voltage to charge the first storage capacitor to a charging voltage greater than the reference voltage. When the first and second electronic switches are on, the decoding device uses one of the coupled voltage-biased memory arrays as the target memory array, and the first storage capacitor charges the second storage capacitor through the target memory array to complete the programming or erasing operation.

[0007] In one embodiment of the present invention, the decoding device includes a first decoder, a second decoder, and a third decoder. The first decoder is coupled to a common-source line and a second electronic switch, and is coupled to a medium voltage, a low voltage, and a ground voltage. The second decoder is coupled to a word line and the first electronic switch, and is coupled to a high voltage, a low voltage, and a ground voltage. The third decoder is coupled to a bit line and the first electronic switch, and is coupled to a high voltage. The first decoder, the second decoder, and the third decoder are used to bias the target memory array according to the coupled voltages.

[0008] In one embodiment of the present invention, the common source line includes a first common source line, the word line includes a first word line, and the bit lines include a first bit line, a second bit line, a third bit line, and a fourth bit line. Each memory array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The control terminal of the first memory cell is coupled to the first word line, and the data terminal is coupled to the first common source line and the first bit line. The control terminal of the second memory cell is coupled to the first word line, and the data terminal is coupled to the first common source line and the second bit line. The control terminal of the third memory cell is coupled to the first word line, and the data terminal is coupled to the first common source line and the third bit line. The control terminal of the fourth memory cell is coupled to the first word line, and the data terminal is coupled to the first common source line and the fourth bit line. The first memory cell and the second memory cell are arranged symmetrically about the first common source line, and the third memory cell and the fourth memory cell are arranged symmetrically about the first common source line. The first memory cell and the fourth memory cell are located between the first word line and the first common source line.

[0009] In one embodiment of the present invention, a first memory cell includes a first N-type metal-oxide-semiconductor (MOSFET) and a first capacitor. The drain of the first N-type MOSFET is coupled to a first bit line, and the source is coupled to a first common-source line. One end of the first capacitor is coupled to the gate of the first N-type MOSFET, and the other end is coupled to a first word line. A second memory cell includes a second N-type MOSFET and a second capacitor. The drain of the second N-type MOSFET is coupled to a second bit line, and the source is coupled to a first common-source line. One end of the second capacitor is coupled to the gate of the second N-type MOSFET, and the other end is coupled to a first word line. A third memory cell includes a third N-type MOSFET and a third capacitor. The drain of the third N-type MOSFET is coupled to a third bit line, and the source is coupled to a first common-source line. One end of the third capacitor is coupled to the gate of the third N-type MOSFET, and the other end is coupled to a first word line. The fourth memory cell includes a fourth N-type metal-oxide-semiconductor field-effect transistor (MOSFET) and a fourth capacitor. The drain of the fourth N-type MOSFET is coupled to the fourth bit line, and the source is coupled to the first common-source line. One end of the fourth capacitor is coupled to the gate of the fourth N-type MOSFET, and the other end is coupled to the first word line.

[0010] In one embodiment of the present invention, when the first memory cell is selected to perform programmed operation, the base of the first N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the first word line is coupled to high voltage, the first common source line is coupled to ground voltage or low voltage, and the first word line is coupled to high voltage.

[0011] In one embodiment of the present invention, when the first memory cell is not selected for programmed operation, the base of the first N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the first word line is electrically floated, the first common source line is coupled to medium voltage, and the first word line is coupled to low voltage or ground voltage.

[0012] In one embodiment of the present invention, when the second memory cell is selected to perform programmed operation, the base of the second N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the second bit line is coupled to high voltage, the first common source line is coupled to ground voltage or low voltage, and the first word line is coupled to high voltage.

[0013] In one embodiment of the present invention, when the second memory cell is not selected for programmed operation, the base of the second N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the second bit line is electrically floated, the first common source line is coupled to medium voltage, and the first word line is coupled to low voltage or ground voltage.

[0014] In one embodiment of the present invention, when the third memory cell is selected to perform programmed operation, the base of the third N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the third bit line is coupled to high voltage, the first common source line is coupled to ground voltage or low voltage, and the first word line is coupled to high voltage.

[0015] In one embodiment of the present invention, when the third memory cell is not selected for programmed operation, the base of the third N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the third bit line is electrically floated, the first common source line is coupled to medium voltage, and the first word line is coupled to low voltage or ground voltage.

[0016] In one embodiment of the present invention, when the fourth memory cell is selected to perform programmed operation, the base of the fourth N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the fourth bit line is coupled to high voltage, the first common source line is coupled to ground voltage or low voltage, and the first word line is coupled to high voltage.

[0017] In one embodiment of the present invention, when the fourth memory cell is not selected for programmed operation, the base of the fourth N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the fourth bit line is electrically floated, the first common source line is coupled to medium voltage, and the first word line is coupled to low voltage or ground voltage.

[0018] In one embodiment of the present invention, when the first memory cell is selected to perform an erase operation, the base of the first N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the first word line is coupled to high voltage, the first common source line is coupled to ground voltage, and the first word line is coupled to low voltage or ground voltage.

[0019] In one embodiment of the present invention, when the first memory cell is not selected for erasure, the base of the first N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the first word line is electrically floated, the first common source line is coupled to medium voltage, and the first word line is coupled to low voltage or ground voltage.

[0020] In one embodiment of the present invention, when the second memory cell is selected to perform an erase operation, the base of the second N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the second bit line is coupled to high voltage, the first common source line is coupled to ground voltage, and the first word line is coupled to low voltage or ground voltage.

[0021] In one embodiment of the present invention, when the second memory cell is not selected for erasure, the base of the second N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the second bit line is electrically floated, the first common source line is coupled to medium voltage, and the first word line is coupled to low voltage or ground voltage.

[0022] In one embodiment of the present invention, when the third memory cell is selected to perform an erase operation, the base of the third N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the third bit line is coupled to high voltage, the first common source line is coupled to ground voltage, and the first word line is coupled to low voltage or ground voltage.

[0023] In one embodiment of the present invention, when the third memory cell is not selected for erasure, the base of the third N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the third bit line is electrically floated, the first common source line is coupled to medium voltage, and the first word line is coupled to low voltage or ground voltage.

[0024] In one embodiment of the present invention, when the fourth memory cell is selected to perform an erase operation, the base of the fourth N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the fourth bit line is coupled to high voltage, the first common source line is coupled to ground voltage, and the first word line is coupled to low voltage or ground voltage.

[0025] In one embodiment of the present invention, when the fourth memory cell is not selected for erasure, the base of the fourth N-type metal-oxide-semiconductor field-effect transistor is coupled to ground voltage, the fourth bit line is electrically floated, the first common source line is coupled to medium voltage, and the first word line is coupled to low voltage or ground voltage.

[0026] Based on the above, low-power write-erase non-volatile memory stores high-voltage charge in capacitors with low power and provides a pulse voltage for programming and erasing operations, thereby reducing power consumption and improving the stability of stored data. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a circuit diagram of a low-power write-erase non-volatile memory provided in an embodiment of the present invention.

[0029] Figure 2 A schematic diagram of the operation of a low-power write-erase non-volatile memory provided in an embodiment of the present invention;

[0030] Figure 3 This is another operational schematic diagram of a low-power write-erase non-volatile memory provided in an embodiment of the present invention.

[0031] Figure label:

[0032] 1: Low-power write-erase non-volatile memory; 10: Memory array; 100: First memory cell; 101: Second memory cell; 102: Third memory cell; 103: Fourth memory cell; 11: Decoding device; 110: First decoder; 111: Second decoder; 112: Third decoder; 12: First storage capacitor; 13: Second storage capacitor; 14: Boost circuit.

[0033] SW1: First electronic switch, SW2: Second electronic switch, SL: Common source line, SL1: First common source line, WL: Word line, WL1: First word line, BL: Bit line, BL1: First bit line, BL2: Second bit line, BL3: Third bit line, BL4: Fourth bit line, HV: High voltage, MV: Medium voltage, LV: Low voltage, VIN: Input voltage, VDD: Supply voltage, T1: First N-type MOSFET, T2: Second N-type MOSFET, T3: Third N-type MOSFET, T4: Fourth N-type MOSFET, C1: First capacitor, C2: Second capacitor, C3: Third capacitor, C4: Fourth capacitor. Detailed Implementation

[0034] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals represent the same or similar components in the drawings and description. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0035] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be necessary. In other embodiments, these features, elements, or steps may be unnecessary.

[0036] In the following description of "one embodiment" or "an embodiment," the reference refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "one embodiment" or "an embodiment" appearing in various places below do not refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0037] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "including but not limited to". Furthermore, "coupled" herein includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signalally connected to the second element through other elements or connection means.

[0038] This invention is described in particular by way of the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure is determined by the appended claims. Throughout this specification and the claims, unless explicitly specified, the words "a" and "the" include statements containing "a or at least one" of the element or component. Furthermore, as used in this disclosure, the singular article also includes statements of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and throughout the claims, unless explicitly specified, "in which" can mean both "in which" and "therein". The terms used throughout this specification and the claims, unless otherwise specified, generally have their ordinary meaning in the art, in this disclosure, and in specific contexts. Certain terms used to describe this application will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing the application. Examples throughout this specification, including examples of any terms discussed herein, are for illustrative purposes only and do not limit the scope or meaning of this application or any illustrative terms. Similarly, this application is not limited to the various embodiments set forth in this specification.

[0039] In the following description, a low-power write-erase non-volatile memory is provided, which stores high-voltage charge in a capacitor with low power and provides a pulse voltage for programming and erasing operations, thereby reducing power consumption and improving the stability of stored data.

[0040] Figure 1 This is a circuit diagram of a low-power write-erase non-volatile memory according to an embodiment of the present invention. Please refer to [link / reference]. Figure 1 The following describes the low-power write-erase non-volatile memory 1 of the present invention. It includes multiple parallel common-source lines SL, multiple parallel word lines WL, multiple parallel bit lines BL, multiple memory arrays 10, a first electronic switch SW1, a second electronic switch SW2, a decoding device 11, at least one first storage capacitor 12, at least one second storage capacitor 13, and a boost circuit 14. For convenience and clarity, multiple first storage capacitors 12 and second storage capacitors 13 are used as examples. The word lines WL and common-source lines SL are parallel to each other, and the bit lines BL and common-source lines SL are perpendicular to each other. Each memory array 10 is coupled to one common-source line SL, one word line WL, and four bit lines BL. The decoding device 11 is coupled to the common-source line SL, the word lines WL, and the bit lines BL, and is coupled to a high voltage HV, a medium voltage MV, a low voltage LV, and a ground voltage, wherein the high voltage HV is greater than the medium voltage MV, the medium voltage MV is greater than the low voltage LV, and the low voltage LV is greater than the ground voltage. One end of the first storage capacitor 12 is coupled to a reference voltage, such as ground voltage, and the other end of the first storage capacitor 12 is coupled to the decoding device 11 through the first electronic switch SW1. One end of the second storage capacitor 13 is coupled to a supply voltage VDD, and the other end is coupled to the decoding device 11 through the second electronic switch SW2. The boost circuit 14 is coupled to the first storage capacitor 12.

[0041] Figure 2 and Figure 3 This is a schematic diagram illustrating the operation of a low-power write-erase non-volatile memory according to an embodiment of the present invention. Figure 2 As shown, when the first electronic switch SW1 and the second electronic switch SW2 are turned off, the boost circuit 14 receives an input voltage VIN to charge the first storage capacitor 12 to a charging voltage greater than the reference voltage. Figure 3As shown, when the first electronic switch SW1 and the second electronic switch SW2 are turned on, the decoding device 11 selects one of the coupled voltage-biased memory arrays 10 as the target memory array, and the first storage capacitor 12 charges the second storage capacitor 13 through the target memory array to complete the programming or erasing operation. In other words, the boost circuit 14 stores high-voltage charge in the first storage capacitor 12 with a low power supply and provides a pulse voltage to perform programming and erasing operations, thereby reducing power consumption and improving the stability of the stored data.

[0042] Please see Figure 1 In some embodiments of the present invention, the decoding device 11 may include a first decoder 110, a second decoder 111, and a third decoder 112, which are voltage-biased target memory arrays based on coupled voltages. The first decoder 110 is coupled to a common-source line SL and a second electronic switch SW2, and is coupled to a medium voltage MV, a low voltage LV, and ground. The first decoder 110 biases the target memory array with the medium voltage MV, the low voltage LV, and ground. The second decoder 111 is coupled to a word line WL and a first electronic switch SW1, and is coupled to a high voltage HV, a low voltage LV, and ground. The second decoder 111 biases the target memory array with the high voltage HV, the low voltage LV, and ground. The third decoder 112 is coupled to a bit line BL and the first electronic switch SW1, and is coupled to a high voltage HV. The third decoder 112 biases the target memory array with the high voltage HV.

[0043] The common-source line SL may include a first common-source line SL1, the word line WL may include a first word line WL1, and the bit line BL may include a first bit line BL1, a second bit line BL2, a third bit line BL3, and a fourth bit line BL4. Each memory array 10 may include a first memory cell 100, a second memory cell 101, a third memory cell 102, and a fourth memory cell 103. The control terminal of the first memory cell 100 is coupled to the first word line WL1, and the data terminal is coupled to the first common-source line SL1 and the first bit line BL1. The control terminal of the second memory cell 101 is coupled to the first word line WL1, and the data terminal is coupled to the first common-source line SL1 and the second bit line BL2. The control terminal of the third memory cell 102 is coupled to the first word line WL1, and the data terminal is coupled to the first common-source line SL1 and the third bit line BL3. The control terminal of the fourth memory cell 103 is coupled to the first word line WL1, and the data terminal is coupled to the first common source line SL1 and the fourth bit line BL4. The first memory cell 100 and the second memory cell 101 are arranged symmetrically about the first common source line SL1, and the third memory cell 102 and the fourth memory cell 103 are arranged symmetrically about the first common source line SL1. The first memory cell 100 and the fourth memory cell 103 are located between the first word line WL1 and the first common source line SL1.

[0044] The first memory cell 100 may include a first N-type metal-oxide-semiconductor (MOSFET) T1 and a first capacitor C1. The drain of the first N-type MOSFET T1 is coupled to the first bit line BL1, and the source is coupled to the first common-source line SL1. One end of the first capacitor C1 is coupled to the gate of the first N-type MOSFET T1, and the other end is coupled to the first word line WL1. The second memory cell 101 may include a second N-type MOSFET T2 and a second capacitor C2. The drain of the second N-type MOSFET T2 is coupled to the second bit line BL2, and the source is coupled to the first common-source line SL1. One end of the second capacitor C2 is coupled to the gate of the second N-type MOSFET T2, and the other end is coupled to the first word line WL1. The third memory cell 102 may include a third N-type MOSFET T3 and a third capacitor C3. The drain of the third N-type MOSFET T3 is coupled to the third bit line BL3, and the source is coupled to the first common-source line SL1. One end of the third capacitor C3 is coupled to the gate of the third N-type MOSFET T3, and the other end is coupled to the first word line WL1. The fourth memory cell 103 may include a fourth N-type MOSFET T4 and a fourth capacitor C4. The drain of the fourth N-type MOSFET T4 is coupled to the fourth bit line BL4, and the source is coupled to the first common-source line SL1. One end of the fourth capacitor C4 is coupled to the gate of the fourth N-type MOSFET T4, and the other end is coupled to the first word line WL1.

[0045] The following describes the operation of the first memory cell 100, including programmed operations and erase operations. The common-source line SL or word line WL couples to either a low voltage LV or ground voltage according to process characteristics. The high voltage HV is equal to the breakdown voltage of the first N-type MOSFET T1 from its drain to its source minus the critical voltage of the first N-type MOSFET T1. The medium voltage MV is equal to the breakdown voltage of the first N-type MOSFET T1 from its drain to its source multiplied by 0.5. The low voltage LV is equal to the breakdown voltage of the first N-type MOSFET T1 from its drain to its source multiplied by 0.25. The ground voltage is zero.

[0046] When the first memory cell 100 is selected for programmed operation, the base of the first N-type MOSFET T1 is coupled to ground voltage, the first bit line BL1 is coupled to high voltage HV, the first common source line SL1 is coupled to ground voltage or low voltage LV, and the first word line WL1 is coupled to high voltage HV. When the first memory cell 100 is not selected for programmed operation, the base of the first N-type MOSFET T1 is coupled to ground voltage, the first bit line BL1 is electrically floated, the first common source line SL1 is coupled to medium voltage MV, and the first word line WL1 is coupled to low voltage LV or ground voltage. When the first memory cell 100 is selected for erase operation, the base of the first N-type MOSFET T1 is coupled to ground voltage, the first bit line BL1 is coupled to high voltage HV, the first common source line SL1 is coupled to ground voltage, and the first word line WL1 is coupled to low voltage LV or ground voltage. When the first memory cell 100 is not selected for erasure, the base of the first N-type metal-oxide-semiconductor field-effect transistor T1 is coupled to the ground voltage, the first word line BL1 is electrically floated, the first common source line SL1 is coupled to the medium voltage MV, and the first word line WL1 is coupled to the low voltage LV or the ground voltage.

[0047] The following describes the operation of the second memory cell 101, including programmed operation and erase operation. The common-source line SL or word line WL couples to the low voltage LV or ground voltage according to process characteristics. The high voltage HV is equal to the breakdown voltage of the drain-to-source of the second N-type MOSFET T2 minus the critical voltage of the second N-type MOSFET T2. The medium voltage MV is equal to the breakdown voltage of the drain-to-source of the second N-type MOSFET T2 multiplied by 0.5. The low voltage LV is equal to the breakdown voltage of the drain-to-source of the second N-type MOSFET T2 multiplied by 0.25. The ground voltage is zero.

[0048] When the second memory cell 101 is selected for programmed operation, the base of the second N-type MOSFET T2 is coupled to ground, the second bit line BL2 is coupled to a high voltage HV, the first common-source line SL1 is coupled to ground or a low voltage LV, and the first word line WL1 is coupled to a high voltage HV. When the second memory cell 101 is not selected for programmed operation, the base of the second N-type MOSFET T2 is coupled to ground, the second bit line BL2 is electrically floated, the first common-source line SL1 is coupled to a medium voltage MV, and the first word line WL1 is coupled to a low voltage LV or ground. When the second memory cell 101 is selected for erase operation, the base of the second N-type MOSFET T2 is coupled to ground, the second bit line BL2 is coupled to a high voltage HV, the first common-source line SL1 is coupled to ground, and the first word line WL1 is coupled to a low voltage LV or ground. When the second memory cell 101 is not selected for the erase operation, the base of the second N-type metal-oxide-semiconductor field-effect transistor T2 is coupled to the ground voltage, the second bit line BL2 is electrically floated, the first common source line SL1 is coupled to the medium voltage MV, and the first word line WL1 is coupled to the low voltage LV or the ground voltage.

[0049] The following describes the operation of the third memory cell 102, including programmed operation and erase operation. The common-source line SL or word line WL couples to the low voltage LV or ground voltage according to process characteristics. The high voltage HV is equal to the breakdown voltage of the drain-to-source of the third N-type MOSFET T3 minus the critical voltage of the third N-type MOSFET T3. The medium voltage MV is equal to the breakdown voltage of the drain-to-source of the third N-type MOSFET T3 multiplied by 0.5. The low voltage LV is equal to the breakdown voltage of the drain-to-source of the third N-type MOSFET T3 multiplied by 0.25. The ground voltage is zero.

[0050] When the third memory cell 102 is selected for programmed operation, the base of the third N-type MOSFET T3 is coupled to ground voltage, the third bit line BL3 is coupled to high voltage HV, the first common source line SL1 is coupled to ground voltage or low voltage LV, and the first word line WL1 is coupled to high voltage HV. When the third memory cell 102 is not selected for programmed operation, the base of the third N-type MOSFET T3 is coupled to ground voltage, the third bit line BL3 is electrically floated, the first common source line SL1 is coupled to medium voltage MV, and the first word line WL1 is coupled to low voltage LV or ground voltage. When the third memory cell 102 is selected for erase operation, the base of the third N-type MOSFET T3 is coupled to ground voltage, the third bit line BL3 is coupled to high voltage HV, the first common source line SL1 is coupled to ground voltage, and the first word line WL1 is coupled to low voltage LV or ground voltage. When the third memory cell 102 is not selected for the erase operation, the base of the third N-type metal-oxide-semiconductor field-effect transistor T3 is coupled to the ground voltage, the third bit line BL3 is electrically floated, the first common source line SL1 is coupled to the medium voltage MV, and the first word line WL1 is coupled to the low voltage LV or the ground voltage.

[0051] The following describes the operation of the fourth memory cell 103, including programmed operation and erase operation. The common-source line SL or word line WL couples to the low voltage LV or ground voltage according to process characteristics. The high voltage HV is equal to the breakdown voltage of the fourth N-type MOSFET T4 from its drain to its source minus the critical voltage of the fourth N-type MOSFET T4. The medium voltage MV is equal to the breakdown voltage of the fourth N-type MOSFET T4 from its drain to its source multiplied by 0.5. The low voltage LV is equal to the breakdown voltage of the fourth N-type MOSFET T4 from its drain to its source multiplied by 0.25. The ground voltage is zero.

[0052] When the fourth memory cell 103 is selected for programmed operation, the base of the fourth N-type MOSFET T4 is coupled to ground, the fourth bit line BL4 is coupled to a high voltage HV, the first common-source line SL1 is coupled to ground or a low voltage LV, and the first word line WL1 is coupled to a high voltage HV. When the fourth memory cell 103 is not selected for programmed operation, the base of the fourth N-type MOSFET T4 is coupled to ground, the fourth bit line BL4 is electrically floated, the first common-source line SL1 is coupled to a medium voltage MV, and the first word line WL1 is coupled to a low voltage LV or ground. When the fourth memory cell 103 is selected for erase operation, the base of the fourth N-type MOSFET T4 is coupled to ground, the fourth bit line BL4 is coupled to a high voltage HV, the first common-source line SL1 is coupled to ground, and the first word line WL1 is coupled to a low voltage LV or ground. When the fourth memory cell 103 is not selected for erasure, the base of the fourth N-type metal-oxide-semiconductor field-effect transistor T4 is coupled to the ground voltage, the fourth bit line BL4 is electrically floated, the first common source line SL1 is coupled to the medium voltage MV, and the first word line WL1 is coupled to the low voltage LV or the ground voltage.

[0053] According to the above embodiments, the low-power write-erase non-volatile memory stores high-voltage charge in a capacitor with low power and provides a pulse voltage to perform programming and erasure operations, thereby reducing power consumption and improving the stability of stored data.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A low-power write-erase non-volatile memory, characterized in that, The low-power write-erase non-volatile memory includes: Multiple parallel common source lines; Multiple parallel character lines are parallel to each other, as are the multiple parallel common source lines; Multiple parallel bit lines are perpendicular to each other with the multiple parallel common source lines; Multiple memory arrays, each of the memory arrays being coupled to one common source line, one word line and four bit lines; A first electronic switch and a second electronic switch; A decoding device is coupled to the plurality of parallel common source lines, the plurality of parallel word lines and the plurality of parallel bit lines, and coupled to a high voltage, a medium voltage, a low voltage and a ground voltage, wherein the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage and the low voltage is greater than the ground voltage; At least one first storage capacitor, one end of which is coupled to a reference voltage, and the other end of which is coupled to the decoding device via the first electronic switch; At least one second storage capacitor, one end of which is coupled to a supply voltage, and the other end of which is coupled to the decoding device via the second electronic switch; and A boost circuit is coupled to the at least one first storage capacitor, wherein when the first electronic switch and the second electronic switch are turned off, the boost circuit receives an input voltage to charge the at least one first storage capacitor to a charging voltage greater than the reference voltage. When the first electronic switch and the second electronic switch are turned on, the decoding device biases one of the plurality of memory arrays according to the coupled voltage and uses it as the target memory array. The at least one first storage capacitor charges the at least one second storage capacitor through the target memory array to complete the programmed action or the erase action.

2. The low-power write-erase non-volatile memory according to claim 1, characterized in that, The decoding device includes: A first decoder is coupled to the plurality of parallel common-source lines and the second electronic switch, and coupled to the medium voltage, the low voltage and the ground voltage; A second decoder, coupled to the plurality of parallel word lines and the first electronic switch, and coupled to the high voltage, the low voltage and the ground voltage; and A third decoder is coupled to the multiple parallel bit lines and the first electronic switch, and coupled to the high voltage; The first decoder, the second decoder, and the third decoder are used to bias the target memory array according to the coupled voltage.

3. The low-power write-erase non-volatile memory according to claim 1, characterized in that, The plurality of parallel common-source lines include a first common-source line, the plurality of parallel word lines include a first word line, and the plurality of parallel bit lines include a first bit line, a second bit line, a third bit line, and a fourth bit line. Each memory array includes: A first memory cell, the control terminal of which is coupled to the first word line, and the data terminal of which is coupled to the first common source line and the first bit line; A second memory cell, wherein the control terminal is coupled to the first word line and the data terminal is coupled to the first common source line and the second bit line; A third memory cell, wherein the control terminal is coupled to the first word line, and the data terminal is coupled to the first common-source line and the third bit line; and A fourth memory cell, whose control terminal is coupled to the first word line and whose data terminal is coupled to the first common source line and the fourth bit line; The first memory cell and the second memory cell are arranged symmetrically about the first common source line, and the third memory cell and the fourth memory cell are arranged symmetrically about the first common source line. The first memory cell and the fourth memory cell are located between the first word line and the first common source line.

4. The low-power write-erase non-volatile memory according to claim 3, characterized in that, The first memory cell includes: A first N-type metal-oxide-semiconductor field-effect transistor, wherein its drain is coupled to the first bit line and its source is coupled to the first common-source line; and A first capacitor, one end of which is coupled to the gate of the first N-type metal-oxide-semiconductor field-effect transistor, and the other end of which is coupled to the first word line; The second memory cell includes: A second N-type metal-oxide-semiconductor field-effect transistor, wherein its drain is coupled to the second bit line and its source is coupled to the first common-source line; and A second capacitor, one end of which is coupled to the gate of the second N-type metal-oxide-semiconductor field-effect transistor, and the other end of which is coupled to the first word line; The third memory cell includes: A third N-type metal-oxide-semiconductor field-effect transistor, wherein its drain is coupled to the third bit line and its source is coupled to the first common-source line; and A third capacitor, one end of which is coupled to the gate of the third N-type metal-oxide-semiconductor field-effect transistor, and the other end of which is coupled to the first word line; and The fourth memory cell includes: A fourth N-type metal-oxide-semiconductor field-effect transistor, wherein its drain is coupled to the fourth bit line and its source is coupled to the first common-source line; and A fourth capacitor, one end of which is coupled to the gate of the fourth N-type metal-oxide-semiconductor field-effect transistor, and the other end of which is coupled to the first word line.

5. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the first memory cell is selected to perform the programmed operation, the base of the first N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the first bit line is coupled to the high voltage, the first common-source line is coupled to the ground voltage or the low voltage, and the first word line is coupled to the high voltage.

6. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the first memory cell is not selected to perform the programmed operation, the base of the first N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the first bit line is electrically floating, the first common-source line is coupled to the intermediate voltage, and the first word line is coupled to the low voltage or the ground voltage.

7. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the second memory cell is selected to perform the programmed operation, the base of the second N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the second bit line is coupled to the high voltage, the first common-source line is coupled to the ground voltage or the low voltage, and the first word line is coupled to the high voltage.

8. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the second memory cell is not selected to perform the programmed operation, the base of the second N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the second bit line is electrically floating, the first common-source line is coupled to the medium voltage, and the first word line is coupled to the low voltage or the ground voltage.

9. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the third memory cell is selected to perform the programmed operation, the base of the third N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the third bit line is coupled to the high voltage, the first common-source line is coupled to the ground voltage or the low voltage, and the first word line is coupled to the high voltage.

10. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the third memory cell is not selected to perform the programmed operation, the base of the third N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the third bit line is electrically floating, the first common source line is coupled to the medium voltage, and the first word line is coupled to the low voltage or the ground voltage.

11. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the fourth memory cell is selected to perform the programmed operation, the base of the fourth N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the fourth bit line is coupled to the high voltage, the first common-source line is coupled to the ground voltage or the low voltage, and the first word line is coupled to the high voltage.

12. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the fourth memory cell is not selected to perform the programmed operation, the base of the fourth N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the fourth bit line is electrically floating, the first common source line is coupled to the medium voltage, and the first word line is coupled to the low voltage or the ground voltage.

13. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the first memory cell is selected to perform the erase operation, the base of the first N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the first bit line is coupled to the high voltage, the first common-source line is coupled to the ground voltage, and the first word line is coupled to the low voltage or the ground voltage.

14. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the first memory cell is not selected to perform the erase operation, the base of the first N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the first bit line is electrically floating, the first common-source line is coupled to the medium voltage, and the first word line is coupled to the low voltage or the ground voltage.

15. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the second memory cell is selected to perform the erase operation, the base of the second N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the second bit line is coupled to the high voltage, the first common-source line is coupled to the ground voltage, and the first word line is coupled to the low voltage or the ground voltage.

16. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the second memory cell is not selected for the erase operation, the base of the second N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the second bit line is electrically floating, the first common source line is coupled to the intermediate voltage, and the first word line is coupled to the low voltage or the ground voltage.

17. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the third memory cell is selected to perform the erase operation, the base of the third N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the third bit line is coupled to the high voltage, the first common source line is coupled to the ground voltage, and the first word line is coupled to the low voltage or the ground voltage.

18. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the third memory cell is not selected to perform the erase operation, the base of the third N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the third bit line is electrically floating, the first common source line is coupled to the medium voltage, and the first word line is coupled to the low voltage or the ground voltage.

19. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the fourth memory cell is selected to perform the erase operation, the base of the fourth N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the fourth bit line is coupled to the high voltage, the first common source line is coupled to the ground voltage, and the first word line is coupled to the low voltage or the ground voltage.

20. The low-power write-erase non-volatile memory according to claim 4, characterized in that, When the fourth memory cell is not selected to perform the erase operation, the base of the fourth N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the fourth bit line is electrically floating, the first common source line is coupled to the medium voltage, and the first word line is coupled to the low voltage or the ground voltage.

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